git.oblomov.eu Git - linux-2.6/blob - drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004-2008 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/timer.h>
  18 #include <linux/errno.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/pci.h>
  24 #include <linux/init.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/bitops.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <linux/delay.h>
  33 #include <asm/byteorder.h>
  34 #include <asm/page.h>
  35 #include <linux/time.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/mii.h>
  38 #ifdef NETIF_F_HW_VLAN_TX
  39 #include <linux/if_vlan.h>
  40 #define BCM_VLAN 1
  41 #endif
  42 #include <net/ip.h>
  43 #include <net/tcp.h>
  44 #include <net/checksum.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/crc32.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/zlib.h>
  50
  51 #include "bnx2.h"
  52 #include "bnx2_fw.h"
  53 #include "bnx2_fw2.h"
  54
  55 #define FW_BUF_SIZE             0x10000
  56
  57 #define DRV_MODULE_NAME         "bnx2"
  58 #define PFX DRV_MODULE_NAME     ": "
  59 #define DRV_MODULE_VERSION      "1.7.4"
  60 #define DRV_MODULE_RELDATE      "February 18, 2008"
  61
  62 #define RUN_AT(x) (jiffies + (x))
  63
  64 /* Time in jiffies before concluding the transmitter is hung. */
  65 #define TX_TIMEOUT  (5*HZ)
  66
  67 static char version[] __devinitdata =
  68         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  69
  70 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  71 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
  72 MODULE_LICENSE("GPL");
  73 MODULE_VERSION(DRV_MODULE_VERSION);
  74
  75 static int disable_msi = 0;
  76
  77 module_param(disable_msi, int, 0);
  78 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  79
  80 typedef enum {
  81         BCM5706 = 0,
  82         NC370T,
  83         NC370I,
  84         BCM5706S,
  85         NC370F,
  86         BCM5708,
  87         BCM5708S,
  88         BCM5709,
  89         BCM5709S,
  90 } board_t;
  91
  92 /* indexed by board_t, above */
  93 static struct {
  94         char *name;
  95 } board_info[] __devinitdata = {
  96         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  97         { "HP NC370T Multifunction Gigabit Server Adapter" },
  98         { "HP NC370i Multifunction Gigabit Server Adapter" },
  99         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 100         { "HP NC370F Multifunction Gigabit Server Adapter" },
 101         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
 102         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 103         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
 104         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 105         };
 106
 107 static struct pci_device_id bnx2_pci_tbl[] = {
 108         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 109           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
 110         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 111           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
 112         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 113           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
 114         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
 115           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
 116         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 117           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
 118         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 119           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
 120         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
 121           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
 122         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
 123           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
 124         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
 125           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
 126         { 0, }
 127 };
 128
 129 static struct flash_spec flash_table[] =
 130 {
 131 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
 132 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
 133         /* Slow EEPROM */
 134         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 135          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 136          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 137          "EEPROM - slow"},
 138         /* Expansion entry 0001 */
 139         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 140          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 141          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 142          "Entry 0001"},
 143         /* Saifun SA25F010 (non-buffered flash) */
 144         /* strap, cfg1, & write1 need updates */
 145         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 146          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 147          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 148          "Non-buffered flash (128kB)"},
 149         /* Saifun SA25F020 (non-buffered flash) */
 150         /* strap, cfg1, & write1 need updates */
 151         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 152          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 153          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 154          "Non-buffered flash (256kB)"},
 155         /* Expansion entry 0100 */
 156         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 157          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 158          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 159          "Entry 0100"},
 160         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 161         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 162          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 163          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 164          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 165         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 166         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 167          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 168          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 169          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 170         /* Saifun SA25F005 (non-buffered flash) */
 171         /* strap, cfg1, & write1 need updates */
 172         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 173          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 174          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 175          "Non-buffered flash (64kB)"},
 176         /* Fast EEPROM */
 177         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 178          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 179          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 180          "EEPROM - fast"},
 181         /* Expansion entry 1001 */
 182         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 183          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 184          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 185          "Entry 1001"},
 186         /* Expansion entry 1010 */
 187         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 189          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 190          "Entry 1010"},
 191         /* ATMEL AT45DB011B (buffered flash) */
 192         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 193          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 194          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 195          "Buffered flash (128kB)"},
 196         /* Expansion entry 1100 */
 197         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 198          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 199          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 200          "Entry 1100"},
 201         /* Expansion entry 1101 */
 202         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 203          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 204          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 205          "Entry 1101"},
 206         /* Ateml Expansion entry 1110 */
 207         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 208          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 209          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 210          "Entry 1110 (Atmel)"},
 211         /* ATMEL AT45DB021B (buffered flash) */
 212         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 213          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 214          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 215          "Buffered flash (256kB)"},
 216 };
 217
 218 static struct flash_spec flash_5709 = {
 219         .flags          = BNX2_NV_BUFFERED,
 220         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 221         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 222         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 223         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
 224         .name           = "5709 Buffered flash (256kB)",
 225 };
 226
 227 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 228
 229 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi)
 230 {
 231         u32 diff;
 232
 233         smp_mb();
 234
 235         /* The ring uses 256 indices for 255 entries, one of them
 236          * needs to be skipped.
 237          */
 238         diff = bp->tx_prod - bnapi->tx_cons;
 239         if (unlikely(diff >= TX_DESC_CNT)) {
 240                 diff &= 0xffff;
 241                 if (diff == TX_DESC_CNT)
 242                         diff = MAX_TX_DESC_CNT;
 243         }
 244         return (bp->tx_ring_size - diff);
 245 }
 246
 247 static u32
 248 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 249 {
 250         u32 val;
 251
 252         spin_lock_bh(&bp->indirect_lock);
 253         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 254         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
 255         spin_unlock_bh(&bp->indirect_lock);
 256         return val;
 257 }
 258
 259 static void
 260 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 261 {
 262         spin_lock_bh(&bp->indirect_lock);
 263         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 264         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 265         spin_unlock_bh(&bp->indirect_lock);
 266 }
 267
 268 static void
 269 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
 270 {
 271         bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
 272 }
 273
 274 static u32
 275 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
 276 {
 277         return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
 278 }
 279
 280 static void
 281 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 282 {
 283         offset += cid_addr;
 284         spin_lock_bh(&bp->indirect_lock);
 285         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 286                 int i;
 287
 288                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
 289                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
 290                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
 291                 for (i = 0; i < 5; i++) {
 292                         u32 val;
 293                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
 294                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
 295                                 break;
 296                         udelay(5);
 297                 }
 298         } else {
 299                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 300                 REG_WR(bp, BNX2_CTX_DATA, val);
 301         }
 302         spin_unlock_bh(&bp->indirect_lock);
 303 }
 304
 305 static int
 306 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 307 {
 308         u32 val1;
 309         int i, ret;
 310
 311         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 312                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 313                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 314
 315                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 316                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 317
 318                 udelay(40);
 319         }
 320
 321         val1 = (bp->phy_addr << 21) | (reg << 16) |
 322                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 323                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 324         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 325
 326         for (i = 0; i < 50; i++) {
 327                 udelay(10);
 328
 329                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 330                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 331                         udelay(5);
 332
 333                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 334                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 335
 336                         break;
 337                 }
 338         }
 339
 340         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 341                 *val = 0x0;
 342                 ret = -EBUSY;
 343         }
 344         else {
 345                 *val = val1;
 346                 ret = 0;
 347         }
 348
 349         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 350                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 351                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 352
 353                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 354                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 355
 356                 udelay(40);
 357         }
 358
 359         return ret;
 360 }
 361
 362 static int
 363 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 364 {
 365         u32 val1;
 366         int i, ret;
 367
 368         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 369                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 370                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 371
 372                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 373                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 374
 375                 udelay(40);
 376         }
 377
 378         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 379                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 380                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 381         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 382
 383         for (i = 0; i < 50; i++) {
 384                 udelay(10);
 385
 386                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 387                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 388                         udelay(5);
 389                         break;
 390                 }
 391         }
 392
 393         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 394                 ret = -EBUSY;
 395         else
 396                 ret = 0;
 397
 398         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 399                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 400                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 401
 402                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 403                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 404
 405                 udelay(40);
 406         }
 407
 408         return ret;
 409 }
 410
 411 static void
 412 bnx2_disable_int(struct bnx2 *bp)
 413 {
 414         int i;
 415         struct bnx2_napi *bnapi;
 416
 417         for (i = 0; i < bp->irq_nvecs; i++) {
 418                 bnapi = &bp->bnx2_napi[i];
 419                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 420                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 421         }
 422         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 423 }
 424
 425 static void
 426 bnx2_enable_int(struct bnx2 *bp)
 427 {
 428         int i;
 429         struct bnx2_napi *bnapi;
 430
 431         for (i = 0; i < bp->irq_nvecs; i++) {
 432                 bnapi = &bp->bnx2_napi[i];
 433
 434                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 435                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 436                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
 437                        bnapi->last_status_idx);
 438
 439                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 440                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 441                        bnapi->last_status_idx);
 442         }
 443         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 444 }
 445
 446 static void
 447 bnx2_disable_int_sync(struct bnx2 *bp)
 448 {
 449         int i;
 450
 451         atomic_inc(&bp->intr_sem);
 452         bnx2_disable_int(bp);
 453         for (i = 0; i < bp->irq_nvecs; i++)
 454                 synchronize_irq(bp->irq_tbl[i].vector);
 455 }
 456
 457 static void
 458 bnx2_napi_disable(struct bnx2 *bp)
 459 {
 460         int i;
 461
 462         for (i = 0; i < bp->irq_nvecs; i++)
 463                 napi_disable(&bp->bnx2_napi[i].napi);
 464 }
 465
 466 static void
 467 bnx2_napi_enable(struct bnx2 *bp)
 468 {
 469         int i;
 470
 471         for (i = 0; i < bp->irq_nvecs; i++)
 472                 napi_enable(&bp->bnx2_napi[i].napi);
 473 }
 474
 475 static void
 476 bnx2_netif_stop(struct bnx2 *bp)
 477 {
 478         bnx2_disable_int_sync(bp);
 479         if (netif_running(bp->dev)) {
 480                 bnx2_napi_disable(bp);
 481                 netif_tx_disable(bp->dev);
 482                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 483         }
 484 }
 485
 486 static void
 487 bnx2_netif_start(struct bnx2 *bp)
 488 {
 489         if (atomic_dec_and_test(&bp->intr_sem)) {
 490                 if (netif_running(bp->dev)) {
 491                         netif_wake_queue(bp->dev);
 492                         bnx2_napi_enable(bp);
 493                         bnx2_enable_int(bp);
 494                 }
 495         }
 496 }
 497
 498 static void
 499 bnx2_free_mem(struct bnx2 *bp)
 500 {
 501         int i;
 502
 503         for (i = 0; i < bp->ctx_pages; i++) {
 504                 if (bp->ctx_blk[i]) {
 505                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
 506                                             bp->ctx_blk[i],
 507                                             bp->ctx_blk_mapping[i]);
 508                         bp->ctx_blk[i] = NULL;
 509                 }
 510         }
 511         if (bp->status_blk) {
 512                 pci_free_consistent(bp->pdev, bp->status_stats_size,
 513                                     bp->status_blk, bp->status_blk_mapping);
 514                 bp->status_blk = NULL;
 515                 bp->stats_blk = NULL;
 516         }
 517         if (bp->tx_desc_ring) {
 518                 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
 519                                     bp->tx_desc_ring, bp->tx_desc_mapping);
 520                 bp->tx_desc_ring = NULL;
 521         }
 522         kfree(bp->tx_buf_ring);
 523         bp->tx_buf_ring = NULL;
 524         for (i = 0; i < bp->rx_max_ring; i++) {
 525                 if (bp->rx_desc_ring[i])
 526                         pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 527                                             bp->rx_desc_ring[i],
 528                                             bp->rx_desc_mapping[i]);
 529                 bp->rx_desc_ring[i] = NULL;
 530         }
 531         vfree(bp->rx_buf_ring);
 532         bp->rx_buf_ring = NULL;
 533         for (i = 0; i < bp->rx_max_pg_ring; i++) {
 534                 if (bp->rx_pg_desc_ring[i])
 535                         pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 536                                             bp->rx_pg_desc_ring[i],
 537                                             bp->rx_pg_desc_mapping[i]);
 538                 bp->rx_pg_desc_ring[i] = NULL;
 539         }
 540         if (bp->rx_pg_ring)
 541                 vfree(bp->rx_pg_ring);
 542         bp->rx_pg_ring = NULL;
 543 }
 544
 545 static int
 546 bnx2_alloc_mem(struct bnx2 *bp)
 547 {
 548         int i, status_blk_size;
 549
 550         bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
 551         if (bp->tx_buf_ring == NULL)
 552                 return -ENOMEM;
 553
 554         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
 555                                                 &bp->tx_desc_mapping);
 556         if (bp->tx_desc_ring == NULL)
 557                 goto alloc_mem_err;
 558
 559         bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
 560         if (bp->rx_buf_ring == NULL)
 561                 goto alloc_mem_err;
 562
 563         memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring);
 564
 565         for (i = 0; i < bp->rx_max_ring; i++) {
 566                 bp->rx_desc_ring[i] =
 567                         pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 568                                              &bp->rx_desc_mapping[i]);
 569                 if (bp->rx_desc_ring[i] == NULL)
 570                         goto alloc_mem_err;
 571
 572         }
 573
 574         if (bp->rx_pg_ring_size) {
 575                 bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
 576                                          bp->rx_max_pg_ring);
 577                 if (bp->rx_pg_ring == NULL)
 578                         goto alloc_mem_err;
 579
 580                 memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
 581                        bp->rx_max_pg_ring);
 582         }
 583
 584         for (i = 0; i < bp->rx_max_pg_ring; i++) {
 585                 bp->rx_pg_desc_ring[i] =
 586                         pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 587                                              &bp->rx_pg_desc_mapping[i]);
 588                 if (bp->rx_pg_desc_ring[i] == NULL)
 589                         goto alloc_mem_err;
 590
 591         }
 592
 593         /* Combine status and statistics blocks into one allocation. */
 594         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
 595         if (bp->flags & BNX2_FLAG_MSIX_CAP)
 596                 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
 597                                                  BNX2_SBLK_MSIX_ALIGN_SIZE);
 598         bp->status_stats_size = status_blk_size +
 599                                 sizeof(struct statistics_block);
 600
 601         bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
 602                                               &bp->status_blk_mapping);
 603         if (bp->status_blk == NULL)
 604                 goto alloc_mem_err;
 605
 606         memset(bp->status_blk, 0, bp->status_stats_size);
 607
 608         bp->bnx2_napi[0].status_blk = bp->status_blk;
 609         if (bp->flags & BNX2_FLAG_MSIX_CAP) {
 610                 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
 611                         struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 612
 613                         bnapi->status_blk_msix = (void *)
 614                                 ((unsigned long) bp->status_blk +
 615                                  BNX2_SBLK_MSIX_ALIGN_SIZE * i);
 616                         bnapi->int_num = i << 24;
 617                 }
 618         }
 619
 620         bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
 621                                   status_blk_size);
 622
 623         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 624
 625         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 626                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
 627                 if (bp->ctx_pages == 0)
 628                         bp->ctx_pages = 1;
 629                 for (i = 0; i < bp->ctx_pages; i++) {
 630                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
 631                                                 BCM_PAGE_SIZE,
 632                                                 &bp->ctx_blk_mapping[i]);
 633                         if (bp->ctx_blk[i] == NULL)
 634                                 goto alloc_mem_err;
 635                 }
 636         }
 637         return 0;
 638
 639 alloc_mem_err:
 640         bnx2_free_mem(bp);
 641         return -ENOMEM;
 642 }
 643
 644 static void
 645 bnx2_report_fw_link(struct bnx2 *bp)
 646 {
 647         u32 fw_link_status = 0;
 648
 649         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
 650                 return;
 651
 652         if (bp->link_up) {
 653                 u32 bmsr;
 654
 655                 switch (bp->line_speed) {
 656                 case SPEED_10:
 657                         if (bp->duplex == DUPLEX_HALF)
 658                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 659                         else
 660                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 661                         break;
 662                 case SPEED_100:
 663                         if (bp->duplex == DUPLEX_HALF)
 664                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 665                         else
 666                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 667                         break;
 668                 case SPEED_1000:
 669                         if (bp->duplex == DUPLEX_HALF)
 670                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 671                         else
 672                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 673                         break;
 674                 case SPEED_2500:
 675                         if (bp->duplex == DUPLEX_HALF)
 676                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 677                         else
 678                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 679                         break;
 680                 }
 681
 682                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 683
 684                 if (bp->autoneg) {
 685                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 686
 687                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 688                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 689
 690                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 691                             bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
 692                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 693                         else
 694                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 695                 }
 696         }
 697         else
 698                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 699
 700         bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
 701 }
 702
 703 static char *
 704 bnx2_xceiver_str(struct bnx2 *bp)
 705 {
 706         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
 707                 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
 708                  "Copper"));
 709 }
 710
 711 static void
 712 bnx2_report_link(struct bnx2 *bp)
 713 {
 714         if (bp->link_up) {
 715                 netif_carrier_on(bp->dev);
 716                 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
 717                        bnx2_xceiver_str(bp));
 718
 719                 printk("%d Mbps ", bp->line_speed);
 720
 721                 if (bp->duplex == DUPLEX_FULL)
 722                         printk("full duplex");
 723                 else
 724                         printk("half duplex");
 725
 726                 if (bp->flow_ctrl) {
 727                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 728                                 printk(", receive ");
 729                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 730                                         printk("& transmit ");
 731                         }
 732                         else {
 733                                 printk(", transmit ");
 734                         }
 735                         printk("flow control ON");
 736                 }
 737                 printk("\n");
 738         }
 739         else {
 740                 netif_carrier_off(bp->dev);
 741                 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
 742                        bnx2_xceiver_str(bp));
 743         }
 744
 745         bnx2_report_fw_link(bp);
 746 }
 747
 748 static void
 749 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 750 {
 751         u32 local_adv, remote_adv;
 752
 753         bp->flow_ctrl = 0;
 754         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 755                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 756
 757                 if (bp->duplex == DUPLEX_FULL) {
 758                         bp->flow_ctrl = bp->req_flow_ctrl;
 759                 }
 760                 return;
 761         }
 762
 763         if (bp->duplex != DUPLEX_FULL) {
 764                 return;
 765         }
 766
 767         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
 768             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
 769                 u32 val;
 770
 771                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 772                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
 773                         bp->flow_ctrl |= FLOW_CTRL_TX;
 774                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
 775                         bp->flow_ctrl |= FLOW_CTRL_RX;
 776                 return;
 777         }
 778
 779         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 780         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 781
 782         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
 783                 u32 new_local_adv = 0;
 784                 u32 new_remote_adv = 0;
 785
 786                 if (local_adv & ADVERTISE_1000XPAUSE)
 787                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 788                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 789                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 790                 if (remote_adv & ADVERTISE_1000XPAUSE)
 791                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 792                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 793                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 794
 795                 local_adv = new_local_adv;
 796                 remote_adv = new_remote_adv;
 797         }
 798
 799         /* See Table 28B-3 of 802.3ab-1999 spec. */
 800         if (local_adv & ADVERTISE_PAUSE_CAP) {
 801                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 802                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 803                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 804                         }
 805                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 806                                 bp->flow_ctrl = FLOW_CTRL_RX;
 807                         }
 808                 }
 809                 else {
 810                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 811                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 812                         }
 813                 }
 814         }
 815         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 816                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 817                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 818
 819                         bp->flow_ctrl = FLOW_CTRL_TX;
 820                 }
 821         }
 822 }
 823
 824 static int
 825 bnx2_5709s_linkup(struct bnx2 *bp)
 826 {
 827         u32 val, speed;
 828
 829         bp->link_up = 1;
 830
 831         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
 832         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
 833         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
 834
 835         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
 836                 bp->line_speed = bp->req_line_speed;
 837                 bp->duplex = bp->req_duplex;
 838                 return 0;
 839         }
 840         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
 841         switch (speed) {
 842                 case MII_BNX2_GP_TOP_AN_SPEED_10:
 843                         bp->line_speed = SPEED_10;
 844                         break;
 845                 case MII_BNX2_GP_TOP_AN_SPEED_100:
 846                         bp->line_speed = SPEED_100;
 847                         break;
 848                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
 849                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
 850                         bp->line_speed = SPEED_1000;
 851                         break;
 852                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
 853                         bp->line_speed = SPEED_2500;
 854                         break;
 855         }
 856         if (val & MII_BNX2_GP_TOP_AN_FD)
 857                 bp->duplex = DUPLEX_FULL;
 858         else
 859                 bp->duplex = DUPLEX_HALF;
 860         return 0;
 861 }
 862
 863 static int
 864 bnx2_5708s_linkup(struct bnx2 *bp)
 865 {
 866         u32 val;
 867
 868         bp->link_up = 1;
 869         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 870         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
 871                 case BCM5708S_1000X_STAT1_SPEED_10:
 872                         bp->line_speed = SPEED_10;
 873                         break;
 874                 case BCM5708S_1000X_STAT1_SPEED_100:
 875                         bp->line_speed = SPEED_100;
 876                         break;
 877                 case BCM5708S_1000X_STAT1_SPEED_1G:
 878                         bp->line_speed = SPEED_1000;
 879                         break;
 880                 case BCM5708S_1000X_STAT1_SPEED_2G5:
 881                         bp->line_speed = SPEED_2500;
 882                         break;
 883         }
 884         if (val & BCM5708S_1000X_STAT1_FD)
 885                 bp->duplex = DUPLEX_FULL;
 886         else
 887                 bp->duplex = DUPLEX_HALF;
 888
 889         return 0;
 890 }
 891
 892 static int
 893 bnx2_5706s_linkup(struct bnx2 *bp)
 894 {
 895         u32 bmcr, local_adv, remote_adv, common;
 896
 897         bp->link_up = 1;
 898         bp->line_speed = SPEED_1000;
 899
 900         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
 901         if (bmcr & BMCR_FULLDPLX) {
 902                 bp->duplex = DUPLEX_FULL;
 903         }
 904         else {
 905                 bp->duplex = DUPLEX_HALF;
 906         }
 907
 908         if (!(bmcr & BMCR_ANENABLE)) {
 909                 return 0;
 910         }
 911
 912         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 913         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 914
 915         common = local_adv & remote_adv;
 916         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
 917
 918                 if (common & ADVERTISE_1000XFULL) {
 919                         bp->duplex = DUPLEX_FULL;
 920                 }
 921                 else {
 922                         bp->duplex = DUPLEX_HALF;
 923                 }
 924         }
 925
 926         return 0;
 927 }
 928
 929 static int
 930 bnx2_copper_linkup(struct bnx2 *bp)
 931 {
 932         u32 bmcr;
 933
 934         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
 935         if (bmcr & BMCR_ANENABLE) {
 936                 u32 local_adv, remote_adv, common;
 937
 938                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
 939                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
 940
 941                 common = local_adv & (remote_adv >> 2);
 942                 if (common & ADVERTISE_1000FULL) {
 943                         bp->line_speed = SPEED_1000;
 944                         bp->duplex = DUPLEX_FULL;
 945                 }
 946                 else if (common & ADVERTISE_1000HALF) {
 947                         bp->line_speed = SPEED_1000;
 948                         bp->duplex = DUPLEX_HALF;
 949                 }
 950                 else {
 951                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 952                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 953
 954                         common = local_adv & remote_adv;
 955                         if (common & ADVERTISE_100FULL) {
 956                                 bp->line_speed = SPEED_100;
 957                                 bp->duplex = DUPLEX_FULL;
 958                         }
 959                         else if (common & ADVERTISE_100HALF) {
 960                                 bp->line_speed = SPEED_100;
 961                                 bp->duplex = DUPLEX_HALF;
 962                         }
 963                         else if (common & ADVERTISE_10FULL) {
 964                                 bp->line_speed = SPEED_10;
 965                                 bp->duplex = DUPLEX_FULL;
 966                         }
 967                         else if (common & ADVERTISE_10HALF) {
 968                                 bp->line_speed = SPEED_10;
 969                                 bp->duplex = DUPLEX_HALF;
 970                         }
 971                         else {
 972                                 bp->line_speed = 0;
 973                                 bp->link_up = 0;
 974                         }
 975                 }
 976         }
 977         else {
 978                 if (bmcr & BMCR_SPEED100) {
 979                         bp->line_speed = SPEED_100;
 980                 }
 981                 else {
 982                         bp->line_speed = SPEED_10;
 983                 }
 984                 if (bmcr & BMCR_FULLDPLX) {
 985                         bp->duplex = DUPLEX_FULL;
 986                 }
 987                 else {
 988                         bp->duplex = DUPLEX_HALF;
 989                 }
 990         }
 991
 992         return 0;
 993 }
 994
 995 static void
 996 bnx2_init_rx_context0(struct bnx2 *bp)
 997 {
 998         u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
 999
1000         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1001         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1002         val |= 0x02 << 8;
1003
1004         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1005                 u32 lo_water, hi_water;
1006
1007                 if (bp->flow_ctrl & FLOW_CTRL_TX)
1008                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1009                 else
1010                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1011                 if (lo_water >= bp->rx_ring_size)
1012                         lo_water = 0;
1013
1014                 hi_water = bp->rx_ring_size / 4;
1015
1016                 if (hi_water <= lo_water)
1017                         lo_water = 0;
1018
1019                 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1020                 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1021
1022                 if (hi_water > 0xf)
1023                         hi_water = 0xf;
1024                 else if (hi_water == 0)
1025                         lo_water = 0;
1026                 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1027         }
1028         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1029 }
1030
1031 static int
1032 bnx2_set_mac_link(struct bnx2 *bp)
1033 {
1034         u32 val;
1035
1036         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1037         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1038                 (bp->duplex == DUPLEX_HALF)) {
1039                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1040         }
1041
1042         /* Configure the EMAC mode register. */
1043         val = REG_RD(bp, BNX2_EMAC_MODE);
1044
1045         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1046                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1047                 BNX2_EMAC_MODE_25G_MODE);
1048
1049         if (bp->link_up) {
1050                 switch (bp->line_speed) {
1051                         case SPEED_10:
1052                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1053                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
1054                                         break;
1055                                 }
1056                                 /* fall through */
1057                         case SPEED_100:
1058                                 val |= BNX2_EMAC_MODE_PORT_MII;
1059                                 break;
1060                         case SPEED_2500:
1061                                 val |= BNX2_EMAC_MODE_25G_MODE;
1062                                 /* fall through */
1063                         case SPEED_1000:
1064                                 val |= BNX2_EMAC_MODE_PORT_GMII;
1065                                 break;
1066                 }
1067         }
1068         else {
1069                 val |= BNX2_EMAC_MODE_PORT_GMII;
1070         }
1071
1072         /* Set the MAC to operate in the appropriate duplex mode. */
1073         if (bp->duplex == DUPLEX_HALF)
1074                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1075         REG_WR(bp, BNX2_EMAC_MODE, val);
1076
1077         /* Enable/disable rx PAUSE. */
1078         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1079
1080         if (bp->flow_ctrl & FLOW_CTRL_RX)
1081                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1082         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1083
1084         /* Enable/disable tx PAUSE. */
1085         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1086         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1087
1088         if (bp->flow_ctrl & FLOW_CTRL_TX)
1089                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1090         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1091
1092         /* Acknowledge the interrupt. */
1093         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1094
1095         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1096                 bnx2_init_rx_context0(bp);
1097
1098         return 0;
1099 }
1100
1101 static void
1102 bnx2_enable_bmsr1(struct bnx2 *bp)
1103 {
1104         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1105             (CHIP_NUM(bp) == CHIP_NUM_5709))
1106                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1107                                MII_BNX2_BLK_ADDR_GP_STATUS);
1108 }
1109
1110 static void
1111 bnx2_disable_bmsr1(struct bnx2 *bp)
1112 {
1113         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1114             (CHIP_NUM(bp) == CHIP_NUM_5709))
1115                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1116                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1117 }
1118
1119 static int
1120 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1121 {
1122         u32 up1;
1123         int ret = 1;
1124
1125         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1126                 return 0;
1127
1128         if (bp->autoneg & AUTONEG_SPEED)
1129                 bp->advertising |= ADVERTISED_2500baseX_Full;
1130
1131         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1132                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1133
1134         bnx2_read_phy(bp, bp->mii_up1, &up1);
1135         if (!(up1 & BCM5708S_UP1_2G5)) {
1136                 up1 |= BCM5708S_UP1_2G5;
1137                 bnx2_write_phy(bp, bp->mii_up1, up1);
1138                 ret = 0;
1139         }
1140
1141         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1142                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1143                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1144
1145         return ret;
1146 }
1147
1148 static int
1149 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1150 {
1151         u32 up1;
1152         int ret = 0;
1153
1154         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1155                 return 0;
1156
1157         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1158                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1159
1160         bnx2_read_phy(bp, bp->mii_up1, &up1);
1161         if (up1 & BCM5708S_UP1_2G5) {
1162                 up1 &= ~BCM5708S_UP1_2G5;
1163                 bnx2_write_phy(bp, bp->mii_up1, up1);
1164                 ret = 1;
1165         }
1166
1167         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1168                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1169                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1170
1171         return ret;
1172 }
1173
1174 static void
1175 bnx2_enable_forced_2g5(struct bnx2 *bp)
1176 {
1177         u32 bmcr;
1178
1179         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1180                 return;
1181
1182         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1183                 u32 val;
1184
1185                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1186                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1187                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1188                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1189                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1190                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1191
1192                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1193                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1194                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1195
1196         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1197                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1198                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1199         }
1200
1201         if (bp->autoneg & AUTONEG_SPEED) {
1202                 bmcr &= ~BMCR_ANENABLE;
1203                 if (bp->req_duplex == DUPLEX_FULL)
1204                         bmcr |= BMCR_FULLDPLX;
1205         }
1206         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1207 }
1208
1209 static void
1210 bnx2_disable_forced_2g5(struct bnx2 *bp)
1211 {
1212         u32 bmcr;
1213
1214         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1215                 return;
1216
1217         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1218                 u32 val;
1219
1220                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1221                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1222                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1223                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1224                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1225
1226                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1227                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1228                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1229
1230         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1231                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1232                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1233         }
1234
1235         if (bp->autoneg & AUTONEG_SPEED)
1236                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1237         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1238 }
1239
1240 static void
1241 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1242 {
1243         u32 val;
1244
1245         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1246         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1247         if (start)
1248                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1249         else
1250                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1251 }
1252
1253 static int
1254 bnx2_set_link(struct bnx2 *bp)
1255 {
1256         u32 bmsr;
1257         u8 link_up;
1258
1259         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1260                 bp->link_up = 1;
1261                 return 0;
1262         }
1263
1264         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1265                 return 0;
1266
1267         link_up = bp->link_up;
1268
1269         bnx2_enable_bmsr1(bp);
1270         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1271         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1272         bnx2_disable_bmsr1(bp);
1273
1274         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1275             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1276                 u32 val, an_dbg;
1277
1278                 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1279                         bnx2_5706s_force_link_dn(bp, 0);
1280                         bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1281                 }
1282                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1283
1284                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1285                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1286                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1287
1288                 if ((val & BNX2_EMAC_STATUS_LINK) &&
1289                     !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1290                         bmsr |= BMSR_LSTATUS;
1291                 else
1292                         bmsr &= ~BMSR_LSTATUS;
1293         }
1294
1295         if (bmsr & BMSR_LSTATUS) {
1296                 bp->link_up = 1;
1297
1298                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1299                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1300                                 bnx2_5706s_linkup(bp);
1301                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1302                                 bnx2_5708s_linkup(bp);
1303                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1304                                 bnx2_5709s_linkup(bp);
1305                 }
1306                 else {
1307                         bnx2_copper_linkup(bp);
1308                 }
1309                 bnx2_resolve_flow_ctrl(bp);
1310         }
1311         else {
1312                 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1313                     (bp->autoneg & AUTONEG_SPEED))
1314                         bnx2_disable_forced_2g5(bp);
1315
1316                 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1317                         u32 bmcr;
1318
1319                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1320                         bmcr |= BMCR_ANENABLE;
1321                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1322
1323                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1324                 }
1325                 bp->link_up = 0;
1326         }
1327
1328         if (bp->link_up != link_up) {
1329                 bnx2_report_link(bp);
1330         }
1331
1332         bnx2_set_mac_link(bp);
1333
1334         return 0;
1335 }
1336
1337 static int
1338 bnx2_reset_phy(struct bnx2 *bp)
1339 {
1340         int i;
1341         u32 reg;
1342
1343         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1344
1345 #define PHY_RESET_MAX_WAIT 100
1346         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1347                 udelay(10);
1348
1349                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1350                 if (!(reg & BMCR_RESET)) {
1351                         udelay(20);
1352                         break;
1353                 }
1354         }
1355         if (i == PHY_RESET_MAX_WAIT) {
1356                 return -EBUSY;
1357         }
1358         return 0;
1359 }
1360
1361 static u32
1362 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1363 {
1364         u32 adv = 0;
1365
1366         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1367                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1368
1369                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1370                         adv = ADVERTISE_1000XPAUSE;
1371                 }
1372                 else {
1373                         adv = ADVERTISE_PAUSE_CAP;
1374                 }
1375         }
1376         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1377                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1378                         adv = ADVERTISE_1000XPSE_ASYM;
1379                 }
1380                 else {
1381                         adv = ADVERTISE_PAUSE_ASYM;
1382                 }
1383         }
1384         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1385                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1386                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1387                 }
1388                 else {
1389                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1390                 }
1391         }
1392         return adv;
1393 }
1394
1395 static int bnx2_fw_sync(struct bnx2 *, u32, int);
1396
1397 static int
1398 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1399 {
1400         u32 speed_arg = 0, pause_adv;
1401
1402         pause_adv = bnx2_phy_get_pause_adv(bp);
1403
1404         if (bp->autoneg & AUTONEG_SPEED) {
1405                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1406                 if (bp->advertising & ADVERTISED_10baseT_Half)
1407                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1408                 if (bp->advertising & ADVERTISED_10baseT_Full)
1409                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1410                 if (bp->advertising & ADVERTISED_100baseT_Half)
1411                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1412                 if (bp->advertising & ADVERTISED_100baseT_Full)
1413                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1414                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1415                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1416                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1417                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1418         } else {
1419                 if (bp->req_line_speed == SPEED_2500)
1420                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1421                 else if (bp->req_line_speed == SPEED_1000)
1422                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1423                 else if (bp->req_line_speed == SPEED_100) {
1424                         if (bp->req_duplex == DUPLEX_FULL)
1425                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1426                         else
1427                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1428                 } else if (bp->req_line_speed == SPEED_10) {
1429                         if (bp->req_duplex == DUPLEX_FULL)
1430                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1431                         else
1432                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1433                 }
1434         }
1435
1436         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1437                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1438         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1439                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1440
1441         if (port == PORT_TP)
1442                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1443                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1444
1445         bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1446
1447         spin_unlock_bh(&bp->phy_lock);
1448         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1449         spin_lock_bh(&bp->phy_lock);
1450
1451         return 0;
1452 }
1453
1454 static int
1455 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1456 {
1457         u32 adv, bmcr;
1458         u32 new_adv = 0;
1459
1460         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1461                 return (bnx2_setup_remote_phy(bp, port));
1462
1463         if (!(bp->autoneg & AUTONEG_SPEED)) {
1464                 u32 new_bmcr;
1465                 int force_link_down = 0;
1466
1467                 if (bp->req_line_speed == SPEED_2500) {
1468                         if (!bnx2_test_and_enable_2g5(bp))
1469                                 force_link_down = 1;
1470                 } else if (bp->req_line_speed == SPEED_1000) {
1471                         if (bnx2_test_and_disable_2g5(bp))
1472                                 force_link_down = 1;
1473                 }
1474                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1475                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1476
1477                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1478                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1479                 new_bmcr |= BMCR_SPEED1000;
1480
1481                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1482                         if (bp->req_line_speed == SPEED_2500)
1483                                 bnx2_enable_forced_2g5(bp);
1484                         else if (bp->req_line_speed == SPEED_1000) {
1485                                 bnx2_disable_forced_2g5(bp);
1486                                 new_bmcr &= ~0x2000;
1487                         }
1488
1489                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1490                         if (bp->req_line_speed == SPEED_2500)
1491                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1492                         else
1493                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1494                 }
1495
1496                 if (bp->req_duplex == DUPLEX_FULL) {
1497                         adv |= ADVERTISE_1000XFULL;
1498                         new_bmcr |= BMCR_FULLDPLX;
1499                 }
1500                 else {
1501                         adv |= ADVERTISE_1000XHALF;
1502                         new_bmcr &= ~BMCR_FULLDPLX;
1503                 }
1504                 if ((new_bmcr != bmcr) || (force_link_down)) {
1505                         /* Force a link down visible on the other side */
1506                         if (bp->link_up) {
1507                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1508                                                ~(ADVERTISE_1000XFULL |
1509                                                  ADVERTISE_1000XHALF));
1510                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1511                                         BMCR_ANRESTART | BMCR_ANENABLE);
1512
1513                                 bp->link_up = 0;
1514                                 netif_carrier_off(bp->dev);
1515                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1516                                 bnx2_report_link(bp);
1517                         }
1518                         bnx2_write_phy(bp, bp->mii_adv, adv);
1519                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1520                 } else {
1521                         bnx2_resolve_flow_ctrl(bp);
1522                         bnx2_set_mac_link(bp);
1523                 }
1524                 return 0;
1525         }
1526
1527         bnx2_test_and_enable_2g5(bp);
1528
1529         if (bp->advertising & ADVERTISED_1000baseT_Full)
1530                 new_adv |= ADVERTISE_1000XFULL;
1531
1532         new_adv |= bnx2_phy_get_pause_adv(bp);
1533
1534         bnx2_read_phy(bp, bp->mii_adv, &adv);
1535         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1536
1537         bp->serdes_an_pending = 0;
1538         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1539                 /* Force a link down visible on the other side */
1540                 if (bp->link_up) {
1541                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1542                         spin_unlock_bh(&bp->phy_lock);
1543                         msleep(20);
1544                         spin_lock_bh(&bp->phy_lock);
1545                 }
1546
1547                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1548                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1549                         BMCR_ANENABLE);
1550                 /* Speed up link-up time when the link partner
1551                  * does not autonegotiate which is very common
1552                  * in blade servers. Some blade servers use
1553                  * IPMI for kerboard input and it's important
1554                  * to minimize link disruptions. Autoneg. involves
1555                  * exchanging base pages plus 3 next pages and
1556                  * normally completes in about 120 msec.
1557                  */
1558                 bp->current_interval = SERDES_AN_TIMEOUT;
1559                 bp->serdes_an_pending = 1;
1560                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1561         } else {
1562                 bnx2_resolve_flow_ctrl(bp);
1563                 bnx2_set_mac_link(bp);
1564         }
1565
1566         return 0;
1567 }
1568
1569 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1570         (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?                  \
1571                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1572                 (ADVERTISED_1000baseT_Full)
1573
1574 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1575         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1576         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1577         ADVERTISED_1000baseT_Full)
1578
1579 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1580         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1581
1582 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1583
1584 static void
1585 bnx2_set_default_remote_link(struct bnx2 *bp)
1586 {
1587         u32 link;
1588
1589         if (bp->phy_port == PORT_TP)
1590                 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1591         else
1592                 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1593
1594         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1595                 bp->req_line_speed = 0;
1596                 bp->autoneg |= AUTONEG_SPEED;
1597                 bp->advertising = ADVERTISED_Autoneg;
1598                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1599                         bp->advertising |= ADVERTISED_10baseT_Half;
1600                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1601                         bp->advertising |= ADVERTISED_10baseT_Full;
1602                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1603                         bp->advertising |= ADVERTISED_100baseT_Half;
1604                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1605                         bp->advertising |= ADVERTISED_100baseT_Full;
1606                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1607                         bp->advertising |= ADVERTISED_1000baseT_Full;
1608                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1609                         bp->advertising |= ADVERTISED_2500baseX_Full;
1610         } else {
1611                 bp->autoneg = 0;
1612                 bp->advertising = 0;
1613                 bp->req_duplex = DUPLEX_FULL;
1614                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1615                         bp->req_line_speed = SPEED_10;
1616                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1617                                 bp->req_duplex = DUPLEX_HALF;
1618                 }
1619                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1620                         bp->req_line_speed = SPEED_100;
1621                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1622                                 bp->req_duplex = DUPLEX_HALF;
1623                 }
1624                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1625                         bp->req_line_speed = SPEED_1000;
1626                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1627                         bp->req_line_speed = SPEED_2500;
1628         }
1629 }
1630
1631 static void
1632 bnx2_set_default_link(struct bnx2 *bp)
1633 {
1634         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1635                 return bnx2_set_default_remote_link(bp);
1636
1637         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1638         bp->req_line_speed = 0;
1639         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1640                 u32 reg;
1641
1642                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1643
1644                 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1645                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1646                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1647                         bp->autoneg = 0;
1648                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1649                         bp->req_duplex = DUPLEX_FULL;
1650                 }
1651         } else
1652                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1653 }
1654
1655 static void
1656 bnx2_send_heart_beat(struct bnx2 *bp)
1657 {
1658         u32 msg;
1659         u32 addr;
1660
1661         spin_lock(&bp->indirect_lock);
1662         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1663         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1664         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1665         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1666         spin_unlock(&bp->indirect_lock);
1667 }
1668
1669 static void
1670 bnx2_remote_phy_event(struct bnx2 *bp)
1671 {
1672         u32 msg;
1673         u8 link_up = bp->link_up;
1674         u8 old_port;
1675
1676         msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1677
1678         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1679                 bnx2_send_heart_beat(bp);
1680
1681         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1682
1683         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1684                 bp->link_up = 0;
1685         else {
1686                 u32 speed;
1687
1688                 bp->link_up = 1;
1689                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1690                 bp->duplex = DUPLEX_FULL;
1691                 switch (speed) {
1692                         case BNX2_LINK_STATUS_10HALF:
1693                                 bp->duplex = DUPLEX_HALF;
1694                         case BNX2_LINK_STATUS_10FULL:
1695                                 bp->line_speed = SPEED_10;
1696                                 break;
1697                         case BNX2_LINK_STATUS_100HALF:
1698                                 bp->duplex = DUPLEX_HALF;
1699                         case BNX2_LINK_STATUS_100BASE_T4:
1700                         case BNX2_LINK_STATUS_100FULL:
1701                                 bp->line_speed = SPEED_100;
1702                                 break;
1703                         case BNX2_LINK_STATUS_1000HALF:
1704                                 bp->duplex = DUPLEX_HALF;
1705                         case BNX2_LINK_STATUS_1000FULL:
1706                                 bp->line_speed = SPEED_1000;
1707                                 break;
1708                         case BNX2_LINK_STATUS_2500HALF:
1709                                 bp->duplex = DUPLEX_HALF;
1710                         case BNX2_LINK_STATUS_2500FULL:
1711                                 bp->line_speed = SPEED_2500;
1712                                 break;
1713                         default:
1714                                 bp->line_speed = 0;
1715                                 break;
1716                 }
1717
1718                 spin_lock(&bp->phy_lock);
1719                 bp->flow_ctrl = 0;
1720                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1721                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1722                         if (bp->duplex == DUPLEX_FULL)
1723                                 bp->flow_ctrl = bp->req_flow_ctrl;
1724                 } else {
1725                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1726                                 bp->flow_ctrl |= FLOW_CTRL_TX;
1727                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1728                                 bp->flow_ctrl |= FLOW_CTRL_RX;
1729                 }
1730
1731                 old_port = bp->phy_port;
1732                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1733                         bp->phy_port = PORT_FIBRE;
1734                 else
1735                         bp->phy_port = PORT_TP;
1736
1737                 if (old_port != bp->phy_port)
1738                         bnx2_set_default_link(bp);
1739
1740                 spin_unlock(&bp->phy_lock);
1741         }
1742         if (bp->link_up != link_up)
1743                 bnx2_report_link(bp);
1744
1745         bnx2_set_mac_link(bp);
1746 }
1747
1748 static int
1749 bnx2_set_remote_link(struct bnx2 *bp)
1750 {
1751         u32 evt_code;
1752
1753         evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1754         switch (evt_code) {
1755                 case BNX2_FW_EVT_CODE_LINK_EVENT:
1756                         bnx2_remote_phy_event(bp);
1757                         break;
1758                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1759                 default:
1760                         bnx2_send_heart_beat(bp);
1761                         break;
1762         }
1763         return 0;
1764 }
1765
1766 static int
1767 bnx2_setup_copper_phy(struct bnx2 *bp)
1768 {
1769         u32 bmcr;
1770         u32 new_bmcr;
1771
1772         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1773
1774         if (bp->autoneg & AUTONEG_SPEED) {
1775                 u32 adv_reg, adv1000_reg;
1776                 u32 new_adv_reg = 0;
1777                 u32 new_adv1000_reg = 0;
1778
1779                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1780                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1781                         ADVERTISE_PAUSE_ASYM);
1782
1783                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1784                 adv1000_reg &= PHY_ALL_1000_SPEED;
1785
1786                 if (bp->advertising & ADVERTISED_10baseT_Half)
1787                         new_adv_reg |= ADVERTISE_10HALF;
1788                 if (bp->advertising & ADVERTISED_10baseT_Full)
1789                         new_adv_reg |= ADVERTISE_10FULL;
1790                 if (bp->advertising & ADVERTISED_100baseT_Half)
1791                         new_adv_reg |= ADVERTISE_100HALF;
1792                 if (bp->advertising & ADVERTISED_100baseT_Full)
1793                         new_adv_reg |= ADVERTISE_100FULL;
1794                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1795                         new_adv1000_reg |= ADVERTISE_1000FULL;
1796
1797                 new_adv_reg |= ADVERTISE_CSMA;
1798
1799                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1800
1801                 if ((adv1000_reg != new_adv1000_reg) ||
1802                         (adv_reg != new_adv_reg) ||
1803                         ((bmcr & BMCR_ANENABLE) == 0)) {
1804
1805                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1806                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1807                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1808                                 BMCR_ANENABLE);
1809                 }
1810                 else if (bp->link_up) {
1811                         /* Flow ctrl may have changed from auto to forced */
1812                         /* or vice-versa. */
1813
1814                         bnx2_resolve_flow_ctrl(bp);
1815                         bnx2_set_mac_link(bp);
1816                 }
1817                 return 0;
1818         }
1819
1820         new_bmcr = 0;
1821         if (bp->req_line_speed == SPEED_100) {
1822                 new_bmcr |= BMCR_SPEED100;
1823         }
1824         if (bp->req_duplex == DUPLEX_FULL) {
1825                 new_bmcr |= BMCR_FULLDPLX;
1826         }
1827         if (new_bmcr != bmcr) {
1828                 u32 bmsr;
1829
1830                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1831                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1832
1833                 if (bmsr & BMSR_LSTATUS) {
1834                         /* Force link down */
1835                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1836                         spin_unlock_bh(&bp->phy_lock);
1837                         msleep(50);
1838                         spin_lock_bh(&bp->phy_lock);
1839
1840                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1841                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1842                 }
1843
1844                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1845
1846                 /* Normally, the new speed is setup after the link has
1847                  * gone down and up again. In some cases, link will not go
1848                  * down so we need to set up the new speed here.
1849                  */
1850                 if (bmsr & BMSR_LSTATUS) {
1851                         bp->line_speed = bp->req_line_speed;
1852                         bp->duplex = bp->req_duplex;
1853                         bnx2_resolve_flow_ctrl(bp);
1854                         bnx2_set_mac_link(bp);
1855                 }
1856         } else {
1857                 bnx2_resolve_flow_ctrl(bp);
1858                 bnx2_set_mac_link(bp);
1859         }
1860         return 0;
1861 }
1862
1863 static int
1864 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1865 {
1866         if (bp->loopback == MAC_LOOPBACK)
1867                 return 0;
1868
1869         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1870                 return (bnx2_setup_serdes_phy(bp, port));
1871         }
1872         else {
1873                 return (bnx2_setup_copper_phy(bp));
1874         }
1875 }
1876
1877 static int
1878 bnx2_init_5709s_phy(struct bnx2 *bp)
1879 {
1880         u32 val;
1881
1882         bp->mii_bmcr = MII_BMCR + 0x10;
1883         bp->mii_bmsr = MII_BMSR + 0x10;
1884         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1885         bp->mii_adv = MII_ADVERTISE + 0x10;
1886         bp->mii_lpa = MII_LPA + 0x10;
1887         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1888
1889         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1890         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1891
1892         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1893         bnx2_reset_phy(bp);
1894
1895         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1896
1897         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1898         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1899         val |= MII_BNX2_SD_1000XCTL1_FIBER;
1900         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1901
1902         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1903         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1904         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
1905                 val |= BCM5708S_UP1_2G5;
1906         else
1907                 val &= ~BCM5708S_UP1_2G5;
1908         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1909
1910         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1911         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1912         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1913         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1914
1915         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1916
1917         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1918               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1919         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1920
1921         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1922
1923         return 0;
1924 }
1925
1926 static int
1927 bnx2_init_5708s_phy(struct bnx2 *bp)
1928 {
1929         u32 val;
1930
1931         bnx2_reset_phy(bp);
1932
1933         bp->mii_up1 = BCM5708S_UP1;
1934
1935         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1936         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1937         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1938
1939         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1940         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1941         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1942
1943         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1944         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1945         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1946
1947         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
1948                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1949                 val |= BCM5708S_UP1_2G5;
1950                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1951         }
1952
1953         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1954             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1955             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1956                 /* increase tx signal amplitude */
1957                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1958                                BCM5708S_BLK_ADDR_TX_MISC);
1959                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1960                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1961                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1962                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1963         }
1964
1965         val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
1966               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1967
1968         if (val) {
1969                 u32 is_backplane;
1970
1971                 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
1972                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1973                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1974                                        BCM5708S_BLK_ADDR_TX_MISC);
1975                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1976                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1977                                        BCM5708S_BLK_ADDR_DIG);
1978                 }
1979         }
1980         return 0;
1981 }
1982
1983 static int
1984 bnx2_init_5706s_phy(struct bnx2 *bp)
1985 {
1986         bnx2_reset_phy(bp);
1987
1988         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1989
1990         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1991                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1992
1993         if (bp->dev->mtu > 1500) {
1994                 u32 val;
1995
1996                 /* Set extended packet length bit */
1997                 bnx2_write_phy(bp, 0x18, 0x7);
1998                 bnx2_read_phy(bp, 0x18, &val);
1999                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2000
2001                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2002                 bnx2_read_phy(bp, 0x1c, &val);
2003                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2004         }
2005         else {
2006                 u32 val;
2007
2008                 bnx2_write_phy(bp, 0x18, 0x7);
2009                 bnx2_read_phy(bp, 0x18, &val);
2010                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2011
2012                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2013                 bnx2_read_phy(bp, 0x1c, &val);
2014                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2015         }
2016
2017         return 0;
2018 }
2019
2020 static int
2021 bnx2_init_copper_phy(struct bnx2 *bp)
2022 {
2023         u32 val;
2024
2025         bnx2_reset_phy(bp);
2026
2027         if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2028                 bnx2_write_phy(bp, 0x18, 0x0c00);
2029                 bnx2_write_phy(bp, 0x17, 0x000a);
2030                 bnx2_write_phy(bp, 0x15, 0x310b);
2031                 bnx2_write_phy(bp, 0x17, 0x201f);
2032                 bnx2_write_phy(bp, 0x15, 0x9506);
2033                 bnx2_write_phy(bp, 0x17, 0x401f);
2034                 bnx2_write_phy(bp, 0x15, 0x14e2);
2035                 bnx2_write_phy(bp, 0x18, 0x0400);
2036         }
2037
2038         if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2039                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2040                                MII_BNX2_DSP_EXPAND_REG | 0x8);
2041                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2042                 val &= ~(1 << 8);
2043                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2044         }
2045
2046         if (bp->dev->mtu > 1500) {
2047                 /* Set extended packet length bit */
2048                 bnx2_write_phy(bp, 0x18, 0x7);
2049                 bnx2_read_phy(bp, 0x18, &val);
2050                 bnx2_write_phy(bp, 0x18, val | 0x4000);
2051
2052                 bnx2_read_phy(bp, 0x10, &val);
2053                 bnx2_write_phy(bp, 0x10, val | 0x1);
2054         }
2055         else {
2056                 bnx2_write_phy(bp, 0x18, 0x7);
2057                 bnx2_read_phy(bp, 0x18, &val);
2058                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2059
2060                 bnx2_read_phy(bp, 0x10, &val);
2061                 bnx2_write_phy(bp, 0x10, val & ~0x1);
2062         }
2063
2064         /* ethernet@wirespeed */
2065         bnx2_write_phy(bp, 0x18, 0x7007);
2066         bnx2_read_phy(bp, 0x18, &val);
2067         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2068         return 0;
2069 }
2070
2071
2072 static int
2073 bnx2_init_phy(struct bnx2 *bp)
2074 {
2075         u32 val;
2076         int rc = 0;
2077
2078         bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2079         bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2080
2081         bp->mii_bmcr = MII_BMCR;
2082         bp->mii_bmsr = MII_BMSR;
2083         bp->mii_bmsr1 = MII_BMSR;
2084         bp->mii_adv = MII_ADVERTISE;
2085         bp->mii_lpa = MII_LPA;
2086
2087         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2088
2089         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2090                 goto setup_phy;
2091
2092         bnx2_read_phy(bp, MII_PHYSID1, &val);
2093         bp->phy_id = val << 16;
2094         bnx2_read_phy(bp, MII_PHYSID2, &val);
2095         bp->phy_id |= val & 0xffff;
2096
2097         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2098                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2099                         rc = bnx2_init_5706s_phy(bp);
2100                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2101                         rc = bnx2_init_5708s_phy(bp);
2102                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2103                         rc = bnx2_init_5709s_phy(bp);
2104         }
2105         else {
2106                 rc = bnx2_init_copper_phy(bp);
2107         }
2108
2109 setup_phy:
2110         if (!rc)
2111                 rc = bnx2_setup_phy(bp, bp->phy_port);
2112
2113         return rc;
2114 }
2115
2116 static int
2117 bnx2_set_mac_loopback(struct bnx2 *bp)
2118 {
2119         u32 mac_mode;
2120
2121         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2122         mac_mode &= ~BNX2_EMAC_MODE_PORT;
2123         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2124         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2125         bp->link_up = 1;
2126         return 0;
2127 }
2128
2129 static int bnx2_test_link(struct bnx2 *);
2130
2131 static int
2132 bnx2_set_phy_loopback(struct bnx2 *bp)
2133 {
2134         u32 mac_mode;
2135         int rc, i;
2136
2137         spin_lock_bh(&bp->phy_lock);
2138         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2139                             BMCR_SPEED1000);
2140         spin_unlock_bh(&bp->phy_lock);
2141         if (rc)
2142                 return rc;
2143
2144         for (i = 0; i < 10; i++) {
2145                 if (bnx2_test_link(bp) == 0)
2146                         break;
2147                 msleep(100);
2148         }
2149
2150         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2151         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2152                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2153                       BNX2_EMAC_MODE_25G_MODE);
2154
2155         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2156         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2157         bp->link_up = 1;
2158         return 0;
2159 }
2160
2161 static int
2162 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
2163 {
2164         int i;
2165         u32 val;
2166
2167         bp->fw_wr_seq++;
2168         msg_data |= bp->fw_wr_seq;
2169
2170         bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2171
2172         /* wait for an acknowledgement. */
2173         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2174                 msleep(10);
2175
2176                 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2177
2178                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2179                         break;
2180         }
2181         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2182                 return 0;
2183
2184         /* If we timed out, inform the firmware that this is the case. */
2185         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2186                 if (!silent)
2187                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
2188                                             "%x\n", msg_data);
2189
2190                 msg_data &= ~BNX2_DRV_MSG_CODE;
2191                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2192
2193                 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2194
2195                 return -EBUSY;
2196         }
2197
2198         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2199                 return -EIO;
2200
2201         return 0;
2202 }
2203
2204 static int
2205 bnx2_init_5709_context(struct bnx2 *bp)
2206 {
2207         int i, ret = 0;
2208         u32 val;
2209
2210         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2211         val |= (BCM_PAGE_BITS - 8) << 16;
2212         REG_WR(bp, BNX2_CTX_COMMAND, val);
2213         for (i = 0; i < 10; i++) {
2214                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2215                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2216                         break;
2217                 udelay(2);
2218         }
2219         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2220                 return -EBUSY;
2221
2222         for (i = 0; i < bp->ctx_pages; i++) {
2223                 int j;
2224
2225                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2226                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2227                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2228                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2229                        (u64) bp->ctx_blk_mapping[i] >> 32);
2230                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2231                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2232                 for (j = 0; j < 10; j++) {
2233
2234                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2235                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2236                                 break;
2237                         udelay(5);
2238                 }
2239                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2240                         ret = -EBUSY;
2241                         break;
2242                 }
2243         }
2244         return ret;
2245 }
2246
2247 static void
2248 bnx2_init_context(struct bnx2 *bp)
2249 {
2250         u32 vcid;
2251
2252         vcid = 96;
2253         while (vcid) {
2254                 u32 vcid_addr, pcid_addr, offset;
2255                 int i;
2256
2257                 vcid--;
2258
2259                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2260                         u32 new_vcid;
2261
2262                         vcid_addr = GET_PCID_ADDR(vcid);
2263                         if (vcid & 0x8) {
2264                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2265                         }
2266                         else {
2267                                 new_vcid = vcid;
2268                         }
2269                         pcid_addr = GET_PCID_ADDR(new_vcid);
2270                 }
2271                 else {
2272                         vcid_addr = GET_CID_ADDR(vcid);
2273                         pcid_addr = vcid_addr;
2274                 }
2275
2276                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2277                         vcid_addr += (i << PHY_CTX_SHIFT);
2278                         pcid_addr += (i << PHY_CTX_SHIFT);
2279
2280                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2281                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2282
2283                         /* Zero out the context. */
2284                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2285                                 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2286                 }
2287         }
2288 }
2289
2290 static int
2291 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2292 {
2293         u16 *good_mbuf;
2294         u32 good_mbuf_cnt;
2295         u32 val;
2296
2297         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2298         if (good_mbuf == NULL) {
2299                 printk(KERN_ERR PFX "Failed to allocate memory in "
2300                                     "bnx2_alloc_bad_rbuf\n");
2301                 return -ENOMEM;
2302         }
2303
2304         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2305                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2306
2307         good_mbuf_cnt = 0;
2308
2309         /* Allocate a bunch of mbufs and save the good ones in an array. */
2310         val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2311         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2312                 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2313                                 BNX2_RBUF_COMMAND_ALLOC_REQ);
2314
2315                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2316
2317                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2318
2319                 /* The addresses with Bit 9 set are bad memory blocks. */
2320                 if (!(val & (1 << 9))) {
2321                         good_mbuf[good_mbuf_cnt] = (u16) val;
2322                         good_mbuf_cnt++;
2323                 }
2324
2325                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2326         }
2327
2328         /* Free the good ones back to the mbuf pool thus discarding
2329          * all the bad ones. */
2330         while (good_mbuf_cnt) {
2331                 good_mbuf_cnt--;
2332
2333                 val = good_mbuf[good_mbuf_cnt];
2334                 val = (val << 9) | val | 1;
2335
2336                 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2337         }
2338         kfree(good_mbuf);
2339         return 0;
2340 }
2341
2342 static void
2343 bnx2_set_mac_addr(struct bnx2 *bp)
2344 {
2345         u32 val;
2346         u8 *mac_addr = bp->dev->dev_addr;
2347
2348         val = (mac_addr[0] << 8) | mac_addr[1];
2349
2350         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2351
2352         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2353                 (mac_addr[4] << 8) | mac_addr[5];
2354
2355         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2356 }
2357
2358 static inline int
2359 bnx2_alloc_rx_page(struct bnx2 *bp, u16 index)
2360 {
2361         dma_addr_t mapping;
2362         struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2363         struct rx_bd *rxbd =
2364                 &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2365         struct page *page = alloc_page(GFP_ATOMIC);
2366
2367         if (!page)
2368                 return -ENOMEM;
2369         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2370                                PCI_DMA_FROMDEVICE);
2371         rx_pg->page = page;
2372         pci_unmap_addr_set(rx_pg, mapping, mapping);
2373         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2374         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2375         return 0;
2376 }
2377
2378 static void
2379 bnx2_free_rx_page(struct bnx2 *bp, u16 index)
2380 {
2381         struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2382         struct page *page = rx_pg->page;
2383
2384         if (!page)
2385                 return;
2386
2387         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2388                        PCI_DMA_FROMDEVICE);
2389
2390         __free_page(page);
2391         rx_pg->page = NULL;
2392 }
2393
2394 static inline int
2395 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index)
2396 {
2397         struct sk_buff *skb;
2398         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2399         dma_addr_t mapping;
2400         struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2401         unsigned long align;
2402
2403         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2404         if (skb == NULL) {
2405                 return -ENOMEM;
2406         }
2407
2408         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2409                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2410
2411         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2412                 PCI_DMA_FROMDEVICE);
2413
2414         rx_buf->skb = skb;
2415         pci_unmap_addr_set(rx_buf, mapping, mapping);
2416
2417         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2418         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2419
2420         bnapi->rx_prod_bseq += bp->rx_buf_use_size;
2421
2422         return 0;
2423 }
2424
2425 static int
2426 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2427 {
2428         struct status_block *sblk = bnapi->status_blk;
2429         u32 new_link_state, old_link_state;
2430         int is_set = 1;
2431
2432         new_link_state = sblk->status_attn_bits & event;
2433         old_link_state = sblk->status_attn_bits_ack & event;
2434         if (new_link_state != old_link_state) {
2435                 if (new_link_state)
2436                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2437                 else
2438                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2439         } else
2440                 is_set = 0;
2441
2442         return is_set;
2443 }
2444
2445 static void
2446 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2447 {
2448         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) {
2449                 spin_lock(&bp->phy_lock);
2450                 bnx2_set_link(bp);
2451                 spin_unlock(&bp->phy_lock);
2452         }
2453         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2454                 bnx2_set_remote_link(bp);
2455
2456 }
2457
2458 static inline u16
2459 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2460 {
2461         u16 cons;
2462
2463         if (bnapi->int_num == 0)
2464                 cons = bnapi->status_blk->status_tx_quick_consumer_index0;
2465         else
2466                 cons = bnapi->status_blk_msix->status_tx_quick_consumer_index;
2467
2468         if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2469                 cons++;
2470         return cons;
2471 }
2472
2473 static int
2474 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2475 {
2476         u16 hw_cons, sw_cons, sw_ring_cons;
2477         int tx_pkt = 0;
2478
2479         hw_cons = bnx2_get_hw_tx_cons(bnapi);
2480         sw_cons = bnapi->tx_cons;
2481
2482         while (sw_cons != hw_cons) {
2483                 struct sw_bd *tx_buf;
2484                 struct sk_buff *skb;
2485                 int i, last;
2486
2487                 sw_ring_cons = TX_RING_IDX(sw_cons);
2488
2489                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2490                 skb = tx_buf->skb;
2491
2492                 /* partial BD completions possible with TSO packets */
2493                 if (skb_is_gso(skb)) {
2494                         u16 last_idx, last_ring_idx;
2495
2496                         last_idx = sw_cons +
2497                                 skb_shinfo(skb)->nr_frags + 1;
2498                         last_ring_idx = sw_ring_cons +
2499                                 skb_shinfo(skb)->nr_frags + 1;
2500                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2501                                 last_idx++;
2502                         }
2503                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2504                                 break;
2505                         }
2506                 }
2507
2508                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2509                         skb_headlen(skb), PCI_DMA_TODEVICE);
2510
2511                 tx_buf->skb = NULL;
2512                 last = skb_shinfo(skb)->nr_frags;
2513
2514                 for (i = 0; i < last; i++) {
2515                         sw_cons = NEXT_TX_BD(sw_cons);
2516
2517                         pci_unmap_page(bp->pdev,
2518                                 pci_unmap_addr(
2519                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2520                                         mapping),
2521                                 skb_shinfo(skb)->frags[i].size,
2522                                 PCI_DMA_TODEVICE);
2523                 }
2524
2525                 sw_cons = NEXT_TX_BD(sw_cons);
2526
2527                 dev_kfree_skb(skb);
2528                 tx_pkt++;
2529                 if (tx_pkt == budget)
2530                         break;
2531
2532                 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2533         }
2534
2535         bnapi->hw_tx_cons = hw_cons;
2536         bnapi->tx_cons = sw_cons;
2537         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2538          * before checking for netif_queue_stopped().  Without the
2539          * memory barrier, there is a small possibility that bnx2_start_xmit()
2540          * will miss it and cause the queue to be stopped forever.
2541          */
2542         smp_mb();
2543
2544         if (unlikely(netif_queue_stopped(bp->dev)) &&
2545                      (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) {
2546                 netif_tx_lock(bp->dev);
2547                 if ((netif_queue_stopped(bp->dev)) &&
2548                     (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh))
2549                         netif_wake_queue(bp->dev);
2550                 netif_tx_unlock(bp->dev);
2551         }
2552         return tx_pkt;
2553 }
2554
2555 static void
2556 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi,
2557                         struct sk_buff *skb, int count)
2558 {
2559         struct sw_pg *cons_rx_pg, *prod_rx_pg;
2560         struct rx_bd *cons_bd, *prod_bd;
2561         dma_addr_t mapping;
2562         int i;
2563         u16 hw_prod = bnapi->rx_pg_prod, prod;
2564         u16 cons = bnapi->rx_pg_cons;
2565
2566         for (i = 0; i < count; i++) {
2567                 prod = RX_PG_RING_IDX(hw_prod);
2568
2569                 prod_rx_pg = &bp->rx_pg_ring[prod];
2570                 cons_rx_pg = &bp->rx_pg_ring[cons];
2571                 cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2572                 prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2573
2574                 if (i == 0 && skb) {
2575                         struct page *page;
2576                         struct skb_shared_info *shinfo;
2577
2578                         shinfo = skb_shinfo(skb);
2579                         shinfo->nr_frags--;
2580                         page = shinfo->frags[shinfo->nr_frags].page;
2581                         shinfo->frags[shinfo->nr_frags].page = NULL;
2582                         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2583                                                PCI_DMA_FROMDEVICE);
2584                         cons_rx_pg->page = page;
2585                         pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2586                         dev_kfree_skb(skb);
2587                 }
2588                 if (prod != cons) {
2589                         prod_rx_pg->page = cons_rx_pg->page;
2590                         cons_rx_pg->page = NULL;
2591                         pci_unmap_addr_set(prod_rx_pg, mapping,
2592                                 pci_unmap_addr(cons_rx_pg, mapping));
2593
2594                         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2595                         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2596
2597                 }
2598                 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2599                 hw_prod = NEXT_RX_BD(hw_prod);
2600         }
2601         bnapi->rx_pg_prod = hw_prod;
2602         bnapi->rx_pg_cons = cons;
2603 }
2604
2605 static inline void
2606 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2607         u16 cons, u16 prod)
2608 {
2609         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2610         struct rx_bd *cons_bd, *prod_bd;
2611
2612         cons_rx_buf = &bp->rx_buf_ring[cons];
2613         prod_rx_buf = &bp->rx_buf_ring[prod];
2614
2615         pci_dma_sync_single_for_device(bp->pdev,
2616                 pci_unmap_addr(cons_rx_buf, mapping),
2617                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2618
2619         bnapi->rx_prod_bseq += bp->rx_buf_use_size;
2620
2621         prod_rx_buf->skb = skb;
2622
2623         if (cons == prod)
2624                 return;
2625
2626         pci_unmap_addr_set(prod_rx_buf, mapping,
2627                         pci_unmap_addr(cons_rx_buf, mapping));
2628
2629         cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2630         prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2631         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2632         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2633 }
2634
2635 static int
2636 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2637             unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2638             u32 ring_idx)
2639 {
2640         int err;
2641         u16 prod = ring_idx & 0xffff;
2642
2643         err = bnx2_alloc_rx_skb(bp, bnapi, prod);
2644         if (unlikely(err)) {
2645                 bnx2_reuse_rx_skb(bp, bnapi, skb, (u16) (ring_idx >> 16), prod);
2646                 if (hdr_len) {
2647                         unsigned int raw_len = len + 4;
2648                         int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2649
2650                         bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, pages);
2651                 }
2652                 return err;
2653         }
2654
2655         skb_reserve(skb, bp->rx_offset);
2656         pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2657                          PCI_DMA_FROMDEVICE);
2658
2659         if (hdr_len == 0) {
2660                 skb_put(skb, len);
2661                 return 0;
2662         } else {
2663                 unsigned int i, frag_len, frag_size, pages;
2664                 struct sw_pg *rx_pg;
2665                 u16 pg_cons = bnapi->rx_pg_cons;
2666                 u16 pg_prod = bnapi->rx_pg_prod;
2667
2668                 frag_size = len + 4 - hdr_len;
2669                 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2670                 skb_put(skb, hdr_len);
2671
2672                 for (i = 0; i < pages; i++) {
2673                         frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2674                         if (unlikely(frag_len <= 4)) {
2675                                 unsigned int tail = 4 - frag_len;
2676
2677                                 bnapi->rx_pg_cons = pg_cons;
2678                                 bnapi->rx_pg_prod = pg_prod;
2679                                 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL,
2680                                                         pages - i);
2681                                 skb->len -= tail;
2682                                 if (i == 0) {
2683                                         skb->tail -= tail;
2684                                 } else {
2685                                         skb_frag_t *frag =
2686                                                 &skb_shinfo(skb)->frags[i - 1];
2687                                         frag->size -= tail;
2688                                         skb->data_len -= tail;
2689                                         skb->truesize -= tail;
2690                                 }
2691                                 return 0;
2692                         }
2693                         rx_pg = &bp->rx_pg_ring[pg_cons];
2694
2695                         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2696                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
2697
2698                         if (i == pages - 1)
2699                                 frag_len -= 4;
2700
2701                         skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2702                         rx_pg->page = NULL;
2703
2704                         err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod));
2705                         if (unlikely(err)) {
2706                                 bnapi->rx_pg_cons = pg_cons;
2707                                 bnapi->rx_pg_prod = pg_prod;
2708                                 bnx2_reuse_rx_skb_pages(bp, bnapi, skb,
2709                                                         pages - i);
2710                                 return err;
2711                         }
2712
2713                         frag_size -= frag_len;
2714                         skb->data_len += frag_len;
2715                         skb->truesize += frag_len;
2716                         skb->len += frag_len;
2717
2718                         pg_prod = NEXT_RX_BD(pg_prod);
2719                         pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2720                 }
2721                 bnapi->rx_pg_prod = pg_prod;
2722                 bnapi->rx_pg_cons = pg_cons;
2723         }
2724         return 0;
2725 }
2726
2727 static inline u16
2728 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2729 {
2730         u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0;
2731
2732         if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2733                 cons++;
2734         return cons;
2735 }
2736
2737 static int
2738 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2739 {
2740         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2741         struct l2_fhdr *rx_hdr;
2742         int rx_pkt = 0, pg_ring_used = 0;
2743
2744         hw_cons = bnx2_get_hw_rx_cons(bnapi);
2745         sw_cons = bnapi->rx_cons;
2746         sw_prod = bnapi->rx_prod;
2747
2748         /* Memory barrier necessary as speculative reads of the rx
2749          * buffer can be ahead of the index in the status block
2750          */
2751         rmb();
2752         while (sw_cons != hw_cons) {
2753                 unsigned int len, hdr_len;
2754                 u32 status;
2755                 struct sw_bd *rx_buf;
2756                 struct sk_buff *skb;
2757                 dma_addr_t dma_addr;
2758
2759                 sw_ring_cons = RX_RING_IDX(sw_cons);
2760                 sw_ring_prod = RX_RING_IDX(sw_prod);
2761
2762                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2763                 skb = rx_buf->skb;
2764
2765                 rx_buf->skb = NULL;
2766
2767                 dma_addr = pci_unmap_addr(rx_buf, mapping);
2768
2769                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2770                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2771
2772                 rx_hdr = (struct l2_fhdr *) skb->data;
2773                 len = rx_hdr->l2_fhdr_pkt_len;
2774
2775                 if ((status = rx_hdr->l2_fhdr_status) &
2776                         (L2_FHDR_ERRORS_BAD_CRC |
2777                         L2_FHDR_ERRORS_PHY_DECODE |
2778                         L2_FHDR_ERRORS_ALIGNMENT |
2779                         L2_FHDR_ERRORS_TOO_SHORT |
2780                         L2_FHDR_ERRORS_GIANT_FRAME)) {
2781
2782                         bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2783                                           sw_ring_prod);
2784                         goto next_rx;
2785                 }
2786                 hdr_len = 0;
2787                 if (status & L2_FHDR_STATUS_SPLIT) {
2788                         hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2789                         pg_ring_used = 1;
2790                 } else if (len > bp->rx_jumbo_thresh) {
2791                         hdr_len = bp->rx_jumbo_thresh;
2792                         pg_ring_used = 1;
2793                 }
2794
2795                 len -= 4;
2796
2797                 if (len <= bp->rx_copy_thresh) {
2798                         struct sk_buff *new_skb;
2799
2800                         new_skb = netdev_alloc_skb(bp->dev, len + 2);
2801                         if (new_skb == NULL) {
2802                                 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2803                                                   sw_ring_prod);
2804                                 goto next_rx;
2805                         }
2806
2807                         /* aligned copy */
2808                         skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2809                                       new_skb->data, len + 2);
2810                         skb_reserve(new_skb, 2);
2811                         skb_put(new_skb, len);
2812
2813                         bnx2_reuse_rx_skb(bp, bnapi, skb,
2814                                 sw_ring_cons, sw_ring_prod);
2815
2816                         skb = new_skb;
2817                 } else if (unlikely(bnx2_rx_skb(bp, bnapi, skb, len, hdr_len,
2818                            dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2819                         goto next_rx;
2820
2821                 skb->protocol = eth_type_trans(skb, bp->dev);
2822
2823                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2824                         (ntohs(skb->protocol) != 0x8100)) {
2825
2826                         dev_kfree_skb(skb);
2827                         goto next_rx;
2828
2829                 }
2830
2831                 skb->ip_summed = CHECKSUM_NONE;
2832                 if (bp->rx_csum &&
2833                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2834                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
2835
2836                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2837                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2838                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2839                 }
2840
2841 #ifdef BCM_VLAN
2842                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && bp->vlgrp) {
2843                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2844                                 rx_hdr->l2_fhdr_vlan_tag);
2845                 }
2846                 else
2847 #endif
2848                         netif_receive_skb(skb);
2849
2850                 bp->dev->last_rx = jiffies;
2851                 rx_pkt++;
2852
2853 next_rx:
2854                 sw_cons = NEXT_RX_BD(sw_cons);
2855                 sw_prod = NEXT_RX_BD(sw_prod);
2856
2857                 if ((rx_pkt == budget))
2858                         break;
2859
2860                 /* Refresh hw_cons to see if there is new work */
2861                 if (sw_cons == hw_cons) {
2862                         hw_cons = bnx2_get_hw_rx_cons(bnapi);
2863                         rmb();
2864                 }
2865         }
2866         bnapi->rx_cons = sw_cons;
2867         bnapi->rx_prod = sw_prod;
2868
2869         if (pg_ring_used)
2870                 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
2871                          bnapi->rx_pg_prod);
2872
2873         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2874
2875         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
2876
2877         mmiowb();
2878
2879         return rx_pkt;
2880
2881 }
2882
2883 /* MSI ISR - The only difference between this and the INTx ISR
2884  * is that the MSI interrupt is always serviced.
2885  */
2886 static irqreturn_t
2887 bnx2_msi(int irq, void *dev_instance)
2888 {
2889         struct net_device *dev = dev_instance;
2890         struct bnx2 *bp = netdev_priv(dev);
2891         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
2892
2893         prefetch(bnapi->status_blk);
2894         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2895                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2896                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2897
2898         /* Return here if interrupt is disabled. */
2899         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2900                 return IRQ_HANDLED;
2901
2902         netif_rx_schedule(dev, &bnapi->napi);
2903
2904         return IRQ_HANDLED;
2905 }
2906
2907 static irqreturn_t
2908 bnx2_msi_1shot(int irq, void *dev_instance)
2909 {
2910         struct net_device *dev = dev_instance;
2911         struct bnx2 *bp = netdev_priv(dev);
2912         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
2913
2914         prefetch(bnapi->status_blk);
2915
2916         /* Return here if interrupt is disabled. */
2917         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2918                 return IRQ_HANDLED;
2919
2920         netif_rx_schedule(dev, &bnapi->napi);
2921
2922         return IRQ_HANDLED;
2923 }
2924
2925 static irqreturn_t
2926 bnx2_interrupt(int irq, void *dev_instance)
2927 {
2928         struct net_device *dev = dev_instance;
2929         struct bnx2 *bp = netdev_priv(dev);
2930         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
2931         struct status_block *sblk = bnapi->status_blk;
2932
2933         /* When using INTx, it is possible for the interrupt to arrive
2934          * at the CPU before the status block posted prior to the
2935          * interrupt. Reading a register will flush the status block.
2936          * When using MSI, the MSI message will always complete after
2937          * the status block write.
2938          */
2939         if ((sblk->status_idx == bnapi->last_status_idx) &&
2940             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2941              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2942                 return IRQ_NONE;
2943
2944         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2945                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2946                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2947
2948         /* Read back to deassert IRQ immediately to avoid too many
2949          * spurious interrupts.
2950          */
2951         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2952
2953         /* Return here if interrupt is shared and is disabled. */
2954         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2955                 return IRQ_HANDLED;
2956
2957         if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
2958                 bnapi->last_status_idx = sblk->status_idx;
2959                 __netif_rx_schedule(dev, &bnapi->napi);
2960         }
2961
2962         return IRQ_HANDLED;
2963 }
2964
2965 static irqreturn_t
2966 bnx2_tx_msix(int irq, void *dev_instance)
2967 {
2968         struct net_device *dev = dev_instance;
2969         struct bnx2 *bp = netdev_priv(dev);
2970         struct bnx2_napi *bnapi = &bp->bnx2_napi[BNX2_TX_VEC];
2971
2972         prefetch(bnapi->status_blk_msix);
2973
2974         /* Return here if interrupt is disabled. */
2975         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2976                 return IRQ_HANDLED;
2977
2978         netif_rx_schedule(dev, &bnapi->napi);
2979         return IRQ_HANDLED;
2980 }
2981
2982 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
2983                                  STATUS_ATTN_BITS_TIMER_ABORT)
2984
2985 static inline int
2986 bnx2_has_work(struct bnx2_napi *bnapi)
2987 {
2988         struct status_block *sblk = bnapi->status_blk;
2989
2990         if ((bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) ||
2991             (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons))
2992                 return 1;
2993
2994         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
2995             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
2996                 return 1;
2997
2998         return 0;
2999 }
3000
3001 static int bnx2_tx_poll(struct napi_struct *napi, int budget)
3002 {
3003         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3004         struct bnx2 *bp = bnapi->bp;
3005         int work_done = 0;
3006         struct status_block_msix *sblk = bnapi->status_blk_msix;
3007
3008         do {
3009                 work_done += bnx2_tx_int(bp, bnapi, budget - work_done);
3010                 if (unlikely(work_done >= budget))
3011                         return work_done;
3012
3013                 bnapi->last_status_idx = sblk->status_idx;
3014                 rmb();
3015         } while (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons);
3016
3017         netif_rx_complete(bp->dev, napi);
3018         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3019                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3020                bnapi->last_status_idx);
3021         return work_done;
3022 }
3023
3024 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3025                           int work_done, int budget)
3026 {
3027         struct status_block *sblk = bnapi->status_blk;
3028         u32 status_attn_bits = sblk->status_attn_bits;
3029         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3030
3031         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3032             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3033
3034                 bnx2_phy_int(bp, bnapi);
3035
3036                 /* This is needed to take care of transient status
3037                  * during link changes.
3038                  */
3039                 REG_WR(bp, BNX2_HC_COMMAND,
3040                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3041                 REG_RD(bp, BNX2_HC_COMMAND);
3042         }
3043
3044         if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons)
3045                 bnx2_tx_int(bp, bnapi, 0);
3046
3047         if (bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons)
3048                 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3049
3050         return work_done;
3051 }
3052
3053 static int bnx2_poll(struct napi_struct *napi, int budget)
3054 {
3055         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3056         struct bnx2 *bp = bnapi->bp;
3057         int work_done = 0;
3058         struct status_block *sblk = bnapi->status_blk;
3059
3060         while (1) {
3061                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3062
3063                 if (unlikely(work_done >= budget))
3064                         break;
3065
3066                 /* bnapi->last_status_idx is used below to tell the hw how
3067                  * much work has been processed, so we must read it before
3068                  * checking for more work.
3069                  */
3070                 bnapi->last_status_idx = sblk->status_idx;
3071                 rmb();
3072                 if (likely(!bnx2_has_work(bnapi))) {
3073                         netif_rx_complete(bp->dev, napi);
3074                         if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3075                                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3076                                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3077                                        bnapi->last_status_idx);
3078                                 break;
3079                         }
3080                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3081                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3082                                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3083                                bnapi->last_status_idx);
3084
3085                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3086                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3087                                bnapi->last_status_idx);
3088                         break;
3089                 }
3090         }
3091
3092         return work_done;
3093 }
3094
3095 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3096  * from set_multicast.
3097  */
3098 static void
3099 bnx2_set_rx_mode(struct net_device *dev)
3100 {
3101         struct bnx2 *bp = netdev_priv(dev);
3102         u32 rx_mode, sort_mode;
3103         int i;
3104
3105         spin_lock_bh(&bp->phy_lock);
3106
3107         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3108                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3109         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3110 #ifdef BCM_VLAN
3111         if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE))
3112                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3113 #else
3114         if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
3115                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3116 #endif
3117         if (dev->flags & IFF_PROMISC) {
3118                 /* Promiscuous mode. */
3119                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3120                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3121                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3122         }
3123         else if (dev->flags & IFF_ALLMULTI) {
3124                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3125                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3126                                0xffffffff);
3127                 }
3128                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3129         }
3130         else {
3131                 /* Accept one or more multicast(s). */
3132                 struct dev_mc_list *mclist;
3133                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3134                 u32 regidx;
3135                 u32 bit;
3136                 u32 crc;
3137
3138                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3139
3140                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3141                      i++, mclist = mclist->next) {
3142
3143                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3144                         bit = crc & 0xff;
3145                         regidx = (bit & 0xe0) >> 5;
3146                         bit &= 0x1f;
3147                         mc_filter[regidx] |= (1 << bit);
3148                 }
3149
3150                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3151                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3152                                mc_filter[i]);
3153                 }
3154
3155                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3156         }
3157
3158         if (rx_mode != bp->rx_mode) {
3159                 bp->rx_mode = rx_mode;
3160                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3161         }
3162
3163         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3164         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3165         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3166
3167         spin_unlock_bh(&bp->phy_lock);
3168 }
3169
3170 static void
3171 load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3172         u32 rv2p_proc)
3173 {
3174         int i;
3175         u32 val;
3176
3177
3178         for (i = 0; i < rv2p_code_len; i += 8) {
3179                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3180                 rv2p_code++;
3181                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3182                 rv2p_code++;
3183
3184                 if (rv2p_proc == RV2P_PROC1) {
3185                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3186                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3187                 }
3188                 else {
3189                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3190                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3191                 }
3192         }
3193
3194         /* Reset the processor, un-stall is done later. */
3195         if (rv2p_proc == RV2P_PROC1) {
3196                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3197         }
3198         else {
3199                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3200         }
3201 }
3202
3203 static int
3204 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
3205 {
3206         u32 offset;
3207         u32 val;
3208         int rc;
3209
3210         /* Halt the CPU. */
3211         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3212         val |= cpu_reg->mode_value_halt;
3213         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3214         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3215
3216         /* Load the Text area. */
3217         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3218         if (fw->gz_text) {
3219                 int j;
3220
3221                 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3222                                        fw->gz_text_len);
3223                 if (rc < 0)
3224                         return rc;
3225
3226                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3227                         bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3228                 }
3229         }
3230
3231         /* Load the Data area. */
3232         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3233         if (fw->data) {
3234                 int j;
3235
3236                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3237                         bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3238                 }
3239         }
3240
3241         /* Load the SBSS area. */
3242         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3243         if (fw->sbss_len) {
3244                 int j;
3245
3246                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3247                         bnx2_reg_wr_ind(bp, offset, 0);
3248                 }
3249         }
3250
3251         /* Load the BSS area. */
3252         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3253         if (fw->bss_len) {
3254                 int j;
3255
3256                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3257                         bnx2_reg_wr_ind(bp, offset, 0);
3258                 }
3259         }
3260
3261         /* Load the Read-Only area. */
3262         offset = cpu_reg->spad_base +
3263                 (fw->rodata_addr - cpu_reg->mips_view_base);
3264         if (fw->rodata) {
3265                 int j;
3266
3267                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3268                         bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3269                 }
3270         }
3271
3272         /* Clear the pre-fetch instruction. */
3273         bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3274         bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3275
3276         /* Start the CPU. */
3277         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3278         val &= ~cpu_reg->mode_value_halt;
3279         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3280         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3281
3282         return 0;
3283 }
3284
3285 static int
3286 bnx2_init_cpus(struct bnx2 *bp)
3287 {
3288         struct cpu_reg cpu_reg;
3289         struct fw_info *fw;
3290         int rc, rv2p_len;
3291         void *text, *rv2p;
3292
3293         /* Initialize the RV2P processor. */
3294         text = vmalloc(FW_BUF_SIZE);
3295         if (!text)
3296                 return -ENOMEM;
3297         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3298                 rv2p = bnx2_xi_rv2p_proc1;
3299                 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3300         } else {
3301                 rv2p = bnx2_rv2p_proc1;
3302                 rv2p_len = sizeof(bnx2_rv2p_proc1);
3303         }
3304         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3305         if (rc < 0)
3306                 goto init_cpu_err;
3307
3308         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3309
3310         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3311                 rv2p = bnx2_xi_rv2p_proc2;
3312                 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3313         } else {
3314                 rv2p = bnx2_rv2p_proc2;
3315                 rv2p_len = sizeof(bnx2_rv2p_proc2);
3316         }
3317         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3318         if (rc < 0)
3319                 goto init_cpu_err;
3320
3321         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3322
3323         /* Initialize the RX Processor. */
3324         cpu_reg.mode = BNX2_RXP_CPU_MODE;
3325         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
3326         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
3327         cpu_reg.state = BNX2_RXP_CPU_STATE;
3328         cpu_reg.state_value_clear = 0xffffff;
3329         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
3330         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
3331         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
3332         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
3333         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
3334         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
3335         cpu_reg.mips_view_base = 0x8000000;
3336
3337         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3338                 fw = &bnx2_rxp_fw_09;
3339         else
3340                 fw = &bnx2_rxp_fw_06;
3341
3342         fw->text = text;
3343         rc = load_cpu_fw(bp, &cpu_reg, fw);
3344         if (rc)
3345                 goto init_cpu_err;
3346
3347         /* Initialize the TX Processor. */
3348         cpu_reg.mode = BNX2_TXP_CPU_MODE;
3349         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
3350         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
3351         cpu_reg.state = BNX2_TXP_CPU_STATE;
3352         cpu_reg.state_value_clear = 0xffffff;
3353         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
3354         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
3355         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
3356         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
3357         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
3358         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
3359         cpu_reg.mips_view_base = 0x8000000;
3360
3361         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3362                 fw = &bnx2_txp_fw_09;
3363         else
3364                 fw = &bnx2_txp_fw_06;
3365
3366         fw->text = text;
3367         rc = load_cpu_fw(bp, &cpu_reg, fw);
3368         if (rc)
3369                 goto init_cpu_err;
3370
3371         /* Initialize the TX Patch-up Processor. */
3372         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3373         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3374         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3375         cpu_reg.state = BNX2_TPAT_CPU_STATE;
3376         cpu_reg.state_value_clear = 0xffffff;
3377         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3378         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3379         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3380         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3381         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3382         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3383         cpu_reg.mips_view_base = 0x8000000;
3384
3385         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3386                 fw = &bnx2_tpat_fw_09;
3387         else
3388                 fw = &bnx2_tpat_fw_06;
3389
3390         fw->text = text;
3391         rc = load_cpu_fw(bp, &cpu_reg, fw);
3392         if (rc)
3393                 goto init_cpu_err;
3394
3395         /* Initialize the Completion Processor. */
3396         cpu_reg.mode = BNX2_COM_CPU_MODE;
3397         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3398         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3399         cpu_reg.state = BNX2_COM_CPU_STATE;
3400         cpu_reg.state_value_clear = 0xffffff;
3401         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3402         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3403         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3404         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3405         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3406         cpu_reg.spad_base = BNX2_COM_SCRATCH;
3407         cpu_reg.mips_view_base = 0x8000000;
3408
3409         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3410                 fw = &bnx2_com_fw_09;
3411         else
3412                 fw = &bnx2_com_fw_06;
3413
3414         fw->text = text;
3415         rc = load_cpu_fw(bp, &cpu_reg, fw);
3416         if (rc)
3417                 goto init_cpu_err;
3418
3419         /* Initialize the Command Processor. */
3420         cpu_reg.mode = BNX2_CP_CPU_MODE;
3421         cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3422         cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3423         cpu_reg.state = BNX2_CP_CPU_STATE;
3424         cpu_reg.state_value_clear = 0xffffff;
3425         cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3426         cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3427         cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3428         cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3429         cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3430         cpu_reg.spad_base = BNX2_CP_SCRATCH;
3431         cpu_reg.mips_view_base = 0x8000000;
3432
3433         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3434                 fw = &bnx2_cp_fw_09;
3435         else
3436                 fw = &bnx2_cp_fw_06;
3437
3438         fw->text = text;
3439         rc = load_cpu_fw(bp, &cpu_reg, fw);
3440
3441 init_cpu_err:
3442         vfree(text);
3443         return rc;
3444 }
3445
3446 static int
3447 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3448 {
3449         u16 pmcsr;
3450
3451         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3452
3453         switch (state) {
3454         case PCI_D0: {
3455                 u32 val;
3456
3457                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3458                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3459                         PCI_PM_CTRL_PME_STATUS);
3460
3461                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3462                         /* delay required during transition out of D3hot */
3463                         msleep(20);
3464
3465                 val = REG_RD(bp, BNX2_EMAC_MODE);
3466                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3467                 val &= ~BNX2_EMAC_MODE_MPKT;
3468                 REG_WR(bp, BNX2_EMAC_MODE, val);
3469
3470                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3471                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3472                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3473                 break;
3474         }
3475         case PCI_D3hot: {
3476                 int i;
3477                 u32 val, wol_msg;
3478
3479                 if (bp->wol) {
3480                         u32 advertising;
3481                         u8 autoneg;
3482
3483                         autoneg = bp->autoneg;
3484                         advertising = bp->advertising;
3485
3486                         if (bp->phy_port == PORT_TP) {
3487                                 bp->autoneg = AUTONEG_SPEED;
3488                                 bp->advertising = ADVERTISED_10baseT_Half |
3489                                         ADVERTISED_10baseT_Full |
3490                                         ADVERTISED_100baseT_Half |
3491                                         ADVERTISED_100baseT_Full |
3492                                         ADVERTISED_Autoneg;
3493                         }
3494
3495                         spin_lock_bh(&bp->phy_lock);
3496                         bnx2_setup_phy(bp, bp->phy_port);
3497                         spin_unlock_bh(&bp->phy_lock);
3498
3499                         bp->autoneg = autoneg;
3500                         bp->advertising = advertising;
3501
3502                         bnx2_set_mac_addr(bp);
3503
3504                         val = REG_RD(bp, BNX2_EMAC_MODE);
3505
3506                         /* Enable port mode. */
3507                         val &= ~BNX2_EMAC_MODE_PORT;
3508                         val |= BNX2_EMAC_MODE_MPKT_RCVD |
3509                                BNX2_EMAC_MODE_ACPI_RCVD |
3510                                BNX2_EMAC_MODE_MPKT;
3511                         if (bp->phy_port == PORT_TP)
3512                                 val |= BNX2_EMAC_MODE_PORT_MII;
3513                         else {
3514                                 val |= BNX2_EMAC_MODE_PORT_GMII;
3515                                 if (bp->line_speed == SPEED_2500)
3516                                         val |= BNX2_EMAC_MODE_25G_MODE;
3517                         }
3518
3519                         REG_WR(bp, BNX2_EMAC_MODE, val);
3520
3521                         /* receive all multicast */
3522                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3523                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3524                                        0xffffffff);
3525                         }
3526                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3527                                BNX2_EMAC_RX_MODE_SORT_MODE);
3528
3529                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3530                               BNX2_RPM_SORT_USER0_MC_EN;
3531                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3532                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3533                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3534                                BNX2_RPM_SORT_USER0_ENA);
3535
3536                         /* Need to enable EMAC and RPM for WOL. */
3537                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3538                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3539                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3540                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3541
3542                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3543                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3544                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3545
3546                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3547                 }
3548                 else {
3549                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3550                 }
3551
3552                 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3553                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
3554
3555                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3556                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3557                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3558
3559                         if (bp->wol)
3560                                 pmcsr |= 3;
3561                 }
3562                 else {
3563                         pmcsr |= 3;
3564                 }
3565                 if (bp->wol) {
3566                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3567                 }
3568                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3569                                       pmcsr);
3570
3571                 /* No more memory access after this point until
3572                  * device is brought back to D0.
3573                  */
3574                 udelay(50);
3575                 break;
3576         }
3577         default:
3578                 return -EINVAL;
3579         }
3580         return 0;
3581 }
3582
3583 static int
3584 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3585 {
3586         u32 val;
3587         int j;
3588
3589         /* Request access to the flash interface. */
3590         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3591         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3592                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3593                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3594                         break;
3595
3596                 udelay(5);
3597         }
3598
3599         if (j >= NVRAM_TIMEOUT_COUNT)
3600                 return -EBUSY;
3601
3602         return 0;
3603 }
3604
3605 static int
3606 bnx2_release_nvram_lock(struct bnx2 *bp)
3607 {
3608         int j;
3609         u32 val;
3610
3611         /* Relinquish nvram interface. */
3612         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3613
3614         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3615                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3616                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3617                         break;
3618
3619                 udelay(5);
3620         }
3621
3622         if (j >= NVRAM_TIMEOUT_COUNT)
3623                 return -EBUSY;
3624
3625         return 0;
3626 }
3627
3628
3629 static int
3630 bnx2_enable_nvram_write(struct bnx2 *bp)
3631 {
3632         u32 val;
3633
3634         val = REG_RD(bp, BNX2_MISC_CFG);
3635         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3636
3637         if (bp->flash_info->flags & BNX2_NV_WREN) {
3638                 int j;
3639
3640                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3641                 REG_WR(bp, BNX2_NVM_COMMAND,
3642                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3643
3644                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3645                         udelay(5);
3646
3647                         val = REG_RD(bp, BNX2_NVM_COMMAND);
3648                         if (val & BNX2_NVM_COMMAND_DONE)
3649                                 break;
3650                 }
3651
3652                 if (j >= NVRAM_TIMEOUT_COUNT)
3653                         return -EBUSY;
3654         }
3655         return 0;
3656 }
3657
3658 static void
3659 bnx2_disable_nvram_write(struct bnx2 *bp)
3660 {
3661         u32 val;
3662
3663         val = REG_RD(bp, BNX2_MISC_CFG);
3664         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3665 }
3666
3667
3668 static void
3669 bnx2_enable_nvram_access(struct bnx2 *bp)
3670 {
3671         u32 val;
3672
3673         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3674         /* Enable both bits, even on read. */
3675         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3676                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3677 }
3678
3679 static void
3680 bnx2_disable_nvram_access(struct bnx2 *bp)
3681 {
3682         u32 val;
3683
3684         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3685         /* Disable both bits, even after read. */
3686         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3687                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3688                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
3689 }
3690
3691 static int
3692 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3693 {
3694         u32 cmd;
3695         int j;
3696
3697         if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3698                 /* Buffered flash, no erase needed */
3699                 return 0;
3700
3701         /* Build an erase command */
3702         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3703               BNX2_NVM_COMMAND_DOIT;
3704
3705         /* Need to clear DONE bit separately. */
3706         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3707
3708         /* Address of the NVRAM to read from. */
3709         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3710
3711         /* Issue an erase command. */
3712         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3713
3714         /* Wait for completion. */
3715         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3716                 u32 val;
3717
3718                 udelay(5);
3719
3720                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3721                 if (val & BNX2_NVM_COMMAND_DONE)
3722                         break;
3723         }
3724
3725         if (j >= NVRAM_TIMEOUT_COUNT)
3726                 return -EBUSY;
3727
3728         return 0;
3729 }
3730
3731 static int
3732 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3733 {
3734         u32 cmd;
3735         int j;
3736
3737         /* Build the command word. */
3738         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3739
3740         /* Calculate an offset of a buffered flash, not needed for 5709. */
3741         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3742                 offset = ((offset / bp->flash_info->page_size) <<
3743                            bp->flash_info->page_bits) +
3744                           (offset % bp->flash_info->page_size);
3745         }
3746
3747         /* Need to clear DONE bit separately. */
3748         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3749
3750         /* Address of the NVRAM to read from. */
3751         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3752
3753         /* Issue a read command. */
3754         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3755
3756         /* Wait for completion. */
3757         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3758                 u32 val;
3759
3760                 udelay(5);
3761
3762                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3763                 if (val & BNX2_NVM_COMMAND_DONE) {
3764                         __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3765                         memcpy(ret_val, &v, 4);
3766                         break;
3767                 }
3768         }
3769         if (j >= NVRAM_TIMEOUT_COUNT)
3770                 return -EBUSY;
3771
3772         return 0;
3773 }
3774
3775
3776 static int
3777 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3778 {
3779         u32 cmd;
3780         __be32 val32;
3781         int j;
3782
3783         /* Build the command word. */
3784         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3785
3786         /* Calculate an offset of a buffered flash, not needed for 5709. */
3787         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3788                 offset = ((offset / bp->flash_info->page_size) <<
3789                           bp->flash_info->page_bits) +
3790                          (offset % bp->flash_info->page_size);
3791         }
3792
3793         /* Need to clear DONE bit separately. */
3794         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3795
3796         memcpy(&val32, val, 4);
3797
3798         /* Write the data. */
3799         REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3800
3801         /* Address of the NVRAM to write to. */
3802         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3803
3804         /* Issue the write command. */
3805         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3806
3807         /* Wait for completion. */
3808         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3809                 udelay(5);
3810
3811                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3812                         break;
3813         }
3814         if (j >= NVRAM_TIMEOUT_COUNT)
3815                 return -EBUSY;
3816
3817         return 0;
3818 }
3819
3820 static int
3821 bnx2_init_nvram(struct bnx2 *bp)
3822 {
3823         u32 val;
3824         int j, entry_count, rc = 0;
3825         struct flash_spec *flash;
3826
3827         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3828                 bp->flash_info = &flash_5709;
3829                 goto get_flash_size;
3830         }
3831
3832         /* Determine the selected interface. */
3833         val = REG_RD(bp, BNX2_NVM_CFG1);
3834
3835         entry_count = ARRAY_SIZE(flash_table);
3836
3837         if (val & 0x40000000) {
3838
3839                 /* Flash interface has been reconfigured */
3840                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3841                      j++, flash++) {
3842                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
3843                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3844                                 bp->flash_info = flash;
3845                                 break;
3846                         }
3847                 }
3848         }
3849         else {
3850                 u32 mask;
3851                 /* Not yet been reconfigured */
3852
3853                 if (val & (1 << 23))
3854                         mask = FLASH_BACKUP_STRAP_MASK;
3855                 else
3856                         mask = FLASH_STRAP_MASK;
3857
3858                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3859                         j++, flash++) {
3860
3861                         if ((val & mask) == (flash->strapping & mask)) {
3862                                 bp->flash_info = flash;
3863
3864                                 /* Request access to the flash interface. */
3865                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3866                                         return rc;
3867
3868                                 /* Enable access to flash interface */
3869                                 bnx2_enable_nvram_access(bp);
3870
3871                                 /* Reconfigure the flash interface */
3872                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3873                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3874                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3875                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3876
3877                                 /* Disable access to flash interface */
3878                                 bnx2_disable_nvram_access(bp);
3879                                 bnx2_release_nvram_lock(bp);
3880
3881                                 break;
3882                         }
3883                 }
3884         } /* if (val & 0x40000000) */
3885
3886         if (j == entry_count) {
3887                 bp->flash_info = NULL;
3888                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3889                 return -ENODEV;
3890         }
3891
3892 get_flash_size:
3893         val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
3894         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3895         if (val)
3896                 bp->flash_size = val;
3897         else
3898                 bp->flash_size = bp->flash_info->total_size;
3899
3900         return rc;
3901 }
3902
3903 static int
3904 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3905                 int buf_size)
3906 {
3907         int rc = 0;
3908         u32 cmd_flags, offset32, len32, extra;
3909
3910         if (buf_size == 0)
3911                 return 0;
3912
3913         /* Request access to the flash interface. */
3914         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3915                 return rc;
3916
3917         /* Enable access to flash interface */
3918         bnx2_enable_nvram_access(bp);
3919
3920         len32 = buf_size;
3921         offset32 = offset;
3922         extra = 0;
3923
3924         cmd_flags = 0;
3925
3926         if (offset32 & 3) {
3927                 u8 buf[4];
3928                 u32 pre_len;
3929
3930                 offset32 &= ~3;
3931                 pre_len = 4 - (offset & 3);
3932
3933                 if (pre_len >= len32) {
3934                         pre_len = len32;
3935                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
3936                                     BNX2_NVM_COMMAND_LAST;
3937                 }
3938                 else {
3939                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
3940                 }
3941
3942                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3943
3944                 if (rc)
3945                         return rc;
3946
3947                 memcpy(ret_buf, buf + (offset & 3), pre_len);
3948
3949                 offset32 += 4;
3950                 ret_buf += pre_len;
3951                 len32 -= pre_len;
3952         }
3953         if (len32 & 3) {
3954                 extra = 4 - (len32 & 3);
3955                 len32 = (len32 + 4) & ~3;
3956         }
3957
3958         if (len32 == 4) {
3959                 u8 buf[4];
3960
3961                 if (cmd_flags)
3962                         cmd_flags = BNX2_NVM_COMMAND_LAST;
3963                 else
3964                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
3965                                     BNX2_NVM_COMMAND_LAST;
3966
3967                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3968
3969                 memcpy(ret_buf, buf, 4 - extra);
3970         }
3971         else if (len32 > 0) {
3972                 u8 buf[4];
3973
3974                 /* Read the first word. */
3975                 if (cmd_flags)
3976                         cmd_flags = 0;
3977                 else
3978                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
3979
3980                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3981
3982                 /* Advance to the next dword. */
3983                 offset32 += 4;
3984                 ret_buf += 4;
3985                 len32 -= 4;
3986
3987                 while (len32 > 4 && rc == 0) {
3988                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3989
3990                         /* Advance to the next dword. */
3991                         offset32 += 4;
3992                         ret_buf += 4;
3993                         len32 -= 4;
3994                 }
3995
3996                 if (rc)
3997                         return rc;
3998
3999                 cmd_flags = BNX2_NVM_COMMAND_LAST;
4000                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4001
4002                 memcpy(ret_buf, buf, 4 - extra);
4003         }
4004
4005         /* Disable access to flash interface */
4006         bnx2_disable_nvram_access(bp);
4007
4008         bnx2_release_nvram_lock(bp);
4009
4010         return rc;
4011 }
4012
4013 static int
4014 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4015                 int buf_size)
4016 {
4017         u32 written, offset32, len32;
4018         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4019         int rc = 0;
4020         int align_start, align_end;
4021
4022         buf = data_buf;
4023         offset32 = offset;
4024         len32 = buf_size;
4025         align_start = align_end = 0;
4026
4027         if ((align_start = (offset32 & 3))) {
4028                 offset32 &= ~3;
4029                 len32 += align_start;
4030                 if (len32 < 4)
4031                         len32 = 4;
4032                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4033                         return rc;
4034         }
4035
4036         if (len32 & 3) {
4037                 align_end = 4 - (len32 & 3);
4038                 len32 += align_end;
4039                 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4040                         return rc;
4041         }
4042
4043         if (align_start || align_end) {
4044                 align_buf = kmalloc(len32, GFP_KERNEL);
4045                 if (align_buf == NULL)
4046                         return -ENOMEM;
4047                 if (align_start) {
4048                         memcpy(align_buf, start, 4);
4049                 }
4050                 if (align_end) {
4051                         memcpy(align_buf + len32 - 4, end, 4);
4052                 }
4053                 memcpy(align_buf + align_start, data_buf, buf_size);
4054                 buf = align_buf;
4055         }
4056
4057         if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4058                 flash_buffer = kmalloc(264, GFP_KERNEL);
4059                 if (flash_buffer == NULL) {
4060                         rc = -ENOMEM;
4061                         goto nvram_write_end;
4062                 }
4063         }
4064
4065         written = 0;
4066         while ((written < len32) && (rc == 0)) {
4067                 u32 page_start, page_end, data_start, data_end;
4068                 u32 addr, cmd_flags;
4069                 int i;
4070
4071                 /* Find the page_start addr */
4072                 page_start = offset32 + written;
4073                 page_start -= (page_start % bp->flash_info->page_size);
4074                 /* Find the page_end addr */
4075                 page_end = page_start + bp->flash_info->page_size;
4076                 /* Find the data_start addr */
4077                 data_start = (written == 0) ? offset32 : page_start;
4078                 /* Find the data_end addr */
4079                 data_end = (page_end > offset32 + len32) ?
4080                         (offset32 + len32) : page_end;
4081
4082                 /* Request access to the flash interface. */
4083                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4084                         goto nvram_write_end;
4085
4086                 /* Enable access to flash interface */
4087                 bnx2_enable_nvram_access(bp);
4088
4089                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4090                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4091                         int j;
4092
4093                         /* Read the whole page into the buffer
4094                          * (non-buffer flash only) */
4095                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
4096                                 if (j == (bp->flash_info->page_size - 4)) {
4097                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
4098                                 }
4099                                 rc = bnx2_nvram_read_dword(bp,
4100                                         page_start + j,
4101                                         &flash_buffer[j],
4102                                         cmd_flags);
4103
4104                                 if (rc)
4105                                         goto nvram_write_end;
4106
4107                                 cmd_flags = 0;
4108                         }
4109                 }
4110
4111                 /* Enable writes to flash interface (unlock write-protect) */
4112                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4113                         goto nvram_write_end;
4114
4115                 /* Loop to write back the buffer data from page_start to
4116                  * data_start */
4117                 i = 0;
4118                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4119                         /* Erase the page */
4120                         if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4121                                 goto nvram_write_end;
4122
4123                         /* Re-enable the write again for the actual write */
4124                         bnx2_enable_nvram_write(bp);
4125
4126                         for (addr = page_start; addr < data_start;
4127                                 addr += 4, i += 4) {
4128
4129                                 rc = bnx2_nvram_write_dword(bp, addr,
4130                                         &flash_buffer[i], cmd_flags);
4131
4132                                 if (rc != 0)
4133                                         goto nvram_write_end;
4134
4135                                 cmd_flags = 0;
4136                         }
4137                 }
4138
4139                 /* Loop to write the new data from data_start to data_end */
4140                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4141                         if ((addr == page_end - 4) ||
4142                                 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4143                                  (addr == data_end - 4))) {
4144
4145                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4146                         }
4147                         rc = bnx2_nvram_write_dword(bp, addr, buf,
4148                                 cmd_flags);
4149
4150                         if (rc != 0)
4151                                 goto nvram_write_end;
4152
4153                         cmd_flags = 0;
4154                         buf += 4;
4155                 }
4156
4157                 /* Loop to write back the buffer data from data_end
4158                  * to page_end */
4159                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4160                         for (addr = data_end; addr < page_end;
4161                                 addr += 4, i += 4) {
4162
4163                                 if (addr == page_end-4) {
4164                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4165                                 }
4166                                 rc = bnx2_nvram_write_dword(bp, addr,
4167                                         &flash_buffer[i], cmd_flags);
4168
4169                                 if (rc != 0)
4170                                         goto nvram_write_end;
4171
4172                                 cmd_flags = 0;
4173                         }
4174                 }
4175
4176                 /* Disable writes to flash interface (lock write-protect) */
4177                 bnx2_disable_nvram_write(bp);
4178
4179                 /* Disable access to flash interface */
4180                 bnx2_disable_nvram_access(bp);
4181                 bnx2_release_nvram_lock(bp);
4182
4183                 /* Increment written */
4184                 written += data_end - data_start;
4185         }
4186
4187 nvram_write_end:
4188         kfree(flash_buffer);
4189         kfree(align_buf);
4190         return rc;
4191 }
4192
4193 static void
4194 bnx2_init_remote_phy(struct bnx2 *bp)
4195 {
4196         u32 val;
4197
4198         bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4199         if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES))
4200                 return;
4201
4202         val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4203         if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4204                 return;
4205
4206         if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
4207                 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4208
4209                 val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4210                 if (val & BNX2_LINK_STATUS_SERDES_LINK)
4211                         bp->phy_port = PORT_FIBRE;
4212                 else
4213                         bp->phy_port = PORT_TP;
4214
4215                 if (netif_running(bp->dev)) {
4216                         u32 sig;
4217
4218                         if (val & BNX2_LINK_STATUS_LINK_UP) {
4219                                 bp->link_up = 1;
4220                                 netif_carrier_on(bp->dev);
4221                         } else {
4222                                 bp->link_up = 0;
4223                                 netif_carrier_off(bp->dev);
4224                         }
4225                         sig = BNX2_DRV_ACK_CAP_SIGNATURE |
4226                               BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4227                         bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4228                 }
4229         }
4230 }
4231
4232 static void
4233 bnx2_setup_msix_tbl(struct bnx2 *bp)
4234 {
4235         REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4236
4237         REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4238         REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4239 }
4240
4241 static int
4242 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4243 {
4244         u32 val;
4245         int i, rc = 0;
4246         u8 old_port;
4247
4248         /* Wait for the current PCI transaction to complete before
4249          * issuing a reset. */
4250         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4251                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4252                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4253                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4254                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4255         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4256         udelay(5);
4257
4258         /* Wait for the firmware to tell us it is ok to issue a reset. */
4259         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
4260
4261         /* Deposit a driver reset signature so the firmware knows that
4262          * this is a soft reset. */
4263         bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4264                       BNX2_DRV_RESET_SIGNATURE_MAGIC);
4265
4266         /* Do a dummy read to force the chip to complete all current transaction
4267          * before we issue a reset. */
4268         val = REG_RD(bp, BNX2_MISC_ID);
4269
4270         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4271                 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4272                 REG_RD(bp, BNX2_MISC_COMMAND);
4273                 udelay(5);
4274
4275                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4276                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4277
4278                 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4279
4280         } else {
4281                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4282                       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4283                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4284
4285                 /* Chip reset. */
4286                 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4287
4288                 /* Reading back any register after chip reset will hang the
4289                  * bus on 5706 A0 and A1.  The msleep below provides plenty
4290                  * of margin for write posting.
4291                  */
4292                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4293                     (CHIP_ID(bp) == CHIP_ID_5706_A1))
4294                         msleep(20);
4295
4296                 /* Reset takes approximate 30 usec */
4297                 for (i = 0; i < 10; i++) {
4298                         val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4299                         if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4300                                     BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4301                                 break;
4302                         udelay(10);
4303                 }
4304
4305                 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4306                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4307                         printk(KERN_ERR PFX "Chip reset did not complete\n");
4308                         return -EBUSY;
4309                 }
4310         }
4311
4312         /* Make sure byte swapping is properly configured. */
4313         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4314         if (val != 0x01020304) {
4315                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4316                 return -ENODEV;
4317         }
4318
4319         /* Wait for the firmware to finish its initialization. */
4320         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
4321         if (rc)
4322                 return rc;
4323
4324         spin_lock_bh(&bp->phy_lock);
4325         old_port = bp->phy_port;
4326         bnx2_init_remote_phy(bp);
4327         if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4328             old_port != bp->phy_port)
4329                 bnx2_set_default_remote_link(bp);
4330         spin_unlock_bh(&bp->phy_lock);
4331
4332         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4333                 /* Adjust the voltage regular to two steps lower.  The default
4334                  * of this register is 0x0000000e. */
4335                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4336
4337                 /* Remove bad rbuf memory from the free pool. */
4338                 rc = bnx2_alloc_bad_rbuf(bp);
4339         }
4340
4341         if (bp->flags & BNX2_FLAG_USING_MSIX)
4342                 bnx2_setup_msix_tbl(bp);
4343
4344         return rc;
4345 }
4346
4347 static int
4348 bnx2_init_chip(struct bnx2 *bp)
4349 {
4350         u32 val;
4351         int rc, i;
4352
4353         /* Make sure the interrupt is not active. */
4354         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4355
4356         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4357               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4358 #ifdef __BIG_ENDIAN
4359               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4360 #endif
4361               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4362               DMA_READ_CHANS << 12 |
4363               DMA_WRITE_CHANS << 16;
4364
4365         val |= (0x2 << 20) | (1 << 11);
4366
4367         if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4368                 val |= (1 << 23);
4369
4370         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4371             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4372                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4373
4374         REG_WR(bp, BNX2_DMA_CONFIG, val);
4375
4376         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4377                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4378                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4379                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4380         }
4381
4382         if (bp->flags & BNX2_FLAG_PCIX) {
4383                 u16 val16;
4384
4385                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4386                                      &val16);
4387                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4388                                       val16 & ~PCI_X_CMD_ERO);
4389         }
4390
4391         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4392                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4393                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4394                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4395
4396         /* Initialize context mapping and zero out the quick contexts.  The
4397          * context block must have already been enabled. */
4398         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4399                 rc = bnx2_init_5709_context(bp);
4400                 if (rc)
4401                         return rc;
4402         } else
4403                 bnx2_init_context(bp);
4404
4405         if ((rc = bnx2_init_cpus(bp)) != 0)
4406                 return rc;
4407
4408         bnx2_init_nvram(bp);
4409
4410         bnx2_set_mac_addr(bp);
4411
4412         val = REG_RD(bp, BNX2_MQ_CONFIG);
4413         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4414         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4415         if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4416                 val |= BNX2_MQ_CONFIG_HALT_DIS;
4417
4418         REG_WR(bp, BNX2_MQ_CONFIG, val);
4419
4420         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4421         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4422         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4423
4424         val = (BCM_PAGE_BITS - 8) << 24;
4425         REG_WR(bp, BNX2_RV2P_CONFIG, val);
4426
4427         /* Configure page size. */
4428         val = REG_RD(bp, BNX2_TBDR_CONFIG);
4429         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4430         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4431         REG_WR(bp, BNX2_TBDR_CONFIG, val);
4432
4433         val = bp->mac_addr[0] +
4434               (bp->mac_addr[1] << 8) +
4435               (bp->mac_addr[2] << 16) +
4436               bp->mac_addr[3] +
4437               (bp->mac_addr[4] << 8) +
4438               (bp->mac_addr[5] << 16);
4439         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4440
4441         /* Program the MTU.  Also include 4 bytes for CRC32. */
4442         val = bp->dev->mtu + ETH_HLEN + 4;
4443         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4444                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4445         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4446
4447         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4448                 bp->bnx2_napi[i].last_status_idx = 0;
4449
4450         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4451
4452         /* Set up how to generate a link change interrupt. */
4453         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4454
4455         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4456                (u64) bp->status_blk_mapping & 0xffffffff);
4457         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4458
4459         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4460                (u64) bp->stats_blk_mapping & 0xffffffff);
4461         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4462                (u64) bp->stats_blk_mapping >> 32);
4463
4464         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4465                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4466
4467         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4468                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4469
4470         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4471                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4472
4473         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4474
4475         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4476
4477         REG_WR(bp, BNX2_HC_COM_TICKS,
4478                (bp->com_ticks_int << 16) | bp->com_ticks);
4479
4480         REG_WR(bp, BNX2_HC_CMD_TICKS,
4481                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4482
4483         if (CHIP_NUM(bp) == CHIP_NUM_5708)
4484                 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4485         else
4486                 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4487         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4488
4489         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4490                 val = BNX2_HC_CONFIG_COLLECT_STATS;
4491         else {
4492                 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4493                       BNX2_HC_CONFIG_COLLECT_STATS;
4494         }
4495
4496         if (bp->flags & BNX2_FLAG_USING_MSIX) {
4497                 u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4498                            BNX2_HC_SB_CONFIG_1;
4499
4500                 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4501                        BNX2_HC_MSIX_BIT_VECTOR_VAL);
4502
4503                 REG_WR(bp, base,
4504                         BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4505                         BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4506
4507                 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4508                         (bp->tx_quick_cons_trip_int << 16) |
4509                          bp->tx_quick_cons_trip);
4510
4511                 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4512                         (bp->tx_ticks_int << 16) | bp->tx_ticks);
4513
4514                 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4515         }
4516
4517         if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4518                 val |= BNX2_HC_CONFIG_ONE_SHOT;
4519
4520         REG_WR(bp, BNX2_HC_CONFIG, val);
4521
4522         /* Clear internal stats counters. */
4523         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4524
4525         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4526
4527         /* Initialize the receive filter. */
4528         bnx2_set_rx_mode(bp->dev);
4529
4530         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4531                 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4532                 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4533                 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4534         }
4535         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4536                           0);
4537
4538         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4539         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4540
4541         udelay(20);
4542
4543         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4544
4545         return rc;
4546 }
4547
4548 static void
4549 bnx2_clear_ring_states(struct bnx2 *bp)
4550 {
4551         struct bnx2_napi *bnapi;
4552         int i;
4553
4554         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4555                 bnapi = &bp->bnx2_napi[i];
4556
4557                 bnapi->tx_cons = 0;
4558                 bnapi->hw_tx_cons = 0;
4559                 bnapi->rx_prod_bseq = 0;
4560                 bnapi->rx_prod = 0;
4561                 bnapi->rx_cons = 0;
4562                 bnapi->rx_pg_prod = 0;
4563                 bnapi->rx_pg_cons = 0;
4564         }
4565 }
4566
4567 static void
4568 bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4569 {
4570         u32 val, offset0, offset1, offset2, offset3;
4571         u32 cid_addr = GET_CID_ADDR(cid);
4572
4573         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4574                 offset0 = BNX2_L2CTX_TYPE_XI;
4575                 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4576                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4577                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4578         } else {
4579                 offset0 = BNX2_L2CTX_TYPE;
4580                 offset1 = BNX2_L2CTX_CMD_TYPE;
4581                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4582                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4583         }
4584         val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4585         bnx2_ctx_wr(bp, cid_addr, offset0, val);
4586
4587         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4588         bnx2_ctx_wr(bp, cid_addr, offset1, val);
4589
4590         val = (u64) bp->tx_desc_mapping >> 32;
4591         bnx2_ctx_wr(bp, cid_addr, offset2, val);
4592
4593         val = (u64) bp->tx_desc_mapping & 0xffffffff;
4594         bnx2_ctx_wr(bp, cid_addr, offset3, val);
4595 }
4596
4597 static void
4598 bnx2_init_tx_ring(struct bnx2 *bp)
4599 {
4600         struct tx_bd *txbd;
4601         u32 cid = TX_CID;
4602         struct bnx2_napi *bnapi;
4603
4604         bp->tx_vec = 0;
4605         if (bp->flags & BNX2_FLAG_USING_MSIX) {
4606                 cid = TX_TSS_CID;
4607                 bp->tx_vec = BNX2_TX_VEC;
4608                 REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM |
4609                        (TX_TSS_CID << 7));
4610         }
4611         bnapi = &bp->bnx2_napi[bp->tx_vec];
4612
4613         bp->tx_wake_thresh = bp->tx_ring_size / 2;
4614
4615         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
4616
4617         txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4618         txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4619
4620         bp->tx_prod = 0;
4621         bp->tx_prod_bseq = 0;
4622
4623         bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4624         bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4625
4626         bnx2_init_tx_context(bp, cid);
4627 }
4628
4629 static void
4630 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4631                      int num_rings)
4632 {
4633         int i;
4634         struct rx_bd *rxbd;
4635
4636         for (i = 0; i < num_rings; i++) {
4637                 int j;
4638
4639                 rxbd = &rx_ring[i][0];
4640                 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4641                         rxbd->rx_bd_len = buf_size;
4642                         rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4643                 }
4644                 if (i == (num_rings - 1))
4645                         j = 0;
4646                 else
4647                         j = i + 1;
4648                 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4649                 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4650         }
4651 }
4652
4653 static void
4654 bnx2_init_rx_ring(struct bnx2 *bp)
4655 {
4656         int i;
4657         u16 prod, ring_prod;
4658         u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
4659         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
4660
4661         bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
4662                              bp->rx_buf_use_size, bp->rx_max_ring);
4663
4664         bnx2_init_rx_context0(bp);
4665
4666         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4667                 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4668                 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4669         }
4670
4671         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4672         if (bp->rx_pg_ring_size) {
4673                 bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
4674                                      bp->rx_pg_desc_mapping,
4675                                      PAGE_SIZE, bp->rx_max_pg_ring);
4676                 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4677                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4678                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4679                        BNX2_L2CTX_RBDC_JUMBO_KEY);
4680
4681                 val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
4682                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4683
4684                 val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
4685                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4686
4687                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4688                         REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4689         }
4690
4691         val = (u64) bp->rx_desc_mapping[0] >> 32;
4692         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4693
4694         val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
4695         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4696
4697         ring_prod = prod = bnapi->rx_pg_prod;
4698         for (i = 0; i < bp->rx_pg_ring_size; i++) {
4699                 if (bnx2_alloc_rx_page(bp, ring_prod) < 0)
4700                         break;
4701                 prod = NEXT_RX_BD(prod);
4702                 ring_prod = RX_PG_RING_IDX(prod);
4703         }
4704         bnapi->rx_pg_prod = prod;
4705
4706         ring_prod = prod = bnapi->rx_prod;
4707         for (i = 0; i < bp->rx_ring_size; i++) {
4708                 if (bnx2_alloc_rx_skb(bp, bnapi, ring_prod) < 0) {
4709                         break;
4710                 }
4711                 prod = NEXT_RX_BD(prod);
4712                 ring_prod = RX_RING_IDX(prod);
4713         }
4714         bnapi->rx_prod = prod;
4715
4716         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
4717                  bnapi->rx_pg_prod);
4718         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4719
4720         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
4721 }
4722
4723 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4724 {
4725         u32 max, num_rings = 1;
4726
4727         while (ring_size > MAX_RX_DESC_CNT) {
4728                 ring_size -= MAX_RX_DESC_CNT;
4729                 num_rings++;
4730         }
4731         /* round to next power of 2 */
4732         max = max_size;
4733         while ((max & num_rings) == 0)
4734                 max >>= 1;
4735
4736         if (num_rings != max)
4737                 max <<= 1;
4738
4739         return max;
4740 }
4741
4742 static void
4743 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4744 {
4745         u32 rx_size, rx_space, jumbo_size;
4746
4747         /* 8 for CRC and VLAN */
4748         rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
4749
4750         rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4751                 sizeof(struct skb_shared_info);
4752
4753         bp->rx_copy_thresh = RX_COPY_THRESH;
4754         bp->rx_pg_ring_size = 0;
4755         bp->rx_max_pg_ring = 0;
4756         bp->rx_max_pg_ring_idx = 0;
4757         if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
4758                 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4759
4760                 jumbo_size = size * pages;
4761                 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4762                         jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4763
4764                 bp->rx_pg_ring_size = jumbo_size;
4765                 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4766                                                         MAX_RX_PG_RINGS);
4767                 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4768                 rx_size = RX_COPY_THRESH + bp->rx_offset;
4769                 bp->rx_copy_thresh = 0;
4770         }
4771
4772         bp->rx_buf_use_size = rx_size;
4773         /* hw alignment */
4774         bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4775         bp->rx_jumbo_thresh = rx_size - bp->rx_offset;
4776         bp->rx_ring_size = size;
4777         bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4778         bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4779 }
4780
4781 static void
4782 bnx2_free_tx_skbs(struct bnx2 *bp)
4783 {
4784         int i;
4785
4786         if (bp->tx_buf_ring == NULL)
4787                 return;
4788
4789         for (i = 0; i < TX_DESC_CNT; ) {
4790                 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4791                 struct sk_buff *skb = tx_buf->skb;
4792                 int j, last;
4793
4794                 if (skb == NULL) {
4795                         i++;
4796                         continue;
4797                 }
4798
4799                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4800                         skb_headlen(skb), PCI_DMA_TODEVICE);
4801
4802                 tx_buf->skb = NULL;
4803
4804                 last = skb_shinfo(skb)->nr_frags;
4805                 for (j = 0; j < last; j++) {
4806                         tx_buf = &bp->tx_buf_ring[i + j + 1];
4807                         pci_unmap_page(bp->pdev,
4808                                 pci_unmap_addr(tx_buf, mapping),
4809                                 skb_shinfo(skb)->frags[j].size,
4810                                 PCI_DMA_TODEVICE);
4811                 }
4812                 dev_kfree_skb(skb);
4813                 i += j + 1;
4814         }
4815
4816 }
4817
4818 static void
4819 bnx2_free_rx_skbs(struct bnx2 *bp)
4820 {
4821         int i;
4822
4823         if (bp->rx_buf_ring == NULL)
4824                 return;
4825
4826         for (i = 0; i < bp->rx_max_ring_idx; i++) {
4827                 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4828                 struct sk_buff *skb = rx_buf->skb;
4829
4830                 if (skb == NULL)
4831                         continue;
4832
4833                 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4834                         bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4835
4836                 rx_buf->skb = NULL;
4837
4838                 dev_kfree_skb(skb);
4839         }
4840         for (i = 0; i < bp->rx_max_pg_ring_idx; i++)
4841                 bnx2_free_rx_page(bp, i);
4842 }
4843
4844 static void
4845 bnx2_free_skbs(struct bnx2 *bp)
4846 {
4847         bnx2_free_tx_skbs(bp);
4848         bnx2_free_rx_skbs(bp);
4849 }
4850
4851 static int
4852 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4853 {
4854         int rc;
4855
4856         rc = bnx2_reset_chip(bp, reset_code);
4857         bnx2_free_skbs(bp);
4858         if (rc)
4859                 return rc;
4860
4861         if ((rc = bnx2_init_chip(bp)) != 0)
4862                 return rc;
4863
4864         bnx2_clear_ring_states(bp);
4865         bnx2_init_tx_ring(bp);
4866         bnx2_init_rx_ring(bp);
4867         return 0;
4868 }
4869
4870 static int
4871 bnx2_init_nic(struct bnx2 *bp)
4872 {
4873         int rc;
4874
4875         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4876                 return rc;
4877
4878         spin_lock_bh(&bp->phy_lock);
4879         bnx2_init_phy(bp);
4880         bnx2_set_link(bp);
4881         spin_unlock_bh(&bp->phy_lock);
4882         return 0;
4883 }
4884
4885 static int
4886 bnx2_test_registers(struct bnx2 *bp)
4887 {
4888         int ret;
4889         int i, is_5709;
4890         static const struct {
4891                 u16   offset;
4892                 u16   flags;
4893 #define BNX2_FL_NOT_5709        1
4894                 u32   rw_mask;
4895                 u32   ro_mask;
4896         } reg_tbl[] = {
4897                 { 0x006c, 0, 0x00000000, 0x0000003f },
4898                 { 0x0090, 0, 0xffffffff, 0x00000000 },
4899                 { 0x0094, 0, 0x00000000, 0x00000000 },
4900
4901                 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4902                 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4903                 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4904                 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4905                 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4906                 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4907                 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4908                 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4909                 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4910
4911                 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4912                 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4913                 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4914                 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4915                 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4916                 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4917
4918                 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4919                 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4920                 { 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
4921
4922                 { 0x1000, 0, 0x00000000, 0x00000001 },
4923                 { 0x1004, 0, 0x00000000, 0x000f0001 },
4924
4925                 { 0x1408, 0, 0x01c00800, 0x00000000 },
4926                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4927                 { 0x14a8, 0, 0x00000000, 0x000001ff },
4928                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
4929                 { 0x14b0, 0, 0x00000002, 0x00000001 },
4930                 { 0x14b8, 0, 0x00000000, 0x00000000 },
4931                 { 0x14c0, 0, 0x00000000, 0x00000009 },
4932                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4933                 { 0x14cc, 0, 0x00000000, 0x00000001 },
4934                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
4935
4936                 { 0x1800, 0, 0x00000000, 0x00000001 },
4937                 { 0x1804, 0, 0x00000000, 0x00000003 },
4938
4939                 { 0x2800, 0, 0x00000000, 0x00000001 },
4940                 { 0x2804, 0, 0x00000000, 0x00003f01 },
4941                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4942                 { 0x2810, 0, 0xffff0000, 0x00000000 },
4943                 { 0x2814, 0, 0xffff0000, 0x00000000 },
4944                 { 0x2818, 0, 0xffff0000, 0x00000000 },
4945                 { 0x281c, 0, 0xffff0000, 0x00000000 },
4946                 { 0x2834, 0, 0xffffffff, 0x00000000 },
4947                 { 0x2840, 0, 0x00000000, 0xffffffff },
4948                 { 0x2844, 0, 0x00000000, 0xffffffff },
4949                 { 0x2848, 0, 0xffffffff, 0x00000000 },
4950                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4951
4952                 { 0x2c00, 0, 0x00000000, 0x00000011 },
4953                 { 0x2c04, 0, 0x00000000, 0x00030007 },
4954
4955                 { 0x3c00, 0, 0x00000000, 0x00000001 },
4956                 { 0x3c04, 0, 0x00000000, 0x00070000 },
4957                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4958                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4959                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4960                 { 0x3c14, 0, 0x00000000, 0xffffffff },
4961                 { 0x3c18, 0, 0x00000000, 0xffffffff },
4962                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4963                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
4964
4965                 { 0x5004, 0, 0x00000000, 0x0000007f },
4966                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
4967
4968                 { 0x5c00, 0, 0x00000000, 0x00000001 },
4969                 { 0x5c04, 0, 0x00000000, 0x0003000f },
4970                 { 0x5c08, 0, 0x00000003, 0x00000000 },
4971                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4972                 { 0x5c10, 0, 0x00000000, 0xffffffff },
4973                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4974                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4975                 { 0x5c88, 0, 0x00000000, 0x00077373 },
4976                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4977
4978                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4979                 { 0x680c, 0, 0xffffffff, 0x00000000 },
4980                 { 0x6810, 0, 0xffffffff, 0x00000000 },
4981                 { 0x6814, 0, 0xffffffff, 0x00000000 },
4982                 { 0x6818, 0, 0xffffffff, 0x00000000 },
4983                 { 0x681c, 0, 0xffffffff, 0x00000000 },
4984                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4985                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4986                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4987                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
4988                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
4989                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
4990                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
4991                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
4992                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
4993                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
4994                 { 0x684c, 0, 0xffffffff, 0x00000000 },
4995                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
4996                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
4997                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
4998                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
4999                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5000                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5001
5002                 { 0xffff, 0, 0x00000000, 0x00000000 },
5003         };
5004
5005         ret = 0;
5006         is_5709 = 0;
5007         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5008                 is_5709 = 1;
5009
5010         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5011                 u32 offset, rw_mask, ro_mask, save_val, val;
5012                 u16 flags = reg_tbl[i].flags;
5013
5014                 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5015                         continue;
5016
5017                 offset = (u32) reg_tbl[i].offset;
5018                 rw_mask = reg_tbl[i].rw_mask;
5019                 ro_mask = reg_tbl[i].ro_mask;
5020
5021                 save_val = readl(bp->regview + offset);
5022
5023                 writel(0, bp->regview + offset);
5024
5025                 val = readl(bp->regview + offset);
5026                 if ((val & rw_mask) != 0) {
5027                         goto reg_test_err;
5028                 }
5029
5030                 if ((val & ro_mask) != (save_val & ro_mask)) {
5031                         goto reg_test_err;
5032                 }
5033
5034                 writel(0xffffffff, bp->regview + offset);
5035
5036                 val = readl(bp->regview + offset);
5037                 if ((val & rw_mask) != rw_mask) {
5038                         goto reg_test_err;
5039                 }
5040
5041                 if ((val & ro_mask) != (save_val & ro_mask)) {
5042                         goto reg_test_err;
5043                 }
5044
5045                 writel(save_val, bp->regview + offset);
5046                 continue;
5047
5048 reg_test_err:
5049                 writel(save_val, bp->regview + offset);
5050                 ret = -ENODEV;
5051                 break;
5052         }
5053         return ret;
5054 }
5055
5056 static int
5057 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5058 {
5059         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5060                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5061         int i;
5062
5063         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5064                 u32 offset;
5065
5066                 for (offset = 0; offset < size; offset += 4) {
5067
5068                         bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5069
5070                         if (bnx2_reg_rd_ind(bp, start + offset) !=
5071                                 test_pattern[i]) {
5072                                 return -ENODEV;
5073                         }
5074                 }
5075         }
5076         return 0;
5077 }
5078
5079 static int
5080 bnx2_test_memory(struct bnx2 *bp)
5081 {
5082         int ret = 0;
5083         int i;
5084         static struct mem_entry {
5085                 u32   offset;
5086                 u32   len;
5087         } mem_tbl_5706[] = {
5088                 { 0x60000,  0x4000 },
5089                 { 0xa0000,  0x3000 },
5090                 { 0xe0000,  0x4000 },
5091                 { 0x120000, 0x4000 },
5092                 { 0x1a0000, 0x4000 },
5093                 { 0x160000, 0x4000 },
5094                 { 0xffffffff, 0    },
5095         },
5096         mem_tbl_5709[] = {
5097                 { 0x60000,  0x4000 },
5098                 { 0xa0000,  0x3000 },
5099                 { 0xe0000,  0x4000 },
5100                 { 0x120000, 0x4000 },
5101                 { 0x1a0000, 0x4000 },
5102                 { 0xffffffff, 0    },
5103         };
5104         struct mem_entry *mem_tbl;
5105
5106         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5107                 mem_tbl = mem_tbl_5709;
5108         else
5109                 mem_tbl = mem_tbl_5706;
5110
5111         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5112                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5113                         mem_tbl[i].len)) != 0) {
5114                         return ret;
5115                 }
5116         }
5117
5118         return ret;
5119 }
5120
5121 #define BNX2_MAC_LOOPBACK       0
5122 #define BNX2_PHY_LOOPBACK       1
5123
5124 static int
5125 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5126 {
5127         unsigned int pkt_size, num_pkts, i;
5128         struct sk_buff *skb, *rx_skb;
5129         unsigned char *packet;
5130         u16 rx_start_idx, rx_idx;
5131         dma_addr_t map;
5132         struct tx_bd *txbd;
5133         struct sw_bd *rx_buf;
5134         struct l2_fhdr *rx_hdr;
5135         int ret = -ENODEV;
5136         struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5137
5138         tx_napi = bnapi;
5139         if (bp->flags & BNX2_FLAG_USING_MSIX)
5140                 tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
5141
5142         if (loopback_mode == BNX2_MAC_LOOPBACK) {
5143                 bp->loopback = MAC_LOOPBACK;
5144                 bnx2_set_mac_loopback(bp);
5145         }
5146         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5147                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5148                         return 0;
5149
5150                 bp->loopback = PHY_LOOPBACK;
5151                 bnx2_set_phy_loopback(bp);
5152         }
5153         else
5154                 return -EINVAL;
5155
5156         pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5157         skb = netdev_alloc_skb(bp->dev, pkt_size);
5158         if (!skb)
5159                 return -ENOMEM;
5160         packet = skb_put(skb, pkt_size);
5161         memcpy(packet, bp->dev->dev_addr, 6);
5162         memset(packet + 6, 0x0, 8);
5163         for (i = 14; i < pkt_size; i++)
5164                 packet[i] = (unsigned char) (i & 0xff);
5165
5166         map = pci_map_single(bp->pdev, skb->data, pkt_size,
5167                 PCI_DMA_TODEVICE);
5168
5169         REG_WR(bp, BNX2_HC_COMMAND,
5170                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5171
5172         REG_RD(bp, BNX2_HC_COMMAND);
5173
5174         udelay(5);
5175         rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5176
5177         num_pkts = 0;
5178
5179         txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
5180
5181         txbd->tx_bd_haddr_hi = (u64) map >> 32;
5182         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5183         txbd->tx_bd_mss_nbytes = pkt_size;
5184         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5185
5186         num_pkts++;
5187         bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
5188         bp->tx_prod_bseq += pkt_size;
5189
5190         REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
5191         REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5192
5193         udelay(100);
5194
5195         REG_WR(bp, BNX2_HC_COMMAND,
5196                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5197
5198         REG_RD(bp, BNX2_HC_COMMAND);
5199
5200         udelay(5);
5201
5202         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5203         dev_kfree_skb(skb);
5204
5205         if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod)
5206                 goto loopback_test_done;
5207
5208         rx_idx = bnx2_get_hw_rx_cons(bnapi);
5209         if (rx_idx != rx_start_idx + num_pkts) {
5210                 goto loopback_test_done;
5211         }
5212
5213         rx_buf = &bp->rx_buf_ring[rx_start_idx];
5214         rx_skb = rx_buf->skb;
5215
5216         rx_hdr = (struct l2_fhdr *) rx_skb->data;
5217         skb_reserve(rx_skb, bp->rx_offset);
5218
5219         pci_dma_sync_single_for_cpu(bp->pdev,
5220                 pci_unmap_addr(rx_buf, mapping),
5221                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5222
5223         if (rx_hdr->l2_fhdr_status &
5224                 (L2_FHDR_ERRORS_BAD_CRC |
5225                 L2_FHDR_ERRORS_PHY_DECODE |
5226                 L2_FHDR_ERRORS_ALIGNMENT |
5227                 L2_FHDR_ERRORS_TOO_SHORT |
5228                 L2_FHDR_ERRORS_GIANT_FRAME)) {
5229
5230                 goto loopback_test_done;
5231         }
5232
5233         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5234                 goto loopback_test_done;
5235         }
5236
5237         for (i = 14; i < pkt_size; i++) {
5238                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5239                         goto loopback_test_done;
5240                 }
5241         }
5242
5243         ret = 0;
5244
5245 loopback_test_done:
5246         bp->loopback = 0;
5247         return ret;
5248 }
5249
5250 #define BNX2_MAC_LOOPBACK_FAILED        1
5251 #define BNX2_PHY_LOOPBACK_FAILED        2
5252 #define BNX2_LOOPBACK_FAILED            (BNX2_MAC_LOOPBACK_FAILED |     \
5253                                          BNX2_PHY_LOOPBACK_FAILED)
5254
5255 static int
5256 bnx2_test_loopback(struct bnx2 *bp)
5257 {
5258         int rc = 0;
5259
5260         if (!netif_running(bp->dev))
5261                 return BNX2_LOOPBACK_FAILED;
5262
5263         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5264         spin_lock_bh(&bp->phy_lock);
5265         bnx2_init_phy(bp);
5266         spin_unlock_bh(&bp->phy_lock);
5267         if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5268                 rc |= BNX2_MAC_LOOPBACK_FAILED;
5269         if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5270                 rc |= BNX2_PHY_LOOPBACK_FAILED;
5271         return rc;
5272 }
5273
5274 #define NVRAM_SIZE 0x200
5275 #define CRC32_RESIDUAL 0xdebb20e3
5276
5277 static int
5278 bnx2_test_nvram(struct bnx2 *bp)
5279 {
5280         __be32 buf[NVRAM_SIZE / 4];
5281         u8 *data = (u8 *) buf;
5282         int rc = 0;
5283         u32 magic, csum;
5284
5285         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5286                 goto test_nvram_done;
5287
5288         magic = be32_to_cpu(buf[0]);
5289         if (magic != 0x669955aa) {
5290                 rc = -ENODEV;
5291                 goto test_nvram_done;
5292         }
5293
5294         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5295                 goto test_nvram_done;
5296
5297         csum = ether_crc_le(0x100, data);
5298         if (csum != CRC32_RESIDUAL) {
5299                 rc = -ENODEV;
5300                 goto test_nvram_done;
5301         }
5302
5303         csum = ether_crc_le(0x100, data + 0x100);
5304         if (csum != CRC32_RESIDUAL) {
5305                 rc = -ENODEV;
5306         }
5307
5308 test_nvram_done:
5309         return rc;
5310 }
5311
5312 static int
5313 bnx2_test_link(struct bnx2 *bp)
5314 {
5315         u32 bmsr;
5316
5317         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5318                 if (bp->link_up)
5319                         return 0;
5320                 return -ENODEV;
5321         }
5322         spin_lock_bh(&bp->phy_lock);
5323         bnx2_enable_bmsr1(bp);
5324         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5325         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5326         bnx2_disable_bmsr1(bp);
5327         spin_unlock_bh(&bp->phy_lock);
5328
5329         if (bmsr & BMSR_LSTATUS) {
5330                 return 0;
5331         }
5332         return -ENODEV;
5333 }
5334
5335 static int
5336 bnx2_test_intr(struct bnx2 *bp)
5337 {
5338         int i;
5339         u16 status_idx;
5340
5341         if (!netif_running(bp->dev))
5342                 return -ENODEV;
5343
5344         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5345
5346         /* This register is not touched during run-time. */
5347         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5348         REG_RD(bp, BNX2_HC_COMMAND);
5349
5350         for (i = 0; i < 10; i++) {
5351                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5352                         status_idx) {
5353
5354                         break;
5355                 }
5356
5357                 msleep_interruptible(10);
5358         }
5359         if (i < 10)
5360                 return 0;
5361
5362         return -ENODEV;
5363 }
5364
5365 /* Determining link for parallel detection. */
5366 static int
5367 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5368 {
5369         u32 mode_ctl, an_dbg, exp;
5370
5371         if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5372                 return 0;
5373
5374         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5375         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5376
5377         if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5378                 return 0;
5379
5380         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5381         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5382         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5383
5384         if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5385                 return 0;
5386
5387         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5388         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5389         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5390
5391         if (exp & MII_EXPAND_REG1_RUDI_C)       /* receiving CONFIG */
5392                 return 0;
5393
5394         return 1;
5395 }
5396
5397 static void
5398 bnx2_5706_serdes_timer(struct bnx2 *bp)
5399 {
5400         int check_link = 1;
5401
5402         spin_lock(&bp->phy_lock);
5403         if (bp->serdes_an_pending) {
5404                 bp->serdes_an_pending--;
5405                 check_link = 0;
5406         } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5407                 u32 bmcr;
5408
5409                 bp->current_interval = bp->timer_interval;
5410
5411                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5412
5413                 if (bmcr & BMCR_ANENABLE) {
5414                         if (bnx2_5706_serdes_has_link(bp)) {
5415                                 bmcr &= ~BMCR_ANENABLE;
5416                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5417                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5418                                 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5419                         }
5420                 }
5421         }
5422         else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5423                  (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5424                 u32 phy2;
5425
5426                 bnx2_write_phy(bp, 0x17, 0x0f01);
5427                 bnx2_read_phy(bp, 0x15, &phy2);
5428                 if (phy2 & 0x20) {
5429                         u32 bmcr;
5430
5431                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5432                         bmcr |= BMCR_ANENABLE;
5433                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5434
5435                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5436                 }
5437         } else
5438                 bp->current_interval = bp->timer_interval;
5439
5440         if (check_link) {
5441                 u32 val;
5442
5443                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5444                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5445                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5446
5447                 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5448                         if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5449                                 bnx2_5706s_force_link_dn(bp, 1);
5450                                 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5451                         } else
5452                                 bnx2_set_link(bp);
5453                 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5454                         bnx2_set_link(bp);
5455         }
5456         spin_unlock(&bp->phy_lock);
5457 }
5458
5459 static void
5460 bnx2_5708_serdes_timer(struct bnx2 *bp)
5461 {
5462         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5463                 return;
5464
5465         if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5466                 bp->serdes_an_pending = 0;
5467                 return;
5468         }
5469
5470         spin_lock(&bp->phy_lock);
5471         if (bp->serdes_an_pending)
5472                 bp->serdes_an_pending--;
5473         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5474                 u32 bmcr;
5475
5476                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5477                 if (bmcr & BMCR_ANENABLE) {
5478                         bnx2_enable_forced_2g5(bp);
5479                         bp->current_interval = SERDES_FORCED_TIMEOUT;
5480                 } else {
5481                         bnx2_disable_forced_2g5(bp);
5482                         bp->serdes_an_pending = 2;
5483                         bp->current_interval = bp->timer_interval;
5484                 }
5485
5486         } else
5487                 bp->current_interval = bp->timer_interval;
5488
5489         spin_unlock(&bp->phy_lock);
5490 }
5491
5492 static void
5493 bnx2_timer(unsigned long data)
5494 {
5495         struct bnx2 *bp = (struct bnx2 *) data;
5496
5497         if (!netif_running(bp->dev))
5498                 return;
5499
5500         if (atomic_read(&bp->intr_sem) != 0)
5501                 goto bnx2_restart_timer;
5502
5503         bnx2_send_heart_beat(bp);
5504
5505         bp->stats_blk->stat_FwRxDrop =
5506                 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5507
5508         /* workaround occasional corrupted counters */
5509         if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5510                 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5511                                             BNX2_HC_COMMAND_STATS_NOW);
5512
5513         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5514                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5515                         bnx2_5706_serdes_timer(bp);
5516                 else
5517                         bnx2_5708_serdes_timer(bp);
5518         }
5519
5520 bnx2_restart_timer:
5521         mod_timer(&bp->timer, jiffies + bp->current_interval);
5522 }
5523
5524 static int
5525 bnx2_request_irq(struct bnx2 *bp)
5526 {
5527         struct net_device *dev = bp->dev;
5528         unsigned long flags;
5529         struct bnx2_irq *irq;
5530         int rc = 0, i;
5531
5532         if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5533                 flags = 0;
5534         else
5535                 flags = IRQF_SHARED;
5536
5537         for (i = 0; i < bp->irq_nvecs; i++) {
5538                 irq = &bp->irq_tbl[i];
5539                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5540                                  dev);
5541                 if (rc)
5542                         break;
5543                 irq->requested = 1;
5544         }
5545         return rc;
5546 }
5547
5548 static void
5549 bnx2_free_irq(struct bnx2 *bp)
5550 {
5551         struct net_device *dev = bp->dev;
5552         struct bnx2_irq *irq;
5553         int i;
5554
5555         for (i = 0; i < bp->irq_nvecs; i++) {
5556                 irq = &bp->irq_tbl[i];
5557                 if (irq->requested)
5558                         free_irq(irq->vector, dev);
5559                 irq->requested = 0;
5560         }
5561         if (bp->flags & BNX2_FLAG_USING_MSI)
5562                 pci_disable_msi(bp->pdev);
5563         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5564                 pci_disable_msix(bp->pdev);
5565
5566         bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5567 }
5568
5569 static void
5570 bnx2_enable_msix(struct bnx2 *bp)
5571 {
5572         int i, rc;
5573         struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5574
5575         bnx2_setup_msix_tbl(bp);
5576         REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5577         REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5578         REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5579
5580         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5581                 msix_ent[i].entry = i;
5582                 msix_ent[i].vector = 0;
5583         }
5584
5585         rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5586         if (rc != 0)
5587                 return;
5588
5589         bp->irq_tbl[BNX2_BASE_VEC].handler = bnx2_msi_1shot;
5590         bp->irq_tbl[BNX2_TX_VEC].handler = bnx2_tx_msix;
5591
5592         strcpy(bp->irq_tbl[BNX2_BASE_VEC].name, bp->dev->name);
5593         strcat(bp->irq_tbl[BNX2_BASE_VEC].name, "-base");
5594         strcpy(bp->irq_tbl[BNX2_TX_VEC].name, bp->dev->name);
5595         strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx");
5596
5597         bp->irq_nvecs = BNX2_MAX_MSIX_VEC;
5598         bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5599         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5600                 bp->irq_tbl[i].vector = msix_ent[i].vector;
5601 }
5602
5603 static void
5604 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5605 {
5606         bp->irq_tbl[0].handler = bnx2_interrupt;
5607         strcpy(bp->irq_tbl[0].name, bp->dev->name);
5608         bp->irq_nvecs = 1;
5609         bp->irq_tbl[0].vector = bp->pdev->irq;
5610
5611         if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5612                 bnx2_enable_msix(bp);
5613
5614         if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5615             !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5616                 if (pci_enable_msi(bp->pdev) == 0) {
5617                         bp->flags |= BNX2_FLAG_USING_MSI;
5618                         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5619                                 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5620                                 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5621                         } else
5622                                 bp->irq_tbl[0].handler = bnx2_msi;
5623
5624                         bp->irq_tbl[0].vector = bp->pdev->irq;
5625                 }
5626         }
5627 }
5628
5629 /* Called with rtnl_lock */
5630 static int
5631 bnx2_open(struct net_device *dev)
5632 {
5633         struct bnx2 *bp = netdev_priv(dev);
5634         int rc;
5635
5636         netif_carrier_off(dev);
5637
5638         bnx2_set_power_state(bp, PCI_D0);
5639         bnx2_disable_int(bp);
5640
5641         rc = bnx2_alloc_mem(bp);
5642         if (rc)
5643                 return rc;
5644
5645         bnx2_setup_int_mode(bp, disable_msi);
5646         bnx2_napi_enable(bp);
5647         rc = bnx2_request_irq(bp);
5648
5649         if (rc) {
5650                 bnx2_napi_disable(bp);
5651                 bnx2_free_mem(bp);
5652                 return rc;
5653         }
5654
5655         rc = bnx2_init_nic(bp);
5656
5657         if (rc) {
5658                 bnx2_napi_disable(bp);
5659                 bnx2_free_irq(bp);
5660                 bnx2_free_skbs(bp);
5661                 bnx2_free_mem(bp);
5662                 return rc;
5663         }
5664
5665         mod_timer(&bp->timer, jiffies + bp->current_interval);
5666
5667         atomic_set(&bp->intr_sem, 0);
5668
5669         bnx2_enable_int(bp);
5670
5671         if (bp->flags & BNX2_FLAG_USING_MSI) {
5672                 /* Test MSI to make sure it is working
5673                  * If MSI test fails, go back to INTx mode
5674                  */
5675                 if (bnx2_test_intr(bp) != 0) {
5676                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
5677                                " using MSI, switching to INTx mode. Please"
5678                                " report this failure to the PCI maintainer"
5679                                " and include system chipset information.\n",
5680                                bp->dev->name);
5681
5682                         bnx2_disable_int(bp);
5683                         bnx2_free_irq(bp);
5684
5685                         bnx2_setup_int_mode(bp, 1);
5686
5687                         rc = bnx2_init_nic(bp);
5688
5689                         if (!rc)
5690                                 rc = bnx2_request_irq(bp);
5691
5692                         if (rc) {
5693                                 bnx2_napi_disable(bp);
5694                                 bnx2_free_skbs(bp);
5695                                 bnx2_free_mem(bp);
5696                                 del_timer_sync(&bp->timer);
5697                                 return rc;
5698                         }
5699                         bnx2_enable_int(bp);
5700                 }
5701         }
5702         if (bp->flags & BNX2_FLAG_USING_MSI)
5703                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5704         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5705                 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5706
5707         netif_start_queue(dev);
5708
5709         return 0;
5710 }
5711
5712 static void
5713 bnx2_reset_task(struct work_struct *work)
5714 {
5715         struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5716
5717         if (!netif_running(bp->dev))
5718                 return;
5719
5720         bp->in_reset_task = 1;
5721         bnx2_netif_stop(bp);
5722
5723         bnx2_init_nic(bp);
5724
5725         atomic_set(&bp->intr_sem, 1);
5726         bnx2_netif_start(bp);
5727         bp->in_reset_task = 0;
5728 }
5729
5730 static void
5731 bnx2_tx_timeout(struct net_device *dev)
5732 {
5733         struct bnx2 *bp = netdev_priv(dev);
5734
5735         /* This allows the netif to be shutdown gracefully before resetting */
5736         schedule_work(&bp->reset_task);
5737 }
5738
5739 #ifdef BCM_VLAN
5740 /* Called with rtnl_lock */
5741 static void
5742 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5743 {
5744         struct bnx2 *bp = netdev_priv(dev);
5745
5746         bnx2_netif_stop(bp);
5747
5748         bp->vlgrp = vlgrp;
5749         bnx2_set_rx_mode(dev);
5750
5751         bnx2_netif_start(bp);
5752 }
5753 #endif
5754
5755 /* Called with netif_tx_lock.
5756  * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5757  * netif_wake_queue().
5758  */
5759 static int
5760 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5761 {
5762         struct bnx2 *bp = netdev_priv(dev);
5763         dma_addr_t mapping;
5764         struct tx_bd *txbd;
5765         struct sw_bd *tx_buf;
5766         u32 len, vlan_tag_flags, last_frag, mss;
5767         u16 prod, ring_prod;
5768         int i;
5769         struct bnx2_napi *bnapi = &bp->bnx2_napi[bp->tx_vec];
5770
5771         if (unlikely(bnx2_tx_avail(bp, bnapi) <
5772             (skb_shinfo(skb)->nr_frags + 1))) {
5773                 netif_stop_queue(dev);
5774                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5775                         dev->name);
5776
5777                 return NETDEV_TX_BUSY;
5778         }
5779         len = skb_headlen(skb);
5780         prod = bp->tx_prod;
5781         ring_prod = TX_RING_IDX(prod);
5782
5783         vlan_tag_flags = 0;
5784         if (skb->ip_summed == CHECKSUM_PARTIAL) {
5785                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5786         }
5787
5788         if (bp->vlgrp && vlan_tx_tag_present(skb)) {
5789                 vlan_tag_flags |=
5790                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5791         }
5792         if ((mss = skb_shinfo(skb)->gso_size)) {
5793                 u32 tcp_opt_len, ip_tcp_len;
5794                 struct iphdr *iph;
5795
5796                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5797
5798                 tcp_opt_len = tcp_optlen(skb);
5799
5800                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5801                         u32 tcp_off = skb_transport_offset(skb) -
5802                                       sizeof(struct ipv6hdr) - ETH_HLEN;
5803
5804                         vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5805                                           TX_BD_FLAGS_SW_FLAGS;
5806                         if (likely(tcp_off == 0))
5807                                 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5808                         else {
5809                                 tcp_off >>= 3;
5810                                 vlan_tag_flags |= ((tcp_off & 0x3) <<
5811                                                    TX_BD_FLAGS_TCP6_OFF0_SHL) |
5812                                                   ((tcp_off & 0x10) <<
5813                                                    TX_BD_FLAGS_TCP6_OFF4_SHL);
5814                                 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5815                         }
5816                 } else {
5817                         if (skb_header_cloned(skb) &&
5818                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5819                                 dev_kfree_skb(skb);
5820                                 return NETDEV_TX_OK;
5821                         }
5822
5823                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5824
5825                         iph = ip_hdr(skb);
5826                         iph->check = 0;
5827                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5828                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5829                                                                  iph->daddr, 0,
5830                                                                  IPPROTO_TCP,
5831                                                                  0);
5832                         if (tcp_opt_len || (iph->ihl > 5)) {
5833                                 vlan_tag_flags |= ((iph->ihl - 5) +
5834                                                    (tcp_opt_len >> 2)) << 8;
5835                         }
5836                 }
5837         } else
5838                 mss = 0;
5839
5840         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5841
5842         tx_buf = &bp->tx_buf_ring[ring_prod];
5843         tx_buf->skb = skb;
5844         pci_unmap_addr_set(tx_buf, mapping, mapping);
5845
5846         txbd = &bp->tx_desc_ring[ring_prod];
5847
5848         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5849         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5850         txbd->tx_bd_mss_nbytes = len | (mss << 16);
5851         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5852
5853         last_frag = skb_shinfo(skb)->nr_frags;
5854
5855         for (i = 0; i < last_frag; i++) {
5856                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5857
5858                 prod = NEXT_TX_BD(prod);
5859                 ring_prod = TX_RING_IDX(prod);
5860                 txbd = &bp->tx_desc_ring[ring_prod];
5861
5862                 len = frag->size;
5863                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5864                         len, PCI_DMA_TODEVICE);
5865                 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5866                                 mapping, mapping);
5867
5868                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5869                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5870                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5871                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5872
5873         }
5874         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5875
5876         prod = NEXT_TX_BD(prod);
5877         bp->tx_prod_bseq += skb->len;
5878
5879         REG_WR16(bp, bp->tx_bidx_addr, prod);
5880         REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5881
5882         mmiowb();
5883
5884         bp->tx_prod = prod;
5885         dev->trans_start = jiffies;
5886
5887         if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) {
5888                 netif_stop_queue(dev);
5889                 if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)
5890                         netif_wake_queue(dev);
5891         }
5892
5893         return NETDEV_TX_OK;
5894 }
5895
5896 /* Called with rtnl_lock */
5897 static int
5898 bnx2_close(struct net_device *dev)
5899 {
5900         struct bnx2 *bp = netdev_priv(dev);
5901         u32 reset_code;
5902
5903         /* Calling flush_scheduled_work() may deadlock because
5904          * linkwatch_event() may be on the workqueue and it will try to get
5905          * the rtnl_lock which we are holding.
5906          */
5907         while (bp->in_reset_task)
5908                 msleep(1);
5909
5910         bnx2_disable_int_sync(bp);
5911         bnx2_napi_disable(bp);
5912         del_timer_sync(&bp->timer);
5913         if (bp->flags & BNX2_FLAG_NO_WOL)
5914                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5915         else if (bp->wol)
5916                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5917         else
5918                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5919         bnx2_reset_chip(bp, reset_code);
5920         bnx2_free_irq(bp);
5921         bnx2_free_skbs(bp);
5922         bnx2_free_mem(bp);
5923         bp->link_up = 0;
5924         netif_carrier_off(bp->dev);
5925         bnx2_set_power_state(bp, PCI_D3hot);
5926         return 0;
5927 }
5928
5929 #define GET_NET_STATS64(ctr)                                    \
5930         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
5931         (unsigned long) (ctr##_lo)
5932
5933 #define GET_NET_STATS32(ctr)            \
5934         (ctr##_lo)
5935
5936 #if (BITS_PER_LONG == 64)
5937 #define GET_NET_STATS   GET_NET_STATS64
5938 #else
5939 #define GET_NET_STATS   GET_NET_STATS32
5940 #endif
5941
5942 static struct net_device_stats *
5943 bnx2_get_stats(struct net_device *dev)
5944 {
5945         struct bnx2 *bp = netdev_priv(dev);
5946         struct statistics_block *stats_blk = bp->stats_blk;
5947         struct net_device_stats *net_stats = &bp->net_stats;
5948
5949         if (bp->stats_blk == NULL) {
5950                 return net_stats;
5951         }
5952         net_stats->rx_packets =
5953                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5954                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5955                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5956
5957         net_stats->tx_packets =
5958                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5959                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5960                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5961
5962         net_stats->rx_bytes =
5963                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5964
5965         net_stats->tx_bytes =
5966                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5967
5968         net_stats->multicast =
5969                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5970
5971         net_stats->collisions =
5972                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5973
5974         net_stats->rx_length_errors =
5975                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5976                 stats_blk->stat_EtherStatsOverrsizePkts);
5977
5978         net_stats->rx_over_errors =
5979                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5980
5981         net_stats->rx_frame_errors =
5982                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5983
5984         net_stats->rx_crc_errors =
5985                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5986
5987         net_stats->rx_errors = net_stats->rx_length_errors +
5988                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
5989                 net_stats->rx_crc_errors;
5990
5991         net_stats->tx_aborted_errors =
5992                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
5993                 stats_blk->stat_Dot3StatsLateCollisions);
5994
5995         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
5996             (CHIP_ID(bp) == CHIP_ID_5708_A0))
5997                 net_stats->tx_carrier_errors = 0;
5998         else {
5999                 net_stats->tx_carrier_errors =
6000                         (unsigned long)
6001                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
6002         }
6003
6004         net_stats->tx_errors =
6005                 (unsigned long)
6006                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6007                 +
6008                 net_stats->tx_aborted_errors +
6009                 net_stats->tx_carrier_errors;
6010
6011         net_stats->rx_missed_errors =
6012                 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6013                 stats_blk->stat_FwRxDrop);
6014
6015         return net_stats;
6016 }
6017
6018 /* All ethtool functions called with rtnl_lock */
6019
6020 static int
6021 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6022 {
6023         struct bnx2 *bp = netdev_priv(dev);
6024         int support_serdes = 0, support_copper = 0;
6025
6026         cmd->supported = SUPPORTED_Autoneg;
6027         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6028                 support_serdes = 1;
6029                 support_copper = 1;
6030         } else if (bp->phy_port == PORT_FIBRE)
6031                 support_serdes = 1;
6032         else
6033                 support_copper = 1;
6034
6035         if (support_serdes) {
6036                 cmd->supported |= SUPPORTED_1000baseT_Full |
6037                         SUPPORTED_FIBRE;
6038                 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6039                         cmd->supported |= SUPPORTED_2500baseX_Full;
6040
6041         }
6042         if (support_copper) {
6043                 cmd->supported |= SUPPORTED_10baseT_Half |
6044                         SUPPORTED_10baseT_Full |
6045                         SUPPORTED_100baseT_Half |
6046                         SUPPORTED_100baseT_Full |
6047                         SUPPORTED_1000baseT_Full |
6048                         SUPPORTED_TP;
6049
6050         }
6051
6052         spin_lock_bh(&bp->phy_lock);
6053         cmd->port = bp->phy_port;
6054         cmd->advertising = bp->advertising;
6055
6056         if (bp->autoneg & AUTONEG_SPEED) {
6057                 cmd->autoneg = AUTONEG_ENABLE;
6058         }
6059         else {
6060                 cmd->autoneg = AUTONEG_DISABLE;
6061         }
6062
6063         if (netif_carrier_ok(dev)) {
6064                 cmd->speed = bp->line_speed;
6065                 cmd->duplex = bp->duplex;
6066         }
6067         else {
6068                 cmd->speed = -1;
6069                 cmd->duplex = -1;
6070         }
6071         spin_unlock_bh(&bp->phy_lock);
6072
6073         cmd->transceiver = XCVR_INTERNAL;
6074         cmd->phy_address = bp->phy_addr;
6075
6076         return 0;
6077 }
6078
6079 static int
6080 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6081 {
6082         struct bnx2 *bp = netdev_priv(dev);
6083         u8 autoneg = bp->autoneg;
6084         u8 req_duplex = bp->req_duplex;
6085         u16 req_line_speed = bp->req_line_speed;
6086         u32 advertising = bp->advertising;
6087         int err = -EINVAL;
6088
6089         spin_lock_bh(&bp->phy_lock);
6090
6091         if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6092                 goto err_out_unlock;
6093
6094         if (cmd->port != bp->phy_port &&
6095             !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6096                 goto err_out_unlock;
6097
6098         if (cmd->autoneg == AUTONEG_ENABLE) {
6099                 autoneg |= AUTONEG_SPEED;
6100
6101                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6102
6103                 /* allow advertising 1 speed */
6104                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6105                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
6106                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
6107                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
6108
6109                         if (cmd->port == PORT_FIBRE)
6110                                 goto err_out_unlock;
6111
6112                         advertising = cmd->advertising;
6113
6114                 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6115                         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6116                             (cmd->port == PORT_TP))
6117                                 goto err_out_unlock;
6118                 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6119                         advertising = cmd->advertising;
6120                 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6121                         goto err_out_unlock;
6122                 else {
6123                         if (cmd->port == PORT_FIBRE)
6124                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6125                         else
6126                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
6127                 }
6128                 advertising |= ADVERTISED_Autoneg;
6129         }
6130         else {
6131                 if (cmd->port == PORT_FIBRE) {
6132                         if ((cmd->speed != SPEED_1000 &&
6133                              cmd->speed != SPEED_2500) ||
6134                             (cmd->duplex != DUPLEX_FULL))
6135                                 goto err_out_unlock;
6136
6137                         if (cmd->speed == SPEED_2500 &&
6138                             !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6139                                 goto err_out_unlock;
6140                 }
6141                 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6142                         goto err_out_unlock;
6143
6144                 autoneg &= ~AUTONEG_SPEED;
6145                 req_line_speed = cmd->speed;
6146                 req_duplex = cmd->duplex;
6147                 advertising = 0;
6148         }
6149
6150         bp->autoneg = autoneg;
6151         bp->advertising = advertising;
6152         bp->req_line_speed = req_line_speed;
6153         bp->req_duplex = req_duplex;
6154
6155         err = bnx2_setup_phy(bp, cmd->port);
6156
6157 err_out_unlock:
6158         spin_unlock_bh(&bp->phy_lock);
6159
6160         return err;
6161 }
6162
6163 static void
6164 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6165 {
6166         struct bnx2 *bp = netdev_priv(dev);
6167
6168         strcpy(info->driver, DRV_MODULE_NAME);
6169         strcpy(info->version, DRV_MODULE_VERSION);
6170         strcpy(info->bus_info, pci_name(bp->pdev));
6171         strcpy(info->fw_version, bp->fw_version);
6172 }
6173
6174 #define BNX2_REGDUMP_LEN                (32 * 1024)
6175
6176 static int
6177 bnx2_get_regs_len(struct net_device *dev)
6178 {
6179         return BNX2_REGDUMP_LEN;
6180 }
6181
6182 static void
6183 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6184 {
6185         u32 *p = _p, i, offset;
6186         u8 *orig_p = _p;
6187         struct bnx2 *bp = netdev_priv(dev);
6188         u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6189                                  0x0800, 0x0880, 0x0c00, 0x0c10,
6190                                  0x0c30, 0x0d08, 0x1000, 0x101c,
6191                                  0x1040, 0x1048, 0x1080, 0x10a4,
6192                                  0x1400, 0x1490, 0x1498, 0x14f0,
6193                                  0x1500, 0x155c, 0x1580, 0x15dc,
6194                                  0x1600, 0x1658, 0x1680, 0x16d8,
6195                                  0x1800, 0x1820, 0x1840, 0x1854,
6196                                  0x1880, 0x1894, 0x1900, 0x1984,
6197                                  0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6198                                  0x1c80, 0x1c94, 0x1d00, 0x1d84,
6199                                  0x2000, 0x2030, 0x23c0, 0x2400,
6200                                  0x2800, 0x2820, 0x2830, 0x2850,
6201                                  0x2b40, 0x2c10, 0x2fc0, 0x3058,
6202                                  0x3c00, 0x3c94, 0x4000, 0x4010,
6203                                  0x4080, 0x4090, 0x43c0, 0x4458,
6204                                  0x4c00, 0x4c18, 0x4c40, 0x4c54,
6205                                  0x4fc0, 0x5010, 0x53c0, 0x5444,
6206                                  0x5c00, 0x5c18, 0x5c80, 0x5c90,
6207                                  0x5fc0, 0x6000, 0x6400, 0x6428,
6208                                  0x6800, 0x6848, 0x684c, 0x6860,
6209                                  0x6888, 0x6910, 0x8000 };
6210
6211         regs->version = 0;
6212
6213         memset(p, 0, BNX2_REGDUMP_LEN);
6214
6215         if (!netif_running(bp->dev))
6216                 return;
6217
6218         i = 0;
6219         offset = reg_boundaries[0];
6220         p += offset;
6221         while (offset < BNX2_REGDUMP_LEN) {
6222                 *p++ = REG_RD(bp, offset);
6223                 offset += 4;
6224                 if (offset == reg_boundaries[i + 1]) {
6225                         offset = reg_boundaries[i + 2];
6226                         p = (u32 *) (orig_p + offset);
6227                         i += 2;
6228                 }
6229         }
6230 }
6231
6232 static void
6233 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6234 {
6235         struct bnx2 *bp = netdev_priv(dev);
6236
6237         if (bp->flags & BNX2_FLAG_NO_WOL) {
6238                 wol->supported = 0;
6239                 wol->wolopts = 0;
6240         }
6241         else {
6242                 wol->supported = WAKE_MAGIC;
6243                 if (bp->wol)
6244                         wol->wolopts = WAKE_MAGIC;
6245                 else
6246                         wol->wolopts = 0;
6247         }
6248         memset(&wol->sopass, 0, sizeof(wol->sopass));
6249 }
6250
6251 static int
6252 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6253 {
6254         struct bnx2 *bp = netdev_priv(dev);
6255
6256         if (wol->wolopts & ~WAKE_MAGIC)
6257                 return -EINVAL;
6258
6259         if (wol->wolopts & WAKE_MAGIC) {
6260                 if (bp->flags & BNX2_FLAG_NO_WOL)
6261                         return -EINVAL;
6262
6263                 bp->wol = 1;
6264         }
6265         else {
6266                 bp->wol = 0;
6267         }
6268         return 0;
6269 }
6270
6271 static int
6272 bnx2_nway_reset(struct net_device *dev)
6273 {
6274         struct bnx2 *bp = netdev_priv(dev);
6275         u32 bmcr;
6276
6277         if (!(bp->autoneg & AUTONEG_SPEED)) {
6278                 return -EINVAL;
6279         }
6280
6281         spin_lock_bh(&bp->phy_lock);
6282
6283         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6284                 int rc;
6285
6286                 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6287                 spin_unlock_bh(&bp->phy_lock);
6288                 return rc;
6289         }
6290
6291         /* Force a link down visible on the other side */
6292         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6293                 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6294                 spin_unlock_bh(&bp->phy_lock);
6295
6296                 msleep(20);
6297
6298                 spin_lock_bh(&bp->phy_lock);
6299
6300                 bp->current_interval = SERDES_AN_TIMEOUT;
6301                 bp->serdes_an_pending = 1;
6302                 mod_timer(&bp->timer, jiffies + bp->current_interval);
6303         }
6304
6305         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6306         bmcr &= ~BMCR_LOOPBACK;
6307         bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6308
6309         spin_unlock_bh(&bp->phy_lock);
6310
6311         return 0;
6312 }
6313
6314 static int
6315 bnx2_get_eeprom_len(struct net_device *dev)
6316 {
6317         struct bnx2 *bp = netdev_priv(dev);
6318
6319         if (bp->flash_info == NULL)
6320                 return 0;
6321
6322         return (int) bp->flash_size;
6323 }
6324
6325 static int
6326 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6327                 u8 *eebuf)
6328 {
6329         struct bnx2 *bp = netdev_priv(dev);
6330         int rc;
6331
6332         /* parameters already validated in ethtool_get_eeprom */
6333
6334         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6335
6336         return rc;
6337 }
6338
6339 static int
6340 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6341                 u8 *eebuf)
6342 {
6343         struct bnx2 *bp = netdev_priv(dev);
6344         int rc;
6345
6346         /* parameters already validated in ethtool_set_eeprom */
6347
6348         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6349
6350         return rc;
6351 }
6352
6353 static int
6354 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6355 {
6356         struct bnx2 *bp = netdev_priv(dev);
6357
6358         memset(coal, 0, sizeof(struct ethtool_coalesce));
6359
6360         coal->rx_coalesce_usecs = bp->rx_ticks;
6361         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6362         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6363         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6364
6365         coal->tx_coalesce_usecs = bp->tx_ticks;
6366         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6367         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6368         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6369
6370         coal->stats_block_coalesce_usecs = bp->stats_ticks;
6371
6372         return 0;
6373 }
6374
6375 static int
6376 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6377 {
6378         struct bnx2 *bp = netdev_priv(dev);
6379
6380         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6381         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6382
6383         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6384         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6385
6386         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6387         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6388
6389         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6390         if (bp->rx_quick_cons_trip_int > 0xff)
6391                 bp->rx_quick_cons_trip_int = 0xff;
6392
6393         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6394         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6395
6396         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6397         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6398
6399         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6400         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6401
6402         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6403         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6404                 0xff;
6405
6406         bp->stats_ticks = coal->stats_block_coalesce_usecs;
6407         if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6408                 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6409                         bp->stats_ticks = USEC_PER_SEC;
6410         }
6411         if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6412                 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6413         bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6414
6415         if (netif_running(bp->dev)) {
6416                 bnx2_netif_stop(bp);
6417                 bnx2_init_nic(bp);
6418                 bnx2_netif_start(bp);
6419         }
6420
6421         return 0;
6422 }
6423
6424 static void
6425 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6426 {
6427         struct bnx2 *bp = netdev_priv(dev);
6428
6429         ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6430         ering->rx_mini_max_pending = 0;
6431         ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6432
6433         ering->rx_pending = bp->rx_ring_size;
6434         ering->rx_mini_pending = 0;
6435         ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6436
6437         ering->tx_max_pending = MAX_TX_DESC_CNT;
6438         ering->tx_pending = bp->tx_ring_size;
6439 }
6440
6441 static int
6442 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6443 {
6444         if (netif_running(bp->dev)) {
6445                 bnx2_netif_stop(bp);
6446                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6447                 bnx2_free_skbs(bp);
6448                 bnx2_free_mem(bp);
6449         }
6450
6451         bnx2_set_rx_ring_size(bp, rx);
6452         bp->tx_ring_size = tx;
6453
6454         if (netif_running(bp->dev)) {
6455                 int rc;
6456
6457                 rc = bnx2_alloc_mem(bp);
6458                 if (rc)
6459                         return rc;
6460                 bnx2_init_nic(bp);
6461                 bnx2_netif_start(bp);
6462         }
6463         return 0;
6464 }
6465
6466 static int
6467 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6468 {
6469         struct bnx2 *bp = netdev_priv(dev);
6470         int rc;
6471
6472         if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6473                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6474                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6475
6476                 return -EINVAL;
6477         }
6478         rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6479         return rc;
6480 }
6481
6482 static void
6483 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6484 {
6485         struct bnx2 *bp = netdev_priv(dev);
6486
6487         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6488         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6489         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6490 }
6491
6492 static int
6493 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6494 {
6495         struct bnx2 *bp = netdev_priv(dev);
6496
6497         bp->req_flow_ctrl = 0;
6498         if (epause->rx_pause)
6499                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6500         if (epause->tx_pause)
6501                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6502
6503         if (epause->autoneg) {
6504                 bp->autoneg |= AUTONEG_FLOW_CTRL;
6505         }
6506         else {
6507                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6508         }
6509
6510         spin_lock_bh(&bp->phy_lock);
6511
6512         bnx2_setup_phy(bp, bp->phy_port);
6513
6514         spin_unlock_bh(&bp->phy_lock);
6515
6516         return 0;
6517 }
6518
6519 static u32
6520 bnx2_get_rx_csum(struct net_device *dev)
6521 {
6522         struct bnx2 *bp = netdev_priv(dev);
6523
6524         return bp->rx_csum;
6525 }
6526
6527 static int
6528 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6529 {
6530         struct bnx2 *bp = netdev_priv(dev);
6531
6532         bp->rx_csum = data;
6533         return 0;
6534 }
6535
6536 static int
6537 bnx2_set_tso(struct net_device *dev, u32 data)
6538 {
6539         struct bnx2 *bp = netdev_priv(dev);
6540
6541         if (data) {
6542                 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6543                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6544                         dev->features |= NETIF_F_TSO6;
6545         } else
6546                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6547                                    NETIF_F_TSO_ECN);
6548         return 0;
6549 }
6550
6551 #define BNX2_NUM_STATS 46
6552
6553 static struct {
6554         char string[ETH_GSTRING_LEN];
6555 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6556         { "rx_bytes" },
6557         { "rx_error_bytes" },
6558         { "tx_bytes" },
6559         { "tx_error_bytes" },
6560         { "rx_ucast_packets" },
6561         { "rx_mcast_packets" },
6562         { "rx_bcast_packets" },
6563         { "tx_ucast_packets" },
6564         { "tx_mcast_packets" },
6565         { "tx_bcast_packets" },
6566         { "tx_mac_errors" },
6567         { "tx_carrier_errors" },
6568         { "rx_crc_errors" },
6569         { "rx_align_errors" },
6570         { "tx_single_collisions" },
6571         { "tx_multi_collisions" },
6572         { "tx_deferred" },
6573         { "tx_excess_collisions" },
6574         { "tx_late_collisions" },
6575         { "tx_total_collisions" },
6576         { "rx_fragments" },
6577         { "rx_jabbers" },
6578         { "rx_undersize_packets" },
6579         { "rx_oversize_packets" },
6580         { "rx_64_byte_packets" },
6581         { "rx_65_to_127_byte_packets" },
6582         { "rx_128_to_255_byte_packets" },
6583         { "rx_256_to_511_byte_packets" },
6584         { "rx_512_to_1023_byte_packets" },
6585         { "rx_1024_to_1522_byte_packets" },
6586         { "rx_1523_to_9022_byte_packets" },
6587         { "tx_64_byte_packets" },
6588         { "tx_65_to_127_byte_packets" },
6589         { "tx_128_to_255_byte_packets" },
6590         { "tx_256_to_511_byte_packets" },
6591         { "tx_512_to_1023_byte_packets" },
6592         { "tx_1024_to_1522_byte_packets" },
6593         { "tx_1523_to_9022_byte_packets" },
6594         { "rx_xon_frames" },
6595         { "rx_xoff_frames" },
6596         { "tx_xon_frames" },
6597         { "tx_xoff_frames" },
6598         { "rx_mac_ctrl_frames" },
6599         { "rx_filtered_packets" },
6600         { "rx_discards" },
6601         { "rx_fw_discards" },
6602 };
6603
6604 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6605
6606 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6607     STATS_OFFSET32(stat_IfHCInOctets_hi),
6608     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6609     STATS_OFFSET32(stat_IfHCOutOctets_hi),
6610     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6611     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6612     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6613     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6614     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6615     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6616     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6617     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6618     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6619     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6620     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6621     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6622     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6623     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6624     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6625     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6626     STATS_OFFSET32(stat_EtherStatsCollisions),
6627     STATS_OFFSET32(stat_EtherStatsFragments),
6628     STATS_OFFSET32(stat_EtherStatsJabbers),
6629     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6630     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6631     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6632     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6633     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6634     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6635     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6636     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6637     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6638     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6639     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6640     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6641     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6642     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6643     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6644     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6645     STATS_OFFSET32(stat_XonPauseFramesReceived),
6646     STATS_OFFSET32(stat_XoffPauseFramesReceived),
6647     STATS_OFFSET32(stat_OutXonSent),
6648     STATS_OFFSET32(stat_OutXoffSent),
6649     STATS_OFFSET32(stat_MacControlFramesReceived),
6650     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6651     STATS_OFFSET32(stat_IfInMBUFDiscards),
6652     STATS_OFFSET32(stat_FwRxDrop),
6653 };
6654
6655 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6656  * skipped because of errata.
6657  */
6658 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6659         8,0,8,8,8,8,8,8,8,8,
6660         4,0,4,4,4,4,4,4,4,4,
6661         4,4,4,4,4,4,4,4,4,4,
6662         4,4,4,4,4,4,4,4,4,4,
6663         4,4,4,4,4,4,
6664 };
6665
6666 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6667         8,0,8,8,8,8,8,8,8,8,
6668         4,4,4,4,4,4,4,4,4,4,
6669         4,4,4,4,4,4,4,4,4,4,
6670         4,4,4,4,4,4,4,4,4,4,
6671         4,4,4,4,4,4,
6672 };
6673
6674 #define BNX2_NUM_TESTS 6
6675
6676 static struct {
6677         char string[ETH_GSTRING_LEN];
6678 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6679         { "register_test (offline)" },
6680         { "memory_test (offline)" },
6681         { "loopback_test (offline)" },
6682         { "nvram_test (online)" },
6683         { "interrupt_test (online)" },
6684         { "link_test (online)" },
6685 };
6686
6687 static int
6688 bnx2_get_sset_count(struct net_device *dev, int sset)
6689 {
6690         switch (sset) {
6691         case ETH_SS_TEST:
6692                 return BNX2_NUM_TESTS;
6693         case ETH_SS_STATS:
6694                 return BNX2_NUM_STATS;
6695         default:
6696                 return -EOPNOTSUPP;
6697         }
6698 }
6699
6700 static void
6701 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6702 {
6703         struct bnx2 *bp = netdev_priv(dev);
6704
6705         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6706         if (etest->flags & ETH_TEST_FL_OFFLINE) {
6707                 int i;
6708
6709                 bnx2_netif_stop(bp);
6710                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6711                 bnx2_free_skbs(bp);
6712
6713                 if (bnx2_test_registers(bp) != 0) {
6714                         buf[0] = 1;
6715                         etest->flags |= ETH_TEST_FL_FAILED;
6716                 }
6717                 if (bnx2_test_memory(bp) != 0) {
6718                         buf[1] = 1;
6719                         etest->flags |= ETH_TEST_FL_FAILED;
6720                 }
6721                 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6722                         etest->flags |= ETH_TEST_FL_FAILED;
6723
6724                 if (!netif_running(bp->dev)) {
6725                         bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6726                 }
6727                 else {
6728                         bnx2_init_nic(bp);
6729                         bnx2_netif_start(bp);
6730                 }
6731
6732                 /* wait for link up */
6733                 for (i = 0; i < 7; i++) {
6734                         if (bp->link_up)
6735                                 break;
6736                         msleep_interruptible(1000);
6737                 }
6738         }
6739
6740         if (bnx2_test_nvram(bp) != 0) {
6741                 buf[3] = 1;
6742                 etest->flags |= ETH_TEST_FL_FAILED;
6743         }
6744         if (bnx2_test_intr(bp) != 0) {
6745                 buf[4] = 1;
6746                 etest->flags |= ETH_TEST_FL_FAILED;
6747         }
6748
6749         if (bnx2_test_link(bp) != 0) {
6750                 buf[5] = 1;
6751                 etest->flags |= ETH_TEST_FL_FAILED;
6752
6753         }
6754 }
6755
6756 static void
6757 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6758 {
6759         switch (stringset) {
6760         case ETH_SS_STATS:
6761                 memcpy(buf, bnx2_stats_str_arr,
6762                         sizeof(bnx2_stats_str_arr));
6763                 break;
6764         case ETH_SS_TEST:
6765                 memcpy(buf, bnx2_tests_str_arr,
6766                         sizeof(bnx2_tests_str_arr));
6767                 break;
6768         }
6769 }
6770
6771 static void
6772 bnx2_get_ethtool_stats(struct net_device *dev,
6773                 struct ethtool_stats *stats, u64 *buf)
6774 {
6775         struct bnx2 *bp = netdev_priv(dev);
6776         int i;
6777         u32 *hw_stats = (u32 *) bp->stats_blk;
6778         u8 *stats_len_arr = NULL;
6779
6780         if (hw_stats == NULL) {
6781                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6782                 return;
6783         }
6784
6785         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6786             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6787             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6788             (CHIP_ID(bp) == CHIP_ID_5708_A0))
6789                 stats_len_arr = bnx2_5706_stats_len_arr;
6790         else
6791                 stats_len_arr = bnx2_5708_stats_len_arr;
6792
6793         for (i = 0; i < BNX2_NUM_STATS; i++) {
6794                 if (stats_len_arr[i] == 0) {
6795                         /* skip this counter */
6796                         buf[i] = 0;
6797                         continue;
6798                 }
6799                 if (stats_len_arr[i] == 4) {
6800                         /* 4-byte counter */
6801                         buf[i] = (u64)
6802                                 *(hw_stats + bnx2_stats_offset_arr[i]);
6803                         continue;
6804                 }
6805                 /* 8-byte counter */
6806                 buf[i] = (((u64) *(hw_stats +
6807                                         bnx2_stats_offset_arr[i])) << 32) +
6808                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6809         }
6810 }
6811
6812 static int
6813 bnx2_phys_id(struct net_device *dev, u32 data)
6814 {
6815         struct bnx2 *bp = netdev_priv(dev);
6816         int i;
6817         u32 save;
6818
6819         if (data == 0)
6820                 data = 2;
6821
6822         save = REG_RD(bp, BNX2_MISC_CFG);
6823         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6824
6825         for (i = 0; i < (data * 2); i++) {
6826                 if ((i % 2) == 0) {
6827                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6828                 }
6829                 else {
6830                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6831                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
6832                                 BNX2_EMAC_LED_100MB_OVERRIDE |
6833                                 BNX2_EMAC_LED_10MB_OVERRIDE |
6834                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6835                                 BNX2_EMAC_LED_TRAFFIC);
6836                 }
6837                 msleep_interruptible(500);
6838                 if (signal_pending(current))
6839                         break;
6840         }
6841         REG_WR(bp, BNX2_EMAC_LED, 0);
6842         REG_WR(bp, BNX2_MISC_CFG, save);
6843         return 0;
6844 }
6845
6846 static int
6847 bnx2_set_tx_csum(struct net_device *dev, u32 data)
6848 {
6849         struct bnx2 *bp = netdev_priv(dev);
6850
6851         if (CHIP_NUM(bp) == CHIP_NUM_5709)
6852                 return (ethtool_op_set_tx_ipv6_csum(dev, data));
6853         else
6854                 return (ethtool_op_set_tx_csum(dev, data));
6855 }
6856
6857 static const struct ethtool_ops bnx2_ethtool_ops = {
6858         .get_settings           = bnx2_get_settings,
6859         .set_settings           = bnx2_set_settings,
6860         .get_drvinfo            = bnx2_get_drvinfo,
6861         .get_regs_len           = bnx2_get_regs_len,
6862         .get_regs               = bnx2_get_regs,
6863         .get_wol                = bnx2_get_wol,
6864         .set_wol                = bnx2_set_wol,
6865         .nway_reset             = bnx2_nway_reset,
6866         .get_link               = ethtool_op_get_link,
6867         .get_eeprom_len         = bnx2_get_eeprom_len,
6868         .get_eeprom             = bnx2_get_eeprom,
6869         .set_eeprom             = bnx2_set_eeprom,
6870         .get_coalesce           = bnx2_get_coalesce,
6871         .set_coalesce           = bnx2_set_coalesce,
6872         .get_ringparam          = bnx2_get_ringparam,
6873         .set_ringparam          = bnx2_set_ringparam,
6874         .get_pauseparam         = bnx2_get_pauseparam,
6875         .set_pauseparam         = bnx2_set_pauseparam,
6876         .get_rx_csum            = bnx2_get_rx_csum,
6877         .set_rx_csum            = bnx2_set_rx_csum,
6878         .set_tx_csum            = bnx2_set_tx_csum,
6879         .set_sg                 = ethtool_op_set_sg,
6880         .set_tso                = bnx2_set_tso,
6881         .self_test              = bnx2_self_test,
6882         .get_strings            = bnx2_get_strings,
6883         .phys_id                = bnx2_phys_id,
6884         .get_ethtool_stats      = bnx2_get_ethtool_stats,
6885         .get_sset_count         = bnx2_get_sset_count,
6886 };
6887
6888 /* Called with rtnl_lock */
6889 static int
6890 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6891 {
6892         struct mii_ioctl_data *data = if_mii(ifr);
6893         struct bnx2 *bp = netdev_priv(dev);
6894         int err;
6895
6896         switch(cmd) {
6897         case SIOCGMIIPHY:
6898                 data->phy_id = bp->phy_addr;
6899
6900                 /* fallthru */
6901         case SIOCGMIIREG: {
6902                 u32 mii_regval;
6903
6904                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6905                         return -EOPNOTSUPP;
6906
6907                 if (!netif_running(dev))
6908                         return -EAGAIN;
6909
6910                 spin_lock_bh(&bp->phy_lock);
6911                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
6912                 spin_unlock_bh(&bp->phy_lock);
6913
6914                 data->val_out = mii_regval;
6915
6916                 return err;
6917         }
6918
6919         case SIOCSMIIREG:
6920                 if (!capable(CAP_NET_ADMIN))
6921                         return -EPERM;
6922
6923                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6924                         return -EOPNOTSUPP;
6925
6926                 if (!netif_running(dev))
6927                         return -EAGAIN;
6928
6929                 spin_lock_bh(&bp->phy_lock);
6930                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
6931                 spin_unlock_bh(&bp->phy_lock);
6932
6933                 return err;
6934
6935         default:
6936                 /* do nothing */
6937                 break;
6938         }
6939         return -EOPNOTSUPP;
6940 }
6941
6942 /* Called with rtnl_lock */
6943 static int
6944 bnx2_change_mac_addr(struct net_device *dev, void *p)
6945 {
6946         struct sockaddr *addr = p;
6947         struct bnx2 *bp = netdev_priv(dev);
6948
6949         if (!is_valid_ether_addr(addr->sa_data))
6950                 return -EINVAL;
6951
6952         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6953         if (netif_running(dev))
6954                 bnx2_set_mac_addr(bp);
6955
6956         return 0;
6957 }
6958
6959 /* Called with rtnl_lock */
6960 static int
6961 bnx2_change_mtu(struct net_device *dev, int new_mtu)
6962 {
6963         struct bnx2 *bp = netdev_priv(dev);
6964
6965         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6966                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6967                 return -EINVAL;
6968
6969         dev->mtu = new_mtu;
6970         return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
6971 }
6972
6973 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6974 static void
6975 poll_bnx2(struct net_device *dev)
6976 {
6977         struct bnx2 *bp = netdev_priv(dev);
6978
6979         disable_irq(bp->pdev->irq);
6980         bnx2_interrupt(bp->pdev->irq, dev);
6981         enable_irq(bp->pdev->irq);
6982 }
6983 #endif
6984
6985 static void __devinit
6986 bnx2_get_5709_media(struct bnx2 *bp)
6987 {
6988         u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
6989         u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
6990         u32 strap;
6991
6992         if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
6993                 return;
6994         else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
6995                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
6996                 return;
6997         }
6998
6999         if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7000                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7001         else
7002                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7003
7004         if (PCI_FUNC(bp->pdev->devfn) == 0) {
7005                 switch (strap) {
7006                 case 0x4:
7007                 case 0x5:
7008                 case 0x6:
7009                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7010                         return;
7011                 }
7012         } else {
7013                 switch (strap) {
7014                 case 0x1:
7015                 case 0x2:
7016                 case 0x4:
7017                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7018                         return;
7019                 }
7020         }
7021 }
7022
7023 static void __devinit
7024 bnx2_get_pci_speed(struct bnx2 *bp)
7025 {
7026         u32 reg;
7027
7028         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7029         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7030                 u32 clkreg;
7031
7032                 bp->flags |= BNX2_FLAG_PCIX;
7033
7034                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7035
7036                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7037                 switch (clkreg) {
7038                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7039                         bp->bus_speed_mhz = 133;
7040                         break;
7041
7042                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7043                         bp->bus_speed_mhz = 100;
7044                         break;
7045
7046                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7047                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7048                         bp->bus_speed_mhz = 66;
7049                         break;
7050
7051                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7052                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7053                         bp->bus_speed_mhz = 50;
7054                         break;
7055
7056                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7057                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7058                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7059                         bp->bus_speed_mhz = 33;
7060                         break;
7061                 }
7062         }
7063         else {
7064                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7065                         bp->bus_speed_mhz = 66;
7066                 else
7067                         bp->bus_speed_mhz = 33;
7068         }
7069
7070         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7071                 bp->flags |= BNX2_FLAG_PCI_32BIT;
7072
7073 }
7074
7075 static int __devinit
7076 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7077 {
7078         struct bnx2 *bp;
7079         unsigned long mem_len;
7080         int rc, i, j;
7081         u32 reg;
7082         u64 dma_mask, persist_dma_mask;
7083
7084         SET_NETDEV_DEV(dev, &pdev->dev);
7085         bp = netdev_priv(dev);
7086
7087         bp->flags = 0;
7088         bp->phy_flags = 0;
7089
7090         /* enable device (incl. PCI PM wakeup), and bus-mastering */
7091         rc = pci_enable_device(pdev);
7092         if (rc) {
7093                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7094                 goto err_out;
7095         }
7096
7097         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7098                 dev_err(&pdev->dev,
7099                         "Cannot find PCI device base address, aborting.\n");
7100                 rc = -ENODEV;
7101                 goto err_out_disable;
7102         }
7103
7104         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7105         if (rc) {
7106                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7107                 goto err_out_disable;
7108         }
7109
7110         pci_set_master(pdev);
7111
7112         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7113         if (bp->pm_cap == 0) {
7114                 dev_err(&pdev->dev,
7115                         "Cannot find power management capability, aborting.\n");
7116                 rc = -EIO;
7117                 goto err_out_release;
7118         }
7119
7120         bp->dev = dev;
7121         bp->pdev = pdev;
7122
7123         spin_lock_init(&bp->phy_lock);
7124         spin_lock_init(&bp->indirect_lock);
7125         INIT_WORK(&bp->reset_task, bnx2_reset_task);
7126
7127         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7128         mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
7129         dev->mem_end = dev->mem_start + mem_len;
7130         dev->irq = pdev->irq;
7131
7132         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7133
7134         if (!bp->regview) {
7135                 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7136                 rc = -ENOMEM;
7137                 goto err_out_release;
7138         }
7139
7140         /* Configure byte swap and enable write to the reg_window registers.
7141          * Rely on CPU to do target byte swapping on big endian systems
7142          * The chip's target access swapping will not swap all accesses
7143          */
7144         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7145                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7146                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7147
7148         bnx2_set_power_state(bp, PCI_D0);
7149
7150         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7151
7152         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7153                 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7154                         dev_err(&pdev->dev,
7155                                 "Cannot find PCIE capability, aborting.\n");
7156                         rc = -EIO;
7157                         goto err_out_unmap;
7158                 }
7159                 bp->flags |= BNX2_FLAG_PCIE;
7160                 if (CHIP_REV(bp) == CHIP_REV_Ax)
7161                         bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7162         } else {
7163                 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7164                 if (bp->pcix_cap == 0) {
7165                         dev_err(&pdev->dev,
7166                                 "Cannot find PCIX capability, aborting.\n");
7167                         rc = -EIO;
7168                         goto err_out_unmap;
7169                 }
7170         }
7171
7172         if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7173                 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7174                         bp->flags |= BNX2_FLAG_MSIX_CAP;
7175         }
7176
7177         if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7178                 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7179                         bp->flags |= BNX2_FLAG_MSI_CAP;
7180         }
7181
7182         /* 5708 cannot support DMA addresses > 40-bit.  */
7183         if (CHIP_NUM(bp) == CHIP_NUM_5708)
7184                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7185         else
7186                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7187
7188         /* Configure DMA attributes. */
7189         if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7190                 dev->features |= NETIF_F_HIGHDMA;
7191                 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7192                 if (rc) {
7193                         dev_err(&pdev->dev,
7194                                 "pci_set_consistent_dma_mask failed, aborting.\n");
7195                         goto err_out_unmap;
7196                 }
7197         } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7198                 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7199                 goto err_out_unmap;
7200         }
7201
7202         if (!(bp->flags & BNX2_FLAG_PCIE))
7203                 bnx2_get_pci_speed(bp);
7204
7205         /* 5706A0 may falsely detect SERR and PERR. */
7206         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7207                 reg = REG_RD(bp, PCI_COMMAND);
7208                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7209                 REG_WR(bp, PCI_COMMAND, reg);
7210         }
7211         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7212                 !(bp->flags & BNX2_FLAG_PCIX)) {
7213
7214                 dev_err(&pdev->dev,
7215                         "5706 A1 can only be used in a PCIX bus, aborting.\n");
7216                 goto err_out_unmap;
7217         }
7218
7219         bnx2_init_nvram(bp);
7220
7221         reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7222
7223         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7224             BNX2_SHM_HDR_SIGNATURE_SIG) {
7225                 u32 off = PCI_FUNC(pdev->devfn) << 2;
7226
7227                 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7228         } else
7229                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7230
7231         /* Get the permanent MAC address.  First we need to make sure the
7232          * firmware is actually running.
7233          */
7234         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7235
7236         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7237             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7238                 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7239                 rc = -ENODEV;
7240                 goto err_out_unmap;
7241         }
7242
7243         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7244         for (i = 0, j = 0; i < 3; i++) {
7245                 u8 num, k, skip0;
7246
7247                 num = (u8) (reg >> (24 - (i * 8)));
7248                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7249                         if (num >= k || !skip0 || k == 1) {
7250                                 bp->fw_version[j++] = (num / k) + '0';
7251                                 skip0 = 0;
7252                         }
7253                 }
7254                 if (i != 2)
7255                         bp->fw_version[j++] = '.';
7256         }
7257         reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7258         if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7259                 bp->wol = 1;
7260
7261         if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7262                 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7263
7264                 for (i = 0; i < 30; i++) {
7265                         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7266                         if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7267                                 break;
7268                         msleep(10);
7269                 }
7270         }
7271         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7272         reg &= BNX2_CONDITION_MFW_RUN_MASK;
7273         if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7274             reg != BNX2_CONDITION_MFW_RUN_NONE) {
7275                 int i;
7276                 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7277
7278                 bp->fw_version[j++] = ' ';
7279                 for (i = 0; i < 3; i++) {
7280                         reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7281                         reg = swab32(reg);
7282                         memcpy(&bp->fw_version[j], &reg, 4);
7283                         j += 4;
7284                 }
7285         }
7286
7287         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7288         bp->mac_addr[0] = (u8) (reg >> 8);
7289         bp->mac_addr[1] = (u8) reg;
7290
7291         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7292         bp->mac_addr[2] = (u8) (reg >> 24);
7293         bp->mac_addr[3] = (u8) (reg >> 16);
7294         bp->mac_addr[4] = (u8) (reg >> 8);
7295         bp->mac_addr[5] = (u8) reg;
7296
7297         bp->rx_offset = sizeof(struct l2_fhdr) + 2;
7298
7299         bp->tx_ring_size = MAX_TX_DESC_CNT;
7300         bnx2_set_rx_ring_size(bp, 255);
7301
7302         bp->rx_csum = 1;
7303
7304         bp->tx_quick_cons_trip_int = 20;
7305         bp->tx_quick_cons_trip = 20;
7306         bp->tx_ticks_int = 80;
7307         bp->tx_ticks = 80;
7308
7309         bp->rx_quick_cons_trip_int = 6;
7310         bp->rx_quick_cons_trip = 6;
7311         bp->rx_ticks_int = 18;
7312         bp->rx_ticks = 18;
7313
7314         bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7315
7316         bp->timer_interval =  HZ;
7317         bp->current_interval =  HZ;
7318
7319         bp->phy_addr = 1;
7320
7321         /* Disable WOL support if we are running on a SERDES chip. */
7322         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7323                 bnx2_get_5709_media(bp);
7324         else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7325                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7326
7327         bp->phy_port = PORT_TP;
7328         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7329                 bp->phy_port = PORT_FIBRE;
7330                 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7331                 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7332                         bp->flags |= BNX2_FLAG_NO_WOL;
7333                         bp->wol = 0;
7334                 }
7335                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7336                         /* Don't do parallel detect on this board because of
7337                          * some board problems.  The link will not go down
7338                          * if we do parallel detect.
7339                          */
7340                         if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7341                             pdev->subsystem_device == 0x310c)
7342                                 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7343                 } else {
7344                         bp->phy_addr = 2;
7345                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7346                                 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7347                 }
7348                 bnx2_init_remote_phy(bp);
7349
7350         } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7351                    CHIP_NUM(bp) == CHIP_NUM_5708)
7352                 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7353         else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7354                  (CHIP_REV(bp) == CHIP_REV_Ax ||
7355                   CHIP_REV(bp) == CHIP_REV_Bx))
7356                 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7357
7358         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7359             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7360             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
7361                 bp->flags |= BNX2_FLAG_NO_WOL;
7362                 bp->wol = 0;
7363         }
7364
7365         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7366                 bp->tx_quick_cons_trip_int =
7367                         bp->tx_quick_cons_trip;
7368                 bp->tx_ticks_int = bp->tx_ticks;
7369                 bp->rx_quick_cons_trip_int =
7370                         bp->rx_quick_cons_trip;
7371                 bp->rx_ticks_int = bp->rx_ticks;
7372                 bp->comp_prod_trip_int = bp->comp_prod_trip;
7373                 bp->com_ticks_int = bp->com_ticks;
7374                 bp->cmd_ticks_int = bp->cmd_ticks;
7375         }
7376
7377         /* Disable MSI on 5706 if AMD 8132 bridge is found.
7378          *
7379          * MSI is defined to be 32-bit write.  The 5706 does 64-bit MSI writes
7380          * with byte enables disabled on the unused 32-bit word.  This is legal
7381          * but causes problems on the AMD 8132 which will eventually stop
7382          * responding after a while.
7383          *
7384          * AMD believes this incompatibility is unique to the 5706, and
7385          * prefers to locally disable MSI rather than globally disabling it.
7386          */
7387         if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7388                 struct pci_dev *amd_8132 = NULL;
7389
7390                 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7391                                                   PCI_DEVICE_ID_AMD_8132_BRIDGE,
7392                                                   amd_8132))) {
7393
7394                         if (amd_8132->revision >= 0x10 &&
7395                             amd_8132->revision <= 0x13) {
7396                                 disable_msi = 1;
7397                                 pci_dev_put(amd_8132);
7398                                 break;
7399                         }
7400                 }
7401         }
7402
7403         bnx2_set_default_link(bp);
7404         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7405
7406         init_timer(&bp->timer);
7407         bp->timer.expires = RUN_AT(bp->timer_interval);
7408         bp->timer.data = (unsigned long) bp;
7409         bp->timer.function = bnx2_timer;
7410
7411         return 0;
7412
7413 err_out_unmap:
7414         if (bp->regview) {
7415                 iounmap(bp->regview);
7416                 bp->regview = NULL;
7417         }
7418
7419 err_out_release:
7420         pci_release_regions(pdev);
7421
7422 err_out_disable:
7423         pci_disable_device(pdev);
7424         pci_set_drvdata(pdev, NULL);
7425
7426 err_out:
7427         return rc;
7428 }
7429
7430 static char * __devinit
7431 bnx2_bus_string(struct bnx2 *bp, char *str)
7432 {
7433         char *s = str;
7434
7435         if (bp->flags & BNX2_FLAG_PCIE) {
7436                 s += sprintf(s, "PCI Express");
7437         } else {
7438                 s += sprintf(s, "PCI");
7439                 if (bp->flags & BNX2_FLAG_PCIX)
7440                         s += sprintf(s, "-X");
7441                 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7442                         s += sprintf(s, " 32-bit");
7443                 else
7444                         s += sprintf(s, " 64-bit");
7445                 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7446         }
7447         return str;
7448 }
7449
7450 static void __devinit
7451 bnx2_init_napi(struct bnx2 *bp)
7452 {
7453         int i;
7454         struct bnx2_napi *bnapi;
7455
7456         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7457                 bnapi = &bp->bnx2_napi[i];
7458                 bnapi->bp = bp;
7459         }
7460         netif_napi_add(bp->dev, &bp->bnx2_napi[0].napi, bnx2_poll, 64);
7461         netif_napi_add(bp->dev, &bp->bnx2_napi[BNX2_TX_VEC].napi, bnx2_tx_poll,
7462                        64);
7463 }
7464
7465 static int __devinit
7466 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7467 {
7468         static int version_printed = 0;
7469         struct net_device *dev = NULL;
7470         struct bnx2 *bp;
7471         int rc;
7472         char str[40];
7473         DECLARE_MAC_BUF(mac);
7474
7475         if (version_printed++ == 0)
7476                 printk(KERN_INFO "%s", version);
7477
7478         /* dev zeroed in init_etherdev */
7479         dev = alloc_etherdev(sizeof(*bp));
7480
7481         if (!dev)
7482                 return -ENOMEM;
7483
7484         rc = bnx2_init_board(pdev, dev);
7485         if (rc < 0) {
7486                 free_netdev(dev);
7487                 return rc;
7488         }
7489
7490         dev->open = bnx2_open;
7491         dev->hard_start_xmit = bnx2_start_xmit;
7492         dev->stop = bnx2_close;
7493         dev->get_stats = bnx2_get_stats;
7494         dev->set_multicast_list = bnx2_set_rx_mode;
7495         dev->do_ioctl = bnx2_ioctl;
7496         dev->set_mac_address = bnx2_change_mac_addr;
7497         dev->change_mtu = bnx2_change_mtu;
7498         dev->tx_timeout = bnx2_tx_timeout;
7499         dev->watchdog_timeo = TX_TIMEOUT;
7500 #ifdef BCM_VLAN
7501         dev->vlan_rx_register = bnx2_vlan_rx_register;
7502 #endif
7503         dev->ethtool_ops = &bnx2_ethtool_ops;
7504
7505         bp = netdev_priv(dev);
7506         bnx2_init_napi(bp);
7507
7508 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7509         dev->poll_controller = poll_bnx2;
7510 #endif
7511
7512         pci_set_drvdata(pdev, dev);
7513
7514         memcpy(dev->dev_addr, bp->mac_addr, 6);
7515         memcpy(dev->perm_addr, bp->mac_addr, 6);
7516         bp->name = board_info[ent->driver_data].name;
7517
7518         dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7519         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7520                 dev->features |= NETIF_F_IPV6_CSUM;
7521
7522 #ifdef BCM_VLAN
7523         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7524 #endif
7525         dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7526         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7527                 dev->features |= NETIF_F_TSO6;
7528
7529         if ((rc = register_netdev(dev))) {
7530                 dev_err(&pdev->dev, "Cannot register net device\n");
7531                 if (bp->regview)
7532                         iounmap(bp->regview);
7533                 pci_release_regions(pdev);
7534                 pci_disable_device(pdev);
7535                 pci_set_drvdata(pdev, NULL);
7536                 free_netdev(dev);
7537                 return rc;
7538         }
7539
7540         printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7541                 "IRQ %d, node addr %s\n",
7542                 dev->name,
7543                 bp->name,
7544                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7545                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7546                 bnx2_bus_string(bp, str),
7547                 dev->base_addr,
7548                 bp->pdev->irq, print_mac(mac, dev->dev_addr));
7549
7550         return 0;
7551 }
7552
7553 static void __devexit
7554 bnx2_remove_one(struct pci_dev *pdev)
7555 {
7556         struct net_device *dev = pci_get_drvdata(pdev);
7557         struct bnx2 *bp = netdev_priv(dev);
7558
7559         flush_scheduled_work();
7560
7561         unregister_netdev(dev);
7562
7563         if (bp->regview)
7564                 iounmap(bp->regview);
7565
7566         free_netdev(dev);
7567         pci_release_regions(pdev);
7568         pci_disable_device(pdev);
7569         pci_set_drvdata(pdev, NULL);
7570 }
7571
7572 static int
7573 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7574 {
7575         struct net_device *dev = pci_get_drvdata(pdev);
7576         struct bnx2 *bp = netdev_priv(dev);
7577         u32 reset_code;
7578
7579         /* PCI register 4 needs to be saved whether netif_running() or not.
7580          * MSI address and data need to be saved if using MSI and
7581          * netif_running().
7582          */
7583         pci_save_state(pdev);
7584         if (!netif_running(dev))
7585                 return 0;
7586
7587         flush_scheduled_work();
7588         bnx2_netif_stop(bp);
7589         netif_device_detach(dev);
7590         del_timer_sync(&bp->timer);
7591         if (bp->flags & BNX2_FLAG_NO_WOL)
7592                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
7593         else if (bp->wol)
7594                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
7595         else
7596                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
7597         bnx2_reset_chip(bp, reset_code);
7598         bnx2_free_skbs(bp);
7599         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7600         return 0;
7601 }
7602
7603 static int
7604 bnx2_resume(struct pci_dev *pdev)
7605 {
7606         struct net_device *dev = pci_get_drvdata(pdev);
7607         struct bnx2 *bp = netdev_priv(dev);
7608
7609         pci_restore_state(pdev);
7610         if (!netif_running(dev))
7611                 return 0;
7612
7613         bnx2_set_power_state(bp, PCI_D0);
7614         netif_device_attach(dev);
7615         bnx2_init_nic(bp);
7616         bnx2_netif_start(bp);
7617         return 0;
7618 }
7619
7620 static struct pci_driver bnx2_pci_driver = {
7621         .name           = DRV_MODULE_NAME,
7622         .id_table       = bnx2_pci_tbl,
7623         .probe          = bnx2_init_one,
7624         .remove         = __devexit_p(bnx2_remove_one),
7625         .suspend        = bnx2_suspend,
7626         .resume         = bnx2_resume,
7627 };
7628
7629 static int __init bnx2_init(void)
7630 {
7631         return pci_register_driver(&bnx2_pci_driver);
7632 }
7633
7634 static void __exit bnx2_cleanup(void)
7635 {
7636         pci_unregister_driver(&bnx2_pci_driver);
7637 }
7638
7639 module_init(bnx2_init);
7640 module_exit(bnx2_cleanup);
7641
7642
7643