Merge master.kernel.org:/home/rmk/linux-2.6-arm
[linux-2.6] / arch / x86 / kernel / apic / x2apic_uv_x.c
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * SGI UV APIC functions (note: not an Intel compatible APIC)
7  *
8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9  */
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/cpu.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23
24 #include <asm/uv/uv_mmrs.h>
25 #include <asm/uv/uv_hub.h>
26 #include <asm/current.h>
27 #include <asm/pgtable.h>
28 #include <asm/uv/bios.h>
29 #include <asm/uv/uv.h>
30 #include <asm/apic.h>
31 #include <asm/ipi.h>
32 #include <asm/smp.h>
33
34 DEFINE_PER_CPU(int, x2apic_extra_bits);
35
36 static enum uv_system_type uv_system_type;
37
38 static int early_get_nodeid(void)
39 {
40         union uvh_node_id_u node_id;
41         unsigned long *mmr;
42
43         mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr));
44         node_id.v = *mmr;
45         early_iounmap(mmr, sizeof(*mmr));
46         return node_id.s.node_id;
47 }
48
49 static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
50 {
51         if (!strcmp(oem_id, "SGI")) {
52                 if (!strcmp(oem_table_id, "UVL"))
53                         uv_system_type = UV_LEGACY_APIC;
54                 else if (!strcmp(oem_table_id, "UVX"))
55                         uv_system_type = UV_X2APIC;
56                 else if (!strcmp(oem_table_id, "UVH")) {
57                         __get_cpu_var(x2apic_extra_bits) =
58                                 early_get_nodeid() << (UV_APIC_PNODE_SHIFT - 1);
59                         uv_system_type = UV_NON_UNIQUE_APIC;
60                         return 1;
61                 }
62         }
63         return 0;
64 }
65
66 enum uv_system_type get_uv_system_type(void)
67 {
68         return uv_system_type;
69 }
70
71 int is_uv_system(void)
72 {
73         return uv_system_type != UV_NONE;
74 }
75 EXPORT_SYMBOL_GPL(is_uv_system);
76
77 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
78 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
79
80 struct uv_blade_info *uv_blade_info;
81 EXPORT_SYMBOL_GPL(uv_blade_info);
82
83 short *uv_node_to_blade;
84 EXPORT_SYMBOL_GPL(uv_node_to_blade);
85
86 short *uv_cpu_to_blade;
87 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
88
89 short uv_possible_blades;
90 EXPORT_SYMBOL_GPL(uv_possible_blades);
91
92 unsigned long sn_rtc_cycles_per_second;
93 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
94
95 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
96
97 static const struct cpumask *uv_target_cpus(void)
98 {
99         return cpumask_of(0);
100 }
101
102 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
103 {
104         cpumask_clear(retmask);
105         cpumask_set_cpu(cpu, retmask);
106 }
107
108 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
109 {
110 #ifdef CONFIG_SMP
111         unsigned long val;
112         int pnode;
113
114         pnode = uv_apicid_to_pnode(phys_apicid);
115         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
116             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
117             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
118             APIC_DM_INIT;
119         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
120         mdelay(10);
121
122         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
123             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
124             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
125             APIC_DM_STARTUP;
126         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
127
128         atomic_set(&init_deasserted, 1);
129 #endif
130         return 0;
131 }
132
133 static void uv_send_IPI_one(int cpu, int vector)
134 {
135         unsigned long apicid;
136         int pnode;
137
138         apicid = per_cpu(x86_cpu_to_apicid, cpu);
139         pnode = uv_apicid_to_pnode(apicid);
140         uv_hub_send_ipi(pnode, apicid, vector);
141 }
142
143 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
144 {
145         unsigned int cpu;
146
147         for_each_cpu(cpu, mask)
148                 uv_send_IPI_one(cpu, vector);
149 }
150
151 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
152 {
153         unsigned int this_cpu = smp_processor_id();
154         unsigned int cpu;
155
156         for_each_cpu(cpu, mask) {
157                 if (cpu != this_cpu)
158                         uv_send_IPI_one(cpu, vector);
159         }
160 }
161
162 static void uv_send_IPI_allbutself(int vector)
163 {
164         unsigned int this_cpu = smp_processor_id();
165         unsigned int cpu;
166
167         for_each_online_cpu(cpu) {
168                 if (cpu != this_cpu)
169                         uv_send_IPI_one(cpu, vector);
170         }
171 }
172
173 static void uv_send_IPI_all(int vector)
174 {
175         uv_send_IPI_mask(cpu_online_mask, vector);
176 }
177
178 static int uv_apic_id_registered(void)
179 {
180         return 1;
181 }
182
183 static void uv_init_apic_ldr(void)
184 {
185 }
186
187 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
188 {
189         /*
190          * We're using fixed IRQ delivery, can only return one phys APIC ID.
191          * May as well be the first.
192          */
193         int cpu = cpumask_first(cpumask);
194
195         if ((unsigned)cpu < nr_cpu_ids)
196                 return per_cpu(x86_cpu_to_apicid, cpu);
197         else
198                 return BAD_APICID;
199 }
200
201 static unsigned int
202 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
203                           const struct cpumask *andmask)
204 {
205         int cpu;
206
207         /*
208          * We're using fixed IRQ delivery, can only return one phys APIC ID.
209          * May as well be the first.
210          */
211         for_each_cpu_and(cpu, cpumask, andmask) {
212                 if (cpumask_test_cpu(cpu, cpu_online_mask))
213                         break;
214         }
215         if (cpu < nr_cpu_ids)
216                 return per_cpu(x86_cpu_to_apicid, cpu);
217
218         return BAD_APICID;
219 }
220
221 static unsigned int x2apic_get_apic_id(unsigned long x)
222 {
223         unsigned int id;
224
225         WARN_ON(preemptible() && num_online_cpus() > 1);
226         id = x | __get_cpu_var(x2apic_extra_bits);
227
228         return id;
229 }
230
231 static unsigned long set_apic_id(unsigned int id)
232 {
233         unsigned long x;
234
235         /* maskout x2apic_extra_bits ? */
236         x = id;
237         return x;
238 }
239
240 static unsigned int uv_read_apic_id(void)
241 {
242
243         return x2apic_get_apic_id(apic_read(APIC_ID));
244 }
245
246 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
247 {
248         return uv_read_apic_id() >> index_msb;
249 }
250
251 static void uv_send_IPI_self(int vector)
252 {
253         apic_write(APIC_SELF_IPI, vector);
254 }
255
256 struct apic apic_x2apic_uv_x = {
257
258         .name                           = "UV large system",
259         .probe                          = NULL,
260         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
261         .apic_id_registered             = uv_apic_id_registered,
262
263         .irq_delivery_mode              = dest_Fixed,
264         .irq_dest_mode                  = 0, /* physical */
265
266         .target_cpus                    = uv_target_cpus,
267         .disable_esr                    = 0,
268         .dest_logical                   = APIC_DEST_LOGICAL,
269         .check_apicid_used              = NULL,
270         .check_apicid_present           = NULL,
271
272         .vector_allocation_domain       = uv_vector_allocation_domain,
273         .init_apic_ldr                  = uv_init_apic_ldr,
274
275         .ioapic_phys_id_map             = NULL,
276         .setup_apic_routing             = NULL,
277         .multi_timer_check              = NULL,
278         .apicid_to_node                 = NULL,
279         .cpu_to_logical_apicid          = NULL,
280         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
281         .apicid_to_cpu_present          = NULL,
282         .setup_portio_remap             = NULL,
283         .check_phys_apicid_present      = default_check_phys_apicid_present,
284         .enable_apic_mode               = NULL,
285         .phys_pkg_id                    = uv_phys_pkg_id,
286         .mps_oem_check                  = NULL,
287
288         .get_apic_id                    = x2apic_get_apic_id,
289         .set_apic_id                    = set_apic_id,
290         .apic_id_mask                   = 0xFFFFFFFFu,
291
292         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
293         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
294
295         .send_IPI_mask                  = uv_send_IPI_mask,
296         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
297         .send_IPI_allbutself            = uv_send_IPI_allbutself,
298         .send_IPI_all                   = uv_send_IPI_all,
299         .send_IPI_self                  = uv_send_IPI_self,
300
301         .wakeup_secondary_cpu           = uv_wakeup_secondary,
302         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
303         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
304         .wait_for_init_deassert         = NULL,
305         .smp_callin_clear_local_apic    = NULL,
306         .inquire_remote_apic            = NULL,
307
308         .read                           = native_apic_msr_read,
309         .write                          = native_apic_msr_write,
310         .icr_read                       = native_x2apic_icr_read,
311         .icr_write                      = native_x2apic_icr_write,
312         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
313         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
314 };
315
316 static __cpuinit void set_x2apic_extra_bits(int pnode)
317 {
318         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
319 }
320
321 /*
322  * Called on boot cpu.
323  */
324 static __init int boot_pnode_to_blade(int pnode)
325 {
326         int blade;
327
328         for (blade = 0; blade < uv_num_possible_blades(); blade++)
329                 if (pnode == uv_blade_info[blade].pnode)
330                         return blade;
331         BUG();
332 }
333
334 struct redir_addr {
335         unsigned long redirect;
336         unsigned long alias;
337 };
338
339 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
340
341 static __initdata struct redir_addr redir_addrs[] = {
342         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
343         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
344         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
345 };
346
347 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
348 {
349         union uvh_si_alias0_overlay_config_u alias;
350         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
351         int i;
352
353         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
354                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
355                 if (alias.s.base == 0) {
356                         *size = (1UL << alias.s.m_alias);
357                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
358                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
359                         return;
360                 }
361         }
362         BUG();
363 }
364
365 enum map_type {map_wb, map_uc};
366
367 static __init void map_high(char *id, unsigned long base, int shift,
368                             int max_pnode, enum map_type map_type)
369 {
370         unsigned long bytes, paddr;
371
372         paddr = base << shift;
373         bytes = (1UL << shift) * (max_pnode + 1);
374         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
375                                                 paddr + bytes);
376         if (map_type == map_uc)
377                 init_extra_mapping_uc(paddr, bytes);
378         else
379                 init_extra_mapping_wb(paddr, bytes);
380
381 }
382 static __init void map_gru_high(int max_pnode)
383 {
384         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
385         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
386
387         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
388         if (gru.s.enable)
389                 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
390 }
391
392 static __init void map_mmioh_high(int max_pnode)
393 {
394         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
395         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
396
397         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
398         if (mmioh.s.enable)
399                 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
400 }
401
402 static __init void uv_rtc_init(void)
403 {
404         long status;
405         u64 ticks_per_sec;
406
407         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
408                                         &ticks_per_sec);
409         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
410                 printk(KERN_WARNING
411                         "unable to determine platform RTC clock frequency, "
412                         "guessing.\n");
413                 /* BIOS gives wrong value for clock freq. so guess */
414                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
415         } else
416                 sn_rtc_cycles_per_second = ticks_per_sec;
417 }
418
419 /*
420  * percpu heartbeat timer
421  */
422 static void uv_heartbeat(unsigned long ignored)
423 {
424         struct timer_list *timer = &uv_hub_info->scir.timer;
425         unsigned char bits = uv_hub_info->scir.state;
426
427         /* flip heartbeat bit */
428         bits ^= SCIR_CPU_HEARTBEAT;
429
430         /* is this cpu idle? */
431         if (idle_cpu(raw_smp_processor_id()))
432                 bits &= ~SCIR_CPU_ACTIVITY;
433         else
434                 bits |= SCIR_CPU_ACTIVITY;
435
436         /* update system controller interface reg */
437         uv_set_scir_bits(bits);
438
439         /* enable next timer period */
440         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
441 }
442
443 static void __cpuinit uv_heartbeat_enable(int cpu)
444 {
445         if (!uv_cpu_hub_info(cpu)->scir.enabled) {
446                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
447
448                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
449                 setup_timer(timer, uv_heartbeat, cpu);
450                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
451                 add_timer_on(timer, cpu);
452                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
453         }
454
455         /* check boot cpu */
456         if (!uv_cpu_hub_info(0)->scir.enabled)
457                 uv_heartbeat_enable(0);
458 }
459
460 #ifdef CONFIG_HOTPLUG_CPU
461 static void __cpuinit uv_heartbeat_disable(int cpu)
462 {
463         if (uv_cpu_hub_info(cpu)->scir.enabled) {
464                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
465                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
466         }
467         uv_set_cpu_scir_bits(cpu, 0xff);
468 }
469
470 /*
471  * cpu hotplug notifier
472  */
473 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
474                                        unsigned long action, void *hcpu)
475 {
476         long cpu = (long)hcpu;
477
478         switch (action) {
479         case CPU_ONLINE:
480                 uv_heartbeat_enable(cpu);
481                 break;
482         case CPU_DOWN_PREPARE:
483                 uv_heartbeat_disable(cpu);
484                 break;
485         default:
486                 break;
487         }
488         return NOTIFY_OK;
489 }
490
491 static __init void uv_scir_register_cpu_notifier(void)
492 {
493         hotcpu_notifier(uv_scir_cpu_notify, 0);
494 }
495
496 #else /* !CONFIG_HOTPLUG_CPU */
497
498 static __init void uv_scir_register_cpu_notifier(void)
499 {
500 }
501
502 static __init int uv_init_heartbeat(void)
503 {
504         int cpu;
505
506         if (is_uv_system())
507                 for_each_online_cpu(cpu)
508                         uv_heartbeat_enable(cpu);
509         return 0;
510 }
511
512 late_initcall(uv_init_heartbeat);
513
514 #endif /* !CONFIG_HOTPLUG_CPU */
515
516 /*
517  * Called on each cpu to initialize the per_cpu UV data area.
518  * FIXME: hotplug not supported yet
519  */
520 void __cpuinit uv_cpu_init(void)
521 {
522         /* CPU 0 initilization will be done via uv_system_init. */
523         if (!uv_blade_info)
524                 return;
525
526         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
527
528         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
529                 set_x2apic_extra_bits(uv_hub_info->pnode);
530 }
531
532
533 void __init uv_system_init(void)
534 {
535         union uvh_si_addr_map_config_u m_n_config;
536         union uvh_node_id_u node_id;
537         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
538         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
539         int gnode_extra, max_pnode = 0;
540         unsigned long mmr_base, present, paddr;
541         unsigned short pnode_mask;
542
543         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
544         m_val = m_n_config.s.m_skt;
545         n_val = m_n_config.s.n_skt;
546         mmr_base =
547             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
548             ~UV_MMR_ENABLE;
549         pnode_mask = (1 << n_val) - 1;
550         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
551         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
552         gnode_upper = ((unsigned long)gnode_extra  << m_val);
553         printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
554                         n_val, m_val, gnode_upper, gnode_extra);
555
556         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
557
558         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
559                 uv_possible_blades +=
560                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
561         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
562
563         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
564         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
565         BUG_ON(!uv_blade_info);
566         for (blade = 0; blade < uv_num_possible_blades(); blade++)
567                 uv_blade_info[blade].memory_nid = -1;
568
569         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
570
571         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
572         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
573         BUG_ON(!uv_node_to_blade);
574         memset(uv_node_to_blade, 255, bytes);
575
576         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
577         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
578         BUG_ON(!uv_cpu_to_blade);
579         memset(uv_cpu_to_blade, 255, bytes);
580
581         blade = 0;
582         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
583                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
584                 for (j = 0; j < 64; j++) {
585                         if (!test_bit(j, &present))
586                                 continue;
587                         uv_blade_info[blade].pnode = (i * 64 + j);
588                         uv_blade_info[blade].nr_possible_cpus = 0;
589                         uv_blade_info[blade].nr_online_cpus = 0;
590                         blade++;
591                 }
592         }
593
594         uv_bios_init();
595         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
596                             &sn_coherency_id, &sn_region_size);
597         uv_rtc_init();
598
599         for_each_present_cpu(cpu) {
600                 nid = cpu_to_node(cpu);
601                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
602                 blade = boot_pnode_to_blade(pnode);
603                 lcpu = uv_blade_info[blade].nr_possible_cpus;
604                 uv_blade_info[blade].nr_possible_cpus++;
605
606                 /* Any node on the blade, else will contain -1. */
607                 uv_blade_info[blade].memory_nid = nid;
608
609                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
610                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
611                 uv_cpu_hub_info(cpu)->m_val = m_val;
612                 uv_cpu_hub_info(cpu)->n_val = m_val;
613                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
614                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
615                 uv_cpu_hub_info(cpu)->pnode = pnode;
616                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
617                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
618                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
619                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
620                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
621                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
622                 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;
623                 uv_node_to_blade[nid] = blade;
624                 uv_cpu_to_blade[cpu] = blade;
625                 max_pnode = max(pnode, max_pnode);
626
627                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
628                         "lcpu %d, blade %d\n",
629                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
630                         lcpu, blade);
631         }
632
633         /* Add blade/pnode info for nodes without cpus */
634         for_each_online_node(nid) {
635                 if (uv_node_to_blade[nid] >= 0)
636                         continue;
637                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
638                 paddr = uv_soc_phys_ram_to_gpa(paddr);
639                 pnode = (paddr >> m_val) & pnode_mask;
640                 blade = boot_pnode_to_blade(pnode);
641                 uv_node_to_blade[nid] = blade;
642                 max_pnode = max(pnode, max_pnode);
643         }
644
645         map_gru_high(max_pnode);
646         map_mmioh_high(max_pnode);
647
648         uv_cpu_init();
649         uv_scir_register_cpu_notifier();
650         proc_mkdir("sgi_uv", NULL);
651 }