Merge branch 'master' of /pub/scm/linux/kernel/git/torvalds/linux-2.6
[linux-2.6] / drivers / scsi / stex.c
1 /*
2  * SuperTrak EX Series Storage Controller driver for Linux
3  *
4  *      Copyright (C) 2005, 2006 Promise Technology Inc.
5  *
6  *      This program is free software; you can redistribute it and/or
7  *      modify it under the terms of the GNU General Public License
8  *      as published by the Free Software Foundation; either version
9  *      2 of the License, or (at your option) any later version.
10  *
11  *      Written By:
12  *              Ed Lin <promise_linux@promise.com>
13  *
14  */
15
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/time.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/interrupt.h>
24 #include <linux/types.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <asm/io.h>
28 #include <asm/irq.h>
29 #include <asm/byteorder.h>
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_tcq.h>
35 #include <scsi/scsi_dbg.h>
36 #include <scsi/scsi_eh.h>
37
38 #define DRV_NAME "stex"
39 #define ST_DRIVER_VERSION "3.6.0000.1"
40 #define ST_VER_MAJOR            3
41 #define ST_VER_MINOR            6
42 #define ST_OEM                  0
43 #define ST_BUILD_VER            1
44
45 enum {
46         /* MU register offset */
47         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
48         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
49         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
50         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
51         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
52         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
53         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
54         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
55         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
56         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
57
58         /* MU register value */
59         MU_INBOUND_DOORBELL_HANDSHAKE           = 1,
60         MU_INBOUND_DOORBELL_REQHEADCHANGED      = 2,
61         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = 4,
62         MU_INBOUND_DOORBELL_HMUSTOPPED          = 8,
63         MU_INBOUND_DOORBELL_RESET               = 16,
64
65         MU_OUTBOUND_DOORBELL_HANDSHAKE          = 1,
66         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
67         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = 4,
68         MU_OUTBOUND_DOORBELL_BUSCHANGE          = 8,
69         MU_OUTBOUND_DOORBELL_HASEVENT           = 16,
70
71         /* MU status code */
72         MU_STATE_STARTING                       = 1,
73         MU_STATE_FMU_READY_FOR_HANDSHAKE        = 2,
74         MU_STATE_SEND_HANDSHAKE_FRAME           = 3,
75         MU_STATE_STARTED                        = 4,
76         MU_STATE_RESETTING                      = 5,
77
78         MU_MAX_DELAY                            = 120,
79         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
80         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
81         MU_HARD_RESET_WAIT                      = 30000,
82         HMU_PARTNER_TYPE                        = 2,
83
84         /* firmware returned values */
85         SRB_STATUS_SUCCESS                      = 0x01,
86         SRB_STATUS_ERROR                        = 0x04,
87         SRB_STATUS_BUSY                         = 0x05,
88         SRB_STATUS_INVALID_REQUEST              = 0x06,
89         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
90         SRB_SEE_SENSE                           = 0x80,
91
92         /* task attribute */
93         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
94         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
95         TASK_ATTRIBUTE_ORDERED                  = 0x2,
96         TASK_ATTRIBUTE_ACA                      = 0x4,
97
98         /* request count, etc. */
99         MU_MAX_REQUEST                          = 32,
100
101         /* one message wasted, use MU_MAX_REQUEST+1
102                 to handle MU_MAX_REQUEST messages */
103         MU_REQ_COUNT                            = (MU_MAX_REQUEST + 1),
104         MU_STATUS_COUNT                         = (MU_MAX_REQUEST + 1),
105
106         STEX_CDB_LENGTH                         = MAX_COMMAND_SIZE,
107         REQ_VARIABLE_LEN                        = 1024,
108         STATUS_VAR_LEN                          = 128,
109         ST_CAN_QUEUE                            = MU_MAX_REQUEST,
110         ST_CMD_PER_LUN                          = MU_MAX_REQUEST,
111         ST_MAX_SG                               = 32,
112
113         /* sg flags */
114         SG_CF_EOT                               = 0x80, /* end of table */
115         SG_CF_64B                               = 0x40, /* 64 bit item */
116         SG_CF_HOST                              = 0x20, /* sg in host memory */
117
118         st_shasta                               = 0,
119         st_vsc                                  = 1,
120         st_vsc1                                 = 2,
121         st_yosemite                             = 3,
122
123         PASSTHRU_REQ_TYPE                       = 0x00000001,
124         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
125         ST_INTERNAL_TIMEOUT                     = 30,
126
127         ST_TO_CMD                               = 0,
128         ST_FROM_CMD                             = 1,
129
130         /* vendor specific commands of Promise */
131         MGT_CMD                                 = 0xd8,
132         SINBAND_MGT_CMD                         = 0xd9,
133         ARRAY_CMD                               = 0xe0,
134         CONTROLLER_CMD                          = 0xe1,
135         DEBUGGING_CMD                           = 0xe2,
136         PASSTHRU_CMD                            = 0xe3,
137
138         PASSTHRU_GET_ADAPTER                    = 0x05,
139         PASSTHRU_GET_DRVVER                     = 0x10,
140
141         CTLR_CONFIG_CMD                         = 0x03,
142         CTLR_SHUTDOWN                           = 0x0d,
143
144         CTLR_POWER_STATE_CHANGE                 = 0x0e,
145         CTLR_POWER_SAVING                       = 0x01,
146
147         PASSTHRU_SIGNATURE                      = 0x4e415041,
148         MGT_CMD_SIGNATURE                       = 0xba,
149
150         INQUIRY_EVPD                            = 0x01,
151
152         ST_ADDITIONAL_MEM                       = 0x200000,
153 };
154
155 /* SCSI inquiry data */
156 typedef struct st_inq {
157         u8 DeviceType                   :5;
158         u8 DeviceTypeQualifier          :3;
159         u8 DeviceTypeModifier           :7;
160         u8 RemovableMedia               :1;
161         u8 Versions;
162         u8 ResponseDataFormat           :4;
163         u8 HiSupport                    :1;
164         u8 NormACA                      :1;
165         u8 ReservedBit                  :1;
166         u8 AERC                         :1;
167         u8 AdditionalLength;
168         u8 Reserved[2];
169         u8 SoftReset                    :1;
170         u8 CommandQueue                 :1;
171         u8 Reserved2                    :1;
172         u8 LinkedCommands               :1;
173         u8 Synchronous                  :1;
174         u8 Wide16Bit                    :1;
175         u8 Wide32Bit                    :1;
176         u8 RelativeAddressing           :1;
177         u8 VendorId[8];
178         u8 ProductId[16];
179         u8 ProductRevisionLevel[4];
180         u8 VendorSpecific[20];
181         u8 Reserved3[40];
182 } ST_INQ;
183
184 struct st_sgitem {
185         u8 ctrl;        /* SG_CF_xxx */
186         u8 reserved[3];
187         __le32 count;
188         __le32 addr;
189         __le32 addr_hi;
190 };
191
192 struct st_sgtable {
193         __le16 sg_count;
194         __le16 max_sg_count;
195         __le32 sz_in_byte;
196         struct st_sgitem table[ST_MAX_SG];
197 };
198
199 struct handshake_frame {
200         __le32 rb_phy;          /* request payload queue physical address */
201         __le32 rb_phy_hi;
202         __le16 req_sz;          /* size of each request payload */
203         __le16 req_cnt;         /* count of reqs the buffer can hold */
204         __le16 status_sz;       /* size of each status payload */
205         __le16 status_cnt;      /* count of status the buffer can hold */
206         __le32 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
207         __le32 hosttime_hi;
208         u8 partner_type;        /* who sends this frame */
209         u8 reserved0[7];
210         __le32 partner_ver_major;
211         __le32 partner_ver_minor;
212         __le32 partner_ver_oem;
213         __le32 partner_ver_build;
214         __le32 extra_offset;    /* NEW */
215         __le32 extra_size;      /* NEW */
216         u32 reserved1[2];
217 };
218
219 struct req_msg {
220         __le16 tag;
221         u8 lun;
222         u8 target;
223         u8 task_attr;
224         u8 task_manage;
225         u8 prd_entry;
226         u8 payload_sz;          /* payload size in 4-byte, not used */
227         u8 cdb[STEX_CDB_LENGTH];
228         u8 variable[REQ_VARIABLE_LEN];
229 };
230
231 struct status_msg {
232         __le16 tag;
233         u8 lun;
234         u8 target;
235         u8 srb_status;
236         u8 scsi_status;
237         u8 reserved;
238         u8 payload_sz;          /* payload size in 4-byte */
239         u8 variable[STATUS_VAR_LEN];
240 };
241
242 struct ver_info {
243         u32 major;
244         u32 minor;
245         u32 oem;
246         u32 build;
247         u32 reserved[2];
248 };
249
250 struct st_frame {
251         u32 base[6];
252         u32 rom_addr;
253
254         struct ver_info drv_ver;
255         struct ver_info bios_ver;
256
257         u32 bus;
258         u32 slot;
259         u32 irq_level;
260         u32 irq_vec;
261         u32 id;
262         u32 subid;
263
264         u32 dimm_size;
265         u8 dimm_type;
266         u8 reserved[3];
267
268         u32 channel;
269         u32 reserved1;
270 };
271
272 struct st_drvver {
273         u32 major;
274         u32 minor;
275         u32 oem;
276         u32 build;
277         u32 signature[2];
278         u8 console_id;
279         u8 host_no;
280         u8 reserved0[2];
281         u32 reserved[3];
282 };
283
284 #define MU_REQ_BUFFER_SIZE      (MU_REQ_COUNT * sizeof(struct req_msg))
285 #define MU_STATUS_BUFFER_SIZE   (MU_STATUS_COUNT * sizeof(struct status_msg))
286 #define MU_BUFFER_SIZE          (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
287 #define STEX_EXTRA_SIZE         max(sizeof(struct st_frame), sizeof(ST_INQ))
288 #define STEX_BUFFER_SIZE        (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
289
290 struct st_ccb {
291         struct req_msg *req;
292         struct scsi_cmnd *cmd;
293
294         void *sense_buffer;
295         unsigned int sense_bufflen;
296         int sg_count;
297
298         u32 req_type;
299         u8 srb_status;
300         u8 scsi_status;
301 };
302
303 struct st_hba {
304         void __iomem *mmio_base;        /* iomapped PCI memory space */
305         void *dma_mem;
306         dma_addr_t dma_handle;
307         size_t dma_size;
308
309         struct Scsi_Host *host;
310         struct pci_dev *pdev;
311
312         u32 req_head;
313         u32 req_tail;
314         u32 status_head;
315         u32 status_tail;
316
317         struct status_msg *status_buffer;
318         void *copy_buffer; /* temp buffer for driver-handled commands */
319         struct st_ccb ccb[MU_MAX_REQUEST];
320         struct st_ccb *wait_ccb;
321         wait_queue_head_t waitq;
322
323         unsigned int mu_status;
324         int out_req_cnt;
325
326         unsigned int cardtype;
327 };
328
329 static const char console_inq_page[] =
330 {
331         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
332         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
333         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
334         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
335         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
336         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
337         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
338         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
339 };
340
341 MODULE_AUTHOR("Ed Lin");
342 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
343 MODULE_LICENSE("GPL");
344 MODULE_VERSION(ST_DRIVER_VERSION);
345
346 static void stex_gettime(__le32 *time)
347 {
348         struct timeval tv;
349         do_gettimeofday(&tv);
350
351         *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
352         *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
353 }
354
355 static struct status_msg *stex_get_status(struct st_hba *hba)
356 {
357         struct status_msg *status =
358                 hba->status_buffer + hba->status_tail;
359
360         ++hba->status_tail;
361         hba->status_tail %= MU_STATUS_COUNT;
362
363         return status;
364 }
365
366 static void stex_invalid_field(struct scsi_cmnd *cmd,
367                                void (*done)(struct scsi_cmnd *))
368 {
369         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
370
371         /* "Invalid field in cbd" */
372         scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
373                                 0x0);
374         done(cmd);
375 }
376
377 static struct req_msg *stex_alloc_req(struct st_hba *hba)
378 {
379         struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
380                 hba->req_head;
381
382         ++hba->req_head;
383         hba->req_head %= MU_REQ_COUNT;
384
385         return req;
386 }
387
388 static int stex_map_sg(struct st_hba *hba,
389         struct req_msg *req, struct st_ccb *ccb)
390 {
391         struct scsi_cmnd *cmd;
392         struct scatterlist *sg;
393         struct st_sgtable *dst;
394         int i, nseg;
395
396         cmd = ccb->cmd;
397         dst = (struct st_sgtable *)req->variable;
398         dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
399         dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
400
401         nseg = scsi_dma_map(cmd);
402         if (nseg < 0)
403                 return -EIO;
404         if (nseg) {
405                 ccb->sg_count = nseg;
406                 dst->sg_count = cpu_to_le16((u16)nseg);
407
408                 scsi_for_each_sg(cmd, sg, nseg, i) {
409                         dst->table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
410                         dst->table[i].addr =
411                                 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
412                         dst->table[i].addr_hi =
413                                 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
414                         dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
415                 }
416                 dst->table[--i].ctrl |= SG_CF_EOT;
417         }
418
419         return 0;
420 }
421
422 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
423 {
424         struct st_frame *p;
425         size_t count = sizeof(struct st_frame);
426
427         p = hba->copy_buffer;
428         count = scsi_sg_copy_to_buffer(ccb->cmd, p, count);
429         memset(p->base, 0, sizeof(u32)*6);
430         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
431         p->rom_addr = 0;
432
433         p->drv_ver.major = ST_VER_MAJOR;
434         p->drv_ver.minor = ST_VER_MINOR;
435         p->drv_ver.oem = ST_OEM;
436         p->drv_ver.build = ST_BUILD_VER;
437
438         p->bus = hba->pdev->bus->number;
439         p->slot = hba->pdev->devfn;
440         p->irq_level = 0;
441         p->irq_vec = hba->pdev->irq;
442         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
443         p->subid =
444                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
445
446         count = scsi_sg_copy_from_buffer(ccb->cmd, p, count);
447 }
448
449 static void
450 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
451 {
452         req->tag = cpu_to_le16(tag);
453         req->task_attr = TASK_ATTRIBUTE_SIMPLE;
454         req->task_manage = 0; /* not supported yet */
455
456         hba->ccb[tag].req = req;
457         hba->out_req_cnt++;
458
459         writel(hba->req_head, hba->mmio_base + IMR0);
460         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
461         readl(hba->mmio_base + IDBL); /* flush */
462 }
463
464 static int
465 stex_slave_alloc(struct scsi_device *sdev)
466 {
467         /* Cheat: usually extracted from Inquiry data */
468         sdev->tagged_supported = 1;
469
470         scsi_activate_tcq(sdev, sdev->host->can_queue);
471
472         return 0;
473 }
474
475 static int
476 stex_slave_config(struct scsi_device *sdev)
477 {
478         sdev->use_10_for_rw = 1;
479         sdev->use_10_for_ms = 1;
480         sdev->timeout = 60 * HZ;
481         sdev->tagged_supported = 1;
482
483         return 0;
484 }
485
486 static void
487 stex_slave_destroy(struct scsi_device *sdev)
488 {
489         scsi_deactivate_tcq(sdev, 1);
490 }
491
492 static int
493 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
494 {
495         struct st_hba *hba;
496         struct Scsi_Host *host;
497         unsigned int id,lun;
498         struct req_msg *req;
499         u16 tag;
500         host = cmd->device->host;
501         id = cmd->device->id;
502         lun = cmd->device->lun;
503         hba = (struct st_hba *) &host->hostdata[0];
504
505         switch (cmd->cmnd[0]) {
506         case MODE_SENSE_10:
507         {
508                 static char ms10_caching_page[12] =
509                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
510                 unsigned char page;
511                 page = cmd->cmnd[2] & 0x3f;
512                 if (page == 0x8 || page == 0x3f) {
513                         scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
514                                                  sizeof(ms10_caching_page));
515                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
516                         done(cmd);
517                 } else
518                         stex_invalid_field(cmd, done);
519                 return 0;
520         }
521         case REPORT_LUNS:
522                 /*
523                  * The shasta firmware does not report actual luns in the
524                  * target, so fail the command to force sequential lun scan.
525                  * Also, the console device does not support this command.
526                  */
527                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
528                         stex_invalid_field(cmd, done);
529                         return 0;
530                 }
531                 break;
532         case TEST_UNIT_READY:
533                 if (id == host->max_id - 1) {
534                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
535                         done(cmd);
536                         return 0;
537                 }
538                 break;
539         case INQUIRY:
540                 if (id != host->max_id - 1)
541                         break;
542                 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
543                         scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
544                                                  sizeof(console_inq_page));
545                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
546                         done(cmd);
547                 } else
548                         stex_invalid_field(cmd, done);
549                 return 0;
550         case PASSTHRU_CMD:
551                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
552                         struct st_drvver ver;
553                         size_t cp_len = sizeof(ver);
554                         ver.major = ST_VER_MAJOR;
555                         ver.minor = ST_VER_MINOR;
556                         ver.oem = ST_OEM;
557                         ver.build = ST_BUILD_VER;
558                         ver.signature[0] = PASSTHRU_SIGNATURE;
559                         ver.console_id = host->max_id - 1;
560                         ver.host_no = hba->host->host_no;
561                         cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
562                         cmd->result = sizeof(ver) == cp_len ?
563                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
564                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
565                         done(cmd);
566                         return 0;
567                 }
568         default:
569                 break;
570         }
571
572         cmd->scsi_done = done;
573
574         tag = cmd->request->tag;
575
576         if (unlikely(tag >= host->can_queue))
577                 return SCSI_MLQUEUE_HOST_BUSY;
578
579         req = stex_alloc_req(hba);
580
581         req->lun = lun;
582         req->target = id;
583
584         /* cdb */
585         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
586
587         hba->ccb[tag].cmd = cmd;
588         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
589         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
590         hba->ccb[tag].req_type = 0;
591
592         if (cmd->sc_data_direction != DMA_NONE)
593                 stex_map_sg(hba, req, &hba->ccb[tag]);
594
595         stex_send_cmd(hba, req, tag);
596         return 0;
597 }
598
599 static void stex_scsi_done(struct st_ccb *ccb)
600 {
601         struct scsi_cmnd *cmd = ccb->cmd;
602         int result;
603
604         if (ccb->srb_status == SRB_STATUS_SUCCESS ||  ccb->srb_status == 0) {
605                 result = ccb->scsi_status;
606                 switch (ccb->scsi_status) {
607                 case SAM_STAT_GOOD:
608                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
609                         break;
610                 case SAM_STAT_CHECK_CONDITION:
611                         result |= DRIVER_SENSE << 24;
612                         break;
613                 case SAM_STAT_BUSY:
614                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
615                         break;
616                 default:
617                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
618                         break;
619                 }
620         }
621         else if (ccb->srb_status & SRB_SEE_SENSE)
622                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
623         else switch (ccb->srb_status) {
624                 case SRB_STATUS_SELECTION_TIMEOUT:
625                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
626                         break;
627                 case SRB_STATUS_BUSY:
628                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
629                         break;
630                 case SRB_STATUS_INVALID_REQUEST:
631                 case SRB_STATUS_ERROR:
632                 default:
633                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
634                         break;
635         }
636
637         cmd->result = result;
638         cmd->scsi_done(cmd);
639 }
640
641 static void stex_copy_data(struct st_ccb *ccb,
642         struct status_msg *resp, unsigned int variable)
643 {
644         size_t count = variable;
645         if (resp->scsi_status != SAM_STAT_GOOD) {
646                 if (ccb->sense_buffer != NULL)
647                         memcpy(ccb->sense_buffer, resp->variable,
648                                 min(variable, ccb->sense_bufflen));
649                 return;
650         }
651
652         if (ccb->cmd == NULL)
653                 return;
654         count = scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, count);
655 }
656
657 static void stex_ys_commands(struct st_hba *hba,
658         struct st_ccb *ccb, struct status_msg *resp)
659 {
660         if (ccb->cmd->cmnd[0] == MGT_CMD &&
661                 resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
662                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
663                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
664                 return;
665         }
666
667         if (resp->srb_status != 0)
668                 return;
669
670         /* determine inquiry command status by DeviceTypeQualifier */
671         if (ccb->cmd->cmnd[0] == INQUIRY &&
672                 resp->scsi_status == SAM_STAT_GOOD) {
673                 ST_INQ *inq_data;
674
675                 scsi_sg_copy_to_buffer(ccb->cmd, hba->copy_buffer,
676                                        STEX_EXTRA_SIZE);
677                 inq_data = (ST_INQ *)hba->copy_buffer;
678                 if (inq_data->DeviceTypeQualifier != 0)
679                         ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
680                 else
681                         ccb->srb_status = SRB_STATUS_SUCCESS;
682         }
683 }
684
685 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
686 {
687         void __iomem *base = hba->mmio_base;
688         struct status_msg *resp;
689         struct st_ccb *ccb;
690         unsigned int size;
691         u16 tag;
692
693         if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
694                 return;
695
696         /* status payloads */
697         hba->status_head = readl(base + OMR1);
698         if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
699                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
700                         pci_name(hba->pdev));
701                 return;
702         }
703
704         /*
705          * it's not a valid status payload if:
706          * 1. there are no pending requests(e.g. during init stage)
707          * 2. there are some pending requests, but the controller is in
708          *     reset status, and its type is not st_yosemite
709          * firmware of st_yosemite in reset status will return pending requests
710          * to driver, so we allow it to pass
711          */
712         if (unlikely(hba->out_req_cnt <= 0 ||
713                         (hba->mu_status == MU_STATE_RESETTING &&
714                          hba->cardtype != st_yosemite))) {
715                 hba->status_tail = hba->status_head;
716                 goto update_status;
717         }
718
719         while (hba->status_tail != hba->status_head) {
720                 resp = stex_get_status(hba);
721                 tag = le16_to_cpu(resp->tag);
722                 if (unlikely(tag >= hba->host->can_queue)) {
723                         printk(KERN_WARNING DRV_NAME
724                                 "(%s): invalid tag\n", pci_name(hba->pdev));
725                         continue;
726                 }
727
728                 ccb = &hba->ccb[tag];
729                 if (hba->wait_ccb == ccb)
730                         hba->wait_ccb = NULL;
731                 if (unlikely(ccb->req == NULL)) {
732                         printk(KERN_WARNING DRV_NAME
733                                 "(%s): lagging req\n", pci_name(hba->pdev));
734                         hba->out_req_cnt--;
735                         continue;
736                 }
737
738                 size = resp->payload_sz * sizeof(u32); /* payload size */
739                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
740                         size > sizeof(*resp))) {
741                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
742                                 pci_name(hba->pdev));
743                 } else {
744                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
745                         if (size)
746                                 stex_copy_data(ccb, resp, size);
747                 }
748
749                 ccb->srb_status = resp->srb_status;
750                 ccb->scsi_status = resp->scsi_status;
751
752                 if (likely(ccb->cmd != NULL)) {
753                         if (hba->cardtype == st_yosemite)
754                                 stex_ys_commands(hba, ccb, resp);
755
756                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
757                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
758                                 stex_controller_info(hba, ccb);
759
760                         scsi_dma_unmap(ccb->cmd);
761                         stex_scsi_done(ccb);
762                         hba->out_req_cnt--;
763                 } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
764                         hba->out_req_cnt--;
765                         if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
766                                 ccb->req_type = 0;
767                                 continue;
768                         }
769                         ccb->req_type = 0;
770                         if (waitqueue_active(&hba->waitq))
771                                 wake_up(&hba->waitq);
772                 }
773         }
774
775 update_status:
776         writel(hba->status_head, base + IMR1);
777         readl(base + IMR1); /* flush */
778 }
779
780 static irqreturn_t stex_intr(int irq, void *__hba)
781 {
782         struct st_hba *hba = __hba;
783         void __iomem *base = hba->mmio_base;
784         u32 data;
785         unsigned long flags;
786         int handled = 0;
787
788         spin_lock_irqsave(hba->host->host_lock, flags);
789
790         data = readl(base + ODBL);
791
792         if (data && data != 0xffffffff) {
793                 /* clear the interrupt */
794                 writel(data, base + ODBL);
795                 readl(base + ODBL); /* flush */
796                 stex_mu_intr(hba, data);
797                 handled = 1;
798         }
799
800         spin_unlock_irqrestore(hba->host->host_lock, flags);
801
802         return IRQ_RETVAL(handled);
803 }
804
805 static int stex_handshake(struct st_hba *hba)
806 {
807         void __iomem *base = hba->mmio_base;
808         struct handshake_frame *h;
809         dma_addr_t status_phys;
810         u32 data;
811         unsigned long before;
812
813         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
814                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
815                 readl(base + IDBL);
816                 before = jiffies;
817                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
818                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
819                                 printk(KERN_ERR DRV_NAME
820                                         "(%s): no handshake signature\n",
821                                         pci_name(hba->pdev));
822                                 return -1;
823                         }
824                         rmb();
825                         msleep(1);
826                 }
827         }
828
829         udelay(10);
830
831         data = readl(base + OMR1);
832         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
833                 data &= 0x0000ffff;
834                 if (hba->host->can_queue > data)
835                         hba->host->can_queue = data;
836         }
837
838         h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
839         h->rb_phy = cpu_to_le32(hba->dma_handle);
840         h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
841         h->req_sz = cpu_to_le16(sizeof(struct req_msg));
842         h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
843         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
844         h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
845         stex_gettime(&h->hosttime);
846         h->partner_type = HMU_PARTNER_TYPE;
847         if (hba->dma_size > STEX_BUFFER_SIZE) {
848                 h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
849                 h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
850         } else
851                 h->extra_offset = h->extra_size = 0;
852
853         status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
854         writel(status_phys, base + IMR0);
855         readl(base + IMR0);
856         writel((status_phys >> 16) >> 16, base + IMR1);
857         readl(base + IMR1);
858
859         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
860         readl(base + OMR0);
861         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
862         readl(base + IDBL); /* flush */
863
864         udelay(10);
865         before = jiffies;
866         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
867                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
868                         printk(KERN_ERR DRV_NAME
869                                 "(%s): no signature after handshake frame\n",
870                                 pci_name(hba->pdev));
871                         return -1;
872                 }
873                 rmb();
874                 msleep(1);
875         }
876
877         writel(0, base + IMR0);
878         readl(base + IMR0);
879         writel(0, base + OMR0);
880         readl(base + OMR0);
881         writel(0, base + IMR1);
882         readl(base + IMR1);
883         writel(0, base + OMR1);
884         readl(base + OMR1); /* flush */
885         hba->mu_status = MU_STATE_STARTED;
886         return 0;
887 }
888
889 static int stex_abort(struct scsi_cmnd *cmd)
890 {
891         struct Scsi_Host *host = cmd->device->host;
892         struct st_hba *hba = (struct st_hba *)host->hostdata;
893         u16 tag = cmd->request->tag;
894         void __iomem *base;
895         u32 data;
896         int result = SUCCESS;
897         unsigned long flags;
898
899         printk(KERN_INFO DRV_NAME
900                 "(%s): aborting command\n", pci_name(hba->pdev));
901         scsi_print_command(cmd);
902
903         base = hba->mmio_base;
904         spin_lock_irqsave(host->host_lock, flags);
905         if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
906                 hba->wait_ccb = &hba->ccb[tag];
907         else {
908                 for (tag = 0; tag < host->can_queue; tag++)
909                         if (hba->ccb[tag].cmd == cmd) {
910                                 hba->wait_ccb = &hba->ccb[tag];
911                                 break;
912                         }
913                 if (tag >= host->can_queue)
914                         goto out;
915         }
916
917         data = readl(base + ODBL);
918         if (data == 0 || data == 0xffffffff)
919                 goto fail_out;
920
921         writel(data, base + ODBL);
922         readl(base + ODBL); /* flush */
923
924         stex_mu_intr(hba, data);
925
926         if (hba->wait_ccb == NULL) {
927                 printk(KERN_WARNING DRV_NAME
928                         "(%s): lost interrupt\n", pci_name(hba->pdev));
929                 goto out;
930         }
931
932 fail_out:
933         scsi_dma_unmap(cmd);
934         hba->wait_ccb->req = NULL; /* nullify the req's future return */
935         hba->wait_ccb = NULL;
936         result = FAILED;
937 out:
938         spin_unlock_irqrestore(host->host_lock, flags);
939         return result;
940 }
941
942 static void stex_hard_reset(struct st_hba *hba)
943 {
944         struct pci_bus *bus;
945         int i;
946         u16 pci_cmd;
947         u8 pci_bctl;
948
949         for (i = 0; i < 16; i++)
950                 pci_read_config_dword(hba->pdev, i * 4,
951                         &hba->pdev->saved_config_space[i]);
952
953         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
954            secondary bus. Consult Intel 80331/3 developer's manual for detail */
955         bus = hba->pdev->bus;
956         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
957         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
958         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
959
960         /*
961          * 1 ms may be enough for 8-port controllers. But 16-port controllers
962          * require more time to finish bus reset. Use 100 ms here for safety
963          */
964         msleep(100);
965         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
966         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
967
968         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
969                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
970                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
971                         break;
972                 msleep(1);
973         }
974
975         ssleep(5);
976         for (i = 0; i < 16; i++)
977                 pci_write_config_dword(hba->pdev, i * 4,
978                         hba->pdev->saved_config_space[i]);
979 }
980
981 static int stex_reset(struct scsi_cmnd *cmd)
982 {
983         struct st_hba *hba;
984         unsigned long flags;
985         unsigned long before;
986         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
987
988         printk(KERN_INFO DRV_NAME
989                 "(%s): resetting host\n", pci_name(hba->pdev));
990         scsi_print_command(cmd);
991
992         hba->mu_status = MU_STATE_RESETTING;
993
994         if (hba->cardtype == st_shasta)
995                 stex_hard_reset(hba);
996
997         if (hba->cardtype != st_yosemite) {
998                 if (stex_handshake(hba)) {
999                         printk(KERN_WARNING DRV_NAME
1000                                 "(%s): resetting: handshake failed\n",
1001                                 pci_name(hba->pdev));
1002                         return FAILED;
1003                 }
1004                 spin_lock_irqsave(hba->host->host_lock, flags);
1005                 hba->req_head = 0;
1006                 hba->req_tail = 0;
1007                 hba->status_head = 0;
1008                 hba->status_tail = 0;
1009                 hba->out_req_cnt = 0;
1010                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1011                 return SUCCESS;
1012         }
1013
1014         /* st_yosemite */
1015         writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
1016         readl(hba->mmio_base + IDBL); /* flush */
1017         before = jiffies;
1018         while (hba->out_req_cnt > 0) {
1019                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1020                         printk(KERN_WARNING DRV_NAME
1021                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1022                         return FAILED;
1023                 }
1024                 msleep(1);
1025         }
1026
1027         hba->mu_status = MU_STATE_STARTED;
1028         return SUCCESS;
1029 }
1030
1031 static int stex_biosparam(struct scsi_device *sdev,
1032         struct block_device *bdev, sector_t capacity, int geom[])
1033 {
1034         int heads = 255, sectors = 63;
1035
1036         if (capacity < 0x200000) {
1037                 heads = 64;
1038                 sectors = 32;
1039         }
1040
1041         sector_div(capacity, heads * sectors);
1042
1043         geom[0] = heads;
1044         geom[1] = sectors;
1045         geom[2] = capacity;
1046
1047         return 0;
1048 }
1049
1050 static struct scsi_host_template driver_template = {
1051         .module                         = THIS_MODULE,
1052         .name                           = DRV_NAME,
1053         .proc_name                      = DRV_NAME,
1054         .bios_param                     = stex_biosparam,
1055         .queuecommand                   = stex_queuecommand,
1056         .slave_alloc                    = stex_slave_alloc,
1057         .slave_configure                = stex_slave_config,
1058         .slave_destroy                  = stex_slave_destroy,
1059         .eh_abort_handler               = stex_abort,
1060         .eh_host_reset_handler          = stex_reset,
1061         .can_queue                      = ST_CAN_QUEUE,
1062         .this_id                        = -1,
1063         .sg_tablesize                   = ST_MAX_SG,
1064         .cmd_per_lun                    = ST_CMD_PER_LUN,
1065 };
1066
1067 static int stex_set_dma_mask(struct pci_dev * pdev)
1068 {
1069         int ret;
1070         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1071                 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1072                 return 0;
1073         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1074         if (!ret)
1075                 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1076         return ret;
1077 }
1078
1079 static int __devinit
1080 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1081 {
1082         struct st_hba *hba;
1083         struct Scsi_Host *host;
1084         int err;
1085
1086         err = pci_enable_device(pdev);
1087         if (err)
1088                 return err;
1089
1090         pci_set_master(pdev);
1091
1092         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1093
1094         if (!host) {
1095                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1096                         pci_name(pdev));
1097                 err = -ENOMEM;
1098                 goto out_disable;
1099         }
1100
1101         hba = (struct st_hba *)host->hostdata;
1102         memset(hba, 0, sizeof(struct st_hba));
1103
1104         err = pci_request_regions(pdev, DRV_NAME);
1105         if (err < 0) {
1106                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1107                         pci_name(pdev));
1108                 goto out_scsi_host_put;
1109         }
1110
1111         hba->mmio_base = ioremap_nocache(pci_resource_start(pdev, 0),
1112                 pci_resource_len(pdev, 0));
1113         if ( !hba->mmio_base) {
1114                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1115                         pci_name(pdev));
1116                 err = -ENOMEM;
1117                 goto out_release_regions;
1118         }
1119
1120         err = stex_set_dma_mask(pdev);
1121         if (err) {
1122                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1123                         pci_name(pdev));
1124                 goto out_iounmap;
1125         }
1126
1127         hba->cardtype = (unsigned int) id->driver_data;
1128         if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
1129                 hba->cardtype = st_vsc1;
1130         hba->dma_size = (hba->cardtype == st_vsc1) ?
1131                 (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
1132         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1133                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1134         if (!hba->dma_mem) {
1135                 err = -ENOMEM;
1136                 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1137                         pci_name(pdev));
1138                 goto out_iounmap;
1139         }
1140
1141         hba->status_buffer =
1142                 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1143         hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1144         hba->mu_status = MU_STATE_STARTING;
1145
1146         if (hba->cardtype == st_shasta) {
1147                 host->max_lun = 8;
1148                 host->max_id = 16 + 1;
1149         } else if (hba->cardtype == st_yosemite) {
1150                 host->max_lun = 128;
1151                 host->max_id = 1 + 1;
1152         } else {
1153                 /* st_vsc and st_vsc1 */
1154                 host->max_lun = 1;
1155                 host->max_id = 128 + 1;
1156         }
1157         host->max_channel = 0;
1158         host->unique_id = host->host_no;
1159         host->max_cmd_len = STEX_CDB_LENGTH;
1160
1161         hba->host = host;
1162         hba->pdev = pdev;
1163         init_waitqueue_head(&hba->waitq);
1164
1165         err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1166         if (err) {
1167                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1168                         pci_name(pdev));
1169                 goto out_pci_free;
1170         }
1171
1172         err = stex_handshake(hba);
1173         if (err)
1174                 goto out_free_irq;
1175
1176         err = scsi_init_shared_tag_map(host, host->can_queue);
1177         if (err) {
1178                 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1179                         pci_name(pdev));
1180                 goto out_free_irq;
1181         }
1182
1183         pci_set_drvdata(pdev, hba);
1184
1185         err = scsi_add_host(host, &pdev->dev);
1186         if (err) {
1187                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1188                         pci_name(pdev));
1189                 goto out_free_irq;
1190         }
1191
1192         scsi_scan_host(host);
1193
1194         return 0;
1195
1196 out_free_irq:
1197         free_irq(pdev->irq, hba);
1198 out_pci_free:
1199         dma_free_coherent(&pdev->dev, hba->dma_size,
1200                           hba->dma_mem, hba->dma_handle);
1201 out_iounmap:
1202         iounmap(hba->mmio_base);
1203 out_release_regions:
1204         pci_release_regions(pdev);
1205 out_scsi_host_put:
1206         scsi_host_put(host);
1207 out_disable:
1208         pci_disable_device(pdev);
1209
1210         return err;
1211 }
1212
1213 static void stex_hba_stop(struct st_hba *hba)
1214 {
1215         struct req_msg *req;
1216         unsigned long flags;
1217         unsigned long before;
1218         u16 tag = 0;
1219
1220         spin_lock_irqsave(hba->host->host_lock, flags);
1221         req = stex_alloc_req(hba);
1222         memset(req->cdb, 0, STEX_CDB_LENGTH);
1223
1224         if (hba->cardtype == st_yosemite) {
1225                 req->cdb[0] = MGT_CMD;
1226                 req->cdb[1] = MGT_CMD_SIGNATURE;
1227                 req->cdb[2] = CTLR_CONFIG_CMD;
1228                 req->cdb[3] = CTLR_SHUTDOWN;
1229         } else {
1230                 req->cdb[0] = CONTROLLER_CMD;
1231                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1232                 req->cdb[2] = CTLR_POWER_SAVING;
1233         }
1234
1235         hba->ccb[tag].cmd = NULL;
1236         hba->ccb[tag].sg_count = 0;
1237         hba->ccb[tag].sense_bufflen = 0;
1238         hba->ccb[tag].sense_buffer = NULL;
1239         hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
1240
1241         stex_send_cmd(hba, req, tag);
1242         spin_unlock_irqrestore(hba->host->host_lock, flags);
1243
1244         before = jiffies;
1245         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1246                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
1247                         return;
1248                 msleep(10);
1249         }
1250 }
1251
1252 static void stex_hba_free(struct st_hba *hba)
1253 {
1254         free_irq(hba->pdev->irq, hba);
1255
1256         iounmap(hba->mmio_base);
1257
1258         pci_release_regions(hba->pdev);
1259
1260         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1261                           hba->dma_mem, hba->dma_handle);
1262 }
1263
1264 static void stex_remove(struct pci_dev *pdev)
1265 {
1266         struct st_hba *hba = pci_get_drvdata(pdev);
1267
1268         scsi_remove_host(hba->host);
1269
1270         pci_set_drvdata(pdev, NULL);
1271
1272         stex_hba_stop(hba);
1273
1274         stex_hba_free(hba);
1275
1276         scsi_host_put(hba->host);
1277
1278         pci_disable_device(pdev);
1279 }
1280
1281 static void stex_shutdown(struct pci_dev *pdev)
1282 {
1283         struct st_hba *hba = pci_get_drvdata(pdev);
1284
1285         stex_hba_stop(hba);
1286 }
1287
1288 static struct pci_device_id stex_pci_tbl[] = {
1289         /* st_shasta */
1290         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1291                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1292         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1293                 st_shasta }, /* SuperTrak EX12350 */
1294         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1295                 st_shasta }, /* SuperTrak EX4350 */
1296         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1297                 st_shasta }, /* SuperTrak EX24350 */
1298
1299         /* st_vsc */
1300         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1301
1302         /* st_yosemite */
1303         { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
1304                 st_yosemite }, /* SuperTrak EX4650 */
1305         { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
1306                 st_yosemite }, /* SuperTrak EX4650o */
1307         { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
1308                 st_yosemite }, /* SuperTrak EX8650EL */
1309         { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
1310                 st_yosemite }, /* SuperTrak EX8650 */
1311         { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
1312                 st_yosemite }, /* SuperTrak EX8654 */
1313         { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1314                 st_yosemite }, /* generic st_yosemite */
1315         { }     /* terminate list */
1316 };
1317 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1318
1319 static struct pci_driver stex_pci_driver = {
1320         .name           = DRV_NAME,
1321         .id_table       = stex_pci_tbl,
1322         .probe          = stex_probe,
1323         .remove         = __devexit_p(stex_remove),
1324         .shutdown       = stex_shutdown,
1325 };
1326
1327 static int __init stex_init(void)
1328 {
1329         printk(KERN_INFO DRV_NAME
1330                 ": Promise SuperTrak EX Driver version: %s\n",
1331                  ST_DRIVER_VERSION);
1332
1333         return pci_register_driver(&stex_pci_driver);
1334 }
1335
1336 static void __exit stex_exit(void)
1337 {
1338         pci_unregister_driver(&stex_pci_driver);
1339 }
1340
1341 module_init(stex_init);
1342 module_exit(stex_exit);