Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
[linux-2.6] / drivers / mtd / nand / sharpsl.c
1 /*
2  * drivers/mtd/nand/sharpsl.c
3  *
4  *  Copyright (C) 2004 Richard Purdie
5  *
6  *  Based on Sharp's NAND driver sharp_sl.c
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  */
13
14 #include <linux/genhd.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/delay.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/nand_ecc.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/interrupt.h>
23 #include <asm/io.h>
24 #include <asm/hardware.h>
25 #include <asm/mach-types.h>
26
27 static void __iomem *sharpsl_io_base;
28 static int sharpsl_phys_base = 0x0C000000;
29
30 /* register offset */
31 #define ECCLPLB         sharpsl_io_base+0x00    /* line parity 7 - 0 bit */
32 #define ECCLPUB         sharpsl_io_base+0x04    /* line parity 15 - 8 bit */
33 #define ECCCP           sharpsl_io_base+0x08    /* column parity 5 - 0 bit */
34 #define ECCCNTR         sharpsl_io_base+0x0C    /* ECC byte counter */
35 #define ECCCLRR         sharpsl_io_base+0x10    /* cleare ECC */
36 #define FLASHIO         sharpsl_io_base+0x14    /* Flash I/O */
37 #define FLASHCTL        sharpsl_io_base+0x18    /* Flash Control */
38
39 /* Flash control bit */
40 #define FLRYBY          (1 << 5)
41 #define FLCE1           (1 << 4)
42 #define FLWP            (1 << 3)
43 #define FLALE           (1 << 2)
44 #define FLCLE           (1 << 1)
45 #define FLCE0           (1 << 0)
46
47 /*
48  * MTD structure for SharpSL
49  */
50 static struct mtd_info *sharpsl_mtd = NULL;
51
52 /*
53  * Define partitions for flash device
54  */
55 #define DEFAULT_NUM_PARTITIONS 3
56
57 static int nr_partitions;
58 static struct mtd_partition sharpsl_nand_default_partition_info[] = {
59         {
60          .name = "System Area",
61          .offset = 0,
62          .size = 7 * 1024 * 1024,
63          },
64         {
65          .name = "Root Filesystem",
66          .offset = 7 * 1024 * 1024,
67          .size = 30 * 1024 * 1024,
68          },
69         {
70          .name = "Home Filesystem",
71          .offset = MTDPART_OFS_APPEND,
72          .size = MTDPART_SIZ_FULL,
73          },
74 };
75
76 /*
77  *      hardware specific access to control-lines
78  *      ctrl:
79  *      NAND_CNE: bit 0 -> ! bit 0 & 4
80  *      NAND_CLE: bit 1 -> bit 1
81  *      NAND_ALE: bit 2 -> bit 2
82  *
83  */
84 static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd,
85                                    unsigned int ctrl)
86 {
87         struct nand_chip *chip = mtd->priv;
88
89         if (ctrl & NAND_CTRL_CHANGE) {
90                 unsigned char bits = ctrl & 0x07;
91
92                 bits |= (ctrl & 0x01) << 4;
93
94                 bits ^= 0x11;
95
96                 writeb((readb(FLASHCTL) & ~0x17) | bits, FLASHCTL);
97         }
98
99         if (cmd != NAND_CMD_NONE)
100                 writeb(cmd, chip->IO_ADDR_W);
101 }
102
103 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
104
105 static struct nand_bbt_descr sharpsl_bbt = {
106         .options = 0,
107         .offs = 4,
108         .len = 2,
109         .pattern = scan_ff_pattern
110 };
111
112 static struct nand_bbt_descr sharpsl_akita_bbt = {
113         .options = 0,
114         .offs = 4,
115         .len = 1,
116         .pattern = scan_ff_pattern
117 };
118
119 static struct nand_ecclayout akita_oobinfo = {
120         .eccbytes = 24,
121         .eccpos = {
122                    0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
123                    0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
124                    0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
125         .oobfree = {{0x08, 0x09}}
126 };
127
128 static int sharpsl_nand_dev_ready(struct mtd_info *mtd)
129 {
130         return !((readb(FLASHCTL) & FLRYBY) == 0);
131 }
132
133 static void sharpsl_nand_enable_hwecc(struct mtd_info *mtd, int mode)
134 {
135         writeb(0, ECCCLRR);
136 }
137
138 static int sharpsl_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat, u_char * ecc_code)
139 {
140         ecc_code[0] = ~readb(ECCLPUB);
141         ecc_code[1] = ~readb(ECCLPLB);
142         ecc_code[2] = (~readb(ECCCP) << 2) | 0x03;
143         return readb(ECCCNTR) != 0;
144 }
145
146 #ifdef CONFIG_MTD_PARTITIONS
147 const char *part_probes[] = { "cmdlinepart", NULL };
148 #endif
149
150 /*
151  * Main initialization routine
152  */
153 static int __init sharpsl_nand_init(void)
154 {
155         struct nand_chip *this;
156         struct mtd_partition *sharpsl_partition_info;
157         int err = 0;
158
159         /* Allocate memory for MTD device structure and private data */
160         sharpsl_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
161         if (!sharpsl_mtd) {
162                 printk("Unable to allocate SharpSL NAND MTD device structure.\n");
163                 return -ENOMEM;
164         }
165
166         /* map physical address */
167         sharpsl_io_base = ioremap(sharpsl_phys_base, 0x1000);
168         if (!sharpsl_io_base) {
169                 printk("ioremap to access Sharp SL NAND chip failed\n");
170                 kfree(sharpsl_mtd);
171                 return -EIO;
172         }
173
174         /* Get pointer to private data */
175         this = (struct nand_chip *)(&sharpsl_mtd[1]);
176
177         /* Initialize structures */
178         memset(sharpsl_mtd, 0, sizeof(struct mtd_info));
179         memset(this, 0, sizeof(struct nand_chip));
180
181         /* Link the private data with the MTD structure */
182         sharpsl_mtd->priv = this;
183         sharpsl_mtd->owner = THIS_MODULE;
184
185         /*
186          * PXA initialize
187          */
188         writeb(readb(FLASHCTL) | FLWP, FLASHCTL);
189
190         /* Set address of NAND IO lines */
191         this->IO_ADDR_R = FLASHIO;
192         this->IO_ADDR_W = FLASHIO;
193         /* Set address of hardware control function */
194         this->cmd_ctrl = sharpsl_nand_hwcontrol;
195         this->dev_ready = sharpsl_nand_dev_ready;
196         /* 15 us command delay time */
197         this->chip_delay = 15;
198         /* set eccmode using hardware ECC */
199         this->ecc.mode = NAND_ECC_HW;
200         this->ecc.size = 256;
201         this->ecc.bytes = 3;
202         this->badblock_pattern = &sharpsl_bbt;
203         if (machine_is_akita() || machine_is_borzoi()) {
204                 this->badblock_pattern = &sharpsl_akita_bbt;
205                 this->ecc.layout = &akita_oobinfo;
206         }
207         this->ecc.hwctl = sharpsl_nand_enable_hwecc;
208         this->ecc.calculate = sharpsl_nand_calculate_ecc;
209         this->ecc.correct = nand_correct_data;
210
211         /* Scan to find existence of the device */
212         err = nand_scan(sharpsl_mtd, 1);
213         if (err) {
214                 iounmap(sharpsl_io_base);
215                 kfree(sharpsl_mtd);
216                 return err;
217         }
218
219         /* Register the partitions */
220         sharpsl_mtd->name = "sharpsl-nand";
221         nr_partitions = parse_mtd_partitions(sharpsl_mtd, part_probes, &sharpsl_partition_info, 0);
222
223         if (nr_partitions <= 0) {
224                 nr_partitions = DEFAULT_NUM_PARTITIONS;
225                 sharpsl_partition_info = sharpsl_nand_default_partition_info;
226                 if (machine_is_poodle()) {
227                         sharpsl_partition_info[1].size = 22 * 1024 * 1024;
228                 } else if (machine_is_corgi() || machine_is_shepherd()) {
229                         sharpsl_partition_info[1].size = 25 * 1024 * 1024;
230                 } else if (machine_is_husky()) {
231                         sharpsl_partition_info[1].size = 53 * 1024 * 1024;
232                 } else if (machine_is_spitz()) {
233                         sharpsl_partition_info[1].size = 5 * 1024 * 1024;
234                 } else if (machine_is_akita()) {
235                         sharpsl_partition_info[1].size = 58 * 1024 * 1024;
236                 } else if (machine_is_borzoi()) {
237                         sharpsl_partition_info[1].size = 32 * 1024 * 1024;
238                 }
239         }
240
241         add_mtd_partitions(sharpsl_mtd, sharpsl_partition_info, nr_partitions);
242
243         /* Return happy */
244         return 0;
245 }
246
247 module_init(sharpsl_nand_init);
248
249 /*
250  * Clean up routine
251  */
252 static void __exit sharpsl_nand_cleanup(void)
253 {
254         /* Release resources, unregister device */
255         nand_release(sharpsl_mtd);
256
257         iounmap(sharpsl_io_base);
258
259         /* Free the MTD device structure */
260         kfree(sharpsl_mtd);
261 }
262
263 module_exit(sharpsl_nand_cleanup);
264
265 MODULE_LICENSE("GPL");
266 MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
267 MODULE_DESCRIPTION("Device specific logic for NAND flash on Sharp SL-C7xx Series");