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   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef __ASM_ARCH_MXC_H__
  12 #define __ASM_ARCH_MXC_H__
  13
  14 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
  15 #error "Do not include directly."
  16 #endif
  17
  18 /*
  19  *****************************************
  20  * GPT  Register definitions             *
  21  *****************************************
  22  */
  23 #define MXC_GPT_GPTCR           IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
  24 #define MXC_GPT_GPTPR           IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
  25 #define MXC_GPT_GPTSR           IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
  26 #define MXC_GPT_GPTIR           IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
  27 #define MXC_GPT_GPTOCR1         IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
  28 #define MXC_GPT_GPTOCR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
  29 #define MXC_GPT_GPTOCR3         IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
  30 #define MXC_GPT_GPTICR1         IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
  31 #define MXC_GPT_GPTICR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
  32 #define MXC_GPT_GPTCNT          IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
  33
  34 /*!
  35  * GPT Control register bit definitions
  36  */
  37 #define GPTCR_FO3                       (1 << 31)
  38 #define GPTCR_FO2                       (1 << 30)
  39 #define GPTCR_FO1                       (1 << 29)
  40
  41 #define GPTCR_OM3_SHIFT                 26
  42 #define GPTCR_OM3_MASK                  (7 << GPTCR_OM3_SHIFT)
  43 #define GPTCR_OM3_DISCONNECTED          (0 << GPTCR_OM3_SHIFT)
  44 #define GPTCR_OM3_TOGGLE                (1 << GPTCR_OM3_SHIFT)
  45 #define GPTCR_OM3_CLEAR                 (2 << GPTCR_OM3_SHIFT)
  46 #define GPTCR_OM3_SET                   (3 << GPTCR_OM3_SHIFT)
  47 #define GPTCR_OM3_GENERATE_LOW          (7 << GPTCR_OM3_SHIFT)
  48
  49 #define GPTCR_OM2_SHIFT                 23
  50 #define GPTCR_OM2_MASK                  (7 << GPTCR_OM2_SHIFT)
  51 #define GPTCR_OM2_DISCONNECTED          (0 << GPTCR_OM2_SHIFT)
  52 #define GPTCR_OM2_TOGGLE                (1 << GPTCR_OM2_SHIFT)
  53 #define GPTCR_OM2_CLEAR                 (2 << GPTCR_OM2_SHIFT)
  54 #define GPTCR_OM2_SET                   (3 << GPTCR_OM2_SHIFT)
  55 #define GPTCR_OM2_GENERATE_LOW          (7 << GPTCR_OM2_SHIFT)
  56
  57 #define GPTCR_OM1_SHIFT                 20
  58 #define GPTCR_OM1_MASK                  (7 << GPTCR_OM1_SHIFT)
  59 #define GPTCR_OM1_DISCONNECTED          (0 << GPTCR_OM1_SHIFT)
  60 #define GPTCR_OM1_TOGGLE                (1 << GPTCR_OM1_SHIFT)
  61 #define GPTCR_OM1_CLEAR                 (2 << GPTCR_OM1_SHIFT)
  62 #define GPTCR_OM1_SET                   (3 << GPTCR_OM1_SHIFT)
  63 #define GPTCR_OM1_GENERATE_LOW          (7 << GPTCR_OM1_SHIFT)
  64
  65 #define GPTCR_IM2_SHIFT                 18
  66 #define GPTCR_IM2_MASK                  (3 << GPTCR_IM2_SHIFT)
  67 #define GPTCR_IM2_CAPTURE_DISABLE       (0 << GPTCR_IM2_SHIFT)
  68 #define GPTCR_IM2_CAPTURE_RISING        (1 << GPTCR_IM2_SHIFT)
  69 #define GPTCR_IM2_CAPTURE_FALLING       (2 << GPTCR_IM2_SHIFT)
  70 #define GPTCR_IM2_CAPTURE_BOTH          (3 << GPTCR_IM2_SHIFT)
  71
  72 #define GPTCR_IM1_SHIFT                 16
  73 #define GPTCR_IM1_MASK                  (3 << GPTCR_IM1_SHIFT)
  74 #define GPTCR_IM1_CAPTURE_DISABLE       (0 << GPTCR_IM1_SHIFT)
  75 #define GPTCR_IM1_CAPTURE_RISING        (1 << GPTCR_IM1_SHIFT)
  76 #define GPTCR_IM1_CAPTURE_FALLING       (2 << GPTCR_IM1_SHIFT)
  77 #define GPTCR_IM1_CAPTURE_BOTH          (3 << GPTCR_IM1_SHIFT)
  78
  79 #define GPTCR_SWR                       (1 << 15)
  80 #define GPTCR_FRR                       (1 << 9)
  81
  82 #define GPTCR_CLKSRC_SHIFT              6
  83 #define GPTCR_CLKSRC_MASK               (7 << GPTCR_CLKSRC_SHIFT)
  84 #define GPTCR_CLKSRC_NOCLOCK            (0 << GPTCR_CLKSRC_SHIFT)
  85 #define GPTCR_CLKSRC_HIGHFREQ           (2 << GPTCR_CLKSRC_SHIFT)
  86 #define GPTCR_CLKSRC_CLKIN              (3 << GPTCR_CLKSRC_SHIFT)
  87 #define GPTCR_CLKSRC_CLK32K             (7 << GPTCR_CLKSRC_SHIFT)
  88
  89 #define GPTCR_STOPEN                    (1 << 5)
  90 #define GPTCR_DOZEN                     (1 << 4)
  91 #define GPTCR_WAITEN                    (1 << 3)
  92 #define GPTCR_DBGEN                     (1 << 2)
  93
  94 #define GPTCR_ENMOD                     (1 << 1)
  95 #define GPTCR_ENABLE                    (1 << 0)
  96
  97 #define GPTSR_OF1                       (1 << 0)
  98 #define GPTSR_OF2                       (1 << 1)
  99 #define GPTSR_OF3                       (1 << 2)
 100 #define GPTSR_IF1                       (1 << 3)
 101 #define GPTSR_IF2                       (1 << 4)
 102 #define GPTSR_ROV                       (1 << 5)
 103
 104 #define GPTIR_OF1IE                     GPTSR_OF1
 105 #define GPTIR_OF2IE                     GPTSR_OF2
 106 #define GPTIR_OF3IE                     GPTSR_OF3
 107 #define GPTIR_IF1IE                     GPTSR_IF1
 108 #define GPTIR_IF2IE                     GPTSR_IF2
 109 #define GPTIR_ROVIE                     GPTSR_ROV
 110
 111 /*
 112  *****************************************
 113  * AVIC Registers                        *
 114  *****************************************
 115  */
 116 #define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
 117 #define AVIC_INTCNTL            (AVIC_BASE + 0x00)      /* int control reg */
 118 #define AVIC_NIMASK             (AVIC_BASE + 0x04)      /* int mask reg */
 119 #define AVIC_INTENNUM           (AVIC_BASE + 0x08)      /* int enable number reg */
 120 #define AVIC_INTDISNUM          (AVIC_BASE + 0x0C)      /* int disable number reg */
 121 #define AVIC_INTENABLEH         (AVIC_BASE + 0x10)      /* int enable reg high */
 122 #define AVIC_INTENABLEL         (AVIC_BASE + 0x14)      /* int enable reg low */
 123 #define AVIC_INTTYPEH           (AVIC_BASE + 0x18)      /* int type reg high */
 124 #define AVIC_INTTYPEL           (AVIC_BASE + 0x1C)      /* int type reg low */
 125 #define AVIC_NIPRIORITY7        (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
 126 #define AVIC_NIPRIORITY6        (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
 127 #define AVIC_NIPRIORITY5        (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
 128 #define AVIC_NIPRIORITY4        (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
 129 #define AVIC_NIPRIORITY3        (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
 130 #define AVIC_NIPRIORITY2        (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
 131 #define AVIC_NIPRIORITY1        (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
 132 #define AVIC_NIPRIORITY0        (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
 133 #define AVIC_NIVECSR            (AVIC_BASE + 0x40)      /* norm int vector/status */
 134 #define AVIC_FIVECSR            (AVIC_BASE + 0x44)      /* fast int vector/status */
 135 #define AVIC_INTSRCH            (AVIC_BASE + 0x48)      /* int source reg high */
 136 #define AVIC_INTSRCL            (AVIC_BASE + 0x4C)      /* int source reg low */
 137 #define AVIC_INTFRCH            (AVIC_BASE + 0x50)      /* int force reg high */
 138 #define AVIC_INTFRCL            (AVIC_BASE + 0x54)      /* int force reg low */
 139 #define AVIC_NIPNDH             (AVIC_BASE + 0x58)      /* norm int pending high */
 140 #define AVIC_NIPNDL             (AVIC_BASE + 0x5C)      /* norm int pending low */
 141 #define AVIC_FIPNDH             (AVIC_BASE + 0x60)      /* fast int pending high */
 142 #define AVIC_FIPNDL             (AVIC_BASE + 0x64)      /* fast int pending low */
 143
 144 #define SYSTEM_PREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x20)
 145 #define SYSTEM_SREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x24)
 146 #define IIM_PROD_REV_SH         3
 147 #define IIM_PROD_REV_LEN        5
 148
 149 #endif                          /*  __ASM_ARCH_MXC_H__ */