Pull cpuidle into release branch
[linux-2.6] / drivers / mtd / nand / sharpsl.c
1 /*
2  * drivers/mtd/nand/sharpsl.c
3  *
4  *  Copyright (C) 2004 Richard Purdie
5  *
6  *  $Id: sharpsl.c,v 1.7 2005/11/07 11:14:31 gleixner Exp $
7  *
8  *  Based on Sharp's NAND driver sharp_sl.c
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  *
14  */
15
16 #include <linux/genhd.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/delay.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/nand.h>
22 #include <linux/mtd/nand_ecc.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/interrupt.h>
25 #include <asm/io.h>
26 #include <asm/hardware.h>
27 #include <asm/mach-types.h>
28
29 static void __iomem *sharpsl_io_base;
30 static int sharpsl_phys_base = 0x0C000000;
31
32 /* register offset */
33 #define ECCLPLB         sharpsl_io_base+0x00    /* line parity 7 - 0 bit */
34 #define ECCLPUB         sharpsl_io_base+0x04    /* line parity 15 - 8 bit */
35 #define ECCCP           sharpsl_io_base+0x08    /* column parity 5 - 0 bit */
36 #define ECCCNTR         sharpsl_io_base+0x0C    /* ECC byte counter */
37 #define ECCCLRR         sharpsl_io_base+0x10    /* cleare ECC */
38 #define FLASHIO         sharpsl_io_base+0x14    /* Flash I/O */
39 #define FLASHCTL        sharpsl_io_base+0x18    /* Flash Control */
40
41 /* Flash control bit */
42 #define FLRYBY          (1 << 5)
43 #define FLCE1           (1 << 4)
44 #define FLWP            (1 << 3)
45 #define FLALE           (1 << 2)
46 #define FLCLE           (1 << 1)
47 #define FLCE0           (1 << 0)
48
49 /*
50  * MTD structure for SharpSL
51  */
52 static struct mtd_info *sharpsl_mtd = NULL;
53
54 /*
55  * Define partitions for flash device
56  */
57 #define DEFAULT_NUM_PARTITIONS 3
58
59 static int nr_partitions;
60 static struct mtd_partition sharpsl_nand_default_partition_info[] = {
61         {
62          .name = "System Area",
63          .offset = 0,
64          .size = 7 * 1024 * 1024,
65          },
66         {
67          .name = "Root Filesystem",
68          .offset = 7 * 1024 * 1024,
69          .size = 30 * 1024 * 1024,
70          },
71         {
72          .name = "Home Filesystem",
73          .offset = MTDPART_OFS_APPEND,
74          .size = MTDPART_SIZ_FULL,
75          },
76 };
77
78 /*
79  *      hardware specific access to control-lines
80  *      ctrl:
81  *      NAND_CNE: bit 0 -> ! bit 0 & 4
82  *      NAND_CLE: bit 1 -> bit 1
83  *      NAND_ALE: bit 2 -> bit 2
84  *
85  */
86 static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd,
87                                    unsigned int ctrl)
88 {
89         struct nand_chip *chip = mtd->priv;
90
91         if (ctrl & NAND_CTRL_CHANGE) {
92                 unsigned char bits = ctrl & 0x07;
93
94                 bits |= (ctrl & 0x01) << 4;
95
96                 bits ^= 0x11;
97
98                 writeb((readb(FLASHCTL) & ~0x17) | bits, FLASHCTL);
99         }
100
101         if (cmd != NAND_CMD_NONE)
102                 writeb(cmd, chip->IO_ADDR_W);
103 }
104
105 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
106
107 static struct nand_bbt_descr sharpsl_bbt = {
108         .options = 0,
109         .offs = 4,
110         .len = 2,
111         .pattern = scan_ff_pattern
112 };
113
114 static struct nand_bbt_descr sharpsl_akita_bbt = {
115         .options = 0,
116         .offs = 4,
117         .len = 1,
118         .pattern = scan_ff_pattern
119 };
120
121 static struct nand_ecclayout akita_oobinfo = {
122         .eccbytes = 24,
123         .eccpos = {
124                    0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
125                    0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
126                    0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
127         .oobfree = {{0x08, 0x09}}
128 };
129
130 static int sharpsl_nand_dev_ready(struct mtd_info *mtd)
131 {
132         return !((readb(FLASHCTL) & FLRYBY) == 0);
133 }
134
135 static void sharpsl_nand_enable_hwecc(struct mtd_info *mtd, int mode)
136 {
137         writeb(0, ECCCLRR);
138 }
139
140 static int sharpsl_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat, u_char * ecc_code)
141 {
142         ecc_code[0] = ~readb(ECCLPUB);
143         ecc_code[1] = ~readb(ECCLPLB);
144         ecc_code[2] = (~readb(ECCCP) << 2) | 0x03;
145         return readb(ECCCNTR) != 0;
146 }
147
148 #ifdef CONFIG_MTD_PARTITIONS
149 const char *part_probes[] = { "cmdlinepart", NULL };
150 #endif
151
152 /*
153  * Main initialization routine
154  */
155 static int __init sharpsl_nand_init(void)
156 {
157         struct nand_chip *this;
158         struct mtd_partition *sharpsl_partition_info;
159         int err = 0;
160
161         /* Allocate memory for MTD device structure and private data */
162         sharpsl_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
163         if (!sharpsl_mtd) {
164                 printk("Unable to allocate SharpSL NAND MTD device structure.\n");
165                 return -ENOMEM;
166         }
167
168         /* map physical adress */
169         sharpsl_io_base = ioremap(sharpsl_phys_base, 0x1000);
170         if (!sharpsl_io_base) {
171                 printk("ioremap to access Sharp SL NAND chip failed\n");
172                 kfree(sharpsl_mtd);
173                 return -EIO;
174         }
175
176         /* Get pointer to private data */
177         this = (struct nand_chip *)(&sharpsl_mtd[1]);
178
179         /* Initialize structures */
180         memset(sharpsl_mtd, 0, sizeof(struct mtd_info));
181         memset(this, 0, sizeof(struct nand_chip));
182
183         /* Link the private data with the MTD structure */
184         sharpsl_mtd->priv = this;
185         sharpsl_mtd->owner = THIS_MODULE;
186
187         /*
188          * PXA initialize
189          */
190         writeb(readb(FLASHCTL) | FLWP, FLASHCTL);
191
192         /* Set address of NAND IO lines */
193         this->IO_ADDR_R = FLASHIO;
194         this->IO_ADDR_W = FLASHIO;
195         /* Set address of hardware control function */
196         this->cmd_ctrl = sharpsl_nand_hwcontrol;
197         this->dev_ready = sharpsl_nand_dev_ready;
198         /* 15 us command delay time */
199         this->chip_delay = 15;
200         /* set eccmode using hardware ECC */
201         this->ecc.mode = NAND_ECC_HW;
202         this->ecc.size = 256;
203         this->ecc.bytes = 3;
204         this->badblock_pattern = &sharpsl_bbt;
205         if (machine_is_akita() || machine_is_borzoi()) {
206                 this->badblock_pattern = &sharpsl_akita_bbt;
207                 this->ecc.layout = &akita_oobinfo;
208         }
209         this->ecc.hwctl = sharpsl_nand_enable_hwecc;
210         this->ecc.calculate = sharpsl_nand_calculate_ecc;
211         this->ecc.correct = nand_correct_data;
212
213         /* Scan to find existence of the device */
214         err = nand_scan(sharpsl_mtd, 1);
215         if (err) {
216                 iounmap(sharpsl_io_base);
217                 kfree(sharpsl_mtd);
218                 return err;
219         }
220
221         /* Register the partitions */
222         sharpsl_mtd->name = "sharpsl-nand";
223         nr_partitions = parse_mtd_partitions(sharpsl_mtd, part_probes, &sharpsl_partition_info, 0);
224
225         if (nr_partitions <= 0) {
226                 nr_partitions = DEFAULT_NUM_PARTITIONS;
227                 sharpsl_partition_info = sharpsl_nand_default_partition_info;
228                 if (machine_is_poodle()) {
229                         sharpsl_partition_info[1].size = 22 * 1024 * 1024;
230                 } else if (machine_is_corgi() || machine_is_shepherd()) {
231                         sharpsl_partition_info[1].size = 25 * 1024 * 1024;
232                 } else if (machine_is_husky()) {
233                         sharpsl_partition_info[1].size = 53 * 1024 * 1024;
234                 } else if (machine_is_spitz()) {
235                         sharpsl_partition_info[1].size = 5 * 1024 * 1024;
236                 } else if (machine_is_akita()) {
237                         sharpsl_partition_info[1].size = 58 * 1024 * 1024;
238                 } else if (machine_is_borzoi()) {
239                         sharpsl_partition_info[1].size = 32 * 1024 * 1024;
240                 }
241         }
242
243         add_mtd_partitions(sharpsl_mtd, sharpsl_partition_info, nr_partitions);
244
245         /* Return happy */
246         return 0;
247 }
248
249 module_init(sharpsl_nand_init);
250
251 /*
252  * Clean up routine
253  */
254 static void __exit sharpsl_nand_cleanup(void)
255 {
256         /* Release resources, unregister device */
257         nand_release(sharpsl_mtd);
258
259         iounmap(sharpsl_io_base);
260
261         /* Free the MTD device structure */
262         kfree(sharpsl_mtd);
263 }
264
265 module_exit(sharpsl_nand_cleanup);
266
267 MODULE_LICENSE("GPL");
268 MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
269 MODULE_DESCRIPTION("Device specific logic for NAND flash on Sharp SL-C7xx Series");