Merge branch 'drm-forlinus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[linux-2.6] / arch / powerpc / platforms / powermac / smp.c
1 /*
2  * SMP support for power macintosh.
3  *
4  * We support both the old "powersurge" SMP architecture
5  * and the current Core99 (G4 PowerMac) machines.
6  *
7  * Note that we don't support the very first rev. of
8  * Apple/DayStar 2 CPUs board, the one with the funky
9  * watchdog. Hopefully, none of these should be there except
10  * maybe internally to Apple. I should probably still add some
11  * code to detect this card though and disable SMP. --BenH.
12  *
13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
15  *
16  * Support for DayStar quad CPU cards
17  * Copyright (C) XLR8, Inc. 1994-2000
18  *
19  *  This program is free software; you can redistribute it and/or
20  *  modify it under the terms of the GNU General Public License
21  *  as published by the Free Software Foundation; either version
22  *  2 of the License, or (at your option) any later version.
23  */
24 #include <linux/config.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/smp.h>
28 #include <linux/smp_lock.h>
29 #include <linux/interrupt.h>
30 #include <linux/kernel_stat.h>
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/spinlock.h>
34 #include <linux/errno.h>
35 #include <linux/hardirq.h>
36 #include <linux/cpu.h>
37 #include <linux/compiler.h>
38
39 #include <asm/ptrace.h>
40 #include <asm/atomic.h>
41 #include <asm/irq.h>
42 #include <asm/page.h>
43 #include <asm/pgtable.h>
44 #include <asm/sections.h>
45 #include <asm/io.h>
46 #include <asm/prom.h>
47 #include <asm/smp.h>
48 #include <asm/machdep.h>
49 #include <asm/pmac_feature.h>
50 #include <asm/time.h>
51 #include <asm/mpic.h>
52 #include <asm/cacheflush.h>
53 #include <asm/keylargo.h>
54 #include <asm/pmac_low_i2c.h>
55 #include <asm/pmac_pfunc.h>
56
57 #define DEBUG
58
59 #ifdef DEBUG
60 #define DBG(fmt...) udbg_printf(fmt)
61 #else
62 #define DBG(fmt...)
63 #endif
64
65 extern void __secondary_start_pmac_0(void);
66 extern int pmac_pfunc_base_install(void);
67
68 #ifdef CONFIG_PPC32
69
70 /* Sync flag for HW tb sync */
71 static volatile int sec_tb_reset = 0;
72
73 /*
74  * Powersurge (old powermac SMP) support.
75  */
76
77 /* Addresses for powersurge registers */
78 #define HAMMERHEAD_BASE         0xf8000000
79 #define HHEAD_CONFIG            0x90
80 #define HHEAD_SEC_INTR          0xc0
81
82 /* register for interrupting the primary processor on the powersurge */
83 /* N.B. this is actually the ethernet ROM! */
84 #define PSURGE_PRI_INTR         0xf3019000
85
86 /* register for storing the start address for the secondary processor */
87 /* N.B. this is the PCI config space address register for the 1st bridge */
88 #define PSURGE_START            0xf2800000
89
90 /* Daystar/XLR8 4-CPU card */
91 #define PSURGE_QUAD_REG_ADDR    0xf8800000
92
93 #define PSURGE_QUAD_IRQ_SET     0
94 #define PSURGE_QUAD_IRQ_CLR     1
95 #define PSURGE_QUAD_IRQ_PRIMARY 2
96 #define PSURGE_QUAD_CKSTOP_CTL  3
97 #define PSURGE_QUAD_PRIMARY_ARB 4
98 #define PSURGE_QUAD_BOARD_ID    6
99 #define PSURGE_QUAD_WHICH_CPU   7
100 #define PSURGE_QUAD_CKSTOP_RDBK 8
101 #define PSURGE_QUAD_RESET_CTL   11
102
103 #define PSURGE_QUAD_OUT(r, v)   (out_8(quad_base + ((r) << 4) + 4, (v)))
104 #define PSURGE_QUAD_IN(r)       (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
105 #define PSURGE_QUAD_BIS(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
106 #define PSURGE_QUAD_BIC(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
107
108 /* virtual addresses for the above */
109 static volatile u8 __iomem *hhead_base;
110 static volatile u8 __iomem *quad_base;
111 static volatile u32 __iomem *psurge_pri_intr;
112 static volatile u8 __iomem *psurge_sec_intr;
113 static volatile u32 __iomem *psurge_start;
114
115 /* values for psurge_type */
116 #define PSURGE_NONE             -1
117 #define PSURGE_DUAL             0
118 #define PSURGE_QUAD_OKEE        1
119 #define PSURGE_QUAD_COTTON      2
120 #define PSURGE_QUAD_ICEGRASS    3
121
122 /* what sort of powersurge board we have */
123 static int psurge_type = PSURGE_NONE;
124
125 /*
126  * Set and clear IPIs for powersurge.
127  */
128 static inline void psurge_set_ipi(int cpu)
129 {
130         if (psurge_type == PSURGE_NONE)
131                 return;
132         if (cpu == 0)
133                 in_be32(psurge_pri_intr);
134         else if (psurge_type == PSURGE_DUAL)
135                 out_8(psurge_sec_intr, 0);
136         else
137                 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
138 }
139
140 static inline void psurge_clr_ipi(int cpu)
141 {
142         if (cpu > 0) {
143                 switch(psurge_type) {
144                 case PSURGE_DUAL:
145                         out_8(psurge_sec_intr, ~0);
146                 case PSURGE_NONE:
147                         break;
148                 default:
149                         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
150                 }
151         }
152 }
153
154 /*
155  * On powersurge (old SMP powermac architecture) we don't have
156  * separate IPIs for separate messages like openpic does.  Instead
157  * we have a bitmap for each processor, where a 1 bit means that
158  * the corresponding message is pending for that processor.
159  * Ideally each cpu's entry would be in a different cache line.
160  *  -- paulus.
161  */
162 static unsigned long psurge_smp_message[NR_CPUS];
163
164 void psurge_smp_message_recv(struct pt_regs *regs)
165 {
166         int cpu = smp_processor_id();
167         int msg;
168
169         /* clear interrupt */
170         psurge_clr_ipi(cpu);
171
172         if (num_online_cpus() < 2)
173                 return;
174
175         /* make sure there is a message there */
176         for (msg = 0; msg < 4; msg++)
177                 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
178                         smp_message_recv(msg, regs);
179 }
180
181 irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
182 {
183         psurge_smp_message_recv(regs);
184         return IRQ_HANDLED;
185 }
186
187 static void smp_psurge_message_pass(int target, int msg)
188 {
189         int i;
190
191         if (num_online_cpus() < 2)
192                 return;
193
194         for (i = 0; i < NR_CPUS; i++) {
195                 if (!cpu_online(i))
196                         continue;
197                 if (target == MSG_ALL
198                     || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
199                     || target == i) {
200                         set_bit(msg, &psurge_smp_message[i]);
201                         psurge_set_ipi(i);
202                 }
203         }
204 }
205
206 /*
207  * Determine a quad card presence. We read the board ID register, we
208  * force the data bus to change to something else, and we read it again.
209  * It it's stable, then the register probably exist (ugh !)
210  */
211 static int __init psurge_quad_probe(void)
212 {
213         int type;
214         unsigned int i;
215
216         type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
217         if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
218             || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
219                 return PSURGE_DUAL;
220
221         /* looks OK, try a slightly more rigorous test */
222         /* bogus is not necessarily cacheline-aligned,
223            though I don't suppose that really matters.  -- paulus */
224         for (i = 0; i < 100; i++) {
225                 volatile u32 bogus[8];
226                 bogus[(0+i)%8] = 0x00000000;
227                 bogus[(1+i)%8] = 0x55555555;
228                 bogus[(2+i)%8] = 0xFFFFFFFF;
229                 bogus[(3+i)%8] = 0xAAAAAAAA;
230                 bogus[(4+i)%8] = 0x33333333;
231                 bogus[(5+i)%8] = 0xCCCCCCCC;
232                 bogus[(6+i)%8] = 0xCCCCCCCC;
233                 bogus[(7+i)%8] = 0x33333333;
234                 wmb();
235                 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
236                 mb();
237                 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
238                         return PSURGE_DUAL;
239         }
240         return type;
241 }
242
243 static void __init psurge_quad_init(void)
244 {
245         int procbits;
246
247         if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
248         procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
249         if (psurge_type == PSURGE_QUAD_ICEGRASS)
250                 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
251         else
252                 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
253         mdelay(33);
254         out_8(psurge_sec_intr, ~0);
255         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
256         PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
257         if (psurge_type != PSURGE_QUAD_ICEGRASS)
258                 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
259         PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
260         mdelay(33);
261         PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
262         mdelay(33);
263         PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
264         mdelay(33);
265 }
266
267 static int __init smp_psurge_probe(void)
268 {
269         int i, ncpus;
270
271         /* We don't do SMP on the PPC601 -- paulus */
272         if (PVR_VER(mfspr(SPRN_PVR)) == 1)
273                 return 1;
274
275         /*
276          * The powersurge cpu board can be used in the generation
277          * of powermacs that have a socket for an upgradeable cpu card,
278          * including the 7500, 8500, 9500, 9600.
279          * The device tree doesn't tell you if you have 2 cpus because
280          * OF doesn't know anything about the 2nd processor.
281          * Instead we look for magic bits in magic registers,
282          * in the hammerhead memory controller in the case of the
283          * dual-cpu powersurge board.  -- paulus.
284          */
285         if (find_devices("hammerhead") == NULL)
286                 return 1;
287
288         hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
289         quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
290         psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
291
292         psurge_type = psurge_quad_probe();
293         if (psurge_type != PSURGE_DUAL) {
294                 psurge_quad_init();
295                 /* All released cards using this HW design have 4 CPUs */
296                 ncpus = 4;
297         } else {
298                 iounmap(quad_base);
299                 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
300                         /* not a dual-cpu card */
301                         iounmap(hhead_base);
302                         psurge_type = PSURGE_NONE;
303                         return 1;
304                 }
305                 ncpus = 2;
306         }
307
308         psurge_start = ioremap(PSURGE_START, 4);
309         psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
310
311         /*
312          * This is necessary because OF doesn't know about the
313          * secondary cpu(s), and thus there aren't nodes in the
314          * device tree for them, and smp_setup_cpu_maps hasn't
315          * set their bits in cpu_possible_map and cpu_present_map.
316          */
317         if (ncpus > NR_CPUS)
318                 ncpus = NR_CPUS;
319         for (i = 1; i < ncpus ; ++i) {
320                 cpu_set(i, cpu_present_map);
321                 cpu_set(i, cpu_possible_map);
322                 set_hard_smp_processor_id(i, i);
323         }
324
325         if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
326
327         return ncpus;
328 }
329
330 static void __init smp_psurge_kick_cpu(int nr)
331 {
332         unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
333         unsigned long a;
334
335         /* may need to flush here if secondary bats aren't setup */
336         for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
337                 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
338         asm volatile("sync");
339
340         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
341
342         out_be32(psurge_start, start);
343         mb();
344
345         psurge_set_ipi(nr);
346         udelay(10);
347         psurge_clr_ipi(nr);
348
349         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
350 }
351
352 /*
353  * With the dual-cpu powersurge board, the decrementers and timebases
354  * of both cpus are frozen after the secondary cpu is started up,
355  * until we give the secondary cpu another interrupt.  This routine
356  * uses this to get the timebases synchronized.
357  *  -- paulus.
358  */
359 static void __init psurge_dual_sync_tb(int cpu_nr)
360 {
361         int t;
362
363         set_dec(tb_ticks_per_jiffy);
364         /* XXX fixme */
365         set_tb(0, 0);
366
367         if (cpu_nr > 0) {
368                 mb();
369                 sec_tb_reset = 1;
370                 return;
371         }
372
373         /* wait for the secondary to have reset its TB before proceeding */
374         for (t = 10000000; t > 0 && !sec_tb_reset; --t)
375                 ;
376
377         /* now interrupt the secondary, starting both TBs */
378         psurge_set_ipi(1);
379 }
380
381 static struct irqaction psurge_irqaction = {
382         .handler = psurge_primary_intr,
383         .flags = SA_INTERRUPT,
384         .mask = CPU_MASK_NONE,
385         .name = "primary IPI",
386 };
387
388 static void __init smp_psurge_setup_cpu(int cpu_nr)
389 {
390
391         if (cpu_nr == 0) {
392                 /* If we failed to start the second CPU, we should still
393                  * send it an IPI to start the timebase & DEC or we might
394                  * have them stuck.
395                  */
396                 if (num_online_cpus() < 2) {
397                         if (psurge_type == PSURGE_DUAL)
398                                 psurge_set_ipi(1);
399                         return;
400                 }
401                 /* reset the entry point so if we get another intr we won't
402                  * try to startup again */
403                 out_be32(psurge_start, 0x100);
404                 if (setup_irq(30, &psurge_irqaction))
405                         printk(KERN_ERR "Couldn't get primary IPI interrupt");
406         }
407
408         if (psurge_type == PSURGE_DUAL)
409                 psurge_dual_sync_tb(cpu_nr);
410 }
411
412 void __init smp_psurge_take_timebase(void)
413 {
414         /* Dummy implementation */
415 }
416
417 void __init smp_psurge_give_timebase(void)
418 {
419         /* Dummy implementation */
420 }
421
422 /* PowerSurge-style Macs */
423 struct smp_ops_t psurge_smp_ops = {
424         .message_pass   = smp_psurge_message_pass,
425         .probe          = smp_psurge_probe,
426         .kick_cpu       = smp_psurge_kick_cpu,
427         .setup_cpu      = smp_psurge_setup_cpu,
428         .give_timebase  = smp_psurge_give_timebase,
429         .take_timebase  = smp_psurge_take_timebase,
430 };
431 #endif /* CONFIG_PPC32 - actually powersurge support */
432
433 /*
434  * Core 99 and later support
435  */
436
437 static void (*pmac_tb_freeze)(int freeze);
438 static unsigned long timebase;
439 static int tb_req;
440
441 static void smp_core99_give_timebase(void)
442 {
443         unsigned long flags;
444
445         local_irq_save(flags);
446
447         while(!tb_req)
448                 barrier();
449         tb_req = 0;
450         (*pmac_tb_freeze)(1);
451         mb();
452         timebase = get_tb();
453         mb();
454         while (timebase)
455                 barrier();
456         mb();
457         (*pmac_tb_freeze)(0);
458         mb();
459
460         local_irq_restore(flags);
461 }
462
463
464 static void __devinit smp_core99_take_timebase(void)
465 {
466         unsigned long flags;
467
468         local_irq_save(flags);
469
470         tb_req = 1;
471         mb();
472         while (!timebase)
473                 barrier();
474         mb();
475         set_tb(timebase >> 32, timebase & 0xffffffff);
476         timebase = 0;
477         mb();
478         set_dec(tb_ticks_per_jiffy/2);
479
480         local_irq_restore(flags);
481 }
482
483 #ifdef CONFIG_PPC64
484 /*
485  * G5s enable/disable the timebase via an i2c-connected clock chip.
486  */
487 static struct pmac_i2c_bus *pmac_tb_clock_chip_host;
488 static u8 pmac_tb_pulsar_addr;
489
490 static void smp_core99_cypress_tb_freeze(int freeze)
491 {
492         u8 data;
493         int rc;
494
495         /* Strangely, the device-tree says address is 0xd2, but darwin
496          * accesses 0xd0 ...
497          */
498         pmac_i2c_setmode(pmac_tb_clock_chip_host,
499                          pmac_i2c_mode_combined);
500         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
501                            0xd0 | pmac_i2c_read,
502                            1, 0x81, &data, 1);
503         if (rc != 0)
504                 goto bail;
505
506         data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
507
508         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
509         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
510                            0xd0 | pmac_i2c_write,
511                            1, 0x81, &data, 1);
512
513  bail:
514         if (rc != 0) {
515                 printk("Cypress Timebase %s rc: %d\n",
516                        freeze ? "freeze" : "unfreeze", rc);
517                 panic("Timebase freeze failed !\n");
518         }
519 }
520
521
522 static void smp_core99_pulsar_tb_freeze(int freeze)
523 {
524         u8 data;
525         int rc;
526
527         pmac_i2c_setmode(pmac_tb_clock_chip_host,
528                          pmac_i2c_mode_combined);
529         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
530                            pmac_tb_pulsar_addr | pmac_i2c_read,
531                            1, 0x2e, &data, 1);
532         if (rc != 0)
533                 goto bail;
534
535         data = (data & 0x88) | (freeze ? 0x11 : 0x22);
536
537         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
538         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
539                            pmac_tb_pulsar_addr | pmac_i2c_write,
540                            1, 0x2e, &data, 1);
541  bail:
542         if (rc != 0) {
543                 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
544                        freeze ? "freeze" : "unfreeze", rc);
545                 panic("Timebase freeze failed !\n");
546         }
547 }
548
549 static void __init smp_core99_setup_i2c_hwsync(int ncpus)
550 {
551         struct device_node *cc = NULL;  
552         struct device_node *p;
553         const char *name = NULL;
554         u32 *reg;
555         int ok;
556
557         /* Look for the clock chip */
558         while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) {
559                 p = of_get_parent(cc);
560                 ok = p && device_is_compatible(p, "uni-n-i2c");
561                 of_node_put(p);
562                 if (!ok)
563                         continue;
564
565                 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc);
566                 if (pmac_tb_clock_chip_host == NULL)
567                         continue;
568                 reg = (u32 *)get_property(cc, "reg", NULL);
569                 if (reg == NULL)
570                         continue;
571                 switch (*reg) {
572                 case 0xd2:
573                         if (device_is_compatible(cc,"pulsar-legacy-slewing")) {
574                                 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
575                                 pmac_tb_pulsar_addr = 0xd2;
576                                 name = "Pulsar";
577                         } else if (device_is_compatible(cc, "cy28508")) {
578                                 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
579                                 name = "Cypress";
580                         }
581                         break;
582                 case 0xd4:
583                         pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
584                         pmac_tb_pulsar_addr = 0xd4;
585                         name = "Pulsar";
586                         break;
587                 }
588                 if (pmac_tb_freeze != NULL)
589                         break;
590         }
591         if (pmac_tb_freeze != NULL) {
592                 /* Open i2c bus for synchronous access */
593                 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) {
594                         printk(KERN_ERR "Failed top open i2c bus for clock"
595                                " sync, fallback to software sync !\n");
596                         goto no_i2c_sync;
597                 }
598                 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n",
599                        name);
600                 return;
601         }
602  no_i2c_sync:
603         pmac_tb_freeze = NULL;
604         pmac_tb_clock_chip_host = NULL;
605 }
606
607
608
609 /*
610  * Newer G5s uses a platform function
611  */
612
613 static void smp_core99_pfunc_tb_freeze(int freeze)
614 {
615         struct device_node *cpus;
616         struct pmf_args args;
617
618         cpus = of_find_node_by_path("/cpus");
619         BUG_ON(cpus == NULL);
620         args.count = 1;
621         args.u[0].v = !freeze;
622         pmf_call_function(cpus, "cpu-timebase", &args);
623         of_node_put(cpus);
624 }
625
626 #else /* CONFIG_PPC64 */
627
628 /*
629  * SMP G4 use a GPIO to enable/disable the timebase.
630  */
631
632 static unsigned int core99_tb_gpio;     /* Timebase freeze GPIO */
633
634 static void smp_core99_gpio_tb_freeze(int freeze)
635 {
636         if (freeze)
637                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
638         else
639                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
640         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
641 }
642
643
644 #endif /* !CONFIG_PPC64 */
645
646 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
647 volatile static long int core99_l2_cache;
648 volatile static long int core99_l3_cache;
649
650 static void __devinit core99_init_caches(int cpu)
651 {
652 #ifndef CONFIG_PPC64
653         if (!cpu_has_feature(CPU_FTR_L2CR))
654                 return;
655
656         if (cpu == 0) {
657                 core99_l2_cache = _get_L2CR();
658                 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
659         } else {
660                 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
661                 _set_L2CR(0);
662                 _set_L2CR(core99_l2_cache);
663                 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
664         }
665
666         if (!cpu_has_feature(CPU_FTR_L3CR))
667                 return;
668
669         if (cpu == 0){
670                 core99_l3_cache = _get_L3CR();
671                 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
672         } else {
673                 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
674                 _set_L3CR(0);
675                 _set_L3CR(core99_l3_cache);
676                 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
677         }
678 #endif /* !CONFIG_PPC64 */
679 }
680
681 static void __init smp_core99_setup(int ncpus)
682 {
683 #ifdef CONFIG_PPC64
684
685         /* i2c based HW sync on some G5s */
686         if (machine_is_compatible("PowerMac7,2") ||
687             machine_is_compatible("PowerMac7,3") ||
688             machine_is_compatible("RackMac3,1"))
689                 smp_core99_setup_i2c_hwsync(ncpus);
690
691         /* pfunc based HW sync on recent G5s */
692         if (pmac_tb_freeze == NULL) {
693                 struct device_node *cpus =
694                         of_find_node_by_path("/cpus");
695                 if (cpus &&
696                     get_property(cpus, "platform-cpu-timebase", NULL)) {
697                         pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
698                         printk(KERN_INFO "Processor timebase sync using"
699                                " platform function\n");
700                 }
701         }
702
703 #else /* CONFIG_PPC64 */
704
705         /* GPIO based HW sync on ppc32 Core99 */
706         if (pmac_tb_freeze == NULL && !machine_is_compatible("MacRISC4")) {
707                 struct device_node *cpu;
708                 u32 *tbprop = NULL;
709
710                 core99_tb_gpio = KL_GPIO_TB_ENABLE;     /* default value */
711                 cpu = of_find_node_by_type(NULL, "cpu");
712                 if (cpu != NULL) {
713                         tbprop = (u32 *)get_property(cpu, "timebase-enable",
714                                                      NULL);
715                         if (tbprop)
716                                 core99_tb_gpio = *tbprop;
717                         of_node_put(cpu);
718                 }
719                 pmac_tb_freeze = smp_core99_gpio_tb_freeze;
720                 printk(KERN_INFO "Processor timebase sync using"
721                        " GPIO 0x%02x\n", core99_tb_gpio);
722         }
723
724 #endif /* CONFIG_PPC64 */
725
726         /* No timebase sync, fallback to software */
727         if (pmac_tb_freeze == NULL) {
728                 smp_ops->give_timebase = smp_generic_give_timebase;
729                 smp_ops->take_timebase = smp_generic_take_timebase;
730                 printk(KERN_INFO "Processor timebase sync using software\n");
731         }
732
733 #ifndef CONFIG_PPC64
734         {
735                 int i;
736
737                 /* XXX should get this from reg properties */
738                 for (i = 1; i < ncpus; ++i)
739                         smp_hw_index[i] = i;
740         }
741 #endif
742
743         /* 32 bits SMP can't NAP */
744         if (!machine_is_compatible("MacRISC4"))
745                 powersave_nap = 0;
746 }
747
748 static int __init smp_core99_probe(void)
749 {
750         struct device_node *cpus;
751         int ncpus = 0;
752
753         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
754
755         /* Count CPUs in the device-tree */
756         for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
757                 ++ncpus;
758
759         printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
760
761         /* Nothing more to do if less than 2 of them */
762         if (ncpus <= 1)
763                 return 1;
764
765         /* We need to perform some early initialisations before we can start
766          * setting up SMP as we are running before initcalls
767          */
768         pmac_pfunc_base_install();
769         pmac_i2c_init();
770
771         /* Setup various bits like timebase sync method, ability to nap, ... */
772         smp_core99_setup(ncpus);
773
774         /* Install IPIs */
775         mpic_request_ipis();
776
777         /* Collect l2cr and l3cr values from CPU 0 */
778         core99_init_caches(0);
779
780         return ncpus;
781 }
782
783 static void __devinit smp_core99_kick_cpu(int nr)
784 {
785         unsigned int save_vector;
786         unsigned long target, flags;
787         volatile unsigned int *vector
788                  = ((volatile unsigned int *)(KERNELBASE+0x100));
789
790         if (nr < 0 || nr > 3)
791                 return;
792
793         if (ppc_md.progress)
794                 ppc_md.progress("smp_core99_kick_cpu", 0x346);
795
796         local_irq_save(flags);
797         local_irq_disable();
798
799         /* Save reset vector */
800         save_vector = *vector;
801
802         /* Setup fake reset vector that does
803          *   b __secondary_start_pmac_0 + nr*8 - KERNELBASE
804          */
805         target = (unsigned long) __secondary_start_pmac_0 + nr * 8;
806         create_branch((unsigned long)vector, target, BRANCH_SET_LINK);
807
808         /* Put some life in our friend */
809         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
810
811         /* FIXME: We wait a bit for the CPU to take the exception, I should
812          * instead wait for the entry code to set something for me. Well,
813          * ideally, all that crap will be done in prom.c and the CPU left
814          * in a RAM-based wait loop like CHRP.
815          */
816         mdelay(1);
817
818         /* Restore our exception vector */
819         *vector = save_vector;
820         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
821
822         local_irq_restore(flags);
823         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
824 }
825
826 static void __devinit smp_core99_setup_cpu(int cpu_nr)
827 {
828         /* Setup L2/L3 */
829         if (cpu_nr != 0)
830                 core99_init_caches(cpu_nr);
831
832         /* Setup openpic */
833         mpic_setup_this_cpu();
834
835         if (cpu_nr == 0) {
836 #ifdef CONFIG_PPC64
837                 extern void g5_phy_disable_cpu1(void);
838
839                 /* Close i2c bus if it was used for tb sync */
840                 if (pmac_tb_clock_chip_host) {
841                         pmac_i2c_close(pmac_tb_clock_chip_host);
842                         pmac_tb_clock_chip_host = NULL;
843                 }
844
845                 /* If we didn't start the second CPU, we must take
846                  * it off the bus
847                  */
848                 if (machine_is_compatible("MacRISC4") &&
849                     num_online_cpus() < 2)              
850                         g5_phy_disable_cpu1();
851 #endif /* CONFIG_PPC64 */
852
853                 if (ppc_md.progress)
854                         ppc_md.progress("core99_setup_cpu 0 done", 0x349);
855         }
856 }
857
858
859 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)
860
861 int smp_core99_cpu_disable(void)
862 {
863         cpu_clear(smp_processor_id(), cpu_online_map);
864
865         /* XXX reset cpu affinity here */
866         mpic_cpu_set_priority(0xf);
867         asm volatile("mtdec %0" : : "r" (0x7fffffff));
868         mb();
869         udelay(20);
870         asm volatile("mtdec %0" : : "r" (0x7fffffff));
871         return 0;
872 }
873
874 extern void low_cpu_die(void) __attribute__((noreturn)); /* in sleep.S */
875 static int cpu_dead[NR_CPUS];
876
877 void cpu_die(void)
878 {
879         local_irq_disable();
880         cpu_dead[smp_processor_id()] = 1;
881         mb();
882         low_cpu_die();
883 }
884
885 void smp_core99_cpu_die(unsigned int cpu)
886 {
887         int timeout;
888
889         timeout = 1000;
890         while (!cpu_dead[cpu]) {
891                 if (--timeout == 0) {
892                         printk("CPU %u refused to die!\n", cpu);
893                         break;
894                 }
895                 msleep(1);
896         }
897         cpu_dead[cpu] = 0;
898 }
899
900 #endif
901
902 /* Core99 Macs (dual G4s and G5s) */
903 struct smp_ops_t core99_smp_ops = {
904         .message_pass   = smp_mpic_message_pass,
905         .probe          = smp_core99_probe,
906         .kick_cpu       = smp_core99_kick_cpu,
907         .setup_cpu      = smp_core99_setup_cpu,
908         .give_timebase  = smp_core99_give_timebase,
909         .take_timebase  = smp_core99_take_timebase,
910 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)
911         .cpu_disable    = smp_core99_cpu_disable,
912         .cpu_die        = smp_core99_cpu_die,
913 #endif
914 };