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   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #define RTL8169_VERSION "2.3LK-NAPI"
  32 #define MODULENAME "r8169"
  33 #define PFX MODULENAME ": "
  34
  35 #ifdef RTL8169_DEBUG
  36 #define assert(expr) \
  37         if (!(expr)) {                                  \
  38                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  39                 #expr,__FILE__,__func__,__LINE__);              \
  40         }
  41 #define dprintk(fmt, args...) \
  42         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  43 #else
  44 #define assert(expr) do {} while (0)
  45 #define dprintk(fmt, args...)   do {} while (0)
  46 #endif /* RTL8169_DEBUG */
  47
  48 #define R8169_MSG_DEFAULT \
  49         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  50
  51 #define TX_BUFFS_AVAIL(tp) \
  52         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  53
  54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  55 static const int max_interrupt_work = 20;
  56
  57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  58    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  59 static const int multicast_filter_limit = 32;
  60
  61 /* MAC address length */
  62 #define MAC_ADDR_LEN    6
  63
  64 #define MAX_READ_REQUEST_SHIFT  12
  65 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  66 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  67 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  68 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  69 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  70 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  72
  73 #define R8169_REGS_SIZE         256
  74 #define R8169_NAPI_WEIGHT       64
  75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  76 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  77 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  78 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  79 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  80
  81 #define RTL8169_TX_TIMEOUT      (6*HZ)
  82 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  83
  84 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  85 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  86 #define RTL_EEPROM_SIG_ADDR     0x0000
  87
  88 /* write/read MMIO register */
  89 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  90 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  91 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  92 #define RTL_R8(reg)             readb (ioaddr + (reg))
  93 #define RTL_R16(reg)            readw (ioaddr + (reg))
  94 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
  95
  96 enum mac_version {
  97         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
  98         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
  99         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 100         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 101         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 102         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 103         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 104         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 105         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 106         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 107         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 108         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 109         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 110         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 111         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 112         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 113         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 114         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 115         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 116         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
 117         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
 118         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
 119         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
 120         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
 121         RTL_GIGA_MAC_VER_25 = 0x19  // 8168D
 122 };
 123
 124 #define _R(NAME,MAC,MASK) \
 125         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 126
 127 static const struct {
 128         const char *name;
 129         u8 mac_version;
 130         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 131 } rtl_chip_info[] = {
 132         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 133         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 134         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 135         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 136         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 137         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 138         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 139         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 140         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 141         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 142         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 143         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 144         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 145         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 146         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 147         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 148         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 149         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 150         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 151         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
 152         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
 153         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
 154         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
 155         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
 156         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880)  // PCI-E
 157 };
 158 #undef _R
 159
 160 enum cfg_version {
 161         RTL_CFG_0 = 0x00,
 162         RTL_CFG_1,
 163         RTL_CFG_2
 164 };
 165
 166 static void rtl_hw_start_8169(struct net_device *);
 167 static void rtl_hw_start_8168(struct net_device *);
 168 static void rtl_hw_start_8101(struct net_device *);
 169
 170 static struct pci_device_id rtl8169_pci_tbl[] = {
 171         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 172         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 173         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 174         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 175         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 176         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 177         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 178         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 179         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 180                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 181         { 0x0001,                               0x8168,
 182                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 183         {0,},
 184 };
 185
 186 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 187
 188 static int rx_copybreak = 200;
 189 static int use_dac;
 190 static struct {
 191         u32 msg_enable;
 192 } debug = { -1 };
 193
 194 enum rtl_registers {
 195         MAC0            = 0,    /* Ethernet hardware address. */
 196         MAC4            = 4,
 197         MAR0            = 8,    /* Multicast filter. */
 198         CounterAddrLow          = 0x10,
 199         CounterAddrHigh         = 0x14,
 200         TxDescStartAddrLow      = 0x20,
 201         TxDescStartAddrHigh     = 0x24,
 202         TxHDescStartAddrLow     = 0x28,
 203         TxHDescStartAddrHigh    = 0x2c,
 204         FLASH           = 0x30,
 205         ERSR            = 0x36,
 206         ChipCmd         = 0x37,
 207         TxPoll          = 0x38,
 208         IntrMask        = 0x3c,
 209         IntrStatus      = 0x3e,
 210         TxConfig        = 0x40,
 211         RxConfig        = 0x44,
 212         RxMissed        = 0x4c,
 213         Cfg9346         = 0x50,
 214         Config0         = 0x51,
 215         Config1         = 0x52,
 216         Config2         = 0x53,
 217         Config3         = 0x54,
 218         Config4         = 0x55,
 219         Config5         = 0x56,
 220         MultiIntr       = 0x5c,
 221         PHYAR           = 0x60,
 222         PHYstatus       = 0x6c,
 223         RxMaxSize       = 0xda,
 224         CPlusCmd        = 0xe0,
 225         IntrMitigate    = 0xe2,
 226         RxDescAddrLow   = 0xe4,
 227         RxDescAddrHigh  = 0xe8,
 228         EarlyTxThres    = 0xec,
 229         FuncEvent       = 0xf0,
 230         FuncEventMask   = 0xf4,
 231         FuncPresetState = 0xf8,
 232         FuncForceEvent  = 0xfc,
 233 };
 234
 235 enum rtl8110_registers {
 236         TBICSR                  = 0x64,
 237         TBI_ANAR                = 0x68,
 238         TBI_LPAR                = 0x6a,
 239 };
 240
 241 enum rtl8168_8101_registers {
 242         CSIDR                   = 0x64,
 243         CSIAR                   = 0x68,
 244 #define CSIAR_FLAG                      0x80000000
 245 #define CSIAR_WRITE_CMD                 0x80000000
 246 #define CSIAR_BYTE_ENABLE               0x0f
 247 #define CSIAR_BYTE_ENABLE_SHIFT         12
 248 #define CSIAR_ADDR_MASK                 0x0fff
 249
 250         EPHYAR                  = 0x80,
 251 #define EPHYAR_FLAG                     0x80000000
 252 #define EPHYAR_WRITE_CMD                0x80000000
 253 #define EPHYAR_REG_MASK                 0x1f
 254 #define EPHYAR_REG_SHIFT                16
 255 #define EPHYAR_DATA_MASK                0xffff
 256         DBG_REG                 = 0xd1,
 257 #define FIX_NAK_1                       (1 << 4)
 258 #define FIX_NAK_2                       (1 << 3)
 259 };
 260
 261 enum rtl_register_content {
 262         /* InterruptStatusBits */
 263         SYSErr          = 0x8000,
 264         PCSTimeout      = 0x4000,
 265         SWInt           = 0x0100,
 266         TxDescUnavail   = 0x0080,
 267         RxFIFOOver      = 0x0040,
 268         LinkChg         = 0x0020,
 269         RxOverflow      = 0x0010,
 270         TxErr           = 0x0008,
 271         TxOK            = 0x0004,
 272         RxErr           = 0x0002,
 273         RxOK            = 0x0001,
 274
 275         /* RxStatusDesc */
 276         RxFOVF  = (1 << 23),
 277         RxRWT   = (1 << 22),
 278         RxRES   = (1 << 21),
 279         RxRUNT  = (1 << 20),
 280         RxCRC   = (1 << 19),
 281
 282         /* ChipCmdBits */
 283         CmdReset        = 0x10,
 284         CmdRxEnb        = 0x08,
 285         CmdTxEnb        = 0x04,
 286         RxBufEmpty      = 0x01,
 287
 288         /* TXPoll register p.5 */
 289         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 290         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 291         FSWInt          = 0x01,         /* Forced software interrupt */
 292
 293         /* Cfg9346Bits */
 294         Cfg9346_Lock    = 0x00,
 295         Cfg9346_Unlock  = 0xc0,
 296
 297         /* rx_mode_bits */
 298         AcceptErr       = 0x20,
 299         AcceptRunt      = 0x10,
 300         AcceptBroadcast = 0x08,
 301         AcceptMulticast = 0x04,
 302         AcceptMyPhys    = 0x02,
 303         AcceptAllPhys   = 0x01,
 304
 305         /* RxConfigBits */
 306         RxCfgFIFOShift  = 13,
 307         RxCfgDMAShift   =  8,
 308
 309         /* TxConfigBits */
 310         TxInterFrameGapShift = 24,
 311         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 312
 313         /* Config1 register p.24 */
 314         LEDS1           = (1 << 7),
 315         LEDS0           = (1 << 6),
 316         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 317         Speed_down      = (1 << 4),
 318         MEMMAP          = (1 << 3),
 319         IOMAP           = (1 << 2),
 320         VPD             = (1 << 1),
 321         PMEnable        = (1 << 0),     /* Power Management Enable */
 322
 323         /* Config2 register p. 25 */
 324         PCI_Clock_66MHz = 0x01,
 325         PCI_Clock_33MHz = 0x00,
 326
 327         /* Config3 register p.25 */
 328         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 329         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 330         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 331
 332         /* Config5 register p.27 */
 333         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 334         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 335         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 336         LanWake         = (1 << 1),     /* LanWake enable/disable */
 337         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 338
 339         /* TBICSR p.28 */
 340         TBIReset        = 0x80000000,
 341         TBILoopback     = 0x40000000,
 342         TBINwEnable     = 0x20000000,
 343         TBINwRestart    = 0x10000000,
 344         TBILinkOk       = 0x02000000,
 345         TBINwComplete   = 0x01000000,
 346
 347         /* CPlusCmd p.31 */
 348         EnableBist      = (1 << 15),    // 8168 8101
 349         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 350         Normal_mode     = (1 << 13),    // unused
 351         Force_half_dup  = (1 << 12),    // 8168 8101
 352         Force_rxflow_en = (1 << 11),    // 8168 8101
 353         Force_txflow_en = (1 << 10),    // 8168 8101
 354         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 355         ASF             = (1 << 8),     // 8168 8101
 356         PktCntrDisable  = (1 << 7),     // 8168 8101
 357         Mac_dbgo_sel    = 0x001c,       // 8168
 358         RxVlan          = (1 << 6),
 359         RxChkSum        = (1 << 5),
 360         PCIDAC          = (1 << 4),
 361         PCIMulRW        = (1 << 3),
 362         INTT_0          = 0x0000,       // 8168
 363         INTT_1          = 0x0001,       // 8168
 364         INTT_2          = 0x0002,       // 8168
 365         INTT_3          = 0x0003,       // 8168
 366
 367         /* rtl8169_PHYstatus */
 368         TBI_Enable      = 0x80,
 369         TxFlowCtrl      = 0x40,
 370         RxFlowCtrl      = 0x20,
 371         _1000bpsF       = 0x10,
 372         _100bps         = 0x08,
 373         _10bps          = 0x04,
 374         LinkStatus      = 0x02,
 375         FullDup         = 0x01,
 376
 377         /* _TBICSRBit */
 378         TBILinkOK       = 0x02000000,
 379
 380         /* DumpCounterCommand */
 381         CounterDump     = 0x8,
 382 };
 383
 384 enum desc_status_bit {
 385         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 386         RingEnd         = (1 << 30), /* End of descriptor ring */
 387         FirstFrag       = (1 << 29), /* First segment of a packet */
 388         LastFrag        = (1 << 28), /* Final segment of a packet */
 389
 390         /* Tx private */
 391         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 392         MSSShift        = 16,        /* MSS value position */
 393         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 394         IPCS            = (1 << 18), /* Calculate IP checksum */
 395         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 396         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 397         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 398
 399         /* Rx private */
 400         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 401         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 402
 403 #define RxProtoUDP      (PID1)
 404 #define RxProtoTCP      (PID0)
 405 #define RxProtoIP       (PID1 | PID0)
 406 #define RxProtoMask     RxProtoIP
 407
 408         IPFail          = (1 << 16), /* IP checksum failed */
 409         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 410         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 411         RxVlanTag       = (1 << 16), /* VLAN tag available */
 412 };
 413
 414 #define RsvdMask        0x3fffc000
 415
 416 struct TxDesc {
 417         __le32 opts1;
 418         __le32 opts2;
 419         __le64 addr;
 420 };
 421
 422 struct RxDesc {
 423         __le32 opts1;
 424         __le32 opts2;
 425         __le64 addr;
 426 };
 427
 428 struct ring_info {
 429         struct sk_buff  *skb;
 430         u32             len;
 431         u8              __pad[sizeof(void *) - sizeof(u32)];
 432 };
 433
 434 enum features {
 435         RTL_FEATURE_WOL         = (1 << 0),
 436         RTL_FEATURE_MSI         = (1 << 1),
 437         RTL_FEATURE_GMII        = (1 << 2),
 438 };
 439
 440 struct rtl8169_counters {
 441         __le64  tx_packets;
 442         __le64  rx_packets;
 443         __le64  tx_errors;
 444         __le32  rx_errors;
 445         __le16  rx_missed;
 446         __le16  align_errors;
 447         __le32  tx_one_collision;
 448         __le32  tx_multi_collision;
 449         __le64  rx_unicast;
 450         __le64  rx_broadcast;
 451         __le32  rx_multicast;
 452         __le16  tx_aborted;
 453         __le16  tx_underun;
 454 };
 455
 456 struct rtl8169_private {
 457         void __iomem *mmio_addr;        /* memory map physical address */
 458         struct pci_dev *pci_dev;        /* Index of PCI device */
 459         struct net_device *dev;
 460         struct napi_struct napi;
 461         spinlock_t lock;                /* spin lock flag */
 462         u32 msg_enable;
 463         int chipset;
 464         int mac_version;
 465         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 466         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 467         u32 dirty_rx;
 468         u32 dirty_tx;
 469         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 470         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 471         dma_addr_t TxPhyAddr;
 472         dma_addr_t RxPhyAddr;
 473         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 474         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 475         unsigned align;
 476         unsigned rx_buf_sz;
 477         struct timer_list timer;
 478         u16 cp_cmd;
 479         u16 intr_event;
 480         u16 napi_event;
 481         u16 intr_mask;
 482         int phy_1000_ctrl_reg;
 483 #ifdef CONFIG_R8169_VLAN
 484         struct vlan_group *vlgrp;
 485 #endif
 486         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 487         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 488         void (*phy_reset_enable)(void __iomem *);
 489         void (*hw_start)(struct net_device *);
 490         unsigned int (*phy_reset_pending)(void __iomem *);
 491         unsigned int (*link_ok)(void __iomem *);
 492         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 493         int pcie_cap;
 494         struct delayed_work task;
 495         unsigned features;
 496
 497         struct mii_if_info mii;
 498         struct rtl8169_counters counters;
 499 };
 500
 501 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 502 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 503 module_param(rx_copybreak, int, 0);
 504 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 505 module_param(use_dac, int, 0);
 506 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 507 module_param_named(debug, debug.msg_enable, int, 0);
 508 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 509 MODULE_LICENSE("GPL");
 510 MODULE_VERSION(RTL8169_VERSION);
 511
 512 static int rtl8169_open(struct net_device *dev);
 513 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 514 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 515 static int rtl8169_init_ring(struct net_device *dev);
 516 static void rtl_hw_start(struct net_device *dev);
 517 static int rtl8169_close(struct net_device *dev);
 518 static void rtl_set_rx_mode(struct net_device *dev);
 519 static void rtl8169_tx_timeout(struct net_device *dev);
 520 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 521 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 522                                 void __iomem *, u32 budget);
 523 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 524 static void rtl8169_down(struct net_device *dev);
 525 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 526 static int rtl8169_poll(struct napi_struct *napi, int budget);
 527
 528 static const unsigned int rtl8169_rx_config =
 529         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 530
 531 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 532 {
 533         int i;
 534
 535         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 536
 537         for (i = 20; i > 0; i--) {
 538                 /*
 539                  * Check if the RTL8169 has completed writing to the specified
 540                  * MII register.
 541                  */
 542                 if (!(RTL_R32(PHYAR) & 0x80000000))
 543                         break;
 544                 udelay(25);
 545         }
 546 }
 547
 548 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 549 {
 550         int i, value = -1;
 551
 552         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 553
 554         for (i = 20; i > 0; i--) {
 555                 /*
 556                  * Check if the RTL8169 has completed retrieving data from
 557                  * the specified MII register.
 558                  */
 559                 if (RTL_R32(PHYAR) & 0x80000000) {
 560                         value = RTL_R32(PHYAR) & 0xffff;
 561                         break;
 562                 }
 563                 udelay(25);
 564         }
 565         return value;
 566 }
 567
 568 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
 569 {
 570         mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
 571 }
 572
 573 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 574                            int val)
 575 {
 576         struct rtl8169_private *tp = netdev_priv(dev);
 577         void __iomem *ioaddr = tp->mmio_addr;
 578
 579         mdio_write(ioaddr, location, val);
 580 }
 581
 582 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 583 {
 584         struct rtl8169_private *tp = netdev_priv(dev);
 585         void __iomem *ioaddr = tp->mmio_addr;
 586
 587         return mdio_read(ioaddr, location);
 588 }
 589
 590 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 591 {
 592         unsigned int i;
 593
 594         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 595                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 596
 597         for (i = 0; i < 100; i++) {
 598                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 599                         break;
 600                 udelay(10);
 601         }
 602 }
 603
 604 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 605 {
 606         u16 value = 0xffff;
 607         unsigned int i;
 608
 609         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 610
 611         for (i = 0; i < 100; i++) {
 612                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 613                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 614                         break;
 615                 }
 616                 udelay(10);
 617         }
 618
 619         return value;
 620 }
 621
 622 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 623 {
 624         unsigned int i;
 625
 626         RTL_W32(CSIDR, value);
 627         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 628                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 629
 630         for (i = 0; i < 100; i++) {
 631                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 632                         break;
 633                 udelay(10);
 634         }
 635 }
 636
 637 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 638 {
 639         u32 value = ~0x00;
 640         unsigned int i;
 641
 642         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 643                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 644
 645         for (i = 0; i < 100; i++) {
 646                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 647                         value = RTL_R32(CSIDR);
 648                         break;
 649                 }
 650                 udelay(10);
 651         }
 652
 653         return value;
 654 }
 655
 656 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 657 {
 658         RTL_W16(IntrMask, 0x0000);
 659
 660         RTL_W16(IntrStatus, 0xffff);
 661 }
 662
 663 static void rtl8169_asic_down(void __iomem *ioaddr)
 664 {
 665         RTL_W8(ChipCmd, 0x00);
 666         rtl8169_irq_mask_and_ack(ioaddr);
 667         RTL_R16(CPlusCmd);
 668 }
 669
 670 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 671 {
 672         return RTL_R32(TBICSR) & TBIReset;
 673 }
 674
 675 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 676 {
 677         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 678 }
 679
 680 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 681 {
 682         return RTL_R32(TBICSR) & TBILinkOk;
 683 }
 684
 685 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 686 {
 687         return RTL_R8(PHYstatus) & LinkStatus;
 688 }
 689
 690 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 691 {
 692         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 693 }
 694
 695 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 696 {
 697         unsigned int val;
 698
 699         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 700         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 701 }
 702
 703 static void rtl8169_check_link_status(struct net_device *dev,
 704                                       struct rtl8169_private *tp,
 705                                       void __iomem *ioaddr)
 706 {
 707         unsigned long flags;
 708
 709         spin_lock_irqsave(&tp->lock, flags);
 710         if (tp->link_ok(ioaddr)) {
 711                 netif_carrier_on(dev);
 712                 if (netif_msg_ifup(tp))
 713                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 714         } else {
 715                 if (netif_msg_ifdown(tp))
 716                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 717                 netif_carrier_off(dev);
 718         }
 719         spin_unlock_irqrestore(&tp->lock, flags);
 720 }
 721
 722 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 723 {
 724         struct rtl8169_private *tp = netdev_priv(dev);
 725         void __iomem *ioaddr = tp->mmio_addr;
 726         u8 options;
 727
 728         wol->wolopts = 0;
 729
 730 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 731         wol->supported = WAKE_ANY;
 732
 733         spin_lock_irq(&tp->lock);
 734
 735         options = RTL_R8(Config1);
 736         if (!(options & PMEnable))
 737                 goto out_unlock;
 738
 739         options = RTL_R8(Config3);
 740         if (options & LinkUp)
 741                 wol->wolopts |= WAKE_PHY;
 742         if (options & MagicPacket)
 743                 wol->wolopts |= WAKE_MAGIC;
 744
 745         options = RTL_R8(Config5);
 746         if (options & UWF)
 747                 wol->wolopts |= WAKE_UCAST;
 748         if (options & BWF)
 749                 wol->wolopts |= WAKE_BCAST;
 750         if (options & MWF)
 751                 wol->wolopts |= WAKE_MCAST;
 752
 753 out_unlock:
 754         spin_unlock_irq(&tp->lock);
 755 }
 756
 757 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 758 {
 759         struct rtl8169_private *tp = netdev_priv(dev);
 760         void __iomem *ioaddr = tp->mmio_addr;
 761         unsigned int i;
 762         static struct {
 763                 u32 opt;
 764                 u16 reg;
 765                 u8  mask;
 766         } cfg[] = {
 767                 { WAKE_ANY,   Config1, PMEnable },
 768                 { WAKE_PHY,   Config3, LinkUp },
 769                 { WAKE_MAGIC, Config3, MagicPacket },
 770                 { WAKE_UCAST, Config5, UWF },
 771                 { WAKE_BCAST, Config5, BWF },
 772                 { WAKE_MCAST, Config5, MWF },
 773                 { WAKE_ANY,   Config5, LanWake }
 774         };
 775
 776         spin_lock_irq(&tp->lock);
 777
 778         RTL_W8(Cfg9346, Cfg9346_Unlock);
 779
 780         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 781                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 782                 if (wol->wolopts & cfg[i].opt)
 783                         options |= cfg[i].mask;
 784                 RTL_W8(cfg[i].reg, options);
 785         }
 786
 787         RTL_W8(Cfg9346, Cfg9346_Lock);
 788
 789         if (wol->wolopts)
 790                 tp->features |= RTL_FEATURE_WOL;
 791         else
 792                 tp->features &= ~RTL_FEATURE_WOL;
 793         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
 794
 795         spin_unlock_irq(&tp->lock);
 796
 797         return 0;
 798 }
 799
 800 static void rtl8169_get_drvinfo(struct net_device *dev,
 801                                 struct ethtool_drvinfo *info)
 802 {
 803         struct rtl8169_private *tp = netdev_priv(dev);
 804
 805         strcpy(info->driver, MODULENAME);
 806         strcpy(info->version, RTL8169_VERSION);
 807         strcpy(info->bus_info, pci_name(tp->pci_dev));
 808 }
 809
 810 static int rtl8169_get_regs_len(struct net_device *dev)
 811 {
 812         return R8169_REGS_SIZE;
 813 }
 814
 815 static int rtl8169_set_speed_tbi(struct net_device *dev,
 816                                  u8 autoneg, u16 speed, u8 duplex)
 817 {
 818         struct rtl8169_private *tp = netdev_priv(dev);
 819         void __iomem *ioaddr = tp->mmio_addr;
 820         int ret = 0;
 821         u32 reg;
 822
 823         reg = RTL_R32(TBICSR);
 824         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 825             (duplex == DUPLEX_FULL)) {
 826                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 827         } else if (autoneg == AUTONEG_ENABLE)
 828                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 829         else {
 830                 if (netif_msg_link(tp)) {
 831                         printk(KERN_WARNING "%s: "
 832                                "incorrect speed setting refused in TBI mode\n",
 833                                dev->name);
 834                 }
 835                 ret = -EOPNOTSUPP;
 836         }
 837
 838         return ret;
 839 }
 840
 841 static int rtl8169_set_speed_xmii(struct net_device *dev,
 842                                   u8 autoneg, u16 speed, u8 duplex)
 843 {
 844         struct rtl8169_private *tp = netdev_priv(dev);
 845         void __iomem *ioaddr = tp->mmio_addr;
 846         int auto_nego, giga_ctrl;
 847
 848         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 849         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 850                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 851         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 852         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 853
 854         if (autoneg == AUTONEG_ENABLE) {
 855                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 856                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 857                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 858         } else {
 859                 if (speed == SPEED_10)
 860                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 861                 else if (speed == SPEED_100)
 862                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 863                 else if (speed == SPEED_1000)
 864                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 865
 866                 if (duplex == DUPLEX_HALF)
 867                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 868
 869                 if (duplex == DUPLEX_FULL)
 870                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 871
 872                 /* This tweak comes straight from Realtek's driver. */
 873                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 874                     ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 875                      (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
 876                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 877                 }
 878         }
 879
 880         /* The 8100e/8101e/8102e do Fast Ethernet only. */
 881         if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
 882             (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
 883             (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
 884             (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
 885             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 886             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 887             (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
 888             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
 889                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 890                     netif_msg_link(tp)) {
 891                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 892                                dev->name);
 893                 }
 894                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 895         }
 896
 897         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 898
 899         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
 900             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
 901             (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
 902                 /*
 903                  * Wake up the PHY.
 904                  * Vendor specific (0x1f) and reserved (0x0e) MII registers.
 905                  */
 906                 mdio_write(ioaddr, 0x1f, 0x0000);
 907                 mdio_write(ioaddr, 0x0e, 0x0000);
 908         }
 909
 910         tp->phy_1000_ctrl_reg = giga_ctrl;
 911
 912         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 913         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 914         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 915         return 0;
 916 }
 917
 918 static int rtl8169_set_speed(struct net_device *dev,
 919                              u8 autoneg, u16 speed, u8 duplex)
 920 {
 921         struct rtl8169_private *tp = netdev_priv(dev);
 922         int ret;
 923
 924         ret = tp->set_speed(dev, autoneg, speed, duplex);
 925
 926         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 927                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 928
 929         return ret;
 930 }
 931
 932 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 933 {
 934         struct rtl8169_private *tp = netdev_priv(dev);
 935         unsigned long flags;
 936         int ret;
 937
 938         spin_lock_irqsave(&tp->lock, flags);
 939         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 940         spin_unlock_irqrestore(&tp->lock, flags);
 941
 942         return ret;
 943 }
 944
 945 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 946 {
 947         struct rtl8169_private *tp = netdev_priv(dev);
 948
 949         return tp->cp_cmd & RxChkSum;
 950 }
 951
 952 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 953 {
 954         struct rtl8169_private *tp = netdev_priv(dev);
 955         void __iomem *ioaddr = tp->mmio_addr;
 956         unsigned long flags;
 957
 958         spin_lock_irqsave(&tp->lock, flags);
 959
 960         if (data)
 961                 tp->cp_cmd |= RxChkSum;
 962         else
 963                 tp->cp_cmd &= ~RxChkSum;
 964
 965         RTL_W16(CPlusCmd, tp->cp_cmd);
 966         RTL_R16(CPlusCmd);
 967
 968         spin_unlock_irqrestore(&tp->lock, flags);
 969
 970         return 0;
 971 }
 972
 973 #ifdef CONFIG_R8169_VLAN
 974
 975 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 976                                       struct sk_buff *skb)
 977 {
 978         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 979                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 980 }
 981
 982 static void rtl8169_vlan_rx_register(struct net_device *dev,
 983                                      struct vlan_group *grp)
 984 {
 985         struct rtl8169_private *tp = netdev_priv(dev);
 986         void __iomem *ioaddr = tp->mmio_addr;
 987         unsigned long flags;
 988
 989         spin_lock_irqsave(&tp->lock, flags);
 990         tp->vlgrp = grp;
 991         if (tp->vlgrp)
 992                 tp->cp_cmd |= RxVlan;
 993         else
 994                 tp->cp_cmd &= ~RxVlan;
 995         RTL_W16(CPlusCmd, tp->cp_cmd);
 996         RTL_R16(CPlusCmd);
 997         spin_unlock_irqrestore(&tp->lock, flags);
 998 }
 999
1000 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1001                                struct sk_buff *skb)
1002 {
1003         u32 opts2 = le32_to_cpu(desc->opts2);
1004         struct vlan_group *vlgrp = tp->vlgrp;
1005         int ret;
1006
1007         if (vlgrp && (opts2 & RxVlanTag)) {
1008                 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1009                 ret = 0;
1010         } else
1011                 ret = -1;
1012         desc->opts2 = 0;
1013         return ret;
1014 }
1015
1016 #else /* !CONFIG_R8169_VLAN */
1017
1018 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1019                                       struct sk_buff *skb)
1020 {
1021         return 0;
1022 }
1023
1024 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1025                                struct sk_buff *skb)
1026 {
1027         return -1;
1028 }
1029
1030 #endif
1031
1032 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1033 {
1034         struct rtl8169_private *tp = netdev_priv(dev);
1035         void __iomem *ioaddr = tp->mmio_addr;
1036         u32 status;
1037
1038         cmd->supported =
1039                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1040         cmd->port = PORT_FIBRE;
1041         cmd->transceiver = XCVR_INTERNAL;
1042
1043         status = RTL_R32(TBICSR);
1044         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1045         cmd->autoneg = !!(status & TBINwEnable);
1046
1047         cmd->speed = SPEED_1000;
1048         cmd->duplex = DUPLEX_FULL; /* Always set */
1049
1050         return 0;
1051 }
1052
1053 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1054 {
1055         struct rtl8169_private *tp = netdev_priv(dev);
1056
1057         return mii_ethtool_gset(&tp->mii, cmd);
1058 }
1059
1060 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1061 {
1062         struct rtl8169_private *tp = netdev_priv(dev);
1063         unsigned long flags;
1064         int rc;
1065
1066         spin_lock_irqsave(&tp->lock, flags);
1067
1068         rc = tp->get_settings(dev, cmd);
1069
1070         spin_unlock_irqrestore(&tp->lock, flags);
1071         return rc;
1072 }
1073
1074 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1075                              void *p)
1076 {
1077         struct rtl8169_private *tp = netdev_priv(dev);
1078         unsigned long flags;
1079
1080         if (regs->len > R8169_REGS_SIZE)
1081                 regs->len = R8169_REGS_SIZE;
1082
1083         spin_lock_irqsave(&tp->lock, flags);
1084         memcpy_fromio(p, tp->mmio_addr, regs->len);
1085         spin_unlock_irqrestore(&tp->lock, flags);
1086 }
1087
1088 static u32 rtl8169_get_msglevel(struct net_device *dev)
1089 {
1090         struct rtl8169_private *tp = netdev_priv(dev);
1091
1092         return tp->msg_enable;
1093 }
1094
1095 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1096 {
1097         struct rtl8169_private *tp = netdev_priv(dev);
1098
1099         tp->msg_enable = value;
1100 }
1101
1102 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1103         "tx_packets",
1104         "rx_packets",
1105         "tx_errors",
1106         "rx_errors",
1107         "rx_missed",
1108         "align_errors",
1109         "tx_single_collisions",
1110         "tx_multi_collisions",
1111         "unicast",
1112         "broadcast",
1113         "multicast",
1114         "tx_aborted",
1115         "tx_underrun",
1116 };
1117
1118 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1119 {
1120         switch (sset) {
1121         case ETH_SS_STATS:
1122                 return ARRAY_SIZE(rtl8169_gstrings);
1123         default:
1124                 return -EOPNOTSUPP;
1125         }
1126 }
1127
1128 static void rtl8169_update_counters(struct net_device *dev)
1129 {
1130         struct rtl8169_private *tp = netdev_priv(dev);
1131         void __iomem *ioaddr = tp->mmio_addr;
1132         struct rtl8169_counters *counters;
1133         dma_addr_t paddr;
1134         u32 cmd;
1135         int wait = 1000;
1136
1137         /*
1138          * Some chips are unable to dump tally counters when the receiver
1139          * is disabled.
1140          */
1141         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1142                 return;
1143
1144         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1145         if (!counters)
1146                 return;
1147
1148         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1149         cmd = (u64)paddr & DMA_BIT_MASK(32);
1150         RTL_W32(CounterAddrLow, cmd);
1151         RTL_W32(CounterAddrLow, cmd | CounterDump);
1152
1153         while (wait--) {
1154                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1155                         /* copy updated counters */
1156                         memcpy(&tp->counters, counters, sizeof(*counters));
1157                         break;
1158                 }
1159                 udelay(10);
1160         }
1161
1162         RTL_W32(CounterAddrLow, 0);
1163         RTL_W32(CounterAddrHigh, 0);
1164
1165         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1166 }
1167
1168 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1169                                       struct ethtool_stats *stats, u64 *data)
1170 {
1171         struct rtl8169_private *tp = netdev_priv(dev);
1172
1173         ASSERT_RTNL();
1174
1175         rtl8169_update_counters(dev);
1176
1177         data[0] = le64_to_cpu(tp->counters.tx_packets);
1178         data[1] = le64_to_cpu(tp->counters.rx_packets);
1179         data[2] = le64_to_cpu(tp->counters.tx_errors);
1180         data[3] = le32_to_cpu(tp->counters.rx_errors);
1181         data[4] = le16_to_cpu(tp->counters.rx_missed);
1182         data[5] = le16_to_cpu(tp->counters.align_errors);
1183         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1184         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1185         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1186         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1187         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1188         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1189         data[12] = le16_to_cpu(tp->counters.tx_underun);
1190 }
1191
1192 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1193 {
1194         switch(stringset) {
1195         case ETH_SS_STATS:
1196                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1197                 break;
1198         }
1199 }
1200
1201 static const struct ethtool_ops rtl8169_ethtool_ops = {
1202         .get_drvinfo            = rtl8169_get_drvinfo,
1203         .get_regs_len           = rtl8169_get_regs_len,
1204         .get_link               = ethtool_op_get_link,
1205         .get_settings           = rtl8169_get_settings,
1206         .set_settings           = rtl8169_set_settings,
1207         .get_msglevel           = rtl8169_get_msglevel,
1208         .set_msglevel           = rtl8169_set_msglevel,
1209         .get_rx_csum            = rtl8169_get_rx_csum,
1210         .set_rx_csum            = rtl8169_set_rx_csum,
1211         .set_tx_csum            = ethtool_op_set_tx_csum,
1212         .set_sg                 = ethtool_op_set_sg,
1213         .set_tso                = ethtool_op_set_tso,
1214         .get_regs               = rtl8169_get_regs,
1215         .get_wol                = rtl8169_get_wol,
1216         .set_wol                = rtl8169_set_wol,
1217         .get_strings            = rtl8169_get_strings,
1218         .get_sset_count         = rtl8169_get_sset_count,
1219         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1220 };
1221
1222 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1223                                        int bitnum, int bitval)
1224 {
1225         int val;
1226
1227         val = mdio_read(ioaddr, reg);
1228         val = (bitval == 1) ?
1229                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1230         mdio_write(ioaddr, reg, val & 0xffff);
1231 }
1232
1233 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1234                                     void __iomem *ioaddr)
1235 {
1236         /*
1237          * The driver currently handles the 8168Bf and the 8168Be identically
1238          * but they can be identified more specifically through the test below
1239          * if needed:
1240          *
1241          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1242          *
1243          * Same thing for the 8101Eb and the 8101Ec:
1244          *
1245          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1246          */
1247         const struct {
1248                 u32 mask;
1249                 u32 val;
1250                 int mac_version;
1251         } mac_info[] = {
1252                 /* 8168D family. */
1253                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_25 },
1254
1255                 /* 8168C family. */
1256                 { 0x7cf00000, 0x3ca00000,       RTL_GIGA_MAC_VER_24 },
1257                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1258                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1259                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1260                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1261                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1262                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1263                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1264                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1265
1266                 /* 8168B family. */
1267                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1268                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1269                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1270                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1271
1272                 /* 8101 family. */
1273                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1274                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1275                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1276                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1277                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1278                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1279                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1280                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1281                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1282                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1283                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1284                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1285                 /* FIXME: where did these entries come from ? -- FR */
1286                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1287                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1288
1289                 /* 8110 family. */
1290                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1291                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1292                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1293                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1294                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1295                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1296
1297                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1298         }, *p = mac_info;
1299         u32 reg;
1300
1301         reg = RTL_R32(TxConfig);
1302         while ((reg & p->mask) != p->val)
1303                 p++;
1304         tp->mac_version = p->mac_version;
1305
1306         if (p->mask == 0x00000000) {
1307                 struct pci_dev *pdev = tp->pci_dev;
1308
1309                 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1310         }
1311 }
1312
1313 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1314 {
1315         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1316 }
1317
1318 struct phy_reg {
1319         u16 reg;
1320         u16 val;
1321 };
1322
1323 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1324 {
1325         while (len-- > 0) {
1326                 mdio_write(ioaddr, regs->reg, regs->val);
1327                 regs++;
1328         }
1329 }
1330
1331 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1332 {
1333         struct {
1334                 u16 regs[5]; /* Beware of bit-sign propagation */
1335         } phy_magic[5] = { {
1336                 { 0x0000,       //w 4 15 12 0
1337                   0x00a1,       //w 3 15 0 00a1
1338                   0x0008,       //w 2 15 0 0008
1339                   0x1020,       //w 1 15 0 1020
1340                   0x1000 } },{  //w 0 15 0 1000
1341                 { 0x7000,       //w 4 15 12 7
1342                   0xff41,       //w 3 15 0 ff41
1343                   0xde60,       //w 2 15 0 de60
1344                   0x0140,       //w 1 15 0 0140
1345                   0x0077 } },{  //w 0 15 0 0077
1346                 { 0xa000,       //w 4 15 12 a
1347                   0xdf01,       //w 3 15 0 df01
1348                   0xdf20,       //w 2 15 0 df20
1349                   0xff95,       //w 1 15 0 ff95
1350                   0xfa00 } },{  //w 0 15 0 fa00
1351                 { 0xb000,       //w 4 15 12 b
1352                   0xff41,       //w 3 15 0 ff41
1353                   0xde20,       //w 2 15 0 de20
1354                   0x0140,       //w 1 15 0 0140
1355                   0x00bb } },{  //w 0 15 0 00bb
1356                 { 0xf000,       //w 4 15 12 f
1357                   0xdf01,       //w 3 15 0 df01
1358                   0xdf20,       //w 2 15 0 df20
1359                   0xff95,       //w 1 15 0 ff95
1360                   0xbf00 }      //w 0 15 0 bf00
1361                 }
1362         }, *p = phy_magic;
1363         unsigned int i;
1364
1365         mdio_write(ioaddr, 0x1f, 0x0001);               //w 31 2 0 1
1366         mdio_write(ioaddr, 0x15, 0x1000);               //w 21 15 0 1000
1367         mdio_write(ioaddr, 0x18, 0x65c7);               //w 24 15 0 65c7
1368         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1369
1370         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1371                 int val, pos = 4;
1372
1373                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1374                 mdio_write(ioaddr, pos, val);
1375                 while (--pos >= 0)
1376                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1377                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1378                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1379         }
1380         mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1381 }
1382
1383 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1384 {
1385         struct phy_reg phy_reg_init[] = {
1386                 { 0x1f, 0x0002 },
1387                 { 0x01, 0x90d0 },
1388                 { 0x1f, 0x0000 }
1389         };
1390
1391         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1392 }
1393
1394 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1395 {
1396         struct phy_reg phy_reg_init[] = {
1397                 { 0x10, 0xf41b },
1398                 { 0x1f, 0x0000 }
1399         };
1400
1401         mdio_write(ioaddr, 0x1f, 0x0001);
1402         mdio_patch(ioaddr, 0x16, 1 << 0);
1403
1404         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1405 }
1406
1407 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1408 {
1409         struct phy_reg phy_reg_init[] = {
1410                 { 0x1f, 0x0001 },
1411                 { 0x10, 0xf41b },
1412                 { 0x1f, 0x0000 }
1413         };
1414
1415         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1416 }
1417
1418 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1419 {
1420         struct phy_reg phy_reg_init[] = {
1421                 { 0x1f, 0x0000 },
1422                 { 0x1d, 0x0f00 },
1423                 { 0x1f, 0x0002 },
1424                 { 0x0c, 0x1ec8 },
1425                 { 0x1f, 0x0000 }
1426         };
1427
1428         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1429 }
1430
1431 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1432 {
1433         struct phy_reg phy_reg_init[] = {
1434                 { 0x1f, 0x0001 },
1435                 { 0x1d, 0x3d98 },
1436                 { 0x1f, 0x0000 }
1437         };
1438
1439         mdio_write(ioaddr, 0x1f, 0x0000);
1440         mdio_patch(ioaddr, 0x14, 1 << 5);
1441         mdio_patch(ioaddr, 0x0d, 1 << 5);
1442
1443         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1444 }
1445
1446 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1447 {
1448         struct phy_reg phy_reg_init[] = {
1449                 { 0x1f, 0x0001 },
1450                 { 0x12, 0x2300 },
1451                 { 0x1f, 0x0002 },
1452                 { 0x00, 0x88d4 },
1453                 { 0x01, 0x82b1 },
1454                 { 0x03, 0x7002 },
1455                 { 0x08, 0x9e30 },
1456                 { 0x09, 0x01f0 },
1457                 { 0x0a, 0x5500 },
1458                 { 0x0c, 0x00c8 },
1459                 { 0x1f, 0x0003 },
1460                 { 0x12, 0xc096 },
1461                 { 0x16, 0x000a },
1462                 { 0x1f, 0x0000 },
1463                 { 0x1f, 0x0000 },
1464                 { 0x09, 0x2000 },
1465                 { 0x09, 0x0000 }
1466         };
1467
1468         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1469
1470         mdio_patch(ioaddr, 0x14, 1 << 5);
1471         mdio_patch(ioaddr, 0x0d, 1 << 5);
1472         mdio_write(ioaddr, 0x1f, 0x0000);
1473 }
1474
1475 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1476 {
1477         struct phy_reg phy_reg_init[] = {
1478                 { 0x1f, 0x0001 },
1479                 { 0x12, 0x2300 },
1480                 { 0x03, 0x802f },
1481                 { 0x02, 0x4f02 },
1482                 { 0x01, 0x0409 },
1483                 { 0x00, 0xf099 },
1484                 { 0x04, 0x9800 },
1485                 { 0x04, 0x9000 },
1486                 { 0x1d, 0x3d98 },
1487                 { 0x1f, 0x0002 },
1488                 { 0x0c, 0x7eb8 },
1489                 { 0x06, 0x0761 },
1490                 { 0x1f, 0x0003 },
1491                 { 0x16, 0x0f0a },
1492                 { 0x1f, 0x0000 }
1493         };
1494
1495         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1496
1497         mdio_patch(ioaddr, 0x16, 1 << 0);
1498         mdio_patch(ioaddr, 0x14, 1 << 5);
1499         mdio_patch(ioaddr, 0x0d, 1 << 5);
1500         mdio_write(ioaddr, 0x1f, 0x0000);
1501 }
1502
1503 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1504 {
1505         struct phy_reg phy_reg_init[] = {
1506                 { 0x1f, 0x0001 },
1507                 { 0x12, 0x2300 },
1508                 { 0x1d, 0x3d98 },
1509                 { 0x1f, 0x0002 },
1510                 { 0x0c, 0x7eb8 },
1511                 { 0x06, 0x5461 },
1512                 { 0x1f, 0x0003 },
1513                 { 0x16, 0x0f0a },
1514                 { 0x1f, 0x0000 }
1515         };
1516
1517         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1518
1519         mdio_patch(ioaddr, 0x16, 1 << 0);
1520         mdio_patch(ioaddr, 0x14, 1 << 5);
1521         mdio_patch(ioaddr, 0x0d, 1 << 5);
1522         mdio_write(ioaddr, 0x1f, 0x0000);
1523 }
1524
1525 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1526 {
1527         rtl8168c_3_hw_phy_config(ioaddr);
1528 }
1529
1530 static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1531 {
1532         struct phy_reg phy_reg_init_0[] = {
1533                 { 0x1f, 0x0001 },
1534                 { 0x09, 0x2770 },
1535                 { 0x08, 0x04d0 },
1536                 { 0x0b, 0xad15 },
1537                 { 0x0c, 0x5bf0 },
1538                 { 0x1c, 0xf101 },
1539                 { 0x1f, 0x0003 },
1540                 { 0x14, 0x94d7 },
1541                 { 0x12, 0xf4d6 },
1542                 { 0x09, 0xca0f },
1543                 { 0x1f, 0x0002 },
1544                 { 0x0b, 0x0b10 },
1545                 { 0x0c, 0xd1f7 },
1546                 { 0x1f, 0x0002 },
1547                 { 0x06, 0x5461 },
1548                 { 0x1f, 0x0002 },
1549                 { 0x05, 0x6662 },
1550                 { 0x1f, 0x0000 },
1551                 { 0x14, 0x0060 },
1552                 { 0x1f, 0x0000 },
1553                 { 0x0d, 0xf8a0 },
1554                 { 0x1f, 0x0005 },
1555                 { 0x05, 0xffc2 }
1556         };
1557
1558         rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1559
1560         if (mdio_read(ioaddr, 0x06) == 0xc400) {
1561                 struct phy_reg phy_reg_init_1[] = {
1562                         { 0x1f, 0x0005 },
1563                         { 0x01, 0x0300 },
1564                         { 0x1f, 0x0000 },
1565                         { 0x11, 0x401c },
1566                         { 0x16, 0x4100 },
1567                         { 0x1f, 0x0005 },
1568                         { 0x07, 0x0010 },
1569                         { 0x05, 0x83dc },
1570                         { 0x06, 0x087d },
1571                         { 0x05, 0x8300 },
1572                         { 0x06, 0x0101 },
1573                         { 0x06, 0x05f8 },
1574                         { 0x06, 0xf9fa },
1575                         { 0x06, 0xfbef },
1576                         { 0x06, 0x79e2 },
1577                         { 0x06, 0x835f },
1578                         { 0x06, 0xe0f8 },
1579                         { 0x06, 0x9ae1 },
1580                         { 0x06, 0xf89b },
1581                         { 0x06, 0xef31 },
1582                         { 0x06, 0x3b65 },
1583                         { 0x06, 0xaa07 },
1584                         { 0x06, 0x81e4 },
1585                         { 0x06, 0xf89a },
1586                         { 0x06, 0xe5f8 },
1587                         { 0x06, 0x9baf },
1588                         { 0x06, 0x06ae },
1589                         { 0x05, 0x83dc },
1590                         { 0x06, 0x8300 },
1591                 };
1592
1593                 rtl_phy_write(ioaddr, phy_reg_init_1,
1594                               ARRAY_SIZE(phy_reg_init_1));
1595         }
1596
1597         mdio_write(ioaddr, 0x1f, 0x0000);
1598 }
1599
1600 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1601 {
1602         struct phy_reg phy_reg_init[] = {
1603                 { 0x1f, 0x0003 },
1604                 { 0x08, 0x441d },
1605                 { 0x01, 0x9100 },
1606                 { 0x1f, 0x0000 }
1607         };
1608
1609         mdio_write(ioaddr, 0x1f, 0x0000);
1610         mdio_patch(ioaddr, 0x11, 1 << 12);
1611         mdio_patch(ioaddr, 0x19, 1 << 13);
1612
1613         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1614 }
1615
1616 static void rtl_hw_phy_config(struct net_device *dev)
1617 {
1618         struct rtl8169_private *tp = netdev_priv(dev);
1619         void __iomem *ioaddr = tp->mmio_addr;
1620
1621         rtl8169_print_mac_version(tp);
1622
1623         switch (tp->mac_version) {
1624         case RTL_GIGA_MAC_VER_01:
1625                 break;
1626         case RTL_GIGA_MAC_VER_02:
1627         case RTL_GIGA_MAC_VER_03:
1628                 rtl8169s_hw_phy_config(ioaddr);
1629                 break;
1630         case RTL_GIGA_MAC_VER_04:
1631                 rtl8169sb_hw_phy_config(ioaddr);
1632                 break;
1633         case RTL_GIGA_MAC_VER_07:
1634         case RTL_GIGA_MAC_VER_08:
1635         case RTL_GIGA_MAC_VER_09:
1636                 rtl8102e_hw_phy_config(ioaddr);
1637                 break;
1638         case RTL_GIGA_MAC_VER_11:
1639                 rtl8168bb_hw_phy_config(ioaddr);
1640                 break;
1641         case RTL_GIGA_MAC_VER_12:
1642                 rtl8168bef_hw_phy_config(ioaddr);
1643                 break;
1644         case RTL_GIGA_MAC_VER_17:
1645                 rtl8168bef_hw_phy_config(ioaddr);
1646                 break;
1647         case RTL_GIGA_MAC_VER_18:
1648                 rtl8168cp_1_hw_phy_config(ioaddr);
1649                 break;
1650         case RTL_GIGA_MAC_VER_19:
1651                 rtl8168c_1_hw_phy_config(ioaddr);
1652                 break;
1653         case RTL_GIGA_MAC_VER_20:
1654                 rtl8168c_2_hw_phy_config(ioaddr);
1655                 break;
1656         case RTL_GIGA_MAC_VER_21:
1657                 rtl8168c_3_hw_phy_config(ioaddr);
1658                 break;
1659         case RTL_GIGA_MAC_VER_22:
1660                 rtl8168c_4_hw_phy_config(ioaddr);
1661                 break;
1662         case RTL_GIGA_MAC_VER_23:
1663         case RTL_GIGA_MAC_VER_24:
1664                 rtl8168cp_2_hw_phy_config(ioaddr);
1665                 break;
1666         case RTL_GIGA_MAC_VER_25:
1667                 rtl8168d_hw_phy_config(ioaddr);
1668                 break;
1669
1670         default:
1671                 break;
1672         }
1673 }
1674
1675 static void rtl8169_phy_timer(unsigned long __opaque)
1676 {
1677         struct net_device *dev = (struct net_device *)__opaque;
1678         struct rtl8169_private *tp = netdev_priv(dev);
1679         struct timer_list *timer = &tp->timer;
1680         void __iomem *ioaddr = tp->mmio_addr;
1681         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1682
1683         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1684
1685         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1686                 return;
1687
1688         spin_lock_irq(&tp->lock);
1689
1690         if (tp->phy_reset_pending(ioaddr)) {
1691                 /*
1692                  * A busy loop could burn quite a few cycles on nowadays CPU.
1693                  * Let's delay the execution of the timer for a few ticks.
1694                  */
1695                 timeout = HZ/10;
1696                 goto out_mod_timer;
1697         }
1698
1699         if (tp->link_ok(ioaddr))
1700                 goto out_unlock;
1701
1702         if (netif_msg_link(tp))
1703                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1704
1705         tp->phy_reset_enable(ioaddr);
1706
1707 out_mod_timer:
1708         mod_timer(timer, jiffies + timeout);
1709 out_unlock:
1710         spin_unlock_irq(&tp->lock);
1711 }
1712
1713 static inline void rtl8169_delete_timer(struct net_device *dev)
1714 {
1715         struct rtl8169_private *tp = netdev_priv(dev);
1716         struct timer_list *timer = &tp->timer;
1717
1718         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1719                 return;
1720
1721         del_timer_sync(timer);
1722 }
1723
1724 static inline void rtl8169_request_timer(struct net_device *dev)
1725 {
1726         struct rtl8169_private *tp = netdev_priv(dev);
1727         struct timer_list *timer = &tp->timer;
1728
1729         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1730                 return;
1731
1732         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1733 }
1734
1735 #ifdef CONFIG_NET_POLL_CONTROLLER
1736 /*
1737  * Polling 'interrupt' - used by things like netconsole to send skbs
1738  * without having to re-enable interrupts. It's not called while
1739  * the interrupt routine is executing.
1740  */
1741 static void rtl8169_netpoll(struct net_device *dev)
1742 {
1743         struct rtl8169_private *tp = netdev_priv(dev);
1744         struct pci_dev *pdev = tp->pci_dev;
1745
1746         disable_irq(pdev->irq);
1747         rtl8169_interrupt(pdev->irq, dev);
1748         enable_irq(pdev->irq);
1749 }
1750 #endif
1751
1752 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1753                                   void __iomem *ioaddr)
1754 {
1755         iounmap(ioaddr);
1756         pci_release_regions(pdev);
1757         pci_disable_device(pdev);
1758         free_netdev(dev);
1759 }
1760
1761 static void rtl8169_phy_reset(struct net_device *dev,
1762                               struct rtl8169_private *tp)
1763 {
1764         void __iomem *ioaddr = tp->mmio_addr;
1765         unsigned int i;
1766
1767         tp->phy_reset_enable(ioaddr);
1768         for (i = 0; i < 100; i++) {
1769                 if (!tp->phy_reset_pending(ioaddr))
1770                         return;
1771                 msleep(1);
1772         }
1773         if (netif_msg_link(tp))
1774                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1775 }
1776
1777 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1778 {
1779         void __iomem *ioaddr = tp->mmio_addr;
1780
1781         rtl_hw_phy_config(dev);
1782
1783         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1784                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1785                 RTL_W8(0x82, 0x01);
1786         }
1787
1788         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1789
1790         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1791                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1792
1793         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1794                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1795                 RTL_W8(0x82, 0x01);
1796                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1797                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1798         }
1799
1800         rtl8169_phy_reset(dev, tp);
1801
1802         /*
1803          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1804          * only 8101. Don't panic.
1805          */
1806         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1807
1808         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1809                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1810 }
1811
1812 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1813 {
1814         void __iomem *ioaddr = tp->mmio_addr;
1815         u32 high;
1816         u32 low;
1817
1818         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1819         high = addr[4] | (addr[5] << 8);
1820
1821         spin_lock_irq(&tp->lock);
1822
1823         RTL_W8(Cfg9346, Cfg9346_Unlock);
1824         RTL_W32(MAC0, low);
1825         RTL_W32(MAC4, high);
1826         RTL_W8(Cfg9346, Cfg9346_Lock);
1827
1828         spin_unlock_irq(&tp->lock);
1829 }
1830
1831 static int rtl_set_mac_address(struct net_device *dev, void *p)
1832 {
1833         struct rtl8169_private *tp = netdev_priv(dev);
1834         struct sockaddr *addr = p;
1835
1836         if (!is_valid_ether_addr(addr->sa_data))
1837                 return -EADDRNOTAVAIL;
1838
1839         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1840
1841         rtl_rar_set(tp, dev->dev_addr);
1842
1843         return 0;
1844 }
1845
1846 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1847 {
1848         struct rtl8169_private *tp = netdev_priv(dev);
1849         struct mii_ioctl_data *data = if_mii(ifr);
1850
1851         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
1852 }
1853
1854 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1855 {
1856         switch (cmd) {
1857         case SIOCGMIIPHY:
1858                 data->phy_id = 32; /* Internal PHY */
1859                 return 0;
1860
1861         case SIOCGMIIREG:
1862                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1863                 return 0;
1864
1865         case SIOCSMIIREG:
1866                 if (!capable(CAP_NET_ADMIN))
1867                         return -EPERM;
1868                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1869                 return 0;
1870         }
1871         return -EOPNOTSUPP;
1872 }
1873
1874 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1875 {
1876         return -EOPNOTSUPP;
1877 }
1878
1879 static const struct rtl_cfg_info {
1880         void (*hw_start)(struct net_device *);
1881         unsigned int region;
1882         unsigned int align;
1883         u16 intr_event;
1884         u16 napi_event;
1885         unsigned features;
1886 } rtl_cfg_infos [] = {
1887         [RTL_CFG_0] = {
1888                 .hw_start       = rtl_hw_start_8169,
1889                 .region         = 1,
1890                 .align          = 0,
1891                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1892                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1893                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1894                 .features       = RTL_FEATURE_GMII
1895         },
1896         [RTL_CFG_1] = {
1897                 .hw_start       = rtl_hw_start_8168,
1898                 .region         = 2,
1899                 .align          = 8,
1900                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1901                                   TxErr | TxOK | RxOK | RxErr,
1902                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
1903                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1904         },
1905         [RTL_CFG_2] = {
1906                 .hw_start       = rtl_hw_start_8101,
1907                 .region         = 2,
1908                 .align          = 8,
1909                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1910                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1911                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1912                 .features       = RTL_FEATURE_MSI
1913         }
1914 };
1915
1916 /* Cfg9346_Unlock assumed. */
1917 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1918                             const struct rtl_cfg_info *cfg)
1919 {
1920         unsigned msi = 0;
1921         u8 cfg2;
1922
1923         cfg2 = RTL_R8(Config2) & ~MSIEnable;
1924         if (cfg->features & RTL_FEATURE_MSI) {
1925                 if (pci_enable_msi(pdev)) {
1926                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1927                 } else {
1928                         cfg2 |= MSIEnable;
1929                         msi = RTL_FEATURE_MSI;
1930                 }
1931         }
1932         RTL_W8(Config2, cfg2);
1933         return msi;
1934 }
1935
1936 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1937 {
1938         if (tp->features & RTL_FEATURE_MSI) {
1939                 pci_disable_msi(pdev);
1940                 tp->features &= ~RTL_FEATURE_MSI;
1941         }
1942 }
1943
1944 static const struct net_device_ops rtl8169_netdev_ops = {
1945         .ndo_open               = rtl8169_open,
1946         .ndo_stop               = rtl8169_close,
1947         .ndo_get_stats          = rtl8169_get_stats,
1948         .ndo_start_xmit         = rtl8169_start_xmit,
1949         .ndo_tx_timeout         = rtl8169_tx_timeout,
1950         .ndo_validate_addr      = eth_validate_addr,
1951         .ndo_change_mtu         = rtl8169_change_mtu,
1952         .ndo_set_mac_address    = rtl_set_mac_address,
1953         .ndo_do_ioctl           = rtl8169_ioctl,
1954         .ndo_set_multicast_list = rtl_set_rx_mode,
1955 #ifdef CONFIG_R8169_VLAN
1956         .ndo_vlan_rx_register   = rtl8169_vlan_rx_register,
1957 #endif
1958 #ifdef CONFIG_NET_POLL_CONTROLLER
1959         .ndo_poll_controller    = rtl8169_netpoll,
1960 #endif
1961
1962 };
1963
1964 static int __devinit
1965 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1966 {
1967         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1968         const unsigned int region = cfg->region;
1969         struct rtl8169_private *tp;
1970         struct mii_if_info *mii;
1971         struct net_device *dev;
1972         void __iomem *ioaddr;
1973         unsigned int i;
1974         int rc;
1975
1976         if (netif_msg_drv(&debug)) {
1977                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1978                        MODULENAME, RTL8169_VERSION);
1979         }
1980
1981         dev = alloc_etherdev(sizeof (*tp));
1982         if (!dev) {
1983                 if (netif_msg_drv(&debug))
1984                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1985                 rc = -ENOMEM;
1986                 goto out;
1987         }
1988
1989         SET_NETDEV_DEV(dev, &pdev->dev);
1990         dev->netdev_ops = &rtl8169_netdev_ops;
1991         tp = netdev_priv(dev);
1992         tp->dev = dev;
1993         tp->pci_dev = pdev;
1994         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1995
1996         mii = &tp->mii;
1997         mii->dev = dev;
1998         mii->mdio_read = rtl_mdio_read;
1999         mii->mdio_write = rtl_mdio_write;
2000         mii->phy_id_mask = 0x1f;
2001         mii->reg_num_mask = 0x1f;
2002         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2003
2004         /* enable device (incl. PCI PM wakeup and hotplug setup) */
2005         rc = pci_enable_device(pdev);
2006         if (rc < 0) {
2007                 if (netif_msg_probe(tp))
2008                         dev_err(&pdev->dev, "enable failure\n");
2009                 goto err_out_free_dev_1;
2010         }
2011
2012         rc = pci_set_mwi(pdev);
2013         if (rc < 0)
2014                 goto err_out_disable_2;
2015
2016         /* make sure PCI base addr 1 is MMIO */
2017         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2018                 if (netif_msg_probe(tp)) {
2019                         dev_err(&pdev->dev,
2020                                 "region #%d not an MMIO resource, aborting\n",
2021                                 region);
2022                 }
2023                 rc = -ENODEV;
2024                 goto err_out_mwi_3;
2025         }
2026
2027         /* check for weird/broken PCI region reporting */
2028         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2029                 if (netif_msg_probe(tp)) {
2030                         dev_err(&pdev->dev,
2031                                 "Invalid PCI region size(s), aborting\n");
2032                 }
2033                 rc = -ENODEV;
2034                 goto err_out_mwi_3;
2035         }
2036
2037         rc = pci_request_regions(pdev, MODULENAME);
2038         if (rc < 0) {
2039                 if (netif_msg_probe(tp))
2040                         dev_err(&pdev->dev, "could not request regions.\n");
2041                 goto err_out_mwi_3;
2042         }
2043
2044         tp->cp_cmd = PCIMulRW | RxChkSum;
2045
2046         if ((sizeof(dma_addr_t) > 4) &&
2047             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
2048                 tp->cp_cmd |= PCIDAC;
2049                 dev->features |= NETIF_F_HIGHDMA;
2050         } else {
2051                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2052                 if (rc < 0) {
2053                         if (netif_msg_probe(tp)) {
2054                                 dev_err(&pdev->dev,
2055                                         "DMA configuration failed.\n");
2056                         }
2057                         goto err_out_free_res_4;
2058                 }
2059         }
2060
2061         pci_set_master(pdev);
2062
2063         /* ioremap MMIO region */
2064         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2065         if (!ioaddr) {
2066                 if (netif_msg_probe(tp))
2067                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
2068                 rc = -EIO;
2069                 goto err_out_free_res_4;
2070         }
2071
2072         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2073         if (!tp->pcie_cap && netif_msg_probe(tp))
2074                 dev_info(&pdev->dev, "no PCI Express capability\n");
2075
2076         RTL_W16(IntrMask, 0x0000);
2077
2078         /* Soft reset the chip. */
2079         RTL_W8(ChipCmd, CmdReset);
2080
2081         /* Check that the chip has finished the reset. */
2082         for (i = 0; i < 100; i++) {
2083                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2084                         break;
2085                 msleep_interruptible(1);
2086         }
2087
2088         RTL_W16(IntrStatus, 0xffff);
2089
2090         /* Identify chip attached to board */
2091         rtl8169_get_mac_version(tp, ioaddr);
2092
2093         rtl8169_print_mac_version(tp);
2094
2095         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2096                 if (tp->mac_version == rtl_chip_info[i].mac_version)
2097                         break;
2098         }
2099         if (i == ARRAY_SIZE(rtl_chip_info)) {
2100                 /* Unknown chip: assume array element #0, original RTL-8169 */
2101                 if (netif_msg_probe(tp)) {
2102                         dev_printk(KERN_DEBUG, &pdev->dev,
2103                                 "unknown chip version, assuming %s\n",
2104                                 rtl_chip_info[0].name);
2105                 }
2106                 i = 0;
2107         }
2108         tp->chipset = i;
2109
2110         RTL_W8(Cfg9346, Cfg9346_Unlock);
2111         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2112         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2113         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2114                 tp->features |= RTL_FEATURE_WOL;
2115         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2116                 tp->features |= RTL_FEATURE_WOL;
2117         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2118         RTL_W8(Cfg9346, Cfg9346_Lock);
2119
2120         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2121             (RTL_R8(PHYstatus) & TBI_Enable)) {
2122                 tp->set_speed = rtl8169_set_speed_tbi;
2123                 tp->get_settings = rtl8169_gset_tbi;
2124                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2125                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2126                 tp->link_ok = rtl8169_tbi_link_ok;
2127                 tp->do_ioctl = rtl_tbi_ioctl;
2128
2129                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2130         } else {
2131                 tp->set_speed = rtl8169_set_speed_xmii;
2132                 tp->get_settings = rtl8169_gset_xmii;
2133                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2134                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2135                 tp->link_ok = rtl8169_xmii_link_ok;
2136                 tp->do_ioctl = rtl_xmii_ioctl;
2137         }
2138
2139         spin_lock_init(&tp->lock);
2140
2141         tp->mmio_addr = ioaddr;
2142
2143         /* Get MAC address */
2144         for (i = 0; i < MAC_ADDR_LEN; i++)
2145                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2146         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2147
2148         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2149         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2150         dev->irq = pdev->irq;
2151         dev->base_addr = (unsigned long) ioaddr;
2152
2153         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2154
2155 #ifdef CONFIG_R8169_VLAN
2156         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2157 #endif
2158
2159         tp->intr_mask = 0xffff;
2160         tp->align = cfg->align;
2161         tp->hw_start = cfg->hw_start;
2162         tp->intr_event = cfg->intr_event;
2163         tp->napi_event = cfg->napi_event;
2164
2165         init_timer(&tp->timer);
2166         tp->timer.data = (unsigned long) dev;
2167         tp->timer.function = rtl8169_phy_timer;
2168
2169         rc = register_netdev(dev);
2170         if (rc < 0)
2171                 goto err_out_msi_5;
2172
2173         pci_set_drvdata(pdev, dev);
2174
2175         if (netif_msg_probe(tp)) {
2176                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2177
2178                 printk(KERN_INFO "%s: %s at 0x%lx, "
2179                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2180                        "XID %08x IRQ %d\n",
2181                        dev->name,
2182                        rtl_chip_info[tp->chipset].name,
2183                        dev->base_addr,
2184                        dev->dev_addr[0], dev->dev_addr[1],
2185                        dev->dev_addr[2], dev->dev_addr[3],
2186                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2187         }
2188
2189         rtl8169_init_phy(dev, tp);
2190         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2191
2192 out:
2193         return rc;
2194
2195 err_out_msi_5:
2196         rtl_disable_msi(pdev, tp);
2197         iounmap(ioaddr);
2198 err_out_free_res_4:
2199         pci_release_regions(pdev);
2200 err_out_mwi_3:
2201         pci_clear_mwi(pdev);
2202 err_out_disable_2:
2203         pci_disable_device(pdev);
2204 err_out_free_dev_1:
2205         free_netdev(dev);
2206         goto out;
2207 }
2208
2209 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2210 {
2211         struct net_device *dev = pci_get_drvdata(pdev);
2212         struct rtl8169_private *tp = netdev_priv(dev);
2213
2214         flush_scheduled_work();
2215
2216         unregister_netdev(dev);
2217         rtl_disable_msi(pdev, tp);
2218         rtl8169_release_board(pdev, dev, tp->mmio_addr);
2219         pci_set_drvdata(pdev, NULL);
2220 }
2221
2222 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2223                                   struct net_device *dev)
2224 {
2225         unsigned int mtu = dev->mtu;
2226
2227         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2228 }
2229
2230 static int rtl8169_open(struct net_device *dev)
2231 {
2232         struct rtl8169_private *tp = netdev_priv(dev);
2233         struct pci_dev *pdev = tp->pci_dev;
2234         int retval = -ENOMEM;
2235
2236
2237         rtl8169_set_rxbufsize(tp, dev);
2238
2239         /*
2240          * Rx and Tx desscriptors needs 256 bytes alignment.
2241          * pci_alloc_consistent provides more.
2242          */
2243         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2244                                                &tp->TxPhyAddr);
2245         if (!tp->TxDescArray)
2246                 goto out;
2247
2248         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2249                                                &tp->RxPhyAddr);
2250         if (!tp->RxDescArray)
2251                 goto err_free_tx_0;
2252
2253         retval = rtl8169_init_ring(dev);
2254         if (retval < 0)
2255                 goto err_free_rx_1;
2256
2257         INIT_DELAYED_WORK(&tp->task, NULL);
2258
2259         smp_mb();
2260
2261         retval = request_irq(dev->irq, rtl8169_interrupt,
2262                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2263                              dev->name, dev);
2264         if (retval < 0)
2265                 goto err_release_ring_2;
2266
2267         napi_enable(&tp->napi);
2268
2269         rtl_hw_start(dev);
2270
2271         rtl8169_request_timer(dev);
2272
2273         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2274 out:
2275         return retval;
2276
2277 err_release_ring_2:
2278         rtl8169_rx_clear(tp);
2279 err_free_rx_1:
2280         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2281                             tp->RxPhyAddr);
2282 err_free_tx_0:
2283         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2284                             tp->TxPhyAddr);
2285         goto out;
2286 }
2287
2288 static void rtl8169_hw_reset(void __iomem *ioaddr)
2289 {
2290         /* Disable interrupts */
2291         rtl8169_irq_mask_and_ack(ioaddr);
2292
2293         /* Reset the chipset */
2294         RTL_W8(ChipCmd, CmdReset);
2295
2296         /* PCI commit */
2297         RTL_R8(ChipCmd);
2298 }
2299
2300 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2301 {
2302         void __iomem *ioaddr = tp->mmio_addr;
2303         u32 cfg = rtl8169_rx_config;
2304
2305         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2306         RTL_W32(RxConfig, cfg);
2307
2308         /* Set DMA burst size and Interframe Gap Time */
2309         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2310                 (InterFrameGap << TxInterFrameGapShift));
2311 }
2312
2313 static void rtl_hw_start(struct net_device *dev)
2314 {
2315         struct rtl8169_private *tp = netdev_priv(dev);
2316         void __iomem *ioaddr = tp->mmio_addr;
2317         unsigned int i;
2318
2319         /* Soft reset the chip. */
2320         RTL_W8(ChipCmd, CmdReset);
2321
2322         /* Check that the chip has finished the reset. */
2323         for (i = 0; i < 100; i++) {
2324                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2325                         break;
2326                 msleep_interruptible(1);
2327         }
2328
2329         tp->hw_start(dev);
2330
2331         netif_start_queue(dev);
2332 }
2333
2334
2335 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2336                                          void __iomem *ioaddr)
2337 {
2338         /*
2339          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2340          * register to be written before TxDescAddrLow to work.
2341          * Switching from MMIO to I/O access fixes the issue as well.
2342          */
2343         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2344         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2345         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2346         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2347 }
2348
2349 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2350 {
2351         u16 cmd;
2352
2353         cmd = RTL_R16(CPlusCmd);
2354         RTL_W16(CPlusCmd, cmd);
2355         return cmd;
2356 }
2357
2358 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2359 {
2360         /* Low hurts. Let's disable the filtering. */
2361         RTL_W16(RxMaxSize, 16383);
2362 }
2363
2364 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2365 {
2366         struct {
2367                 u32 mac_version;
2368                 u32 clk;
2369                 u32 val;
2370         } cfg2_info [] = {
2371                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2372                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2373                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2374                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2375         }, *p = cfg2_info;
2376         unsigned int i;
2377         u32 clk;
2378
2379         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2380         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2381                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2382                         RTL_W32(0x7c, p->val);
2383                         break;
2384                 }
2385         }
2386 }
2387
2388 static void rtl_hw_start_8169(struct net_device *dev)
2389 {
2390         struct rtl8169_private *tp = netdev_priv(dev);
2391         void __iomem *ioaddr = tp->mmio_addr;
2392         struct pci_dev *pdev = tp->pci_dev;
2393
2394         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2395                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2396                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2397         }
2398
2399         RTL_W8(Cfg9346, Cfg9346_Unlock);
2400         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2401             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2402             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2403             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2404                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2405
2406         RTL_W8(EarlyTxThres, EarlyTxThld);
2407
2408         rtl_set_rx_max_size(ioaddr);
2409
2410         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2411             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2412             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2413             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2414                 rtl_set_rx_tx_config_registers(tp);
2415
2416         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2417
2418         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2419             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2420                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2421                         "Bit-3 and bit-14 MUST be 1\n");
2422                 tp->cp_cmd |= (1 << 14);
2423         }
2424
2425         RTL_W16(CPlusCmd, tp->cp_cmd);
2426
2427         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2428
2429         /*
2430          * Undocumented corner. Supposedly:
2431          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2432          */
2433         RTL_W16(IntrMitigate, 0x0000);
2434
2435         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2436
2437         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2438             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2439             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2440             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2441                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2442                 rtl_set_rx_tx_config_registers(tp);
2443         }
2444
2445         RTL_W8(Cfg9346, Cfg9346_Lock);
2446
2447         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2448         RTL_R8(IntrMask);
2449
2450         RTL_W32(RxMissed, 0);
2451
2452         rtl_set_rx_mode(dev);
2453
2454         /* no early-rx interrupts */
2455         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2456
2457         /* Enable all known interrupts by setting the interrupt mask. */
2458         RTL_W16(IntrMask, tp->intr_event);
2459 }
2460
2461 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2462 {
2463         struct net_device *dev = pci_get_drvdata(pdev);
2464         struct rtl8169_private *tp = netdev_priv(dev);
2465         int cap = tp->pcie_cap;
2466
2467         if (cap) {
2468                 u16 ctl;
2469
2470                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2471                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2472                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2473         }
2474 }
2475
2476 static void rtl_csi_access_enable(void __iomem *ioaddr)
2477 {
2478         u32 csi;
2479
2480         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2481         rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2482 }
2483
2484 struct ephy_info {
2485         unsigned int offset;
2486         u16 mask;
2487         u16 bits;
2488 };
2489
2490 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2491 {
2492         u16 w;
2493
2494         while (len-- > 0) {
2495                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2496                 rtl_ephy_write(ioaddr, e->offset, w);
2497                 e++;
2498         }
2499 }
2500
2501 static void rtl_disable_clock_request(struct pci_dev *pdev)
2502 {
2503         struct net_device *dev = pci_get_drvdata(pdev);
2504         struct rtl8169_private *tp = netdev_priv(dev);
2505         int cap = tp->pcie_cap;
2506
2507         if (cap) {
2508                 u16 ctl;
2509
2510                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2511                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2512                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2513         }
2514 }
2515
2516 #define R8168_CPCMD_QUIRK_MASK (\
2517         EnableBist | \
2518         Mac_dbgo_oe | \
2519         Force_half_dup | \
2520         Force_rxflow_en | \
2521         Force_txflow_en | \
2522         Cxpl_dbg_sel | \
2523         ASF | \
2524         PktCntrDisable | \
2525         Mac_dbgo_sel)
2526
2527 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2528 {
2529         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2530
2531         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2532
2533         rtl_tx_performance_tweak(pdev,
2534                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2535 }
2536
2537 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2538 {
2539         rtl_hw_start_8168bb(ioaddr, pdev);
2540
2541         RTL_W8(EarlyTxThres, EarlyTxThld);
2542
2543         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2544 }
2545
2546 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2547 {
2548         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2549
2550         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2551
2552         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2553
2554         rtl_disable_clock_request(pdev);
2555
2556         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2557 }
2558
2559 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
2560 {
2561         static struct ephy_info e_info_8168cp[] = {
2562                 { 0x01, 0,      0x0001 },
2563                 { 0x02, 0x0800, 0x1000 },
2564                 { 0x03, 0,      0x0042 },
2565                 { 0x06, 0x0080, 0x0000 },
2566                 { 0x07, 0,      0x2000 }
2567         };
2568
2569         rtl_csi_access_enable(ioaddr);
2570
2571         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2572
2573         __rtl_hw_start_8168cp(ioaddr, pdev);
2574 }
2575
2576 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2577 {
2578         rtl_csi_access_enable(ioaddr);
2579
2580         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2581
2582         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2583
2584         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2585 }
2586
2587 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2588 {
2589         rtl_csi_access_enable(ioaddr);
2590
2591         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2592
2593         /* Magic. */
2594         RTL_W8(DBG_REG, 0x20);
2595
2596         RTL_W8(EarlyTxThres, EarlyTxThld);
2597
2598         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2599
2600         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2601 }
2602
2603 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2604 {
2605         static struct ephy_info e_info_8168c_1[] = {
2606                 { 0x02, 0x0800, 0x1000 },
2607                 { 0x03, 0,      0x0002 },
2608                 { 0x06, 0x0080, 0x0000 }
2609         };
2610
2611         rtl_csi_access_enable(ioaddr);
2612
2613         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2614
2615         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2616
2617         __rtl_hw_start_8168cp(ioaddr, pdev);
2618 }
2619
2620 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2621 {
2622         static struct ephy_info e_info_8168c_2[] = {
2623                 { 0x01, 0,      0x0001 },
2624                 { 0x03, 0x0400, 0x0220 }
2625         };
2626
2627         rtl_csi_access_enable(ioaddr);
2628
2629         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2630
2631         __rtl_hw_start_8168cp(ioaddr, pdev);
2632 }
2633
2634 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2635 {
2636         rtl_hw_start_8168c_2(ioaddr, pdev);
2637 }
2638
2639 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2640 {
2641         rtl_csi_access_enable(ioaddr);
2642
2643         __rtl_hw_start_8168cp(ioaddr, pdev);
2644 }
2645
2646 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2647 {
2648         rtl_csi_access_enable(ioaddr);
2649
2650         rtl_disable_clock_request(pdev);
2651
2652         RTL_W8(EarlyTxThres, EarlyTxThld);
2653
2654         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2655
2656         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2657 }
2658
2659 static void rtl_hw_start_8168(struct net_device *dev)
2660 {
2661         struct rtl8169_private *tp = netdev_priv(dev);
2662         void __iomem *ioaddr = tp->mmio_addr;
2663         struct pci_dev *pdev = tp->pci_dev;
2664
2665         RTL_W8(Cfg9346, Cfg9346_Unlock);
2666
2667         RTL_W8(EarlyTxThres, EarlyTxThld);
2668
2669         rtl_set_rx_max_size(ioaddr);
2670
2671         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2672
2673         RTL_W16(CPlusCmd, tp->cp_cmd);
2674
2675         RTL_W16(IntrMitigate, 0x5151);
2676
2677         /* Work around for RxFIFO overflow. */
2678         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2679                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2680                 tp->intr_event &= ~RxOverflow;
2681         }
2682
2683         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2684
2685         rtl_set_rx_mode(dev);
2686
2687         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2688                 (InterFrameGap << TxInterFrameGapShift));
2689
2690         RTL_R8(IntrMask);
2691
2692         switch (tp->mac_version) {
2693         case RTL_GIGA_MAC_VER_11:
2694                 rtl_hw_start_8168bb(ioaddr, pdev);
2695         break;
2696
2697         case RTL_GIGA_MAC_VER_12:
2698         case RTL_GIGA_MAC_VER_17:
2699                 rtl_hw_start_8168bef(ioaddr, pdev);
2700         break;
2701
2702         case RTL_GIGA_MAC_VER_18:
2703                 rtl_hw_start_8168cp_1(ioaddr, pdev);
2704         break;
2705
2706         case RTL_GIGA_MAC_VER_19:
2707                 rtl_hw_start_8168c_1(ioaddr, pdev);
2708         break;
2709
2710         case RTL_GIGA_MAC_VER_20:
2711                 rtl_hw_start_8168c_2(ioaddr, pdev);
2712         break;
2713
2714         case RTL_GIGA_MAC_VER_21:
2715                 rtl_hw_start_8168c_3(ioaddr, pdev);
2716         break;
2717
2718         case RTL_GIGA_MAC_VER_22:
2719                 rtl_hw_start_8168c_4(ioaddr, pdev);
2720         break;
2721
2722         case RTL_GIGA_MAC_VER_23:
2723                 rtl_hw_start_8168cp_2(ioaddr, pdev);
2724         break;
2725
2726         case RTL_GIGA_MAC_VER_24:
2727                 rtl_hw_start_8168cp_3(ioaddr, pdev);
2728         break;
2729
2730         case RTL_GIGA_MAC_VER_25:
2731                 rtl_hw_start_8168d(ioaddr, pdev);
2732         break;
2733
2734         default:
2735                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2736                         dev->name, tp->mac_version);
2737         break;
2738         }
2739
2740         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2741
2742         RTL_W8(Cfg9346, Cfg9346_Lock);
2743
2744         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2745
2746         RTL_W16(IntrMask, tp->intr_event);
2747 }
2748
2749 #define R810X_CPCMD_QUIRK_MASK (\
2750         EnableBist | \
2751         Mac_dbgo_oe | \
2752         Force_half_dup | \
2753         Force_half_dup | \
2754         Force_txflow_en | \
2755         Cxpl_dbg_sel | \
2756         ASF | \
2757         PktCntrDisable | \
2758         PCIDAC | \
2759         PCIMulRW)
2760
2761 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2762 {
2763         static struct ephy_info e_info_8102e_1[] = {
2764                 { 0x01, 0, 0x6e65 },
2765                 { 0x02, 0, 0x091f },
2766                 { 0x03, 0, 0xc2f9 },
2767                 { 0x06, 0, 0xafb5 },
2768                 { 0x07, 0, 0x0e00 },
2769                 { 0x19, 0, 0xec80 },
2770                 { 0x01, 0, 0x2e65 },
2771                 { 0x01, 0, 0x6e65 }
2772         };
2773         u8 cfg1;
2774
2775         rtl_csi_access_enable(ioaddr);
2776
2777         RTL_W8(DBG_REG, FIX_NAK_1);
2778
2779         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2780
2781         RTL_W8(Config1,
2782                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2783         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2784
2785         cfg1 = RTL_R8(Config1);
2786         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2787                 RTL_W8(Config1, cfg1 & ~LEDS0);
2788
2789         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2790
2791         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2792 }
2793
2794 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2795 {
2796         rtl_csi_access_enable(ioaddr);
2797
2798         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2799
2800         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2801         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2802
2803         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2804 }
2805
2806 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2807 {
2808         rtl_hw_start_8102e_2(ioaddr, pdev);
2809
2810         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2811 }
2812
2813 static void rtl_hw_start_8101(struct net_device *dev)
2814 {
2815         struct rtl8169_private *tp = netdev_priv(dev);
2816         void __iomem *ioaddr = tp->mmio_addr;
2817         struct pci_dev *pdev = tp->pci_dev;
2818
2819         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2820             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2821                 int cap = tp->pcie_cap;
2822
2823                 if (cap) {
2824                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2825                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
2826                 }
2827         }
2828
2829         switch (tp->mac_version) {
2830         case RTL_GIGA_MAC_VER_07:
2831                 rtl_hw_start_8102e_1(ioaddr, pdev);
2832                 break;
2833
2834         case RTL_GIGA_MAC_VER_08:
2835                 rtl_hw_start_8102e_3(ioaddr, pdev);
2836                 break;
2837
2838         case RTL_GIGA_MAC_VER_09:
2839                 rtl_hw_start_8102e_2(ioaddr, pdev);
2840                 break;
2841         }
2842
2843         RTL_W8(Cfg9346, Cfg9346_Unlock);
2844
2845         RTL_W8(EarlyTxThres, EarlyTxThld);
2846
2847         rtl_set_rx_max_size(ioaddr);
2848
2849         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2850
2851         RTL_W16(CPlusCmd, tp->cp_cmd);
2852
2853         RTL_W16(IntrMitigate, 0x0000);
2854
2855         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2856
2857         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2858         rtl_set_rx_tx_config_registers(tp);
2859
2860         RTL_W8(Cfg9346, Cfg9346_Lock);
2861
2862         RTL_R8(IntrMask);
2863
2864         rtl_set_rx_mode(dev);
2865
2866         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2867
2868         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2869
2870         RTL_W16(IntrMask, tp->intr_event);
2871 }
2872
2873 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2874 {
2875         struct rtl8169_private *tp = netdev_priv(dev);
2876         int ret = 0;
2877
2878         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2879                 return -EINVAL;
2880
2881         dev->mtu = new_mtu;
2882
2883         if (!netif_running(dev))
2884                 goto out;
2885
2886         rtl8169_down(dev);
2887
2888         rtl8169_set_rxbufsize(tp, dev);
2889
2890         ret = rtl8169_init_ring(dev);
2891         if (ret < 0)
2892                 goto out;
2893
2894         napi_enable(&tp->napi);
2895
2896         rtl_hw_start(dev);
2897
2898         rtl8169_request_timer(dev);
2899
2900 out:
2901         return ret;
2902 }
2903
2904 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2905 {
2906         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2907         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2908 }
2909
2910 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2911                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2912 {
2913         struct pci_dev *pdev = tp->pci_dev;
2914
2915         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2916                          PCI_DMA_FROMDEVICE);
2917         dev_kfree_skb(*sk_buff);
2918         *sk_buff = NULL;
2919         rtl8169_make_unusable_by_asic(desc);
2920 }
2921
2922 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2923 {
2924         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2925
2926         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2927 }
2928
2929 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2930                                        u32 rx_buf_sz)
2931 {
2932         desc->addr = cpu_to_le64(mapping);
2933         wmb();
2934         rtl8169_mark_to_asic(desc, rx_buf_sz);
2935 }
2936
2937 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2938                                             struct net_device *dev,
2939                                             struct RxDesc *desc, int rx_buf_sz,
2940                                             unsigned int align)
2941 {
2942         struct sk_buff *skb;
2943         dma_addr_t mapping;
2944         unsigned int pad;
2945
2946         pad = align ? align : NET_IP_ALIGN;
2947
2948         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2949         if (!skb)
2950                 goto err_out;
2951
2952         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2953
2954         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2955                                  PCI_DMA_FROMDEVICE);
2956
2957         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2958 out:
2959         return skb;
2960
2961 err_out:
2962         rtl8169_make_unusable_by_asic(desc);
2963         goto out;
2964 }
2965
2966 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2967 {
2968         unsigned int i;
2969
2970         for (i = 0; i < NUM_RX_DESC; i++) {
2971                 if (tp->Rx_skbuff[i]) {
2972                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2973                                             tp->RxDescArray + i);
2974                 }
2975         }
2976 }
2977
2978 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2979                            u32 start, u32 end)
2980 {
2981         u32 cur;
2982
2983         for (cur = start; end - cur != 0; cur++) {
2984                 struct sk_buff *skb;
2985                 unsigned int i = cur % NUM_RX_DESC;
2986
2987                 WARN_ON((s32)(end - cur) < 0);
2988
2989                 if (tp->Rx_skbuff[i])
2990                         continue;
2991
2992                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2993                                            tp->RxDescArray + i,
2994                                            tp->rx_buf_sz, tp->align);
2995                 if (!skb)
2996                         break;
2997
2998                 tp->Rx_skbuff[i] = skb;
2999         }
3000         return cur - start;
3001 }
3002
3003 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3004 {
3005         desc->opts1 |= cpu_to_le32(RingEnd);
3006 }
3007
3008 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3009 {
3010         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3011 }
3012
3013 static int rtl8169_init_ring(struct net_device *dev)
3014 {
3015         struct rtl8169_private *tp = netdev_priv(dev);
3016
3017         rtl8169_init_ring_indexes(tp);
3018
3019         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3020         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3021
3022         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3023                 goto err_out;
3024
3025         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3026
3027         return 0;
3028
3029 err_out:
3030         rtl8169_rx_clear(tp);
3031         return -ENOMEM;
3032 }
3033
3034 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3035                                  struct TxDesc *desc)
3036 {
3037         unsigned int len = tx_skb->len;
3038
3039         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3040         desc->opts1 = 0x00;
3041         desc->opts2 = 0x00;
3042         desc->addr = 0x00;
3043         tx_skb->len = 0;
3044 }
3045
3046 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3047 {
3048         unsigned int i;
3049
3050         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3051                 unsigned int entry = i % NUM_TX_DESC;
3052                 struct ring_info *tx_skb = tp->tx_skb + entry;
3053                 unsigned int len = tx_skb->len;
3054
3055                 if (len) {
3056                         struct sk_buff *skb = tx_skb->skb;
3057
3058                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3059                                              tp->TxDescArray + entry);
3060                         if (skb) {
3061                                 dev_kfree_skb(skb);
3062                                 tx_skb->skb = NULL;
3063                         }
3064                         tp->dev->stats.tx_dropped++;
3065                 }
3066         }
3067         tp->cur_tx = tp->dirty_tx = 0;
3068 }
3069
3070 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3071 {
3072         struct rtl8169_private *tp = netdev_priv(dev);
3073
3074         PREPARE_DELAYED_WORK(&tp->task, task);
3075         schedule_delayed_work(&tp->task, 4);
3076 }
3077
3078 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3079 {
3080         struct rtl8169_private *tp = netdev_priv(dev);
3081         void __iomem *ioaddr = tp->mmio_addr;
3082
3083         synchronize_irq(dev->irq);
3084
3085         /* Wait for any pending NAPI task to complete */
3086         napi_disable(&tp->napi);
3087
3088         rtl8169_irq_mask_and_ack(ioaddr);
3089
3090         tp->intr_mask = 0xffff;
3091         RTL_W16(IntrMask, tp->intr_event);
3092         napi_enable(&tp->napi);
3093 }
3094
3095 static void rtl8169_reinit_task(struct work_struct *work)
3096 {
3097         struct rtl8169_private *tp =
3098                 container_of(work, struct rtl8169_private, task.work);
3099         struct net_device *dev = tp->dev;
3100         int ret;
3101
3102         rtnl_lock();
3103
3104         if (!netif_running(dev))
3105                 goto out_unlock;
3106
3107         rtl8169_wait_for_quiescence(dev);
3108         rtl8169_close(dev);
3109
3110         ret = rtl8169_open(dev);
3111         if (unlikely(ret < 0)) {
3112                 if (net_ratelimit() && netif_msg_drv(tp)) {
3113                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
3114                                " Rescheduling.\n", dev->name, ret);
3115                 }
3116                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3117         }
3118
3119 out_unlock:
3120         rtnl_unlock();
3121 }
3122
3123 static void rtl8169_reset_task(struct work_struct *work)
3124 {
3125         struct rtl8169_private *tp =
3126                 container_of(work, struct rtl8169_private, task.work);
3127         struct net_device *dev = tp->dev;
3128
3129         rtnl_lock();
3130
3131         if (!netif_running(dev))
3132                 goto out_unlock;
3133
3134         rtl8169_wait_for_quiescence(dev);
3135
3136         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3137         rtl8169_tx_clear(tp);
3138
3139         if (tp->dirty_rx == tp->cur_rx) {
3140                 rtl8169_init_ring_indexes(tp);
3141                 rtl_hw_start(dev);
3142                 netif_wake_queue(dev);
3143                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3144         } else {
3145                 if (net_ratelimit() && netif_msg_intr(tp)) {
3146                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3147                                dev->name);
3148                 }
3149                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3150         }
3151
3152 out_unlock:
3153         rtnl_unlock();
3154 }
3155
3156 static void rtl8169_tx_timeout(struct net_device *dev)
3157 {
3158         struct rtl8169_private *tp = netdev_priv(dev);
3159
3160         rtl8169_hw_reset(tp->mmio_addr);
3161
3162         /* Let's wait a bit while any (async) irq lands on */
3163         rtl8169_schedule_work(dev, rtl8169_reset_task);
3164 }
3165
3166 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3167                               u32 opts1)
3168 {
3169         struct skb_shared_info *info = skb_shinfo(skb);
3170         unsigned int cur_frag, entry;
3171         struct TxDesc * uninitialized_var(txd);
3172
3173         entry = tp->cur_tx;
3174         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3175                 skb_frag_t *frag = info->frags + cur_frag;
3176                 dma_addr_t mapping;
3177                 u32 status, len;
3178                 void *addr;
3179
3180                 entry = (entry + 1) % NUM_TX_DESC;
3181
3182                 txd = tp->TxDescArray + entry;
3183                 len = frag->size;
3184                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3185                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3186
3187                 /* anti gcc 2.95.3 bugware (sic) */
3188                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3189
3190                 txd->opts1 = cpu_to_le32(status);
3191                 txd->addr = cpu_to_le64(mapping);
3192
3193                 tp->tx_skb[entry].len = len;
3194         }
3195
3196         if (cur_frag) {
3197                 tp->tx_skb[entry].skb = skb;
3198                 txd->opts1 |= cpu_to_le32(LastFrag);
3199         }
3200
3201         return cur_frag;
3202 }
3203
3204 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3205 {
3206         if (dev->features & NETIF_F_TSO) {
3207                 u32 mss = skb_shinfo(skb)->gso_size;
3208
3209                 if (mss)
3210                         return LargeSend | ((mss & MSSMask) << MSSShift);
3211         }
3212         if (skb->ip_summed == CHECKSUM_PARTIAL) {
3213                 const struct iphdr *ip = ip_hdr(skb);
3214
3215                 if (ip->protocol == IPPROTO_TCP)
3216                         return IPCS | TCPCS;
3217                 else if (ip->protocol == IPPROTO_UDP)
3218                         return IPCS | UDPCS;
3219                 WARN_ON(1);     /* we need a WARN() */
3220         }
3221         return 0;
3222 }
3223
3224 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3225 {
3226         struct rtl8169_private *tp = netdev_priv(dev);
3227         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3228         struct TxDesc *txd = tp->TxDescArray + entry;
3229         void __iomem *ioaddr = tp->mmio_addr;
3230         dma_addr_t mapping;
3231         u32 status, len;
3232         u32 opts1;
3233         int ret = NETDEV_TX_OK;
3234
3235         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3236                 if (netif_msg_drv(tp)) {
3237                         printk(KERN_ERR
3238                                "%s: BUG! Tx Ring full when queue awake!\n",
3239                                dev->name);
3240                 }
3241                 goto err_stop;
3242         }
3243
3244         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3245                 goto err_stop;
3246
3247         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3248
3249         frags = rtl8169_xmit_frags(tp, skb, opts1);
3250         if (frags) {
3251                 len = skb_headlen(skb);
3252                 opts1 |= FirstFrag;
3253         } else {
3254                 len = skb->len;
3255                 opts1 |= FirstFrag | LastFrag;
3256                 tp->tx_skb[entry].skb = skb;
3257         }
3258
3259         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3260
3261         tp->tx_skb[entry].len = len;
3262         txd->addr = cpu_to_le64(mapping);
3263         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3264
3265         wmb();
3266
3267         /* anti gcc 2.95.3 bugware (sic) */
3268         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3269         txd->opts1 = cpu_to_le32(status);
3270
3271         dev->trans_start = jiffies;
3272
3273         tp->cur_tx += frags + 1;
3274
3275         smp_wmb();
3276
3277         RTL_W8(TxPoll, NPQ);    /* set polling bit */
3278
3279         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3280                 netif_stop_queue(dev);
3281                 smp_rmb();
3282                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3283                         netif_wake_queue(dev);
3284         }
3285
3286 out:
3287         return ret;
3288
3289 err_stop:
3290         netif_stop_queue(dev);
3291         ret = NETDEV_TX_BUSY;
3292         dev->stats.tx_dropped++;
3293         goto out;
3294 }
3295
3296 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3297 {
3298         struct rtl8169_private *tp = netdev_priv(dev);
3299         struct pci_dev *pdev = tp->pci_dev;
3300         void __iomem *ioaddr = tp->mmio_addr;
3301         u16 pci_status, pci_cmd;
3302
3303         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3304         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3305
3306         if (netif_msg_intr(tp)) {
3307                 printk(KERN_ERR
3308                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3309                        dev->name, pci_cmd, pci_status);
3310         }
3311
3312         /*
3313          * The recovery sequence below admits a very elaborated explanation:
3314          * - it seems to work;
3315          * - I did not see what else could be done;
3316          * - it makes iop3xx happy.
3317          *
3318          * Feel free to adjust to your needs.
3319          */
3320         if (pdev->broken_parity_status)
3321                 pci_cmd &= ~PCI_COMMAND_PARITY;
3322         else
3323                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3324
3325         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3326
3327         pci_write_config_word(pdev, PCI_STATUS,
3328                 pci_status & (PCI_STATUS_DETECTED_PARITY |
3329                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3330                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3331
3332         /* The infamous DAC f*ckup only happens at boot time */
3333         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3334                 if (netif_msg_intr(tp))
3335                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3336                 tp->cp_cmd &= ~PCIDAC;
3337                 RTL_W16(CPlusCmd, tp->cp_cmd);
3338                 dev->features &= ~NETIF_F_HIGHDMA;
3339         }
3340
3341         rtl8169_hw_reset(ioaddr);
3342
3343         rtl8169_schedule_work(dev, rtl8169_reinit_task);
3344 }
3345
3346 static void rtl8169_tx_interrupt(struct net_device *dev,
3347                                  struct rtl8169_private *tp,
3348                                  void __iomem *ioaddr)
3349 {
3350         unsigned int dirty_tx, tx_left;
3351
3352         dirty_tx = tp->dirty_tx;
3353         smp_rmb();
3354         tx_left = tp->cur_tx - dirty_tx;
3355
3356         while (tx_left > 0) {
3357                 unsigned int entry = dirty_tx % NUM_TX_DESC;
3358                 struct ring_info *tx_skb = tp->tx_skb + entry;
3359                 u32 len = tx_skb->len;
3360                 u32 status;
3361
3362                 rmb();
3363                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3364                 if (status & DescOwn)
3365                         break;
3366
3367                 dev->stats.tx_bytes += len;
3368                 dev->stats.tx_packets++;
3369
3370                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3371
3372                 if (status & LastFrag) {
3373                         dev_kfree_skb_irq(tx_skb->skb);
3374                         tx_skb->skb = NULL;
3375                 }
3376                 dirty_tx++;
3377                 tx_left--;
3378         }
3379
3380         if (tp->dirty_tx != dirty_tx) {
3381                 tp->dirty_tx = dirty_tx;
3382                 smp_wmb();
3383                 if (netif_queue_stopped(dev) &&
3384                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3385                         netif_wake_queue(dev);
3386                 }
3387                 /*
3388                  * 8168 hack: TxPoll requests are lost when the Tx packets are
3389                  * too close. Let's kick an extra TxPoll request when a burst
3390                  * of start_xmit activity is detected (if it is not detected,
3391                  * it is slow enough). -- FR
3392                  */
3393                 smp_rmb();
3394                 if (tp->cur_tx != dirty_tx)
3395                         RTL_W8(TxPoll, NPQ);
3396         }
3397 }
3398
3399 static inline int rtl8169_fragmented_frame(u32 status)
3400 {
3401         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3402 }
3403
3404 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3405 {
3406         u32 opts1 = le32_to_cpu(desc->opts1);
3407         u32 status = opts1 & RxProtoMask;
3408
3409         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3410             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3411             ((status == RxProtoIP) && !(opts1 & IPFail)))
3412                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3413         else
3414                 skb->ip_summed = CHECKSUM_NONE;
3415 }
3416
3417 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3418                                        struct rtl8169_private *tp, int pkt_size,
3419                                        dma_addr_t addr)
3420 {
3421         struct sk_buff *skb;
3422         bool done = false;
3423
3424         if (pkt_size >= rx_copybreak)
3425                 goto out;
3426
3427         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3428         if (!skb)
3429                 goto out;
3430
3431         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3432                                     PCI_DMA_FROMDEVICE);
3433         skb_reserve(skb, NET_IP_ALIGN);
3434         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3435         *sk_buff = skb;
3436         done = true;
3437 out:
3438         return done;
3439 }
3440
3441 static int rtl8169_rx_interrupt(struct net_device *dev,
3442                                 struct rtl8169_private *tp,
3443                                 void __iomem *ioaddr, u32 budget)
3444 {
3445         unsigned int cur_rx, rx_left;
3446         unsigned int delta, count;
3447
3448         cur_rx = tp->cur_rx;
3449         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3450         rx_left = min(rx_left, budget);
3451
3452         for (; rx_left > 0; rx_left--, cur_rx++) {
3453                 unsigned int entry = cur_rx % NUM_RX_DESC;
3454                 struct RxDesc *desc = tp->RxDescArray + entry;
3455                 u32 status;
3456
3457                 rmb();
3458                 status = le32_to_cpu(desc->opts1);
3459
3460                 if (status & DescOwn)
3461                         break;
3462                 if (unlikely(status & RxRES)) {
3463                         if (netif_msg_rx_err(tp)) {
3464                                 printk(KERN_INFO
3465                                        "%s: Rx ERROR. status = %08x\n",
3466                                        dev->name, status);
3467                         }
3468                         dev->stats.rx_errors++;
3469                         if (status & (RxRWT | RxRUNT))
3470                                 dev->stats.rx_length_errors++;
3471                         if (status & RxCRC)
3472                                 dev->stats.rx_crc_errors++;
3473                         if (status & RxFOVF) {
3474                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3475                                 dev->stats.rx_fifo_errors++;
3476                         }
3477                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3478                 } else {
3479                         struct sk_buff *skb = tp->Rx_skbuff[entry];
3480                         dma_addr_t addr = le64_to_cpu(desc->addr);
3481                         int pkt_size = (status & 0x00001FFF) - 4;
3482                         struct pci_dev *pdev = tp->pci_dev;
3483
3484                         /*
3485                          * The driver does not support incoming fragmented
3486                          * frames. They are seen as a symptom of over-mtu
3487                          * sized frames.
3488                          */
3489                         if (unlikely(rtl8169_fragmented_frame(status))) {
3490                                 dev->stats.rx_dropped++;
3491                                 dev->stats.rx_length_errors++;
3492                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3493                                 continue;
3494                         }
3495
3496                         rtl8169_rx_csum(skb, desc);
3497
3498                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3499                                 pci_dma_sync_single_for_device(pdev, addr,
3500                                         pkt_size, PCI_DMA_FROMDEVICE);
3501                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3502                         } else {
3503                                 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3504                                                  PCI_DMA_FROMDEVICE);
3505                                 tp->Rx_skbuff[entry] = NULL;
3506                         }
3507
3508                         skb_put(skb, pkt_size);
3509                         skb->protocol = eth_type_trans(skb, dev);
3510
3511                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3512                                 netif_receive_skb(skb);
3513
3514                         dev->stats.rx_bytes += pkt_size;
3515                         dev->stats.rx_packets++;
3516                 }
3517
3518                 /* Work around for AMD plateform. */
3519                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3520                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3521                         desc->opts2 = 0;
3522                         cur_rx++;
3523                 }
3524         }
3525
3526         count = cur_rx - tp->cur_rx;
3527         tp->cur_rx = cur_rx;
3528
3529         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3530         if (!delta && count && netif_msg_intr(tp))
3531                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3532         tp->dirty_rx += delta;
3533
3534         /*
3535          * FIXME: until there is periodic timer to try and refill the ring,
3536          * a temporary shortage may definitely kill the Rx process.
3537          * - disable the asic to try and avoid an overflow and kick it again
3538          *   after refill ?
3539          * - how do others driver handle this condition (Uh oh...).
3540          */
3541         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3542                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3543
3544         return count;
3545 }
3546
3547 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3548 {
3549         struct net_device *dev = dev_instance;
3550         struct rtl8169_private *tp = netdev_priv(dev);
3551         void __iomem *ioaddr = tp->mmio_addr;
3552         int handled = 0;
3553         int status;
3554
3555         status = RTL_R16(IntrStatus);
3556
3557         /* hotplug/major error/no more work/shared irq */
3558         if ((status == 0xffff) || !status)
3559                 goto out;
3560
3561         handled = 1;
3562
3563         if (unlikely(!netif_running(dev))) {
3564                 rtl8169_asic_down(ioaddr);
3565                 goto out;
3566         }
3567
3568         status &= tp->intr_mask;
3569         RTL_W16(IntrStatus,
3570                 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3571
3572         if (!(status & tp->intr_event))
3573                 goto out;
3574
3575         /* Work around for rx fifo overflow */
3576         if (unlikely(status & RxFIFOOver) &&
3577             (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3578                 netif_stop_queue(dev);
3579                 rtl8169_tx_timeout(dev);
3580                 goto out;
3581         }
3582
3583         if (unlikely(status & SYSErr)) {
3584                 rtl8169_pcierr_interrupt(dev);
3585                 goto out;
3586         }
3587
3588         if (status & LinkChg)
3589                 rtl8169_check_link_status(dev, tp, ioaddr);
3590
3591         if (status & tp->napi_event) {
3592                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3593                 tp->intr_mask = ~tp->napi_event;
3594
3595                 if (likely(napi_schedule_prep(&tp->napi)))
3596                         __napi_schedule(&tp->napi);
3597                 else if (netif_msg_intr(tp)) {
3598                         printk(KERN_INFO "%s: interrupt %04x in poll\n",
3599                                dev->name, status);
3600                 }
3601         }
3602 out:
3603         return IRQ_RETVAL(handled);
3604 }
3605
3606 static int rtl8169_poll(struct napi_struct *napi, int budget)
3607 {
3608         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3609         struct net_device *dev = tp->dev;
3610         void __iomem *ioaddr = tp->mmio_addr;
3611         int work_done;
3612
3613         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3614         rtl8169_tx_interrupt(dev, tp, ioaddr);
3615
3616         if (work_done < budget) {
3617                 napi_complete(napi);
3618                 tp->intr_mask = 0xffff;
3619                 /*
3620                  * 20040426: the barrier is not strictly required but the
3621                  * behavior of the irq handler could be less predictable
3622                  * without it. Btw, the lack of flush for the posted pci
3623                  * write is safe - FR
3624                  */
3625                 smp_wmb();
3626                 RTL_W16(IntrMask, tp->intr_event);
3627         }
3628
3629         return work_done;
3630 }
3631
3632 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3633 {
3634         struct rtl8169_private *tp = netdev_priv(dev);
3635
3636         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3637                 return;
3638
3639         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3640         RTL_W32(RxMissed, 0);
3641 }
3642
3643 static void rtl8169_down(struct net_device *dev)
3644 {
3645         struct rtl8169_private *tp = netdev_priv(dev);
3646         void __iomem *ioaddr = tp->mmio_addr;
3647         unsigned int intrmask;
3648
3649         rtl8169_delete_timer(dev);
3650
3651         netif_stop_queue(dev);
3652
3653         napi_disable(&tp->napi);
3654
3655 core_down:
3656         spin_lock_irq(&tp->lock);
3657
3658         rtl8169_asic_down(ioaddr);
3659
3660         rtl8169_rx_missed(dev, ioaddr);
3661
3662         spin_unlock_irq(&tp->lock);
3663
3664         synchronize_irq(dev->irq);
3665
3666         /* Give a racing hard_start_xmit a few cycles to complete. */
3667         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
3668
3669         /*
3670          * And now for the 50k$ question: are IRQ disabled or not ?
3671          *
3672          * Two paths lead here:
3673          * 1) dev->close
3674          *    -> netif_running() is available to sync the current code and the
3675          *       IRQ handler. See rtl8169_interrupt for details.
3676          * 2) dev->change_mtu
3677          *    -> rtl8169_poll can not be issued again and re-enable the
3678          *       interruptions. Let's simply issue the IRQ down sequence again.
3679          *
3680          * No loop if hotpluged or major error (0xffff).
3681          */
3682         intrmask = RTL_R16(IntrMask);
3683         if (intrmask && (intrmask != 0xffff))
3684                 goto core_down;
3685
3686         rtl8169_tx_clear(tp);
3687
3688         rtl8169_rx_clear(tp);
3689 }
3690
3691 static int rtl8169_close(struct net_device *dev)
3692 {
3693         struct rtl8169_private *tp = netdev_priv(dev);
3694         struct pci_dev *pdev = tp->pci_dev;
3695
3696         /* update counters before going down */
3697         rtl8169_update_counters(dev);
3698
3699         rtl8169_down(dev);
3700
3701         free_irq(dev->irq, dev);
3702
3703         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3704                             tp->RxPhyAddr);
3705         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3706                             tp->TxPhyAddr);
3707         tp->TxDescArray = NULL;
3708         tp->RxDescArray = NULL;
3709
3710         return 0;
3711 }
3712
3713 static void rtl_set_rx_mode(struct net_device *dev)
3714 {
3715         struct rtl8169_private *tp = netdev_priv(dev);
3716         void __iomem *ioaddr = tp->mmio_addr;
3717         unsigned long flags;
3718         u32 mc_filter[2];       /* Multicast hash filter */
3719         int rx_mode;
3720         u32 tmp = 0;
3721
3722         if (dev->flags & IFF_PROMISC) {
3723                 /* Unconditionally log net taps. */
3724                 if (netif_msg_link(tp)) {
3725                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3726                                dev->name);
3727                 }
3728                 rx_mode =
3729                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3730                     AcceptAllPhys;
3731                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3732         } else if ((dev->mc_count > multicast_filter_limit)
3733                    || (dev->flags & IFF_ALLMULTI)) {
3734                 /* Too many to filter perfectly -- accept all multicasts. */
3735                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3736                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3737         } else {
3738                 struct dev_mc_list *mclist;
3739                 unsigned int i;
3740
3741                 rx_mode = AcceptBroadcast | AcceptMyPhys;
3742                 mc_filter[1] = mc_filter[0] = 0;
3743                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3744                      i++, mclist = mclist->next) {
3745                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3746                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3747                         rx_mode |= AcceptMulticast;
3748                 }
3749         }
3750
3751         spin_lock_irqsave(&tp->lock, flags);
3752
3753         tmp = rtl8169_rx_config | rx_mode |
3754               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3755
3756         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3757                 u32 data = mc_filter[0];
3758
3759                 mc_filter[0] = swab32(mc_filter[1]);
3760                 mc_filter[1] = swab32(data);
3761         }
3762
3763         RTL_W32(MAR0 + 0, mc_filter[0]);
3764         RTL_W32(MAR0 + 4, mc_filter[1]);
3765
3766         RTL_W32(RxConfig, tmp);
3767
3768         spin_unlock_irqrestore(&tp->lock, flags);
3769 }
3770
3771 /**
3772  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3773  *  @dev: The Ethernet Device to get statistics for
3774  *
3775  *  Get TX/RX statistics for rtl8169
3776  */
3777 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3778 {
3779         struct rtl8169_private *tp = netdev_priv(dev);
3780         void __iomem *ioaddr = tp->mmio_addr;
3781         unsigned long flags;
3782
3783         if (netif_running(dev)) {
3784                 spin_lock_irqsave(&tp->lock, flags);
3785                 rtl8169_rx_missed(dev, ioaddr);
3786                 spin_unlock_irqrestore(&tp->lock, flags);
3787         }
3788
3789         return &dev->stats;
3790 }
3791
3792 static void rtl8169_net_suspend(struct net_device *dev)
3793 {
3794         struct rtl8169_private *tp = netdev_priv(dev);
3795         void __iomem *ioaddr = tp->mmio_addr;
3796
3797         if (!netif_running(dev))
3798                 return;
3799
3800         netif_device_detach(dev);
3801         netif_stop_queue(dev);
3802
3803         spin_lock_irq(&tp->lock);
3804
3805         rtl8169_asic_down(ioaddr);
3806
3807         rtl8169_rx_missed(dev, ioaddr);
3808
3809         spin_unlock_irq(&tp->lock);
3810 }
3811
3812 #ifdef CONFIG_PM
3813
3814 static int rtl8169_suspend(struct device *device)
3815 {
3816         struct pci_dev *pdev = to_pci_dev(device);
3817         struct net_device *dev = pci_get_drvdata(pdev);
3818
3819         rtl8169_net_suspend(dev);
3820
3821         return 0;
3822 }
3823
3824 static int rtl8169_resume(struct device *device)
3825 {
3826         struct pci_dev *pdev = to_pci_dev(device);
3827         struct net_device *dev = pci_get_drvdata(pdev);
3828
3829         if (!netif_running(dev))
3830                 goto out;
3831
3832         netif_device_attach(dev);
3833
3834         rtl8169_schedule_work(dev, rtl8169_reset_task);
3835 out:
3836         return 0;
3837 }
3838
3839 static struct dev_pm_ops rtl8169_pm_ops = {
3840         .suspend = rtl8169_suspend,
3841         .resume = rtl8169_resume,
3842         .freeze = rtl8169_suspend,
3843         .thaw = rtl8169_resume,
3844         .poweroff = rtl8169_suspend,
3845         .restore = rtl8169_resume,
3846 };
3847
3848 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
3849
3850 #else /* !CONFIG_PM */
3851
3852 #define RTL8169_PM_OPS  NULL
3853
3854 #endif /* !CONFIG_PM */
3855
3856 static void rtl_shutdown(struct pci_dev *pdev)
3857 {
3858         struct net_device *dev = pci_get_drvdata(pdev);
3859
3860         rtl8169_net_suspend(dev);
3861
3862         if (system_state == SYSTEM_POWER_OFF) {
3863                 pci_wake_from_d3(pdev, true);
3864                 pci_set_power_state(pdev, PCI_D3hot);
3865         }
3866 }
3867
3868 static struct pci_driver rtl8169_pci_driver = {
3869         .name           = MODULENAME,
3870         .id_table       = rtl8169_pci_tbl,
3871         .probe          = rtl8169_init_one,
3872         .remove         = __devexit_p(rtl8169_remove_one),
3873         .shutdown       = rtl_shutdown,
3874         .driver.pm      = RTL8169_PM_OPS,
3875 };
3876
3877 static int __init rtl8169_init_module(void)
3878 {
3879         return pci_register_driver(&rtl8169_pci_driver);
3880 }
3881
3882 static void __exit rtl8169_cleanup_module(void)
3883 {
3884         pci_unregister_driver(&rtl8169_pci_driver);
3885 }
3886
3887 module_init(rtl8169_init_module);
3888 module_exit(rtl8169_cleanup_module);