Merge by hand (conflicts between pending drivers and kfree cleanups)
[linux-2.6] / arch / ppc / platforms / 4xx / sycamore.c
1 /*
2  * arch/ppc/platforms/4xx/sycamore.c
3  *
4  * Architecture- / platform-specific boot-time initialization code for
5  * IBM PowerPC 4xx based boards.
6  *
7  * Author: Armin Kuster <akuster@mvista.com>
8  *
9  * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
10  * the terms of the GNU General Public License version 2.  This program
11  * is licensed "as is" without any warranty of any kind, whether express
12  * or implied.
13  */
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/smp.h>
17 #include <linux/threads.h>
18 #include <linux/param.h>
19 #include <linux/string.h>
20 #include <linux/pci.h>
21 #include <linux/rtc.h>
22
23 #include <asm/ocp.h>
24 #include <asm/ppc4xx_pic.h>
25 #include <asm/system.h>
26 #include <asm/pci-bridge.h>
27 #include <asm/machdep.h>
28 #include <asm/page.h>
29 #include <asm/time.h>
30 #include <asm/io.h>
31 #include <asm/ibm_ocp_pci.h>
32 #include <asm/todc.h>
33
34 #undef DEBUG
35
36 #ifdef DEBUG
37 #define DBG(x...) printk(x)
38 #else
39 #define DBG(x...)
40 #endif
41
42 void *kb_cs;
43 void *kb_data;
44 void *sycamore_rtc_base;
45
46 /*
47  * Define external IRQ senses and polarities.
48  */
49 unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
50         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 7 */
51         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 8 */
52         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 9 */
53         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 10 */
54         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 11 */
55         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 12 */
56         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 0 */
57         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 1 */
58         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 2 */
59         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 3 */
60         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 4 */
61         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 5 */
62         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 6 */
63 };
64
65
66 /* Some IRQs unique to Sycamore.
67  * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
68  */
69 int __init
70 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
71 {
72         static char pci_irq_table[][4] =
73             /*
74              *      PCI IDSEL/INTPIN->INTLINE
75              *      A       B       C       D
76              */
77         {
78                 {28, 28, 28, 28},       /* IDSEL 1 - PCI slot 1 */
79                 {29, 29, 29, 29},       /* IDSEL 2 - PCI slot 2 */
80                 {30, 30, 30, 30},       /* IDSEL 3 - PCI slot 3 */
81                 {31, 31, 31, 31},       /* IDSEL 4 - PCI slot 4 */
82         };
83
84         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
85         return PCI_IRQ_TABLE_LOOKUP;
86 };
87
88 void __init
89 sycamore_setup_arch(void)
90 {
91         void *fpga_brdc;
92         unsigned char fpga_brdc_data;
93         void *fpga_enable;
94         void *fpga_polarity;
95         void *fpga_status;
96         void *fpga_trigger;
97
98         ppc4xx_setup_arch();
99
100         ibm_ocp_set_emac(0, 0);
101
102         kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
103         if (!kb_data) {
104                 printk(KERN_CRIT
105                        "sycamore_setup_arch() kb_data ioremap failed\n");
106                 return;
107         }
108
109         kb_cs = kb_data + 1;
110
111         fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
112         if (!fpga_status) {
113                 printk(KERN_CRIT
114                        "sycamore_setup_arch() fpga_status ioremap failed\n");
115                 return;
116         }
117
118         fpga_enable = fpga_status + 1;
119         fpga_polarity = fpga_status + 2;
120         fpga_trigger = fpga_status + 3;
121         fpga_brdc = fpga_status + 4;
122
123         /* split the keyboard and mouse interrupts */
124         fpga_brdc_data = readb(fpga_brdc);
125         fpga_brdc_data |= 0x80;
126         writeb(fpga_brdc_data, fpga_brdc);
127
128         writeb(0x3, fpga_enable);
129
130         writeb(0x3, fpga_polarity);
131
132         writeb(0x3, fpga_trigger);
133
134         /* RTC step for the sycamore */
135         sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
136         TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
137                   sycamore_rtc_base, 8);
138
139         /* Identify the system */
140         printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
141         printk(KERN_INFO
142                "Port by MontaVista Software, Inc. (source@mvista.com)\n");
143 }
144
145 void __init
146 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
147 {
148 #ifdef CONFIG_PCI
149         unsigned int bar_response, bar;
150         /*
151          * Expected PCI mapping:
152          *
153          *  PLB addr             PCI memory addr
154          *  ---------------------       ---------------------
155          *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
156          *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
157          *
158          *  PLB addr             PCI io addr
159          *  ---------------------       ---------------------
160          *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
161          *
162          * The following code is simplified by assuming that the bootrom
163          * has been well behaved in following this mapping.
164          */
165
166 #ifdef DEBUG
167         int i;
168
169         printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
170         printk("PCI bridge regs before fixup \n");
171         for (i = 0; i <= 3; i++) {
172                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
173                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
174                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
175                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
176         }
177         printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
178         printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
179         printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
180         printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
181
182 #endif
183
184         /* added for IBM boot rom version 1.15 bios bar changes  -AK */
185
186         /* Disable region first */
187         out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
188         /* PLB starting addr, PCI: 0x80000000 */
189         out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
190         /* PCI start addr, 0x80000000 */
191         out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
192         /* 512MB range of PLB to PCI */
193         out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
194         /* Enable no pre-fetch, enable region */
195         out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
196                                                 (PPC405_PCI_UPPER_MEM -
197                                                  PPC405_PCI_MEM_BASE)) | 0x01));
198
199         /* Enable inbound region one - 1GB size */
200         out_le32((void *) &(pcip->ptm1ms), 0xc0000001);
201
202         /* Disable outbound region one */
203         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
204         out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
205         out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
206         out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
207         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
208
209         /* Disable inbound region two */
210         out_le32((void *) &(pcip->ptm2ms), 0x00000000);
211
212         /* Disable outbound region two */
213         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
214         out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
215         out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
216         out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
217         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
218
219         /* Zero config bars */
220         for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
221                 early_write_config_dword(hose, hose->first_busno,
222                                          PCI_FUNC(hose->first_busno), bar,
223                                          0x00000000);
224                 early_read_config_dword(hose, hose->first_busno,
225                                         PCI_FUNC(hose->first_busno), bar,
226                                         &bar_response);
227                 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
228                     hose->first_busno, PCI_SLOT(hose->first_busno),
229                     PCI_FUNC(hose->first_busno), bar, bar_response);
230         }
231         /* end work arround */
232
233 #ifdef DEBUG
234         printk("PCI bridge regs after fixup \n");
235         for (i = 0; i <= 3; i++) {
236                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
237                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
238                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
239                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
240         }
241         printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
242         printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
243         printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
244         printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
245
246 #endif
247 #endif
248
249 }
250
251 void __init
252 sycamore_map_io(void)
253 {
254         ppc4xx_map_io();
255         io_block_mapping(SYCAMORE_RTC_VADDR,
256                          SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO);
257 }
258
259 void __init
260 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
261               unsigned long r6, unsigned long r7)
262 {
263         ppc4xx_init(r3, r4, r5, r6, r7);
264
265         ppc_md.setup_arch = sycamore_setup_arch;
266         ppc_md.setup_io_mappings = sycamore_map_io;
267
268 #ifdef CONFIG_GEN_RTC
269         ppc_md.time_init = todc_time_init;
270         ppc_md.set_rtc_time = todc_set_rtc_time;
271         ppc_md.get_rtc_time = todc_get_rtc_time;
272         ppc_md.nvram_read_val = todc_direct_read_val;
273         ppc_md.nvram_write_val = todc_direct_write_val;
274 #endif
275 }