2 * File: arch/blackfin/mach-bf537/dma.c
7 * Description: This file contains the simple DMA Implementation for Blackfin
10 * Copyright 2004-2007 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 #include <linux/module.h>
31 #include <asm/blackfin.h>
34 struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
35 (struct dma_register *) DMA0_NEXT_DESC_PTR,
36 (struct dma_register *) DMA1_NEXT_DESC_PTR,
37 (struct dma_register *) DMA2_NEXT_DESC_PTR,
38 (struct dma_register *) DMA3_NEXT_DESC_PTR,
39 (struct dma_register *) DMA4_NEXT_DESC_PTR,
40 (struct dma_register *) DMA5_NEXT_DESC_PTR,
41 (struct dma_register *) DMA6_NEXT_DESC_PTR,
42 (struct dma_register *) DMA7_NEXT_DESC_PTR,
43 (struct dma_register *) DMA8_NEXT_DESC_PTR,
44 (struct dma_register *) DMA9_NEXT_DESC_PTR,
45 (struct dma_register *) DMA10_NEXT_DESC_PTR,
46 (struct dma_register *) DMA11_NEXT_DESC_PTR,
47 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
48 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
49 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
50 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
52 EXPORT_SYMBOL(dma_io_base_addr);
54 int channel2irq(unsigned int channel)
72 ret_irq = IRQ_UART1_RX;
76 ret_irq = IRQ_UART1_TX;
80 ret_irq = IRQ_SPORT0_RX;
84 ret_irq = IRQ_SPORT0_TX;
88 ret_irq = IRQ_SPORT1_RX;
92 ret_irq = IRQ_SPORT1_TX;
100 ret_irq = IRQ_UART_RX;
104 ret_irq = IRQ_UART_TX;
107 case CH_MEM_STREAM0_SRC:
108 case CH_MEM_STREAM0_DEST:
109 ret_irq = IRQ_MEM_DMA0;
112 case CH_MEM_STREAM1_SRC:
113 case CH_MEM_STREAM1_DEST:
114 ret_irq = IRQ_MEM_DMA1;