2 * MPC8568E MDS Device Tree Source
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "MPC8568EMDS";
16 compatible = "MPC8568EMDS", "MPC85xxMDS";
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
50 device_type = "memory";
51 reg = <0x0 0x10000000>;
55 compatible = "fsl,mpc8568mds-bcsr";
56 reg = <0xf8000000 0x8000>;
63 compatible = "simple-bus";
64 ranges = <0x0 0xe0000000 0x100000>;
65 reg = <0xe0000000 0x1000>;
68 memory-controller@2000 {
69 compatible = "fsl,8568-memory-controller";
70 reg = <0x2000 0x1000>;
71 interrupt-parent = <&mpic>;
75 L2: l2-cache-controller@20000 {
76 compatible = "fsl,8568-l2-cache-controller";
77 reg = <0x20000 0x1000>;
78 cache-line-size = <32>; // 32 bytes
79 cache-size = <0x80000>; // L2, 512K
80 interrupt-parent = <&mpic>;
88 compatible = "fsl-i2c";
91 interrupt-parent = <&mpic>;
95 compatible = "dallas,ds1374";
101 #address-cells = <1>;
104 compatible = "fsl-i2c";
105 reg = <0x3100 0x100>;
107 interrupt-parent = <&mpic>;
112 #address-cells = <1>;
114 compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
116 ranges = <0x0 0x21100 0x200>;
119 compatible = "fsl,mpc8568-dma-channel",
120 "fsl,eloplus-dma-channel";
123 interrupt-parent = <&mpic>;
127 compatible = "fsl,mpc8568-dma-channel",
128 "fsl,eloplus-dma-channel";
131 interrupt-parent = <&mpic>;
135 compatible = "fsl,mpc8568-dma-channel",
136 "fsl,eloplus-dma-channel";
139 interrupt-parent = <&mpic>;
143 compatible = "fsl,mpc8568-dma-channel",
144 "fsl,eloplus-dma-channel";
147 interrupt-parent = <&mpic>;
153 #address-cells = <1>;
155 compatible = "fsl,gianfar-mdio";
156 reg = <0x24520 0x20>;
158 phy0: ethernet-phy@7 {
159 interrupt-parent = <&mpic>;
162 device_type = "ethernet-phy";
164 phy1: ethernet-phy@1 {
165 interrupt-parent = <&mpic>;
168 device_type = "ethernet-phy";
170 phy2: ethernet-phy@2 {
171 interrupt-parent = <&mpic>;
174 device_type = "ethernet-phy";
176 phy3: ethernet-phy@3 {
177 interrupt-parent = <&mpic>;
180 device_type = "ethernet-phy";
184 device_type = "tbi-phy";
189 #address-cells = <1>;
191 compatible = "fsl,gianfar-tbi";
192 reg = <0x25520 0x20>;
196 device_type = "tbi-phy";
200 enet0: ethernet@24000 {
202 device_type = "network";
204 compatible = "gianfar";
205 reg = <0x24000 0x1000>;
206 local-mac-address = [ 00 00 00 00 00 00 ];
207 interrupts = <29 2 30 2 34 2>;
208 interrupt-parent = <&mpic>;
209 tbi-handle = <&tbi0>;
210 phy-handle = <&phy2>;
213 enet1: ethernet@25000 {
215 device_type = "network";
217 compatible = "gianfar";
218 reg = <0x25000 0x1000>;
219 local-mac-address = [ 00 00 00 00 00 00 ];
220 interrupts = <35 2 36 2 40 2>;
221 interrupt-parent = <&mpic>;
222 tbi-handle = <&tbi1>;
223 phy-handle = <&phy3>;
226 serial0: serial@4500 {
228 device_type = "serial";
229 compatible = "ns16550";
230 reg = <0x4500 0x100>;
231 clock-frequency = <0>;
233 interrupt-parent = <&mpic>;
236 global-utilities@e0000 { //global utilities block
237 compatible = "fsl,mpc8548-guts";
238 reg = <0xe0000 0x1000>;
242 serial1: serial@4600 {
244 device_type = "serial";
245 compatible = "ns16550";
246 reg = <0x4600 0x100>;
247 clock-frequency = <0>;
249 interrupt-parent = <&mpic>;
253 compatible = "fsl,sec2.1", "fsl,sec2.0";
254 reg = <0x30000 0x10000>;
256 interrupt-parent = <&mpic>;
257 fsl,num-channels = <4>;
258 fsl,channel-fifo-len = <24>;
259 fsl,exec-units-mask = <0xfe>;
260 fsl,descriptor-types-mask = <0x12b0ebf>;
264 interrupt-controller;
265 #address-cells = <0>;
266 #interrupt-cells = <2>;
267 reg = <0x40000 0x40000>;
268 compatible = "chrp,open-pic";
269 device_type = "open-pic";
273 reg = <0xe0100 0x100>;
274 device_type = "par_io";
279 /* port pin dir open_drain assignment has_irq */
280 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
281 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
282 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
283 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
284 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
285 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
286 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
287 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
288 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
289 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
290 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
291 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
292 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
293 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
294 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
295 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
296 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
297 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
298 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
299 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
300 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
301 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
302 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
307 /* port pin dir open_drain assignment has_irq */
308 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
309 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
310 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
311 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
312 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
313 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
314 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
315 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
316 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
317 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
318 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
319 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
320 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
321 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
322 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
323 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
324 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
325 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
326 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
327 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
328 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
329 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
330 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
331 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
332 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
338 #address-cells = <1>;
341 compatible = "fsl,qe";
342 ranges = <0x0 0xe0080000 0x40000>;
343 reg = <0xe0080000 0x480>;
345 bus-frequency = <396000000>;
348 #address-cells = <1>;
350 compatible = "fsl,qe-muram", "fsl,cpm-muram";
351 ranges = <0x0 0x10000 0x10000>;
354 compatible = "fsl,qe-muram-data",
355 "fsl,cpm-muram-data";
362 compatible = "fsl,spi";
365 interrupt-parent = <&qeic>;
371 compatible = "fsl,spi";
374 interrupt-parent = <&qeic>;
379 device_type = "network";
380 compatible = "ucc_geth";
382 reg = <0x2000 0x200>;
384 interrupt-parent = <&qeic>;
385 local-mac-address = [ 00 00 00 00 00 00 ];
386 rx-clock-name = "none";
387 tx-clock-name = "clk16";
388 pio-handle = <&pio1>;
389 phy-handle = <&phy0>;
390 phy-connection-type = "rgmii-id";
394 device_type = "network";
395 compatible = "ucc_geth";
397 reg = <0x3000 0x200>;
399 interrupt-parent = <&qeic>;
400 local-mac-address = [ 00 00 00 00 00 00 ];
401 rx-clock-name = "none";
402 tx-clock-name = "clk16";
403 pio-handle = <&pio2>;
404 phy-handle = <&phy1>;
405 phy-connection-type = "rgmii-id";
409 #address-cells = <1>;
412 compatible = "fsl,ucc-mdio";
414 /* These are the same PHYs as on
415 * gianfar's MDIO bus */
416 qe_phy0: ethernet-phy@07 {
417 interrupt-parent = <&mpic>;
420 device_type = "ethernet-phy";
422 qe_phy1: ethernet-phy@01 {
423 interrupt-parent = <&mpic>;
426 device_type = "ethernet-phy";
428 qe_phy2: ethernet-phy@02 {
429 interrupt-parent = <&mpic>;
432 device_type = "ethernet-phy";
434 qe_phy3: ethernet-phy@03 {
435 interrupt-parent = <&mpic>;
438 device_type = "ethernet-phy";
442 qeic: interrupt-controller@80 {
443 interrupt-controller;
444 compatible = "fsl,qe-ic";
445 #address-cells = <0>;
446 #interrupt-cells = <1>;
449 interrupts = <46 2 46 2>; //high:30 low:30
450 interrupt-parent = <&mpic>;
457 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
459 /* IDSEL 0x12 AD18 */
460 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
461 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
462 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
463 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
465 /* IDSEL 0x13 AD19 */
466 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
467 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
468 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
469 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
471 interrupt-parent = <&mpic>;
474 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
475 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
476 clock-frequency = <66666666>;
477 #interrupt-cells = <1>;
479 #address-cells = <3>;
480 reg = <0xe0008000 0x1000>;
481 compatible = "fsl,mpc8540-pci";
486 pci1: pcie@e000a000 {
488 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
491 /* IDSEL 0x0 (PEX) */
492 00000 0x0 0x0 0x1 &mpic 0x0 0x1
493 00000 0x0 0x0 0x2 &mpic 0x1 0x1
494 00000 0x0 0x0 0x3 &mpic 0x2 0x1
495 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
497 interrupt-parent = <&mpic>;
500 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
501 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
502 clock-frequency = <33333333>;
503 #interrupt-cells = <1>;
505 #address-cells = <3>;
506 reg = <0xe000a000 0x1000>;
507 compatible = "fsl,mpc8548-pcie";
510 reg = <0x0 0x0 0x0 0x0 0x0>;
512 #address-cells = <3>;
514 ranges = <0x2000000 0x0 0xa0000000
515 0x2000000 0x0 0xa0000000