git.oblomov.eu Git - linux-2.6/blob - drivers/net/niu.c

   1 /* niu.c: Neptune ethernet driver.
   2  *
   3  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/init.h>
   8 #include <linux/pci.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/netdevice.h>
  11 #include <linux/ethtool.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/delay.h>
  15 #include <linux/bitops.h>
  16 #include <linux/mii.h>
  17 #include <linux/if_ether.h>
  18 #include <linux/if_vlan.h>
  19 #include <linux/ip.h>
  20 #include <linux/in.h>
  21 #include <linux/ipv6.h>
  22 #include <linux/log2.h>
  23 #include <linux/jiffies.h>
  24 #include <linux/crc32.h>
  25
  26 #include <linux/io.h>
  27
  28 #ifdef CONFIG_SPARC64
  29 #include <linux/of_device.h>
  30 #endif
  31
  32 #include "niu.h"
  33
  34 #define DRV_MODULE_NAME         "niu"
  35 #define PFX DRV_MODULE_NAME     ": "
  36 #define DRV_MODULE_VERSION      "1.0"
  37 #define DRV_MODULE_RELDATE      "Nov 14, 2008"
  38
  39 static char version[] __devinitdata =
  40         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  41
  42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  43 MODULE_DESCRIPTION("NIU ethernet driver");
  44 MODULE_LICENSE("GPL");
  45 MODULE_VERSION(DRV_MODULE_VERSION);
  46
  47 #ifndef DMA_44BIT_MASK
  48 #define DMA_44BIT_MASK  0x00000fffffffffffULL
  49 #endif
  50
  51 #ifndef readq
  52 static u64 readq(void __iomem *reg)
  53 {
  54         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
  55 }
  56
  57 static void writeq(u64 val, void __iomem *reg)
  58 {
  59         writel(val & 0xffffffff, reg);
  60         writel(val >> 32, reg + 0x4UL);
  61 }
  62 #endif
  63
  64 static struct pci_device_id niu_pci_tbl[] = {
  65         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  66         {}
  67 };
  68
  69 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  70
  71 #define NIU_TX_TIMEOUT                  (5 * HZ)
  72
  73 #define nr64(reg)               readq(np->regs + (reg))
  74 #define nw64(reg, val)          writeq((val), np->regs + (reg))
  75
  76 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
  77 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
  78
  79 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
  80 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
  81
  82 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
  83 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
  84
  85 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
  86 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
  87
  88 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  89
  90 static int niu_debug;
  91 static int debug = -1;
  92 module_param(debug, int, 0);
  93 MODULE_PARM_DESC(debug, "NIU debug level");
  94
  95 #define niudbg(TYPE, f, a...) \
  96 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
  97                 printk(KERN_DEBUG PFX f, ## a); \
  98 } while (0)
  99
 100 #define niuinfo(TYPE, f, a...) \
 101 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 102                 printk(KERN_INFO PFX f, ## a); \
 103 } while (0)
 104
 105 #define niuwarn(TYPE, f, a...) \
 106 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 107                 printk(KERN_WARNING PFX f, ## a); \
 108 } while (0)
 109
 110 #define niu_lock_parent(np, flags) \
 111         spin_lock_irqsave(&np->parent->lock, flags)
 112 #define niu_unlock_parent(np, flags) \
 113         spin_unlock_irqrestore(&np->parent->lock, flags)
 114
 115 static int serdes_init_10g_serdes(struct niu *np);
 116
 117 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
 118                                      u64 bits, int limit, int delay)
 119 {
 120         while (--limit >= 0) {
 121                 u64 val = nr64_mac(reg);
 122
 123                 if (!(val & bits))
 124                         break;
 125                 udelay(delay);
 126         }
 127         if (limit < 0)
 128                 return -ENODEV;
 129         return 0;
 130 }
 131
 132 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
 133                                         u64 bits, int limit, int delay,
 134                                         const char *reg_name)
 135 {
 136         int err;
 137
 138         nw64_mac(reg, bits);
 139         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
 140         if (err)
 141                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 142                         "would not clear, val[%llx]\n",
 143                         np->dev->name, (unsigned long long) bits, reg_name,
 144                         (unsigned long long) nr64_mac(reg));
 145         return err;
 146 }
 147
 148 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 149 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 150         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 151 })
 152
 153 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
 154                                      u64 bits, int limit, int delay)
 155 {
 156         while (--limit >= 0) {
 157                 u64 val = nr64_ipp(reg);
 158
 159                 if (!(val & bits))
 160                         break;
 161                 udelay(delay);
 162         }
 163         if (limit < 0)
 164                 return -ENODEV;
 165         return 0;
 166 }
 167
 168 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
 169                                         u64 bits, int limit, int delay,
 170                                         const char *reg_name)
 171 {
 172         int err;
 173         u64 val;
 174
 175         val = nr64_ipp(reg);
 176         val |= bits;
 177         nw64_ipp(reg, val);
 178
 179         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
 180         if (err)
 181                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 182                         "would not clear, val[%llx]\n",
 183                         np->dev->name, (unsigned long long) bits, reg_name,
 184                         (unsigned long long) nr64_ipp(reg));
 185         return err;
 186 }
 187
 188 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 189 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 190         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 191 })
 192
 193 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
 194                                  u64 bits, int limit, int delay)
 195 {
 196         while (--limit >= 0) {
 197                 u64 val = nr64(reg);
 198
 199                 if (!(val & bits))
 200                         break;
 201                 udelay(delay);
 202         }
 203         if (limit < 0)
 204                 return -ENODEV;
 205         return 0;
 206 }
 207
 208 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
 209 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 210         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
 211 })
 212
 213 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
 214                                     u64 bits, int limit, int delay,
 215                                     const char *reg_name)
 216 {
 217         int err;
 218
 219         nw64(reg, bits);
 220         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
 221         if (err)
 222                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 223                         "would not clear, val[%llx]\n",
 224                         np->dev->name, (unsigned long long) bits, reg_name,
 225                         (unsigned long long) nr64(reg));
 226         return err;
 227 }
 228
 229 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 230 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 231         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 232 })
 233
 234 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
 235 {
 236         u64 val = (u64) lp->timer;
 237
 238         if (on)
 239                 val |= LDG_IMGMT_ARM;
 240
 241         nw64(LDG_IMGMT(lp->ldg_num), val);
 242 }
 243
 244 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
 245 {
 246         unsigned long mask_reg, bits;
 247         u64 val;
 248
 249         if (ldn < 0 || ldn > LDN_MAX)
 250                 return -EINVAL;
 251
 252         if (ldn < 64) {
 253                 mask_reg = LD_IM0(ldn);
 254                 bits = LD_IM0_MASK;
 255         } else {
 256                 mask_reg = LD_IM1(ldn - 64);
 257                 bits = LD_IM1_MASK;
 258         }
 259
 260         val = nr64(mask_reg);
 261         if (on)
 262                 val &= ~bits;
 263         else
 264                 val |= bits;
 265         nw64(mask_reg, val);
 266
 267         return 0;
 268 }
 269
 270 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
 271 {
 272         struct niu_parent *parent = np->parent;
 273         int i;
 274
 275         for (i = 0; i <= LDN_MAX; i++) {
 276                 int err;
 277
 278                 if (parent->ldg_map[i] != lp->ldg_num)
 279                         continue;
 280
 281                 err = niu_ldn_irq_enable(np, i, on);
 282                 if (err)
 283                         return err;
 284         }
 285         return 0;
 286 }
 287
 288 static int niu_enable_interrupts(struct niu *np, int on)
 289 {
 290         int i;
 291
 292         for (i = 0; i < np->num_ldg; i++) {
 293                 struct niu_ldg *lp = &np->ldg[i];
 294                 int err;
 295
 296                 err = niu_enable_ldn_in_ldg(np, lp, on);
 297                 if (err)
 298                         return err;
 299         }
 300         for (i = 0; i < np->num_ldg; i++)
 301                 niu_ldg_rearm(np, &np->ldg[i], on);
 302
 303         return 0;
 304 }
 305
 306 static u32 phy_encode(u32 type, int port)
 307 {
 308         return (type << (port * 2));
 309 }
 310
 311 static u32 phy_decode(u32 val, int port)
 312 {
 313         return (val >> (port * 2)) & PORT_TYPE_MASK;
 314 }
 315
 316 static int mdio_wait(struct niu *np)
 317 {
 318         int limit = 1000;
 319         u64 val;
 320
 321         while (--limit > 0) {
 322                 val = nr64(MIF_FRAME_OUTPUT);
 323                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
 324                         return val & MIF_FRAME_OUTPUT_DATA;
 325
 326                 udelay(10);
 327         }
 328
 329         return -ENODEV;
 330 }
 331
 332 static int mdio_read(struct niu *np, int port, int dev, int reg)
 333 {
 334         int err;
 335
 336         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 337         err = mdio_wait(np);
 338         if (err < 0)
 339                 return err;
 340
 341         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
 342         return mdio_wait(np);
 343 }
 344
 345 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
 346 {
 347         int err;
 348
 349         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 350         err = mdio_wait(np);
 351         if (err < 0)
 352                 return err;
 353
 354         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
 355         err = mdio_wait(np);
 356         if (err < 0)
 357                 return err;
 358
 359         return 0;
 360 }
 361
 362 static int mii_read(struct niu *np, int port, int reg)
 363 {
 364         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
 365         return mdio_wait(np);
 366 }
 367
 368 static int mii_write(struct niu *np, int port, int reg, int data)
 369 {
 370         int err;
 371
 372         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
 373         err = mdio_wait(np);
 374         if (err < 0)
 375                 return err;
 376
 377         return 0;
 378 }
 379
 380 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
 381 {
 382         int err;
 383
 384         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 385                          ESR2_TI_PLL_TX_CFG_L(channel),
 386                          val & 0xffff);
 387         if (!err)
 388                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 389                                  ESR2_TI_PLL_TX_CFG_H(channel),
 390                                  val >> 16);
 391         return err;
 392 }
 393
 394 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
 395 {
 396         int err;
 397
 398         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 399                          ESR2_TI_PLL_RX_CFG_L(channel),
 400                          val & 0xffff);
 401         if (!err)
 402                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 403                                  ESR2_TI_PLL_RX_CFG_H(channel),
 404                                  val >> 16);
 405         return err;
 406 }
 407
 408 /* Mode is always 10G fiber.  */
 409 static int serdes_init_niu_10g_fiber(struct niu *np)
 410 {
 411         struct niu_link_config *lp = &np->link_config;
 412         u32 tx_cfg, rx_cfg;
 413         unsigned long i;
 414
 415         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 416         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 417                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 418                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 419
 420         if (lp->loopback_mode == LOOPBACK_PHY) {
 421                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 422
 423                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 424                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 425
 426                 tx_cfg |= PLL_TX_CFG_ENTEST;
 427                 rx_cfg |= PLL_RX_CFG_ENTEST;
 428         }
 429
 430         /* Initialize all 4 lanes of the SERDES.  */
 431         for (i = 0; i < 4; i++) {
 432                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
 433                 if (err)
 434                         return err;
 435         }
 436
 437         for (i = 0; i < 4; i++) {
 438                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
 439                 if (err)
 440                         return err;
 441         }
 442
 443         return 0;
 444 }
 445
 446 static int serdes_init_niu_1g_serdes(struct niu *np)
 447 {
 448         struct niu_link_config *lp = &np->link_config;
 449         u16 pll_cfg, pll_sts;
 450         int max_retry = 100;
 451         u64 uninitialized_var(sig), mask, val;
 452         u32 tx_cfg, rx_cfg;
 453         unsigned long i;
 454         int err;
 455
 456         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
 457                   PLL_TX_CFG_RATE_HALF);
 458         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 459                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 460                   PLL_RX_CFG_RATE_HALF);
 461
 462         if (np->port == 0)
 463                 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
 464
 465         if (lp->loopback_mode == LOOPBACK_PHY) {
 466                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 467
 468                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 469                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 470
 471                 tx_cfg |= PLL_TX_CFG_ENTEST;
 472                 rx_cfg |= PLL_RX_CFG_ENTEST;
 473         }
 474
 475         /* Initialize PLL for 1G */
 476         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
 477
 478         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 479                          ESR2_TI_PLL_CFG_L, pll_cfg);
 480         if (err) {
 481                 dev_err(np->device, PFX "NIU Port %d "
 482                         "serdes_init_niu_1g_serdes: "
 483                         "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
 484                 return err;
 485         }
 486
 487         pll_sts = PLL_CFG_ENPLL;
 488
 489         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 490                          ESR2_TI_PLL_STS_L, pll_sts);
 491         if (err) {
 492                 dev_err(np->device, PFX "NIU Port %d "
 493                         "serdes_init_niu_1g_serdes: "
 494                         "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
 495                 return err;
 496         }
 497
 498         udelay(200);
 499
 500         /* Initialize all 4 lanes of the SERDES.  */
 501         for (i = 0; i < 4; i++) {
 502                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 503                 if (err)
 504                         return err;
 505         }
 506
 507         for (i = 0; i < 4; i++) {
 508                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 509                 if (err)
 510                         return err;
 511         }
 512
 513         switch (np->port) {
 514         case 0:
 515                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
 516                 mask = val;
 517                 break;
 518
 519         case 1:
 520                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
 521                 mask = val;
 522                 break;
 523
 524         default:
 525                 return -EINVAL;
 526         }
 527
 528         while (max_retry--) {
 529                 sig = nr64(ESR_INT_SIGNALS);
 530                 if ((sig & mask) == val)
 531                         break;
 532
 533                 mdelay(500);
 534         }
 535
 536         if ((sig & mask) != val) {
 537                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 538                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 539                 return -ENODEV;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static int serdes_init_niu_10g_serdes(struct niu *np)
 546 {
 547         struct niu_link_config *lp = &np->link_config;
 548         u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
 549         int max_retry = 100;
 550         u64 uninitialized_var(sig), mask, val;
 551         unsigned long i;
 552         int err;
 553
 554         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 555         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 556                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 557                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 558
 559         if (lp->loopback_mode == LOOPBACK_PHY) {
 560                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 561
 562                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 563                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 564
 565                 tx_cfg |= PLL_TX_CFG_ENTEST;
 566                 rx_cfg |= PLL_RX_CFG_ENTEST;
 567         }
 568
 569         /* Initialize PLL for 10G */
 570         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
 571
 572         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 573                          ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
 574         if (err) {
 575                 dev_err(np->device, PFX "NIU Port %d "
 576                         "serdes_init_niu_10g_serdes: "
 577                         "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
 578                 return err;
 579         }
 580
 581         pll_sts = PLL_CFG_ENPLL;
 582
 583         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 584                          ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
 585         if (err) {
 586                 dev_err(np->device, PFX "NIU Port %d "
 587                         "serdes_init_niu_10g_serdes: "
 588                         "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
 589                 return err;
 590         }
 591
 592         udelay(200);
 593
 594         /* Initialize all 4 lanes of the SERDES.  */
 595         for (i = 0; i < 4; i++) {
 596                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 597                 if (err)
 598                         return err;
 599         }
 600
 601         for (i = 0; i < 4; i++) {
 602                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 603                 if (err)
 604                         return err;
 605         }
 606
 607         /* check if serdes is ready */
 608
 609         switch (np->port) {
 610         case 0:
 611                 mask = ESR_INT_SIGNALS_P0_BITS;
 612                 val = (ESR_INT_SRDY0_P0 |
 613                        ESR_INT_DET0_P0 |
 614                        ESR_INT_XSRDY_P0 |
 615                        ESR_INT_XDP_P0_CH3 |
 616                        ESR_INT_XDP_P0_CH2 |
 617                        ESR_INT_XDP_P0_CH1 |
 618                        ESR_INT_XDP_P0_CH0);
 619                 break;
 620
 621         case 1:
 622                 mask = ESR_INT_SIGNALS_P1_BITS;
 623                 val = (ESR_INT_SRDY0_P1 |
 624                        ESR_INT_DET0_P1 |
 625                        ESR_INT_XSRDY_P1 |
 626                        ESR_INT_XDP_P1_CH3 |
 627                        ESR_INT_XDP_P1_CH2 |
 628                        ESR_INT_XDP_P1_CH1 |
 629                        ESR_INT_XDP_P1_CH0);
 630                 break;
 631
 632         default:
 633                 return -EINVAL;
 634         }
 635
 636         while (max_retry--) {
 637                 sig = nr64(ESR_INT_SIGNALS);
 638                 if ((sig & mask) == val)
 639                         break;
 640
 641                 mdelay(500);
 642         }
 643
 644         if ((sig & mask) != val) {
 645                 pr_info(PFX "NIU Port %u signal bits [%08x] are not "
 646                         "[%08x] for 10G...trying 1G\n",
 647                         np->port, (int) (sig & mask), (int) val);
 648
 649                 /* 10G failed, try initializing at 1G */
 650                 err = serdes_init_niu_1g_serdes(np);
 651                 if (!err) {
 652                         np->flags &= ~NIU_FLAGS_10G;
 653                         np->mac_xcvr = MAC_XCVR_PCS;
 654                 }  else {
 655                         dev_err(np->device, PFX "Port %u 10G/1G SERDES "
 656                                 "Link Failed \n", np->port);
 657                         return -ENODEV;
 658                 }
 659         }
 660         return 0;
 661 }
 662
 663 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
 664 {
 665         int err;
 666
 667         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
 668         if (err >= 0) {
 669                 *val = (err & 0xffff);
 670                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 671                                 ESR_RXTX_CTRL_H(chan));
 672                 if (err >= 0)
 673                         *val |= ((err & 0xffff) << 16);
 674                 err = 0;
 675         }
 676         return err;
 677 }
 678
 679 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
 680 {
 681         int err;
 682
 683         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 684                         ESR_GLUE_CTRL0_L(chan));
 685         if (err >= 0) {
 686                 *val = (err & 0xffff);
 687                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 688                                 ESR_GLUE_CTRL0_H(chan));
 689                 if (err >= 0) {
 690                         *val |= ((err & 0xffff) << 16);
 691                         err = 0;
 692                 }
 693         }
 694         return err;
 695 }
 696
 697 static int esr_read_reset(struct niu *np, u32 *val)
 698 {
 699         int err;
 700
 701         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 702                         ESR_RXTX_RESET_CTRL_L);
 703         if (err >= 0) {
 704                 *val = (err & 0xffff);
 705                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 706                                 ESR_RXTX_RESET_CTRL_H);
 707                 if (err >= 0) {
 708                         *val |= ((err & 0xffff) << 16);
 709                         err = 0;
 710                 }
 711         }
 712         return err;
 713 }
 714
 715 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
 716 {
 717         int err;
 718
 719         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 720                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
 721         if (!err)
 722                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 723                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
 724         return err;
 725 }
 726
 727 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
 728 {
 729         int err;
 730
 731         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 732                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
 733         if (!err)
 734                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 735                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
 736         return err;
 737 }
 738
 739 static int esr_reset(struct niu *np)
 740 {
 741         u32 uninitialized_var(reset);
 742         int err;
 743
 744         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 745                          ESR_RXTX_RESET_CTRL_L, 0x0000);
 746         if (err)
 747                 return err;
 748         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 749                          ESR_RXTX_RESET_CTRL_H, 0xffff);
 750         if (err)
 751                 return err;
 752         udelay(200);
 753
 754         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 755                          ESR_RXTX_RESET_CTRL_L, 0xffff);
 756         if (err)
 757                 return err;
 758         udelay(200);
 759
 760         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 761                          ESR_RXTX_RESET_CTRL_H, 0x0000);
 762         if (err)
 763                 return err;
 764         udelay(200);
 765
 766         err = esr_read_reset(np, &reset);
 767         if (err)
 768                 return err;
 769         if (reset != 0) {
 770                 dev_err(np->device, PFX "Port %u ESR_RESET "
 771                         "did not clear [%08x]\n",
 772                         np->port, reset);
 773                 return -ENODEV;
 774         }
 775
 776         return 0;
 777 }
 778
 779 static int serdes_init_10g(struct niu *np)
 780 {
 781         struct niu_link_config *lp = &np->link_config;
 782         unsigned long ctrl_reg, test_cfg_reg, i;
 783         u64 ctrl_val, test_cfg_val, sig, mask, val;
 784         int err;
 785
 786         switch (np->port) {
 787         case 0:
 788                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 789                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 790                 break;
 791         case 1:
 792                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 793                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 794                 break;
 795
 796         default:
 797                 return -EINVAL;
 798         }
 799         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 800                     ENET_SERDES_CTRL_SDET_1 |
 801                     ENET_SERDES_CTRL_SDET_2 |
 802                     ENET_SERDES_CTRL_SDET_3 |
 803                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 804                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 805                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 806                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 807                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 808                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 809                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 810                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 811         test_cfg_val = 0;
 812
 813         if (lp->loopback_mode == LOOPBACK_PHY) {
 814                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 815                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 816                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 817                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 818                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 819                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 820                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 821                                   ENET_SERDES_TEST_MD_3_SHIFT));
 822         }
 823
 824         nw64(ctrl_reg, ctrl_val);
 825         nw64(test_cfg_reg, test_cfg_val);
 826
 827         /* Initialize all 4 lanes of the SERDES.  */
 828         for (i = 0; i < 4; i++) {
 829                 u32 rxtx_ctrl, glue0;
 830
 831                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 832                 if (err)
 833                         return err;
 834                 err = esr_read_glue0(np, i, &glue0);
 835                 if (err)
 836                         return err;
 837
 838                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 839                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 840                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 841
 842                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 843                            ESR_GLUE_CTRL0_THCNT |
 844                            ESR_GLUE_CTRL0_BLTIME);
 845                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 846                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 847                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 848                           (BLTIME_300_CYCLES <<
 849                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 850
 851                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 852                 if (err)
 853                         return err;
 854                 err = esr_write_glue0(np, i, glue0);
 855                 if (err)
 856                         return err;
 857         }
 858
 859         err = esr_reset(np);
 860         if (err)
 861                 return err;
 862
 863         sig = nr64(ESR_INT_SIGNALS);
 864         switch (np->port) {
 865         case 0:
 866                 mask = ESR_INT_SIGNALS_P0_BITS;
 867                 val = (ESR_INT_SRDY0_P0 |
 868                        ESR_INT_DET0_P0 |
 869                        ESR_INT_XSRDY_P0 |
 870                        ESR_INT_XDP_P0_CH3 |
 871                        ESR_INT_XDP_P0_CH2 |
 872                        ESR_INT_XDP_P0_CH1 |
 873                        ESR_INT_XDP_P0_CH0);
 874                 break;
 875
 876         case 1:
 877                 mask = ESR_INT_SIGNALS_P1_BITS;
 878                 val = (ESR_INT_SRDY0_P1 |
 879                        ESR_INT_DET0_P1 |
 880                        ESR_INT_XSRDY_P1 |
 881                        ESR_INT_XDP_P1_CH3 |
 882                        ESR_INT_XDP_P1_CH2 |
 883                        ESR_INT_XDP_P1_CH1 |
 884                        ESR_INT_XDP_P1_CH0);
 885                 break;
 886
 887         default:
 888                 return -EINVAL;
 889         }
 890
 891         if ((sig & mask) != val) {
 892                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
 893                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 894                         return 0;
 895                 }
 896                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 897                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 898                 return -ENODEV;
 899         }
 900         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
 901                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 902         return 0;
 903 }
 904
 905 static int serdes_init_1g(struct niu *np)
 906 {
 907         u64 val;
 908
 909         val = nr64(ENET_SERDES_1_PLL_CFG);
 910         val &= ~ENET_SERDES_PLL_FBDIV2;
 911         switch (np->port) {
 912         case 0:
 913                 val |= ENET_SERDES_PLL_HRATE0;
 914                 break;
 915         case 1:
 916                 val |= ENET_SERDES_PLL_HRATE1;
 917                 break;
 918         case 2:
 919                 val |= ENET_SERDES_PLL_HRATE2;
 920                 break;
 921         case 3:
 922                 val |= ENET_SERDES_PLL_HRATE3;
 923                 break;
 924         default:
 925                 return -EINVAL;
 926         }
 927         nw64(ENET_SERDES_1_PLL_CFG, val);
 928
 929         return 0;
 930 }
 931
 932 static int serdes_init_1g_serdes(struct niu *np)
 933 {
 934         struct niu_link_config *lp = &np->link_config;
 935         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
 936         u64 ctrl_val, test_cfg_val, sig, mask, val;
 937         int err;
 938         u64 reset_val, val_rd;
 939
 940         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
 941                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
 942                 ENET_SERDES_PLL_FBDIV0;
 943         switch (np->port) {
 944         case 0:
 945                 reset_val =  ENET_SERDES_RESET_0;
 946                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 947                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 948                 pll_cfg = ENET_SERDES_0_PLL_CFG;
 949                 break;
 950         case 1:
 951                 reset_val =  ENET_SERDES_RESET_1;
 952                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 953                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 954                 pll_cfg = ENET_SERDES_1_PLL_CFG;
 955                 break;
 956
 957         default:
 958                 return -EINVAL;
 959         }
 960         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 961                     ENET_SERDES_CTRL_SDET_1 |
 962                     ENET_SERDES_CTRL_SDET_2 |
 963                     ENET_SERDES_CTRL_SDET_3 |
 964                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 965                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 966                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 967                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 968                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 969                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 970                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 971                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 972         test_cfg_val = 0;
 973
 974         if (lp->loopback_mode == LOOPBACK_PHY) {
 975                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 976                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 977                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 978                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 979                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 980                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 981                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 982                                   ENET_SERDES_TEST_MD_3_SHIFT));
 983         }
 984
 985         nw64(ENET_SERDES_RESET, reset_val);
 986         mdelay(20);
 987         val_rd = nr64(ENET_SERDES_RESET);
 988         val_rd &= ~reset_val;
 989         nw64(pll_cfg, val);
 990         nw64(ctrl_reg, ctrl_val);
 991         nw64(test_cfg_reg, test_cfg_val);
 992         nw64(ENET_SERDES_RESET, val_rd);
 993         mdelay(2000);
 994
 995         /* Initialize all 4 lanes of the SERDES.  */
 996         for (i = 0; i < 4; i++) {
 997                 u32 rxtx_ctrl, glue0;
 998
 999                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
1000                 if (err)
1001                         return err;
1002                 err = esr_read_glue0(np, i, &glue0);
1003                 if (err)
1004                         return err;
1005
1006                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
1007                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
1008                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
1009
1010                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
1011                            ESR_GLUE_CTRL0_THCNT |
1012                            ESR_GLUE_CTRL0_BLTIME);
1013                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
1014                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
1015                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
1016                           (BLTIME_300_CYCLES <<
1017                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
1018
1019                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1020                 if (err)
1021                         return err;
1022                 err = esr_write_glue0(np, i, glue0);
1023                 if (err)
1024                         return err;
1025         }
1026
1027
1028         sig = nr64(ESR_INT_SIGNALS);
1029         switch (np->port) {
1030         case 0:
1031                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1032                 mask = val;
1033                 break;
1034
1035         case 1:
1036                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1037                 mask = val;
1038                 break;
1039
1040         default:
1041                 return -EINVAL;
1042         }
1043
1044         if ((sig & mask) != val) {
1045                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
1046                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
1047                 return -ENODEV;
1048         }
1049
1050         return 0;
1051 }
1052
1053 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1054 {
1055         struct niu_link_config *lp = &np->link_config;
1056         int link_up;
1057         u64 val;
1058         u16 current_speed;
1059         unsigned long flags;
1060         u8 current_duplex;
1061
1062         link_up = 0;
1063         current_speed = SPEED_INVALID;
1064         current_duplex = DUPLEX_INVALID;
1065
1066         spin_lock_irqsave(&np->lock, flags);
1067
1068         val = nr64_pcs(PCS_MII_STAT);
1069
1070         if (val & PCS_MII_STAT_LINK_STATUS) {
1071                 link_up = 1;
1072                 current_speed = SPEED_1000;
1073                 current_duplex = DUPLEX_FULL;
1074         }
1075
1076         lp->active_speed = current_speed;
1077         lp->active_duplex = current_duplex;
1078         spin_unlock_irqrestore(&np->lock, flags);
1079
1080         *link_up_p = link_up;
1081         return 0;
1082 }
1083
1084 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1085 {
1086         unsigned long flags;
1087         struct niu_link_config *lp = &np->link_config;
1088         int link_up = 0;
1089         int link_ok = 1;
1090         u64 val, val2;
1091         u16 current_speed;
1092         u8 current_duplex;
1093
1094         if (!(np->flags & NIU_FLAGS_10G))
1095                 return link_status_1g_serdes(np, link_up_p);
1096
1097         current_speed = SPEED_INVALID;
1098         current_duplex = DUPLEX_INVALID;
1099         spin_lock_irqsave(&np->lock, flags);
1100
1101         val = nr64_xpcs(XPCS_STATUS(0));
1102         val2 = nr64_mac(XMAC_INTER2);
1103         if (val2 & 0x01000000)
1104                 link_ok = 0;
1105
1106         if ((val & 0x1000ULL) && link_ok) {
1107                 link_up = 1;
1108                 current_speed = SPEED_10000;
1109                 current_duplex = DUPLEX_FULL;
1110         }
1111         lp->active_speed = current_speed;
1112         lp->active_duplex = current_duplex;
1113         spin_unlock_irqrestore(&np->lock, flags);
1114         *link_up_p = link_up;
1115         return 0;
1116 }
1117
1118 static int link_status_mii(struct niu *np, int *link_up_p)
1119 {
1120         struct niu_link_config *lp = &np->link_config;
1121         int err;
1122         int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1123         int supported, advertising, active_speed, active_duplex;
1124
1125         err = mii_read(np, np->phy_addr, MII_BMCR);
1126         if (unlikely(err < 0))
1127                 return err;
1128         bmcr = err;
1129
1130         err = mii_read(np, np->phy_addr, MII_BMSR);
1131         if (unlikely(err < 0))
1132                 return err;
1133         bmsr = err;
1134
1135         err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1136         if (unlikely(err < 0))
1137                 return err;
1138         advert = err;
1139
1140         err = mii_read(np, np->phy_addr, MII_LPA);
1141         if (unlikely(err < 0))
1142                 return err;
1143         lpa = err;
1144
1145         if (likely(bmsr & BMSR_ESTATEN)) {
1146                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1147                 if (unlikely(err < 0))
1148                         return err;
1149                 estatus = err;
1150
1151                 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1152                 if (unlikely(err < 0))
1153                         return err;
1154                 ctrl1000 = err;
1155
1156                 err = mii_read(np, np->phy_addr, MII_STAT1000);
1157                 if (unlikely(err < 0))
1158                         return err;
1159                 stat1000 = err;
1160         } else
1161                 estatus = ctrl1000 = stat1000 = 0;
1162
1163         supported = 0;
1164         if (bmsr & BMSR_ANEGCAPABLE)
1165                 supported |= SUPPORTED_Autoneg;
1166         if (bmsr & BMSR_10HALF)
1167                 supported |= SUPPORTED_10baseT_Half;
1168         if (bmsr & BMSR_10FULL)
1169                 supported |= SUPPORTED_10baseT_Full;
1170         if (bmsr & BMSR_100HALF)
1171                 supported |= SUPPORTED_100baseT_Half;
1172         if (bmsr & BMSR_100FULL)
1173                 supported |= SUPPORTED_100baseT_Full;
1174         if (estatus & ESTATUS_1000_THALF)
1175                 supported |= SUPPORTED_1000baseT_Half;
1176         if (estatus & ESTATUS_1000_TFULL)
1177                 supported |= SUPPORTED_1000baseT_Full;
1178         lp->supported = supported;
1179
1180         advertising = 0;
1181         if (advert & ADVERTISE_10HALF)
1182                 advertising |= ADVERTISED_10baseT_Half;
1183         if (advert & ADVERTISE_10FULL)
1184                 advertising |= ADVERTISED_10baseT_Full;
1185         if (advert & ADVERTISE_100HALF)
1186                 advertising |= ADVERTISED_100baseT_Half;
1187         if (advert & ADVERTISE_100FULL)
1188                 advertising |= ADVERTISED_100baseT_Full;
1189         if (ctrl1000 & ADVERTISE_1000HALF)
1190                 advertising |= ADVERTISED_1000baseT_Half;
1191         if (ctrl1000 & ADVERTISE_1000FULL)
1192                 advertising |= ADVERTISED_1000baseT_Full;
1193
1194         if (bmcr & BMCR_ANENABLE) {
1195                 int neg, neg1000;
1196
1197                 lp->active_autoneg = 1;
1198                 advertising |= ADVERTISED_Autoneg;
1199
1200                 neg = advert & lpa;
1201                 neg1000 = (ctrl1000 << 2) & stat1000;
1202
1203                 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1204                         active_speed = SPEED_1000;
1205                 else if (neg & LPA_100)
1206                         active_speed = SPEED_100;
1207                 else if (neg & (LPA_10HALF | LPA_10FULL))
1208                         active_speed = SPEED_10;
1209                 else
1210                         active_speed = SPEED_INVALID;
1211
1212                 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1213                         active_duplex = DUPLEX_FULL;
1214                 else if (active_speed != SPEED_INVALID)
1215                         active_duplex = DUPLEX_HALF;
1216                 else
1217                         active_duplex = DUPLEX_INVALID;
1218         } else {
1219                 lp->active_autoneg = 0;
1220
1221                 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1222                         active_speed = SPEED_1000;
1223                 else if (bmcr & BMCR_SPEED100)
1224                         active_speed = SPEED_100;
1225                 else
1226                         active_speed = SPEED_10;
1227
1228                 if (bmcr & BMCR_FULLDPLX)
1229                         active_duplex = DUPLEX_FULL;
1230                 else
1231                         active_duplex = DUPLEX_HALF;
1232         }
1233
1234         lp->active_advertising = advertising;
1235         lp->active_speed = active_speed;
1236         lp->active_duplex = active_duplex;
1237         *link_up_p = !!(bmsr & BMSR_LSTATUS);
1238
1239         return 0;
1240 }
1241
1242 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1243 {
1244         struct niu_link_config *lp = &np->link_config;
1245         u16 current_speed, bmsr;
1246         unsigned long flags;
1247         u8 current_duplex;
1248         int err, link_up;
1249
1250         link_up = 0;
1251         current_speed = SPEED_INVALID;
1252         current_duplex = DUPLEX_INVALID;
1253
1254         spin_lock_irqsave(&np->lock, flags);
1255
1256         err = -EINVAL;
1257
1258         err = mii_read(np, np->phy_addr, MII_BMSR);
1259         if (err < 0)
1260                 goto out;
1261
1262         bmsr = err;
1263         if (bmsr & BMSR_LSTATUS) {
1264                 u16 adv, lpa, common, estat;
1265
1266                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1267                 if (err < 0)
1268                         goto out;
1269                 adv = err;
1270
1271                 err = mii_read(np, np->phy_addr, MII_LPA);
1272                 if (err < 0)
1273                         goto out;
1274                 lpa = err;
1275
1276                 common = adv & lpa;
1277
1278                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1279                 if (err < 0)
1280                         goto out;
1281                 estat = err;
1282                 link_up = 1;
1283                 current_speed = SPEED_1000;
1284                 current_duplex = DUPLEX_FULL;
1285
1286         }
1287         lp->active_speed = current_speed;
1288         lp->active_duplex = current_duplex;
1289         err = 0;
1290
1291 out:
1292         spin_unlock_irqrestore(&np->lock, flags);
1293
1294         *link_up_p = link_up;
1295         return err;
1296 }
1297
1298 static int link_status_1g(struct niu *np, int *link_up_p)
1299 {
1300         struct niu_link_config *lp = &np->link_config;
1301         unsigned long flags;
1302         int err;
1303
1304         spin_lock_irqsave(&np->lock, flags);
1305
1306         err = link_status_mii(np, link_up_p);
1307         lp->supported |= SUPPORTED_TP;
1308         lp->active_advertising |= ADVERTISED_TP;
1309
1310         spin_unlock_irqrestore(&np->lock, flags);
1311         return err;
1312 }
1313
1314 static int bcm8704_reset(struct niu *np)
1315 {
1316         int err, limit;
1317
1318         err = mdio_read(np, np->phy_addr,
1319                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1320         if (err < 0)
1321                 return err;
1322         err |= BMCR_RESET;
1323         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1324                          MII_BMCR, err);
1325         if (err)
1326                 return err;
1327
1328         limit = 1000;
1329         while (--limit >= 0) {
1330                 err = mdio_read(np, np->phy_addr,
1331                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1332                 if (err < 0)
1333                         return err;
1334                 if (!(err & BMCR_RESET))
1335                         break;
1336         }
1337         if (limit < 0) {
1338                 dev_err(np->device, PFX "Port %u PHY will not reset "
1339                         "(bmcr=%04x)\n", np->port, (err & 0xffff));
1340                 return -ENODEV;
1341         }
1342         return 0;
1343 }
1344
1345 /* When written, certain PHY registers need to be read back twice
1346  * in order for the bits to settle properly.
1347  */
1348 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1349 {
1350         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1351         if (err < 0)
1352                 return err;
1353         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1354         if (err < 0)
1355                 return err;
1356         return 0;
1357 }
1358
1359 static int bcm8706_init_user_dev3(struct niu *np)
1360 {
1361         int err;
1362
1363
1364         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1365                         BCM8704_USER_OPT_DIGITAL_CTRL);
1366         if (err < 0)
1367                 return err;
1368         err &= ~USER_ODIG_CTRL_GPIOS;
1369         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1370         err |=  USER_ODIG_CTRL_RESV2;
1371         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1372                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1373         if (err)
1374                 return err;
1375
1376         mdelay(1000);
1377
1378         return 0;
1379 }
1380
1381 static int bcm8704_init_user_dev3(struct niu *np)
1382 {
1383         int err;
1384
1385         err = mdio_write(np, np->phy_addr,
1386                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1387                          (USER_CONTROL_OPTXRST_LVL |
1388                           USER_CONTROL_OPBIASFLT_LVL |
1389                           USER_CONTROL_OBTMPFLT_LVL |
1390                           USER_CONTROL_OPPRFLT_LVL |
1391                           USER_CONTROL_OPTXFLT_LVL |
1392                           USER_CONTROL_OPRXLOS_LVL |
1393                           USER_CONTROL_OPRXFLT_LVL |
1394                           USER_CONTROL_OPTXON_LVL |
1395                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1396         if (err)
1397                 return err;
1398
1399         err = mdio_write(np, np->phy_addr,
1400                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1401                          (USER_PMD_TX_CTL_XFP_CLKEN |
1402                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1403                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1404                           USER_PMD_TX_CTL_TSCK_LPWREN));
1405         if (err)
1406                 return err;
1407
1408         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1409         if (err)
1410                 return err;
1411         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1412         if (err)
1413                 return err;
1414
1415         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1416                         BCM8704_USER_OPT_DIGITAL_CTRL);
1417         if (err < 0)
1418                 return err;
1419         err &= ~USER_ODIG_CTRL_GPIOS;
1420         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1421         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1422                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1423         if (err)
1424                 return err;
1425
1426         mdelay(1000);
1427
1428         return 0;
1429 }
1430
1431 static int mrvl88x2011_act_led(struct niu *np, int val)
1432 {
1433         int     err;
1434
1435         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1436                 MRVL88X2011_LED_8_TO_11_CTL);
1437         if (err < 0)
1438                 return err;
1439
1440         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1441         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1442
1443         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1444                           MRVL88X2011_LED_8_TO_11_CTL, err);
1445 }
1446
1447 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1448 {
1449         int     err;
1450
1451         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1452                         MRVL88X2011_LED_BLINK_CTL);
1453         if (err >= 0) {
1454                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1455                 err |= (rate << 4);
1456
1457                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1458                                  MRVL88X2011_LED_BLINK_CTL, err);
1459         }
1460
1461         return err;
1462 }
1463
1464 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1465 {
1466         int     err;
1467
1468         /* Set LED functions */
1469         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1470         if (err)
1471                 return err;
1472
1473         /* led activity */
1474         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1475         if (err)
1476                 return err;
1477
1478         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1479                         MRVL88X2011_GENERAL_CTL);
1480         if (err < 0)
1481                 return err;
1482
1483         err |= MRVL88X2011_ENA_XFPREFCLK;
1484
1485         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1486                          MRVL88X2011_GENERAL_CTL, err);
1487         if (err < 0)
1488                 return err;
1489
1490         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1491                         MRVL88X2011_PMA_PMD_CTL_1);
1492         if (err < 0)
1493                 return err;
1494
1495         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1496                 err |= MRVL88X2011_LOOPBACK;
1497         else
1498                 err &= ~MRVL88X2011_LOOPBACK;
1499
1500         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1501                          MRVL88X2011_PMA_PMD_CTL_1, err);
1502         if (err < 0)
1503                 return err;
1504
1505         /* Enable PMD  */
1506         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1507                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1508 }
1509
1510
1511 static int xcvr_diag_bcm870x(struct niu *np)
1512 {
1513         u16 analog_stat0, tx_alarm_status;
1514         int err = 0;
1515
1516 #if 1
1517         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1518                         MII_STAT1000);
1519         if (err < 0)
1520                 return err;
1521         pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1522                 np->port, err);
1523
1524         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1525         if (err < 0)
1526                 return err;
1527         pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1528                 np->port, err);
1529
1530         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1531                         MII_NWAYTEST);
1532         if (err < 0)
1533                 return err;
1534         pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1535                 np->port, err);
1536 #endif
1537
1538         /* XXX dig this out it might not be so useful XXX */
1539         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1540                         BCM8704_USER_ANALOG_STATUS0);
1541         if (err < 0)
1542                 return err;
1543         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1544                         BCM8704_USER_ANALOG_STATUS0);
1545         if (err < 0)
1546                 return err;
1547         analog_stat0 = err;
1548
1549         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1550                         BCM8704_USER_TX_ALARM_STATUS);
1551         if (err < 0)
1552                 return err;
1553         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1554                         BCM8704_USER_TX_ALARM_STATUS);
1555         if (err < 0)
1556                 return err;
1557         tx_alarm_status = err;
1558
1559         if (analog_stat0 != 0x03fc) {
1560                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1561                         pr_info(PFX "Port %u cable not connected "
1562                                 "or bad cable.\n", np->port);
1563                 } else if (analog_stat0 == 0x639c) {
1564                         pr_info(PFX "Port %u optical module is bad "
1565                                 "or missing.\n", np->port);
1566                 }
1567         }
1568
1569         return 0;
1570 }
1571
1572 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1573 {
1574         struct niu_link_config *lp = &np->link_config;
1575         int err;
1576
1577         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1578                         MII_BMCR);
1579         if (err < 0)
1580                 return err;
1581
1582         err &= ~BMCR_LOOPBACK;
1583
1584         if (lp->loopback_mode == LOOPBACK_MAC)
1585                 err |= BMCR_LOOPBACK;
1586
1587         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1588                          MII_BMCR, err);
1589         if (err)
1590                 return err;
1591
1592         return 0;
1593 }
1594
1595 static int xcvr_init_10g_bcm8706(struct niu *np)
1596 {
1597         int err = 0;
1598         u64 val;
1599
1600         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1601             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1602                         return err;
1603
1604         val = nr64_mac(XMAC_CONFIG);
1605         val &= ~XMAC_CONFIG_LED_POLARITY;
1606         val |= XMAC_CONFIG_FORCE_LED_ON;
1607         nw64_mac(XMAC_CONFIG, val);
1608
1609         val = nr64(MIF_CONFIG);
1610         val |= MIF_CONFIG_INDIRECT_MODE;
1611         nw64(MIF_CONFIG, val);
1612
1613         err = bcm8704_reset(np);
1614         if (err)
1615                 return err;
1616
1617         err = xcvr_10g_set_lb_bcm870x(np);
1618         if (err)
1619                 return err;
1620
1621         err = bcm8706_init_user_dev3(np);
1622         if (err)
1623                 return err;
1624
1625         err = xcvr_diag_bcm870x(np);
1626         if (err)
1627                 return err;
1628
1629         return 0;
1630 }
1631
1632 static int xcvr_init_10g_bcm8704(struct niu *np)
1633 {
1634         int err;
1635
1636         err = bcm8704_reset(np);
1637         if (err)
1638                 return err;
1639
1640         err = bcm8704_init_user_dev3(np);
1641         if (err)
1642                 return err;
1643
1644         err = xcvr_10g_set_lb_bcm870x(np);
1645         if (err)
1646                 return err;
1647
1648         err =  xcvr_diag_bcm870x(np);
1649         if (err)
1650                 return err;
1651
1652         return 0;
1653 }
1654
1655 static int xcvr_init_10g(struct niu *np)
1656 {
1657         int phy_id, err;
1658         u64 val;
1659
1660         val = nr64_mac(XMAC_CONFIG);
1661         val &= ~XMAC_CONFIG_LED_POLARITY;
1662         val |= XMAC_CONFIG_FORCE_LED_ON;
1663         nw64_mac(XMAC_CONFIG, val);
1664
1665         /* XXX shared resource, lock parent XXX */
1666         val = nr64(MIF_CONFIG);
1667         val |= MIF_CONFIG_INDIRECT_MODE;
1668         nw64(MIF_CONFIG, val);
1669
1670         phy_id = phy_decode(np->parent->port_phy, np->port);
1671         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1672
1673         /* handle different phy types */
1674         switch (phy_id & NIU_PHY_ID_MASK) {
1675         case NIU_PHY_ID_MRVL88X2011:
1676                 err = xcvr_init_10g_mrvl88x2011(np);
1677                 break;
1678
1679         default: /* bcom 8704 */
1680                 err = xcvr_init_10g_bcm8704(np);
1681                 break;
1682         }
1683
1684         return 0;
1685 }
1686
1687 static int mii_reset(struct niu *np)
1688 {
1689         int limit, err;
1690
1691         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1692         if (err)
1693                 return err;
1694
1695         limit = 1000;
1696         while (--limit >= 0) {
1697                 udelay(500);
1698                 err = mii_read(np, np->phy_addr, MII_BMCR);
1699                 if (err < 0)
1700                         return err;
1701                 if (!(err & BMCR_RESET))
1702                         break;
1703         }
1704         if (limit < 0) {
1705                 dev_err(np->device, PFX "Port %u MII would not reset, "
1706                         "bmcr[%04x]\n", np->port, err);
1707                 return -ENODEV;
1708         }
1709
1710         return 0;
1711 }
1712
1713 static int xcvr_init_1g_rgmii(struct niu *np)
1714 {
1715         int err;
1716         u64 val;
1717         u16 bmcr, bmsr, estat;
1718
1719         val = nr64(MIF_CONFIG);
1720         val &= ~MIF_CONFIG_INDIRECT_MODE;
1721         nw64(MIF_CONFIG, val);
1722
1723         err = mii_reset(np);
1724         if (err)
1725                 return err;
1726
1727         err = mii_read(np, np->phy_addr, MII_BMSR);
1728         if (err < 0)
1729                 return err;
1730         bmsr = err;
1731
1732         estat = 0;
1733         if (bmsr & BMSR_ESTATEN) {
1734                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1735                 if (err < 0)
1736                         return err;
1737                 estat = err;
1738         }
1739
1740         bmcr = 0;
1741         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1742         if (err)
1743                 return err;
1744
1745         if (bmsr & BMSR_ESTATEN) {
1746                 u16 ctrl1000 = 0;
1747
1748                 if (estat & ESTATUS_1000_TFULL)
1749                         ctrl1000 |= ADVERTISE_1000FULL;
1750                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1751                 if (err)
1752                         return err;
1753         }
1754
1755         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1756
1757         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1758         if (err)
1759                 return err;
1760
1761         err = mii_read(np, np->phy_addr, MII_BMCR);
1762         if (err < 0)
1763                 return err;
1764         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1765
1766         err = mii_read(np, np->phy_addr, MII_BMSR);
1767         if (err < 0)
1768                 return err;
1769
1770         return 0;
1771 }
1772
1773 static int mii_init_common(struct niu *np)
1774 {
1775         struct niu_link_config *lp = &np->link_config;
1776         u16 bmcr, bmsr, adv, estat;
1777         int err;
1778
1779         err = mii_reset(np);
1780         if (err)
1781                 return err;
1782
1783         err = mii_read(np, np->phy_addr, MII_BMSR);
1784         if (err < 0)
1785                 return err;
1786         bmsr = err;
1787
1788         estat = 0;
1789         if (bmsr & BMSR_ESTATEN) {
1790                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1791                 if (err < 0)
1792                         return err;
1793                 estat = err;
1794         }
1795
1796         bmcr = 0;
1797         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1798         if (err)
1799                 return err;
1800
1801         if (lp->loopback_mode == LOOPBACK_MAC) {
1802                 bmcr |= BMCR_LOOPBACK;
1803                 if (lp->active_speed == SPEED_1000)
1804                         bmcr |= BMCR_SPEED1000;
1805                 if (lp->active_duplex == DUPLEX_FULL)
1806                         bmcr |= BMCR_FULLDPLX;
1807         }
1808
1809         if (lp->loopback_mode == LOOPBACK_PHY) {
1810                 u16 aux;
1811
1812                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1813                        BCM5464R_AUX_CTL_WRITE_1);
1814                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1815                 if (err)
1816                         return err;
1817         }
1818
1819         if (lp->autoneg) {
1820                 u16 ctrl1000;
1821
1822                 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1823                 if ((bmsr & BMSR_10HALF) &&
1824                         (lp->advertising & ADVERTISED_10baseT_Half))
1825                         adv |= ADVERTISE_10HALF;
1826                 if ((bmsr & BMSR_10FULL) &&
1827                         (lp->advertising & ADVERTISED_10baseT_Full))
1828                         adv |= ADVERTISE_10FULL;
1829                 if ((bmsr & BMSR_100HALF) &&
1830                         (lp->advertising & ADVERTISED_100baseT_Half))
1831                         adv |= ADVERTISE_100HALF;
1832                 if ((bmsr & BMSR_100FULL) &&
1833                         (lp->advertising & ADVERTISED_100baseT_Full))
1834                         adv |= ADVERTISE_100FULL;
1835                 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1836                 if (err)
1837                         return err;
1838
1839                 if (likely(bmsr & BMSR_ESTATEN)) {
1840                         ctrl1000 = 0;
1841                         if ((estat & ESTATUS_1000_THALF) &&
1842                                 (lp->advertising & ADVERTISED_1000baseT_Half))
1843                                 ctrl1000 |= ADVERTISE_1000HALF;
1844                         if ((estat & ESTATUS_1000_TFULL) &&
1845                                 (lp->advertising & ADVERTISED_1000baseT_Full))
1846                                 ctrl1000 |= ADVERTISE_1000FULL;
1847                         err = mii_write(np, np->phy_addr,
1848                                         MII_CTRL1000, ctrl1000);
1849                         if (err)
1850                                 return err;
1851                 }
1852
1853                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1854         } else {
1855                 /* !lp->autoneg */
1856                 int fulldpx;
1857
1858                 if (lp->duplex == DUPLEX_FULL) {
1859                         bmcr |= BMCR_FULLDPLX;
1860                         fulldpx = 1;
1861                 } else if (lp->duplex == DUPLEX_HALF)
1862                         fulldpx = 0;
1863                 else
1864                         return -EINVAL;
1865
1866                 if (lp->speed == SPEED_1000) {
1867                         /* if X-full requested while not supported, or
1868                            X-half requested while not supported... */
1869                         if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1870                                 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1871                                 return -EINVAL;
1872                         bmcr |= BMCR_SPEED1000;
1873                 } else if (lp->speed == SPEED_100) {
1874                         if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1875                                 (!fulldpx && !(bmsr & BMSR_100HALF)))
1876                                 return -EINVAL;
1877                         bmcr |= BMCR_SPEED100;
1878                 } else if (lp->speed == SPEED_10) {
1879                         if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1880                                 (!fulldpx && !(bmsr & BMSR_10HALF)))
1881                                 return -EINVAL;
1882                 } else
1883                         return -EINVAL;
1884         }
1885
1886         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1887         if (err)
1888                 return err;
1889
1890 #if 0
1891         err = mii_read(np, np->phy_addr, MII_BMCR);
1892         if (err < 0)
1893                 return err;
1894         bmcr = err;
1895
1896         err = mii_read(np, np->phy_addr, MII_BMSR);
1897         if (err < 0)
1898                 return err;
1899         bmsr = err;
1900
1901         pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1902                 np->port, bmcr, bmsr);
1903 #endif
1904
1905         return 0;
1906 }
1907
1908 static int xcvr_init_1g(struct niu *np)
1909 {
1910         u64 val;
1911
1912         /* XXX shared resource, lock parent XXX */
1913         val = nr64(MIF_CONFIG);
1914         val &= ~MIF_CONFIG_INDIRECT_MODE;
1915         nw64(MIF_CONFIG, val);
1916
1917         return mii_init_common(np);
1918 }
1919
1920 static int niu_xcvr_init(struct niu *np)
1921 {
1922         const struct niu_phy_ops *ops = np->phy_ops;
1923         int err;
1924
1925         err = 0;
1926         if (ops->xcvr_init)
1927                 err = ops->xcvr_init(np);
1928
1929         return err;
1930 }
1931
1932 static int niu_serdes_init(struct niu *np)
1933 {
1934         const struct niu_phy_ops *ops = np->phy_ops;
1935         int err;
1936
1937         err = 0;
1938         if (ops->serdes_init)
1939                 err = ops->serdes_init(np);
1940
1941         return err;
1942 }
1943
1944 static void niu_init_xif(struct niu *);
1945 static void niu_handle_led(struct niu *, int status);
1946
1947 static int niu_link_status_common(struct niu *np, int link_up)
1948 {
1949         struct niu_link_config *lp = &np->link_config;
1950         struct net_device *dev = np->dev;
1951         unsigned long flags;
1952
1953         if (!netif_carrier_ok(dev) && link_up) {
1954                 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1955                        dev->name,
1956                        (lp->active_speed == SPEED_10000 ?
1957                         "10Gb/sec" :
1958                         (lp->active_speed == SPEED_1000 ?
1959                          "1Gb/sec" :
1960                          (lp->active_speed == SPEED_100 ?
1961                           "100Mbit/sec" : "10Mbit/sec"))),
1962                        (lp->active_duplex == DUPLEX_FULL ?
1963                         "full" : "half"));
1964
1965                 spin_lock_irqsave(&np->lock, flags);
1966                 niu_init_xif(np);
1967                 niu_handle_led(np, 1);
1968                 spin_unlock_irqrestore(&np->lock, flags);
1969
1970                 netif_carrier_on(dev);
1971         } else if (netif_carrier_ok(dev) && !link_up) {
1972                 niuwarn(LINK, "%s: Link is down\n", dev->name);
1973                 spin_lock_irqsave(&np->lock, flags);
1974                 niu_handle_led(np, 0);
1975                 spin_unlock_irqrestore(&np->lock, flags);
1976                 netif_carrier_off(dev);
1977         }
1978
1979         return 0;
1980 }
1981
1982 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1983 {
1984         int err, link_up, pma_status, pcs_status;
1985
1986         link_up = 0;
1987
1988         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1989                         MRVL88X2011_10G_PMD_STATUS_2);
1990         if (err < 0)
1991                 goto out;
1992
1993         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1994         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1995                         MRVL88X2011_PMA_PMD_STATUS_1);
1996         if (err < 0)
1997                 goto out;
1998
1999         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2000
2001         /* Check PMC Register : 3.0001.2 == 1: read twice */
2002         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2003                         MRVL88X2011_PMA_PMD_STATUS_1);
2004         if (err < 0)
2005                 goto out;
2006
2007         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2008                         MRVL88X2011_PMA_PMD_STATUS_1);
2009         if (err < 0)
2010                 goto out;
2011
2012         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2013
2014         /* Check XGXS Register : 4.0018.[0-3,12] */
2015         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
2016                         MRVL88X2011_10G_XGXS_LANE_STAT);
2017         if (err < 0)
2018                 goto out;
2019
2020         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
2021                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
2022                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
2023                     0x800))
2024                 link_up = (pma_status && pcs_status) ? 1 : 0;
2025
2026         np->link_config.active_speed = SPEED_10000;
2027         np->link_config.active_duplex = DUPLEX_FULL;
2028         err = 0;
2029 out:
2030         mrvl88x2011_act_led(np, (link_up ?
2031                                  MRVL88X2011_LED_CTL_PCS_ACT :
2032                                  MRVL88X2011_LED_CTL_OFF));
2033
2034         *link_up_p = link_up;
2035         return err;
2036 }
2037
2038 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2039 {
2040         int err, link_up;
2041         link_up = 0;
2042
2043         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2044                         BCM8704_PMD_RCV_SIGDET);
2045         if (err < 0)
2046                 goto out;
2047         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2048                 err = 0;
2049                 goto out;
2050         }
2051
2052         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2053                         BCM8704_PCS_10G_R_STATUS);
2054         if (err < 0)
2055                 goto out;
2056
2057         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2058                 err = 0;
2059                 goto out;
2060         }
2061
2062         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2063                         BCM8704_PHYXS_XGXS_LANE_STAT);
2064         if (err < 0)
2065                 goto out;
2066         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2067                     PHYXS_XGXS_LANE_STAT_MAGIC |
2068                     PHYXS_XGXS_LANE_STAT_PATTEST |
2069                     PHYXS_XGXS_LANE_STAT_LANE3 |
2070                     PHYXS_XGXS_LANE_STAT_LANE2 |
2071                     PHYXS_XGXS_LANE_STAT_LANE1 |
2072                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2073                 err = 0;
2074                 np->link_config.active_speed = SPEED_INVALID;
2075                 np->link_config.active_duplex = DUPLEX_INVALID;
2076                 goto out;
2077         }
2078
2079         link_up = 1;
2080         np->link_config.active_speed = SPEED_10000;
2081         np->link_config.active_duplex = DUPLEX_FULL;
2082         err = 0;
2083
2084 out:
2085         *link_up_p = link_up;
2086         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
2087                 err = 0;
2088         return err;
2089 }
2090
2091 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2092 {
2093         int err, link_up;
2094
2095         link_up = 0;
2096
2097         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2098                         BCM8704_PMD_RCV_SIGDET);
2099         if (err < 0)
2100                 goto out;
2101         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2102                 err = 0;
2103                 goto out;
2104         }
2105
2106         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2107                         BCM8704_PCS_10G_R_STATUS);
2108         if (err < 0)
2109                 goto out;
2110         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2111                 err = 0;
2112                 goto out;
2113         }
2114
2115         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2116                         BCM8704_PHYXS_XGXS_LANE_STAT);
2117         if (err < 0)
2118                 goto out;
2119
2120         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2121                     PHYXS_XGXS_LANE_STAT_MAGIC |
2122                     PHYXS_XGXS_LANE_STAT_LANE3 |
2123                     PHYXS_XGXS_LANE_STAT_LANE2 |
2124                     PHYXS_XGXS_LANE_STAT_LANE1 |
2125                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2126                 err = 0;
2127                 goto out;
2128         }
2129
2130         link_up = 1;
2131         np->link_config.active_speed = SPEED_10000;
2132         np->link_config.active_duplex = DUPLEX_FULL;
2133         err = 0;
2134
2135 out:
2136         *link_up_p = link_up;
2137         return err;
2138 }
2139
2140 static int link_status_10g(struct niu *np, int *link_up_p)
2141 {
2142         unsigned long flags;
2143         int err = -EINVAL;
2144
2145         spin_lock_irqsave(&np->lock, flags);
2146
2147         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2148                 int phy_id;
2149
2150                 phy_id = phy_decode(np->parent->port_phy, np->port);
2151                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2152
2153                 /* handle different phy types */
2154                 switch (phy_id & NIU_PHY_ID_MASK) {
2155                 case NIU_PHY_ID_MRVL88X2011:
2156                         err = link_status_10g_mrvl(np, link_up_p);
2157                         break;
2158
2159                 default: /* bcom 8704 */
2160                         err = link_status_10g_bcom(np, link_up_p);
2161                         break;
2162                 }
2163         }
2164
2165         spin_unlock_irqrestore(&np->lock, flags);
2166
2167         return err;
2168 }
2169
2170 static int niu_10g_phy_present(struct niu *np)
2171 {
2172         u64 sig, mask, val;
2173
2174         sig = nr64(ESR_INT_SIGNALS);
2175         switch (np->port) {
2176         case 0:
2177                 mask = ESR_INT_SIGNALS_P0_BITS;
2178                 val = (ESR_INT_SRDY0_P0 |
2179                        ESR_INT_DET0_P0 |
2180                        ESR_INT_XSRDY_P0 |
2181                        ESR_INT_XDP_P0_CH3 |
2182                        ESR_INT_XDP_P0_CH2 |
2183                        ESR_INT_XDP_P0_CH1 |
2184                        ESR_INT_XDP_P0_CH0);
2185                 break;
2186
2187         case 1:
2188                 mask = ESR_INT_SIGNALS_P1_BITS;
2189                 val = (ESR_INT_SRDY0_P1 |
2190                        ESR_INT_DET0_P1 |
2191                        ESR_INT_XSRDY_P1 |
2192                        ESR_INT_XDP_P1_CH3 |
2193                        ESR_INT_XDP_P1_CH2 |
2194                        ESR_INT_XDP_P1_CH1 |
2195                        ESR_INT_XDP_P1_CH0);
2196                 break;
2197
2198         default:
2199                 return 0;
2200         }
2201
2202         if ((sig & mask) != val)
2203                 return 0;
2204         return 1;
2205 }
2206
2207 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2208 {
2209         unsigned long flags;
2210         int err = 0;
2211         int phy_present;
2212         int phy_present_prev;
2213
2214         spin_lock_irqsave(&np->lock, flags);
2215
2216         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2217                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2218                         1 : 0;
2219                 phy_present = niu_10g_phy_present(np);
2220                 if (phy_present != phy_present_prev) {
2221                         /* state change */
2222                         if (phy_present) {
2223                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2224                                 if (np->phy_ops->xcvr_init)
2225                                         err = np->phy_ops->xcvr_init(np);
2226                                 if (err) {
2227                                         /* debounce */
2228                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2229                                 }
2230                         } else {
2231                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2232                                 *link_up_p = 0;
2233                                 niuwarn(LINK, "%s: Hotplug PHY Removed\n",
2234                                         np->dev->name);
2235                         }
2236                 }
2237                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT)
2238                         err = link_status_10g_bcm8706(np, link_up_p);
2239         }
2240
2241         spin_unlock_irqrestore(&np->lock, flags);
2242
2243         return err;
2244 }
2245
2246 static int niu_link_status(struct niu *np, int *link_up_p)
2247 {
2248         const struct niu_phy_ops *ops = np->phy_ops;
2249         int err;
2250
2251         err = 0;
2252         if (ops->link_status)
2253                 err = ops->link_status(np, link_up_p);
2254
2255         return err;
2256 }
2257
2258 static void niu_timer(unsigned long __opaque)
2259 {
2260         struct niu *np = (struct niu *) __opaque;
2261         unsigned long off;
2262         int err, link_up;
2263
2264         err = niu_link_status(np, &link_up);
2265         if (!err)
2266                 niu_link_status_common(np, link_up);
2267
2268         if (netif_carrier_ok(np->dev))
2269                 off = 5 * HZ;
2270         else
2271                 off = 1 * HZ;
2272         np->timer.expires = jiffies + off;
2273
2274         add_timer(&np->timer);
2275 }
2276
2277 static const struct niu_phy_ops phy_ops_10g_serdes = {
2278         .serdes_init            = serdes_init_10g_serdes,
2279         .link_status            = link_status_10g_serdes,
2280 };
2281
2282 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2283         .serdes_init            = serdes_init_niu_10g_serdes,
2284         .link_status            = link_status_10g_serdes,
2285 };
2286
2287 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2288         .serdes_init            = serdes_init_niu_1g_serdes,
2289         .link_status            = link_status_1g_serdes,
2290 };
2291
2292 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2293         .xcvr_init              = xcvr_init_1g_rgmii,
2294         .link_status            = link_status_1g_rgmii,
2295 };
2296
2297 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2298         .serdes_init            = serdes_init_niu_10g_fiber,
2299         .xcvr_init              = xcvr_init_10g,
2300         .link_status            = link_status_10g,
2301 };
2302
2303 static const struct niu_phy_ops phy_ops_10g_fiber = {
2304         .serdes_init            = serdes_init_10g,
2305         .xcvr_init              = xcvr_init_10g,
2306         .link_status            = link_status_10g,
2307 };
2308
2309 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2310         .serdes_init            = serdes_init_10g,
2311         .xcvr_init              = xcvr_init_10g_bcm8706,
2312         .link_status            = link_status_10g_hotplug,
2313 };
2314
2315 static const struct niu_phy_ops phy_ops_10g_copper = {
2316         .serdes_init            = serdes_init_10g,
2317         .link_status            = link_status_10g, /* XXX */
2318 };
2319
2320 static const struct niu_phy_ops phy_ops_1g_fiber = {
2321         .serdes_init            = serdes_init_1g,
2322         .xcvr_init              = xcvr_init_1g,
2323         .link_status            = link_status_1g,
2324 };
2325
2326 static const struct niu_phy_ops phy_ops_1g_copper = {
2327         .xcvr_init              = xcvr_init_1g,
2328         .link_status            = link_status_1g,
2329 };
2330
2331 struct niu_phy_template {
2332         const struct niu_phy_ops        *ops;
2333         u32                             phy_addr_base;
2334 };
2335
2336 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2337         .ops            = &phy_ops_10g_fiber_niu,
2338         .phy_addr_base  = 16,
2339 };
2340
2341 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2342         .ops            = &phy_ops_10g_serdes_niu,
2343         .phy_addr_base  = 0,
2344 };
2345
2346 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2347         .ops            = &phy_ops_1g_serdes_niu,
2348         .phy_addr_base  = 0,
2349 };
2350
2351 static const struct niu_phy_template phy_template_10g_fiber = {
2352         .ops            = &phy_ops_10g_fiber,
2353         .phy_addr_base  = 8,
2354 };
2355
2356 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2357         .ops            = &phy_ops_10g_fiber_hotplug,
2358         .phy_addr_base  = 8,
2359 };
2360
2361 static const struct niu_phy_template phy_template_10g_copper = {
2362         .ops            = &phy_ops_10g_copper,
2363         .phy_addr_base  = 10,
2364 };
2365
2366 static const struct niu_phy_template phy_template_1g_fiber = {
2367         .ops            = &phy_ops_1g_fiber,
2368         .phy_addr_base  = 0,
2369 };
2370
2371 static const struct niu_phy_template phy_template_1g_copper = {
2372         .ops            = &phy_ops_1g_copper,
2373         .phy_addr_base  = 0,
2374 };
2375
2376 static const struct niu_phy_template phy_template_1g_rgmii = {
2377         .ops            = &phy_ops_1g_rgmii,
2378         .phy_addr_base  = 0,
2379 };
2380
2381 static const struct niu_phy_template phy_template_10g_serdes = {
2382         .ops            = &phy_ops_10g_serdes,
2383         .phy_addr_base  = 0,
2384 };
2385
2386 static int niu_atca_port_num[4] = {
2387         0, 0,  11, 10
2388 };
2389
2390 static int serdes_init_10g_serdes(struct niu *np)
2391 {
2392         struct niu_link_config *lp = &np->link_config;
2393         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2394         u64 ctrl_val, test_cfg_val, sig, mask, val;
2395         u64 reset_val;
2396
2397         switch (np->port) {
2398         case 0:
2399                 reset_val =  ENET_SERDES_RESET_0;
2400                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2401                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2402                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2403                 break;
2404         case 1:
2405                 reset_val =  ENET_SERDES_RESET_1;
2406                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2407                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2408                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2409                 break;
2410
2411         default:
2412                 return -EINVAL;
2413         }
2414         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2415                     ENET_SERDES_CTRL_SDET_1 |
2416                     ENET_SERDES_CTRL_SDET_2 |
2417                     ENET_SERDES_CTRL_SDET_3 |
2418                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2419                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2420                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2421                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2422                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2423                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2424                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2425                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2426         test_cfg_val = 0;
2427
2428         if (lp->loopback_mode == LOOPBACK_PHY) {
2429                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2430                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2431                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2432                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2433                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2434                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2435                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2436                                   ENET_SERDES_TEST_MD_3_SHIFT));
2437         }
2438
2439         esr_reset(np);
2440         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2441         nw64(ctrl_reg, ctrl_val);
2442         nw64(test_cfg_reg, test_cfg_val);
2443
2444         /* Initialize all 4 lanes of the SERDES.  */
2445         for (i = 0; i < 4; i++) {
2446                 u32 rxtx_ctrl, glue0;
2447                 int err;
2448
2449                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2450                 if (err)
2451                         return err;
2452                 err = esr_read_glue0(np, i, &glue0);
2453                 if (err)
2454                         return err;
2455
2456                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2457                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2458                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2459
2460                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2461                            ESR_GLUE_CTRL0_THCNT |
2462                            ESR_GLUE_CTRL0_BLTIME);
2463                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2464                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2465                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2466                           (BLTIME_300_CYCLES <<
2467                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2468
2469                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2470                 if (err)
2471                         return err;
2472                 err = esr_write_glue0(np, i, glue0);
2473                 if (err)
2474                         return err;
2475         }
2476
2477
2478         sig = nr64(ESR_INT_SIGNALS);
2479         switch (np->port) {
2480         case 0:
2481                 mask = ESR_INT_SIGNALS_P0_BITS;
2482                 val = (ESR_INT_SRDY0_P0 |
2483                        ESR_INT_DET0_P0 |
2484                        ESR_INT_XSRDY_P0 |
2485                        ESR_INT_XDP_P0_CH3 |
2486                        ESR_INT_XDP_P0_CH2 |
2487                        ESR_INT_XDP_P0_CH1 |
2488                        ESR_INT_XDP_P0_CH0);
2489                 break;
2490
2491         case 1:
2492                 mask = ESR_INT_SIGNALS_P1_BITS;
2493                 val = (ESR_INT_SRDY0_P1 |
2494                        ESR_INT_DET0_P1 |
2495                        ESR_INT_XSRDY_P1 |
2496                        ESR_INT_XDP_P1_CH3 |
2497                        ESR_INT_XDP_P1_CH2 |
2498                        ESR_INT_XDP_P1_CH1 |
2499                        ESR_INT_XDP_P1_CH0);
2500                 break;
2501
2502         default:
2503                 return -EINVAL;
2504         }
2505
2506         if ((sig & mask) != val) {
2507                 int err;
2508                 err = serdes_init_1g_serdes(np);
2509                 if (!err) {
2510                         np->flags &= ~NIU_FLAGS_10G;
2511                         np->mac_xcvr = MAC_XCVR_PCS;
2512                 }  else {
2513                         dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
2514                          np->port);
2515                         return -ENODEV;
2516                 }
2517         }
2518
2519         return 0;
2520 }
2521
2522 static int niu_determine_phy_disposition(struct niu *np)
2523 {
2524         struct niu_parent *parent = np->parent;
2525         u8 plat_type = parent->plat_type;
2526         const struct niu_phy_template *tp;
2527         u32 phy_addr_off = 0;
2528
2529         if (plat_type == PLAT_TYPE_NIU) {
2530                 switch (np->flags &
2531                         (NIU_FLAGS_10G |
2532                          NIU_FLAGS_FIBER |
2533                          NIU_FLAGS_XCVR_SERDES)) {
2534                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2535                         /* 10G Serdes */
2536                         tp = &phy_template_niu_10g_serdes;
2537                         break;
2538                 case NIU_FLAGS_XCVR_SERDES:
2539                         /* 1G Serdes */
2540                         tp = &phy_template_niu_1g_serdes;
2541                         break;
2542                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2543                         /* 10G Fiber */
2544                 default:
2545                         tp = &phy_template_niu_10g_fiber;
2546                         phy_addr_off += np->port;
2547                         break;
2548                 }
2549         } else {
2550                 switch (np->flags &
2551                         (NIU_FLAGS_10G |
2552                          NIU_FLAGS_FIBER |
2553                          NIU_FLAGS_XCVR_SERDES)) {
2554                 case 0:
2555                         /* 1G copper */
2556                         tp = &phy_template_1g_copper;
2557                         if (plat_type == PLAT_TYPE_VF_P0)
2558                                 phy_addr_off = 10;
2559                         else if (plat_type == PLAT_TYPE_VF_P1)
2560                                 phy_addr_off = 26;
2561
2562                         phy_addr_off += (np->port ^ 0x3);
2563                         break;
2564
2565                 case NIU_FLAGS_10G:
2566                         /* 10G copper */
2567                         tp = &phy_template_10g_copper;
2568                         break;
2569
2570                 case NIU_FLAGS_FIBER:
2571                         /* 1G fiber */
2572                         tp = &phy_template_1g_fiber;
2573                         break;
2574
2575                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2576                         /* 10G fiber */
2577                         tp = &phy_template_10g_fiber;
2578                         if (plat_type == PLAT_TYPE_VF_P0 ||
2579                             plat_type == PLAT_TYPE_VF_P1)
2580                                 phy_addr_off = 8;
2581                         phy_addr_off += np->port;
2582                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2583                                 tp = &phy_template_10g_fiber_hotplug;
2584                                 if (np->port == 0)
2585                                         phy_addr_off = 8;
2586                                 if (np->port == 1)
2587                                         phy_addr_off = 12;
2588                         }
2589                         break;
2590
2591                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2592                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2593                 case NIU_FLAGS_XCVR_SERDES:
2594                         switch(np->port) {
2595                         case 0:
2596                         case 1:
2597                                 tp = &phy_template_10g_serdes;
2598                                 break;
2599                         case 2:
2600                         case 3:
2601                                 tp = &phy_template_1g_rgmii;
2602                                 break;
2603                         default:
2604                                 return -EINVAL;
2605                                 break;
2606                         }
2607                         phy_addr_off = niu_atca_port_num[np->port];
2608                         break;
2609
2610                 default:
2611                         return -EINVAL;
2612                 }
2613         }
2614
2615         np->phy_ops = tp->ops;
2616         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2617
2618         return 0;
2619 }
2620
2621 static int niu_init_link(struct niu *np)
2622 {
2623         struct niu_parent *parent = np->parent;
2624         int err, ignore;
2625
2626         if (parent->plat_type == PLAT_TYPE_NIU) {
2627                 err = niu_xcvr_init(np);
2628                 if (err)
2629                         return err;
2630                 msleep(200);
2631         }
2632         err = niu_serdes_init(np);
2633         if (err)
2634                 return err;
2635         msleep(200);
2636         err = niu_xcvr_init(np);
2637         if (!err)
2638                 niu_link_status(np, &ignore);
2639         return 0;
2640 }
2641
2642 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2643 {
2644         u16 reg0 = addr[4] << 8 | addr[5];
2645         u16 reg1 = addr[2] << 8 | addr[3];
2646         u16 reg2 = addr[0] << 8 | addr[1];
2647
2648         if (np->flags & NIU_FLAGS_XMAC) {
2649                 nw64_mac(XMAC_ADDR0, reg0);
2650                 nw64_mac(XMAC_ADDR1, reg1);
2651                 nw64_mac(XMAC_ADDR2, reg2);
2652         } else {
2653                 nw64_mac(BMAC_ADDR0, reg0);
2654                 nw64_mac(BMAC_ADDR1, reg1);
2655                 nw64_mac(BMAC_ADDR2, reg2);
2656         }
2657 }
2658
2659 static int niu_num_alt_addr(struct niu *np)
2660 {
2661         if (np->flags & NIU_FLAGS_XMAC)
2662                 return XMAC_NUM_ALT_ADDR;
2663         else
2664                 return BMAC_NUM_ALT_ADDR;
2665 }
2666
2667 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2668 {
2669         u16 reg0 = addr[4] << 8 | addr[5];
2670         u16 reg1 = addr[2] << 8 | addr[3];
2671         u16 reg2 = addr[0] << 8 | addr[1];
2672
2673         if (index >= niu_num_alt_addr(np))
2674                 return -EINVAL;
2675
2676         if (np->flags & NIU_FLAGS_XMAC) {
2677                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2678                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2679                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2680         } else {
2681                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2682                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2683                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2684         }
2685
2686         return 0;
2687 }
2688
2689 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2690 {
2691         unsigned long reg;
2692         u64 val, mask;
2693
2694         if (index >= niu_num_alt_addr(np))
2695                 return -EINVAL;
2696
2697         if (np->flags & NIU_FLAGS_XMAC) {
2698                 reg = XMAC_ADDR_CMPEN;
2699                 mask = 1 << index;
2700         } else {
2701                 reg = BMAC_ADDR_CMPEN;
2702                 mask = 1 << (index + 1);
2703         }
2704
2705         val = nr64_mac(reg);
2706         if (on)
2707                 val |= mask;
2708         else
2709                 val &= ~mask;
2710         nw64_mac(reg, val);
2711
2712         return 0;
2713 }
2714
2715 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2716                                    int num, int mac_pref)
2717 {
2718         u64 val = nr64_mac(reg);
2719         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2720         val |= num;
2721         if (mac_pref)
2722                 val |= HOST_INFO_MPR;
2723         nw64_mac(reg, val);
2724 }
2725
2726 static int __set_rdc_table_num(struct niu *np,
2727                                int xmac_index, int bmac_index,
2728                                int rdc_table_num, int mac_pref)
2729 {
2730         unsigned long reg;
2731
2732         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2733                 return -EINVAL;
2734         if (np->flags & NIU_FLAGS_XMAC)
2735                 reg = XMAC_HOST_INFO(xmac_index);
2736         else
2737                 reg = BMAC_HOST_INFO(bmac_index);
2738         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2739         return 0;
2740 }
2741
2742 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2743                                          int mac_pref)
2744 {
2745         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2746 }
2747
2748 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2749                                            int mac_pref)
2750 {
2751         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2752 }
2753
2754 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2755                                      int table_num, int mac_pref)
2756 {
2757         if (idx >= niu_num_alt_addr(np))
2758                 return -EINVAL;
2759         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2760 }
2761
2762 static u64 vlan_entry_set_parity(u64 reg_val)
2763 {
2764         u64 port01_mask;
2765         u64 port23_mask;
2766
2767         port01_mask = 0x00ff;
2768         port23_mask = 0xff00;
2769
2770         if (hweight64(reg_val & port01_mask) & 1)
2771                 reg_val |= ENET_VLAN_TBL_PARITY0;
2772         else
2773                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2774
2775         if (hweight64(reg_val & port23_mask) & 1)
2776                 reg_val |= ENET_VLAN_TBL_PARITY1;
2777         else
2778                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2779
2780         return reg_val;
2781 }
2782
2783 static void vlan_tbl_write(struct niu *np, unsigned long index,
2784                            int port, int vpr, int rdc_table)
2785 {
2786         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2787
2788         reg_val &= ~((ENET_VLAN_TBL_VPR |
2789                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2790                      ENET_VLAN_TBL_SHIFT(port));
2791         if (vpr)
2792                 reg_val |= (ENET_VLAN_TBL_VPR <<
2793                             ENET_VLAN_TBL_SHIFT(port));
2794         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2795
2796         reg_val = vlan_entry_set_parity(reg_val);
2797
2798         nw64(ENET_VLAN_TBL(index), reg_val);
2799 }
2800
2801 static void vlan_tbl_clear(struct niu *np)
2802 {
2803         int i;
2804
2805         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2806                 nw64(ENET_VLAN_TBL(i), 0);
2807 }
2808
2809 static int tcam_wait_bit(struct niu *np, u64 bit)
2810 {
2811         int limit = 1000;
2812
2813         while (--limit > 0) {
2814                 if (nr64(TCAM_CTL) & bit)
2815                         break;
2816                 udelay(1);
2817         }
2818         if (limit < 0)
2819                 return -ENODEV;
2820
2821         return 0;
2822 }
2823
2824 static int tcam_flush(struct niu *np, int index)
2825 {
2826         nw64(TCAM_KEY_0, 0x00);
2827         nw64(TCAM_KEY_MASK_0, 0xff);
2828         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2829
2830         return tcam_wait_bit(np, TCAM_CTL_STAT);
2831 }
2832
2833 #if 0
2834 static int tcam_read(struct niu *np, int index,
2835                      u64 *key, u64 *mask)
2836 {
2837         int err;
2838
2839         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2840         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2841         if (!err) {
2842                 key[0] = nr64(TCAM_KEY_0);
2843                 key[1] = nr64(TCAM_KEY_1);
2844                 key[2] = nr64(TCAM_KEY_2);
2845                 key[3] = nr64(TCAM_KEY_3);
2846                 mask[0] = nr64(TCAM_KEY_MASK_0);
2847                 mask[1] = nr64(TCAM_KEY_MASK_1);
2848                 mask[2] = nr64(TCAM_KEY_MASK_2);
2849                 mask[3] = nr64(TCAM_KEY_MASK_3);
2850         }
2851         return err;
2852 }
2853 #endif
2854
2855 static int tcam_write(struct niu *np, int index,
2856                       u64 *key, u64 *mask)
2857 {
2858         nw64(TCAM_KEY_0, key[0]);
2859         nw64(TCAM_KEY_1, key[1]);
2860         nw64(TCAM_KEY_2, key[2]);
2861         nw64(TCAM_KEY_3, key[3]);
2862         nw64(TCAM_KEY_MASK_0, mask[0]);
2863         nw64(TCAM_KEY_MASK_1, mask[1]);
2864         nw64(TCAM_KEY_MASK_2, mask[2]);
2865         nw64(TCAM_KEY_MASK_3, mask[3]);
2866         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2867
2868         return tcam_wait_bit(np, TCAM_CTL_STAT);
2869 }
2870
2871 #if 0
2872 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2873 {
2874         int err;
2875
2876         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2877         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2878         if (!err)
2879                 *data = nr64(TCAM_KEY_1);
2880
2881         return err;
2882 }
2883 #endif
2884
2885 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2886 {
2887         nw64(TCAM_KEY_1, assoc_data);
2888         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2889
2890         return tcam_wait_bit(np, TCAM_CTL_STAT);
2891 }
2892
2893 static void tcam_enable(struct niu *np, int on)
2894 {
2895         u64 val = nr64(FFLP_CFG_1);
2896
2897         if (on)
2898                 val &= ~FFLP_CFG_1_TCAM_DIS;
2899         else
2900                 val |= FFLP_CFG_1_TCAM_DIS;
2901         nw64(FFLP_CFG_1, val);
2902 }
2903
2904 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2905 {
2906         u64 val = nr64(FFLP_CFG_1);
2907
2908         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2909                  FFLP_CFG_1_CAMLAT |
2910                  FFLP_CFG_1_CAMRATIO);
2911         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2912         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2913         nw64(FFLP_CFG_1, val);
2914
2915         val = nr64(FFLP_CFG_1);
2916         val |= FFLP_CFG_1_FFLPINITDONE;
2917         nw64(FFLP_CFG_1, val);
2918 }
2919
2920 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2921                                       int on)
2922 {
2923         unsigned long reg;
2924         u64 val;
2925
2926         if (class < CLASS_CODE_ETHERTYPE1 ||
2927             class > CLASS_CODE_ETHERTYPE2)
2928                 return -EINVAL;
2929
2930         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2931         val = nr64(reg);
2932         if (on)
2933                 val |= L2_CLS_VLD;
2934         else
2935                 val &= ~L2_CLS_VLD;
2936         nw64(reg, val);
2937
2938         return 0;
2939 }
2940
2941 #if 0
2942 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2943                                    u64 ether_type)
2944 {
2945         unsigned long reg;
2946         u64 val;
2947
2948         if (class < CLASS_CODE_ETHERTYPE1 ||
2949             class > CLASS_CODE_ETHERTYPE2 ||
2950             (ether_type & ~(u64)0xffff) != 0)
2951                 return -EINVAL;
2952
2953         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2954         val = nr64(reg);
2955         val &= ~L2_CLS_ETYPE;
2956         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2957         nw64(reg, val);
2958
2959         return 0;
2960 }
2961 #endif
2962
2963 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2964                                      int on)
2965 {
2966         unsigned long reg;
2967         u64 val;
2968
2969         if (class < CLASS_CODE_USER_PROG1 ||
2970             class > CLASS_CODE_USER_PROG4)
2971                 return -EINVAL;
2972
2973         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2974         val = nr64(reg);
2975         if (on)
2976                 val |= L3_CLS_VALID;
2977         else
2978                 val &= ~L3_CLS_VALID;
2979         nw64(reg, val);
2980
2981         return 0;
2982 }
2983
2984 #if 0
2985 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2986                                   int ipv6, u64 protocol_id,
2987                                   u64 tos_mask, u64 tos_val)
2988 {
2989         unsigned long reg;
2990         u64 val;
2991
2992         if (class < CLASS_CODE_USER_PROG1 ||
2993             class > CLASS_CODE_USER_PROG4 ||
2994             (protocol_id & ~(u64)0xff) != 0 ||
2995             (tos_mask & ~(u64)0xff) != 0 ||
2996             (tos_val & ~(u64)0xff) != 0)
2997                 return -EINVAL;
2998
2999         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
3000         val = nr64(reg);
3001         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
3002                  L3_CLS_TOSMASK | L3_CLS_TOS);
3003         if (ipv6)
3004                 val |= L3_CLS_IPVER;
3005         val |= (protocol_id << L3_CLS_PID_SHIFT);
3006         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3007         val |= (tos_val << L3_CLS_TOS_SHIFT);
3008         nw64(reg, val);
3009
3010         return 0;
3011 }
3012 #endif
3013
3014 static int tcam_early_init(struct niu *np)
3015 {
3016         unsigned long i;
3017         int err;
3018
3019         tcam_enable(np, 0);
3020         tcam_set_lat_and_ratio(np,
3021                                DEFAULT_TCAM_LATENCY,
3022                                DEFAULT_TCAM_ACCESS_RATIO);
3023         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3024                 err = tcam_user_eth_class_enable(np, i, 0);
3025                 if (err)
3026                         return err;
3027         }
3028         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3029                 err = tcam_user_ip_class_enable(np, i, 0);
3030                 if (err)
3031                         return err;
3032         }
3033
3034         return 0;
3035 }
3036
3037 static int tcam_flush_all(struct niu *np)
3038 {
3039         unsigned long i;
3040
3041         for (i = 0; i < np->parent->tcam_num_entries; i++) {
3042                 int err = tcam_flush(np, i);
3043                 if (err)
3044                         return err;
3045         }
3046         return 0;
3047 }
3048
3049 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3050 {
3051         return ((u64)index | (num_entries == 1 ?
3052                               HASH_TBL_ADDR_AUTOINC : 0));
3053 }
3054
3055 #if 0
3056 static int hash_read(struct niu *np, unsigned long partition,
3057                      unsigned long index, unsigned long num_entries,
3058                      u64 *data)
3059 {
3060         u64 val = hash_addr_regval(index, num_entries);
3061         unsigned long i;
3062
3063         if (partition >= FCRAM_NUM_PARTITIONS ||
3064             index + num_entries > FCRAM_SIZE)
3065                 return -EINVAL;
3066
3067         nw64(HASH_TBL_ADDR(partition), val);
3068         for (i = 0; i < num_entries; i++)
3069                 data[i] = nr64(HASH_TBL_DATA(partition));
3070
3071         return 0;
3072 }
3073 #endif
3074
3075 static int hash_write(struct niu *np, unsigned long partition,
3076                       unsigned long index, unsigned long num_entries,
3077                       u64 *data)
3078 {
3079         u64 val = hash_addr_regval(index, num_entries);
3080         unsigned long i;
3081
3082         if (partition >= FCRAM_NUM_PARTITIONS ||
3083             index + (num_entries * 8) > FCRAM_SIZE)
3084                 return -EINVAL;
3085
3086         nw64(HASH_TBL_ADDR(partition), val);
3087         for (i = 0; i < num_entries; i++)
3088                 nw64(HASH_TBL_DATA(partition), data[i]);
3089
3090         return 0;
3091 }
3092
3093 static void fflp_reset(struct niu *np)
3094 {
3095         u64 val;
3096
3097         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3098         udelay(10);
3099         nw64(FFLP_CFG_1, 0);
3100
3101         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3102         nw64(FFLP_CFG_1, val);
3103 }
3104
3105 static void fflp_set_timings(struct niu *np)
3106 {
3107         u64 val = nr64(FFLP_CFG_1);
3108
3109         val &= ~FFLP_CFG_1_FFLPINITDONE;
3110         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3111         nw64(FFLP_CFG_1, val);
3112
3113         val = nr64(FFLP_CFG_1);
3114         val |= FFLP_CFG_1_FFLPINITDONE;
3115         nw64(FFLP_CFG_1, val);
3116
3117         val = nr64(FCRAM_REF_TMR);
3118         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3119         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3120         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3121         nw64(FCRAM_REF_TMR, val);
3122 }
3123
3124 static int fflp_set_partition(struct niu *np, u64 partition,
3125                               u64 mask, u64 base, int enable)
3126 {
3127         unsigned long reg;
3128         u64 val;
3129
3130         if (partition >= FCRAM_NUM_PARTITIONS ||
3131             (mask & ~(u64)0x1f) != 0 ||
3132             (base & ~(u64)0x1f) != 0)
3133                 return -EINVAL;
3134
3135         reg = FLW_PRT_SEL(partition);
3136
3137         val = nr64(reg);
3138         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3139         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3140         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3141         if (enable)
3142                 val |= FLW_PRT_SEL_EXT;
3143         nw64(reg, val);
3144
3145         return 0;
3146 }
3147
3148 static int fflp_disable_all_partitions(struct niu *np)
3149 {
3150         unsigned long i;
3151
3152         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3153                 int err = fflp_set_partition(np, 0, 0, 0, 0);
3154                 if (err)
3155                         return err;
3156         }
3157         return 0;
3158 }
3159
3160 static void fflp_llcsnap_enable(struct niu *np, int on)
3161 {
3162         u64 val = nr64(FFLP_CFG_1);
3163
3164         if (on)
3165                 val |= FFLP_CFG_1_LLCSNAP;
3166         else
3167                 val &= ~FFLP_CFG_1_LLCSNAP;
3168         nw64(FFLP_CFG_1, val);
3169 }
3170
3171 static void fflp_errors_enable(struct niu *np, int on)
3172 {
3173         u64 val = nr64(FFLP_CFG_1);
3174
3175         if (on)
3176                 val &= ~FFLP_CFG_1_ERRORDIS;
3177         else
3178                 val |= FFLP_CFG_1_ERRORDIS;
3179         nw64(FFLP_CFG_1, val);
3180 }
3181
3182 static int fflp_hash_clear(struct niu *np)
3183 {
3184         struct fcram_hash_ipv4 ent;
3185         unsigned long i;
3186
3187         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
3188         memset(&ent, 0, sizeof(ent));
3189         ent.header = HASH_HEADER_EXT;
3190
3191         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3192                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3193                 if (err)
3194                         return err;
3195         }
3196         return 0;
3197 }
3198
3199 static int fflp_early_init(struct niu *np)
3200 {
3201         struct niu_parent *parent;
3202         unsigned long flags;
3203         int err;
3204
3205         niu_lock_parent(np, flags);
3206
3207         parent = np->parent;
3208         err = 0;
3209         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3210                 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
3211                        np->port);
3212                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3213                         fflp_reset(np);
3214                         fflp_set_timings(np);
3215                         err = fflp_disable_all_partitions(np);
3216                         if (err) {
3217                                 niudbg(PROBE, "fflp_disable_all_partitions "
3218                                        "failed, err=%d\n", err);
3219                                 goto out;
3220                         }
3221                 }
3222
3223                 err = tcam_early_init(np);
3224                 if (err) {
3225                         niudbg(PROBE, "tcam_early_init failed, err=%d\n",
3226                                err);
3227                         goto out;
3228                 }
3229                 fflp_llcsnap_enable(np, 1);
3230                 fflp_errors_enable(np, 0);
3231                 nw64(H1POLY, 0);
3232                 nw64(H2POLY, 0);
3233
3234                 err = tcam_flush_all(np);
3235                 if (err) {
3236                         niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
3237                                err);
3238                         goto out;
3239                 }
3240                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3241                         err = fflp_hash_clear(np);
3242                         if (err) {
3243                                 niudbg(PROBE, "fflp_hash_clear failed, "
3244                                        "err=%d\n", err);
3245                                 goto out;
3246                         }
3247                 }
3248
3249                 vlan_tbl_clear(np);
3250
3251                 niudbg(PROBE, "fflp_early_init: Success\n");
3252                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3253         }
3254 out:
3255         niu_unlock_parent(np, flags);
3256         return err;
3257 }
3258
3259 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3260 {
3261         if (class_code < CLASS_CODE_USER_PROG1 ||
3262             class_code > CLASS_CODE_SCTP_IPV6)
3263                 return -EINVAL;
3264
3265         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3266         return 0;
3267 }
3268
3269 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3270 {
3271         if (class_code < CLASS_CODE_USER_PROG1 ||
3272             class_code > CLASS_CODE_SCTP_IPV6)
3273                 return -EINVAL;
3274
3275         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3276         return 0;
3277 }
3278
3279 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3280                               u32 offset, u32 size)
3281 {
3282         int i = skb_shinfo(skb)->nr_frags;
3283         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3284
3285         frag->page = page;
3286         frag->page_offset = offset;
3287         frag->size = size;
3288
3289         skb->len += size;
3290         skb->data_len += size;
3291         skb->truesize += size;
3292
3293         skb_shinfo(skb)->nr_frags = i + 1;
3294 }
3295
3296 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3297 {
3298         a >>= PAGE_SHIFT;
3299         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3300
3301         return (a & (MAX_RBR_RING_SIZE - 1));
3302 }
3303
3304 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3305                                     struct page ***link)
3306 {
3307         unsigned int h = niu_hash_rxaddr(rp, addr);
3308         struct page *p, **pp;
3309
3310         addr &= PAGE_MASK;
3311         pp = &rp->rxhash[h];
3312         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3313                 if (p->index == addr) {
3314                         *link = pp;
3315                         break;
3316                 }
3317         }
3318
3319         return p;
3320 }
3321
3322 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3323 {
3324         unsigned int h = niu_hash_rxaddr(rp, base);
3325
3326         page->index = base;
3327         page->mapping = (struct address_space *) rp->rxhash[h];
3328         rp->rxhash[h] = page;
3329 }
3330
3331 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3332                             gfp_t mask, int start_index)
3333 {
3334         struct page *page;
3335         u64 addr;
3336         int i;
3337
3338         page = alloc_page(mask);
3339         if (!page)
3340                 return -ENOMEM;
3341
3342         addr = np->ops->map_page(np->device, page, 0,
3343                                  PAGE_SIZE, DMA_FROM_DEVICE);
3344
3345         niu_hash_page(rp, page, addr);
3346         if (rp->rbr_blocks_per_page > 1)
3347                 atomic_add(rp->rbr_blocks_per_page - 1,
3348                            &compound_head(page)->_count);
3349
3350         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3351                 __le32 *rbr = &rp->rbr[start_index + i];
3352
3353                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3354                 addr += rp->rbr_block_size;
3355         }
3356
3357         return 0;
3358 }
3359
3360 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3361 {
3362         int index = rp->rbr_index;
3363
3364         rp->rbr_pending++;
3365         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3366                 int err = niu_rbr_add_page(np, rp, mask, index);
3367
3368                 if (unlikely(err)) {
3369                         rp->rbr_pending--;
3370                         return;
3371                 }
3372
3373                 rp->rbr_index += rp->rbr_blocks_per_page;
3374                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3375                 if (rp->rbr_index == rp->rbr_table_size)
3376                         rp->rbr_index = 0;
3377
3378                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3379                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3380                         rp->rbr_pending = 0;
3381                 }
3382         }
3383 }
3384
3385 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3386 {
3387         unsigned int index = rp->rcr_index;
3388         int num_rcr = 0;
3389
3390         rp->rx_dropped++;
3391         while (1) {
3392                 struct page *page, **link;
3393                 u64 addr, val;
3394                 u32 rcr_size;
3395
3396                 num_rcr++;
3397
3398                 val = le64_to_cpup(&rp->rcr[index]);
3399                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3400                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3401                 page = niu_find_rxpage(rp, addr, &link);
3402
3403                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3404                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3405                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3406                         *link = (struct page *) page->mapping;
3407                         np->ops->unmap_page(np->device, page->index,
3408                                             PAGE_SIZE, DMA_FROM_DEVICE);
3409                         page->index = 0;
3410                         page->mapping = NULL;
3411                         __free_page(page);
3412                         rp->rbr_refill_pending++;
3413                 }
3414
3415                 index = NEXT_RCR(rp, index);
3416                 if (!(val & RCR_ENTRY_MULTI))
3417                         break;
3418
3419         }
3420         rp->rcr_index = index;
3421
3422         return num_rcr;
3423 }
3424
3425 static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
3426 {
3427         unsigned int index = rp->rcr_index;
3428         struct sk_buff *skb;
3429         int len, num_rcr;
3430
3431         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3432         if (unlikely(!skb))
3433                 return niu_rx_pkt_ignore(np, rp);
3434
3435         num_rcr = 0;
3436         while (1) {
3437                 struct page *page, **link;
3438                 u32 rcr_size, append_size;
3439                 u64 addr, val, off;
3440
3441                 num_rcr++;
3442
3443                 val = le64_to_cpup(&rp->rcr[index]);
3444
3445                 len = (val & RCR_ENTRY_L2_LEN) >>
3446                         RCR_ENTRY_L2_LEN_SHIFT;
3447                 len -= ETH_FCS_LEN;
3448
3449                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3450                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3451                 page = niu_find_rxpage(rp, addr, &link);
3452
3453                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3454                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3455
3456                 off = addr & ~PAGE_MASK;
3457                 append_size = rcr_size;
3458                 if (num_rcr == 1) {
3459                         int ptype;
3460
3461                         off += 2;
3462                         append_size -= 2;
3463
3464                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3465                         if ((ptype == RCR_PKT_TYPE_TCP ||
3466                              ptype == RCR_PKT_TYPE_UDP) &&
3467                             !(val & (RCR_ENTRY_NOPORT |
3468                                      RCR_ENTRY_ERROR)))
3469                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3470                         else
3471                                 skb->ip_summed = CHECKSUM_NONE;
3472                 }
3473                 if (!(val & RCR_ENTRY_MULTI))
3474                         append_size = len - skb->len;
3475
3476                 niu_rx_skb_append(skb, page, off, append_size);
3477                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3478                         *link = (struct page *) page->mapping;
3479                         np->ops->unmap_page(np->device, page->index,
3480                                             PAGE_SIZE, DMA_FROM_DEVICE);
3481                         page->index = 0;
3482                         page->mapping = NULL;
3483                         rp->rbr_refill_pending++;
3484                 } else
3485                         get_page(page);
3486
3487                 index = NEXT_RCR(rp, index);
3488                 if (!(val & RCR_ENTRY_MULTI))
3489                         break;
3490
3491         }
3492         rp->rcr_index = index;
3493
3494         skb_reserve(skb, NET_IP_ALIGN);
3495         __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
3496
3497         rp->rx_packets++;
3498         rp->rx_bytes += skb->len;
3499
3500         skb->protocol = eth_type_trans(skb, np->dev);
3501         skb_record_rx_queue(skb, rp->rx_channel);
3502         netif_receive_skb(skb);
3503
3504         return num_rcr;
3505 }
3506
3507 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3508 {
3509         int blocks_per_page = rp->rbr_blocks_per_page;
3510         int err, index = rp->rbr_index;
3511
3512         err = 0;
3513         while (index < (rp->rbr_table_size - blocks_per_page)) {
3514                 err = niu_rbr_add_page(np, rp, mask, index);
3515                 if (err)
3516                         break;
3517
3518                 index += blocks_per_page;
3519         }
3520
3521         rp->rbr_index = index;
3522         return err;
3523 }
3524
3525 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3526 {
3527         int i;
3528
3529         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3530                 struct page *page;
3531
3532                 page = rp->rxhash[i];
3533                 while (page) {
3534                         struct page *next = (struct page *) page->mapping;
3535                         u64 base = page->index;
3536
3537                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3538                                             DMA_FROM_DEVICE);
3539                         page->index = 0;
3540                         page->mapping = NULL;
3541
3542                         __free_page(page);
3543
3544                         page = next;
3545                 }
3546         }
3547
3548         for (i = 0; i < rp->rbr_table_size; i++)
3549                 rp->rbr[i] = cpu_to_le32(0);
3550         rp->rbr_index = 0;
3551 }
3552
3553 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3554 {
3555         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3556         struct sk_buff *skb = tb->skb;
3557         struct tx_pkt_hdr *tp;
3558         u64 tx_flags;
3559         int i, len;
3560
3561         tp = (struct tx_pkt_hdr *) skb->data;
3562         tx_flags = le64_to_cpup(&tp->flags);
3563
3564         rp->tx_packets++;
3565         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3566                          ((tx_flags & TXHDR_PAD) / 2));
3567
3568         len = skb_headlen(skb);
3569         np->ops->unmap_single(np->device, tb->mapping,
3570                               len, DMA_TO_DEVICE);
3571
3572         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3573                 rp->mark_pending--;
3574
3575         tb->skb = NULL;
3576         do {
3577                 idx = NEXT_TX(rp, idx);
3578                 len -= MAX_TX_DESC_LEN;
3579         } while (len > 0);
3580
3581         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3582                 tb = &rp->tx_buffs[idx];
3583                 BUG_ON(tb->skb != NULL);
3584                 np->ops->unmap_page(np->device, tb->mapping,
3585                                     skb_shinfo(skb)->frags[i].size,
3586                                     DMA_TO_DEVICE);
3587                 idx = NEXT_TX(rp, idx);
3588         }
3589
3590         dev_kfree_skb(skb);
3591
3592         return idx;
3593 }
3594
3595 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3596
3597 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3598 {
3599         struct netdev_queue *txq;
3600         u16 pkt_cnt, tmp;
3601         int cons, index;
3602         u64 cs;
3603
3604         index = (rp - np->tx_rings);
3605         txq = netdev_get_tx_queue(np->dev, index);
3606
3607         cs = rp->tx_cs;
3608         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3609                 goto out;
3610
3611         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3612         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3613                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3614
3615         rp->last_pkt_cnt = tmp;
3616
3617         cons = rp->cons;
3618
3619         niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3620                np->dev->name, pkt_cnt, cons);
3621
3622         while (pkt_cnt--)
3623                 cons = release_tx_packet(np, rp, cons);
3624
3625         rp->cons = cons;
3626         smp_mb();
3627
3628 out:
3629         if (unlikely(netif_tx_queue_stopped(txq) &&
3630                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3631                 __netif_tx_lock(txq, smp_processor_id());
3632                 if (netif_tx_queue_stopped(txq) &&
3633                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3634                         netif_tx_wake_queue(txq);
3635                 __netif_tx_unlock(txq);
3636         }
3637 }
3638
3639 static inline void niu_sync_rx_discard_stats(struct niu *np,
3640                                              struct rx_ring_info *rp,
3641                                              const int limit)
3642 {
3643         /* This elaborate scheme is needed for reading the RX discard
3644          * counters, as they are only 16-bit and can overflow quickly,
3645          * and because the overflow indication bit is not usable as
3646          * the counter value does not wrap, but remains at max value
3647          * 0xFFFF.
3648          *
3649          * In theory and in practice counters can be lost in between
3650          * reading nr64() and clearing the counter nw64().  For this
3651          * reason, the number of counter clearings nw64() is
3652          * limited/reduced though the limit parameter.
3653          */
3654         int rx_channel = rp->rx_channel;
3655         u32 misc, wred;
3656
3657         /* RXMISC (Receive Miscellaneous Discard Count), covers the
3658          * following discard events: IPP (Input Port Process),
3659          * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3660          * Block Ring) prefetch buffer is empty.
3661          */
3662         misc = nr64(RXMISC(rx_channel));
3663         if (unlikely((misc & RXMISC_COUNT) > limit)) {
3664                 nw64(RXMISC(rx_channel), 0);
3665                 rp->rx_errors += misc & RXMISC_COUNT;
3666
3667                 if (unlikely(misc & RXMISC_OFLOW))
3668                         dev_err(np->device, "rx-%d: Counter overflow "
3669                                 "RXMISC discard\n", rx_channel);
3670
3671                 niudbg(RX_ERR, "%s-rx-%d: MISC drop=%u over=%u\n",
3672                        np->dev->name, rx_channel, misc, misc-limit);
3673         }
3674
3675         /* WRED (Weighted Random Early Discard) by hardware */
3676         wred = nr64(RED_DIS_CNT(rx_channel));
3677         if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3678                 nw64(RED_DIS_CNT(rx_channel), 0);
3679                 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3680
3681                 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3682                         dev_err(np->device, "rx-%d: Counter overflow "
3683                                 "WRED discard\n", rx_channel);
3684
3685                 niudbg(RX_ERR, "%s-rx-%d: WRED drop=%u over=%u\n",
3686                        np->dev->name, rx_channel, wred, wred-limit);
3687         }
3688 }
3689
3690 static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
3691 {
3692         int qlen, rcr_done = 0, work_done = 0;
3693         struct rxdma_mailbox *mbox = rp->mbox;
3694         u64 stat;
3695
3696 #if 1
3697         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3698         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3699 #else
3700         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3701         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3702 #endif
3703         mbox->rx_dma_ctl_stat = 0;
3704         mbox->rcrstat_a = 0;
3705
3706         niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3707                np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3708
3709         rcr_done = work_done = 0;
3710         qlen = min(qlen, budget);
3711         while (work_done < qlen) {
3712                 rcr_done += niu_process_rx_pkt(np, rp);
3713                 work_done++;
3714         }
3715
3716         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3717                 unsigned int i;
3718
3719                 for (i = 0; i < rp->rbr_refill_pending; i++)
3720                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3721                 rp->rbr_refill_pending = 0;
3722         }
3723
3724         stat = (RX_DMA_CTL_STAT_MEX |
3725                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3726                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3727
3728         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3729
3730         /* Only sync discards stats when qlen indicate potential for drops */
3731         if (qlen > 10)
3732                 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3733
3734         return work_done;
3735 }
3736
3737 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3738 {
3739         u64 v0 = lp->v0;
3740         u32 tx_vec = (v0 >> 32);
3741         u32 rx_vec = (v0 & 0xffffffff);
3742         int i, work_done = 0;
3743
3744         niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3745                np->dev->name, (unsigned long long) v0);
3746
3747         for (i = 0; i < np->num_tx_rings; i++) {
3748                 struct tx_ring_info *rp = &np->tx_rings[i];
3749                 if (tx_vec & (1 << rp->tx_channel))
3750                         niu_tx_work(np, rp);
3751                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3752         }
3753
3754         for (i = 0; i < np->num_rx_rings; i++) {
3755                 struct rx_ring_info *rp = &np->rx_rings[i];
3756
3757                 if (rx_vec & (1 << rp->rx_channel)) {
3758                         int this_work_done;
3759
3760                         this_work_done = niu_rx_work(np, rp,
3761                                                      budget);
3762
3763                         budget -= this_work_done;
3764                         work_done += this_work_done;
3765                 }
3766                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3767         }
3768
3769         return work_done;
3770 }
3771
3772 static int niu_poll(struct napi_struct *napi, int budget)
3773 {
3774         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3775         struct niu *np = lp->np;
3776         int work_done;
3777
3778         work_done = niu_poll_core(np, lp, budget);
3779
3780         if (work_done < budget) {
3781                 napi_complete(napi);
3782                 niu_ldg_rearm(np, lp, 1);
3783         }
3784         return work_done;
3785 }
3786
3787 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3788                                   u64 stat)
3789 {
3790         dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3791                 np->dev->name, rp->rx_channel);
3792
3793         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3794                 printk("RBR_TMOUT ");
3795         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3796                 printk("RSP_CNT ");
3797         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3798                 printk("BYTE_EN_BUS ");
3799         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3800                 printk("RSP_DAT ");
3801         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3802                 printk("RCR_ACK ");
3803         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3804                 printk("RCR_SHA_PAR ");
3805         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3806                 printk("RBR_PRE_PAR ");
3807         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3808                 printk("CONFIG ");
3809         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3810                 printk("RCRINCON ");
3811         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3812                 printk("RCRFULL ");
3813         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3814                 printk("RBRFULL ");
3815         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3816                 printk("RBRLOGPAGE ");
3817         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3818                 printk("CFIGLOGPAGE ");
3819         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3820                 printk("DC_FIDO ");
3821
3822         printk(")\n");
3823 }
3824
3825 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3826 {
3827         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3828         int err = 0;
3829
3830
3831         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3832                     RX_DMA_CTL_STAT_PORT_FATAL))
3833                 err = -EINVAL;
3834
3835         if (err) {
3836                 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3837                         np->dev->name, rp->rx_channel,
3838                         (unsigned long long) stat);
3839
3840                 niu_log_rxchan_errors(np, rp, stat);
3841         }
3842
3843         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3844              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3845
3846         return err;
3847 }
3848
3849 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3850                                   u64 cs)
3851 {
3852         dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3853                 np->dev->name, rp->tx_channel);
3854
3855         if (cs & TX_CS_MBOX_ERR)
3856                 printk("MBOX ");
3857         if (cs & TX_CS_PKT_SIZE_ERR)
3858                 printk("PKT_SIZE ");
3859         if (cs & TX_CS_TX_RING_OFLOW)
3860                 printk("TX_RING_OFLOW ");
3861         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3862                 printk("PREF_BUF_PAR ");
3863         if (cs & TX_CS_NACK_PREF)
3864                 printk("NACK_PREF ");
3865         if (cs & TX_CS_NACK_PKT_RD)
3866                 printk("NACK_PKT_RD ");
3867         if (cs & TX_CS_CONF_PART_ERR)
3868                 printk("CONF_PART ");
3869         if (cs & TX_CS_PKT_PRT_ERR)
3870                 printk("PKT_PTR ");
3871
3872         printk(")\n");
3873 }
3874
3875 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3876 {
3877         u64 cs, logh, logl;
3878
3879         cs = nr64(TX_CS(rp->tx_channel));
3880         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3881         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3882
3883         dev_err(np->device, PFX "%s: TX channel %u error, "
3884                 "cs[%llx] logh[%llx] logl[%llx]\n",
3885                 np->dev->name, rp->tx_channel,
3886                 (unsigned long long) cs,
3887                 (unsigned long long) logh,
3888                 (unsigned long long) logl);
3889
3890         niu_log_txchan_errors(np, rp, cs);
3891
3892         return -ENODEV;
3893 }
3894
3895 static int niu_mif_interrupt(struct niu *np)
3896 {
3897         u64 mif_status = nr64(MIF_STATUS);
3898         int phy_mdint = 0;
3899
3900         if (np->flags & NIU_FLAGS_XMAC) {
3901                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3902
3903                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3904                         phy_mdint = 1;
3905         }
3906
3907         dev_err(np->device, PFX "%s: MIF interrupt, "
3908                 "stat[%llx] phy_mdint(%d)\n",
3909                 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3910
3911         return -ENODEV;
3912 }
3913
3914 static void niu_xmac_interrupt(struct niu *np)
3915 {
3916         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3917         u64 val;
3918
3919         val = nr64_mac(XTXMAC_STATUS);
3920         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3921                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3922         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3923                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3924         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3925                 mp->tx_fifo_errors++;
3926         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3927                 mp->tx_overflow_errors++;
3928         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3929                 mp->tx_max_pkt_size_errors++;
3930         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3931                 mp->tx_underflow_errors++;
3932
3933         val = nr64_mac(XRXMAC_STATUS);
3934         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3935                 mp->rx_local_faults++;
3936         if (val & XRXMAC_STATUS_RFLT_DET)
3937                 mp->rx_remote_faults++;
3938         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3939                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3940         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3941                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3942         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3943                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3944         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3945                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3946         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3947                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3948         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3949                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3950         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3951                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3952         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3953                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3954         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3955                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3956         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3957                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3958         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3959                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3960         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3961                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3962         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3963                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3964         if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
3965                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3966         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3967                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3968         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3969                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3970         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3971                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3972         if (val & XRXMAC_STATUS_RXUFLOW)
3973                 mp->rx_underflows++;
3974         if (val & XRXMAC_STATUS_RXOFLOW)
3975                 mp->rx_overflows++;
3976
3977         val = nr64_mac(XMAC_FC_STAT);
3978         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3979                 mp->pause_off_state++;
3980         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3981                 mp->pause_on_state++;
3982         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3983                 mp->pause_received++;
3984 }
3985
3986 static void niu_bmac_interrupt(struct niu *np)
3987 {
3988         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3989         u64 val;
3990
3991         val = nr64_mac(BTXMAC_STATUS);
3992         if (val & BTXMAC_STATUS_UNDERRUN)
3993                 mp->tx_underflow_errors++;
3994         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3995                 mp->tx_max_pkt_size_errors++;
3996         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3997                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3998         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3999                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4000
4001         val = nr64_mac(BRXMAC_STATUS);
4002         if (val & BRXMAC_STATUS_OVERFLOW)
4003                 mp->rx_overflows++;
4004         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4005                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4006         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4007                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4008         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4009                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4010         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4011                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4012
4013         val = nr64_mac(BMAC_CTRL_STATUS);
4014         if (val & BMAC_CTRL_STATUS_NOPAUSE)
4015                 mp->pause_off_state++;
4016         if (val & BMAC_CTRL_STATUS_PAUSE)
4017                 mp->pause_on_state++;
4018         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4019                 mp->pause_received++;
4020 }
4021
4022 static int niu_mac_interrupt(struct niu *np)
4023 {
4024         if (np->flags & NIU_FLAGS_XMAC)
4025                 niu_xmac_interrupt(np);
4026         else
4027                 niu_bmac_interrupt(np);
4028
4029         return 0;
4030 }
4031
4032 static void niu_log_device_error(struct niu *np, u64 stat)
4033 {
4034         dev_err(np->device, PFX "%s: Core device errors ( ",
4035                 np->dev->name);
4036
4037         if (stat & SYS_ERR_MASK_META2)
4038                 printk("META2 ");
4039         if (stat & SYS_ERR_MASK_META1)
4040                 printk("META1 ");
4041         if (stat & SYS_ERR_MASK_PEU)
4042                 printk("PEU ");
4043         if (stat & SYS_ERR_MASK_TXC)
4044                 printk("TXC ");
4045         if (stat & SYS_ERR_MASK_RDMC)
4046                 printk("RDMC ");
4047         if (stat & SYS_ERR_MASK_TDMC)
4048                 printk("TDMC ");
4049         if (stat & SYS_ERR_MASK_ZCP)
4050                 printk("ZCP ");
4051         if (stat & SYS_ERR_MASK_FFLP)
4052                 printk("FFLP ");
4053         if (stat & SYS_ERR_MASK_IPP)
4054                 printk("IPP ");
4055         if (stat & SYS_ERR_MASK_MAC)
4056                 printk("MAC ");
4057         if (stat & SYS_ERR_MASK_SMX)
4058                 printk("SMX ");
4059
4060         printk(")\n");
4061 }
4062
4063 static int niu_device_error(struct niu *np)
4064 {
4065         u64 stat = nr64(SYS_ERR_STAT);
4066
4067         dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
4068                 np->dev->name, (unsigned long long) stat);
4069
4070         niu_log_device_error(np, stat);
4071
4072         return -ENODEV;
4073 }
4074
4075 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4076                               u64 v0, u64 v1, u64 v2)
4077 {
4078
4079         int i, err = 0;
4080
4081         lp->v0 = v0;
4082         lp->v1 = v1;
4083         lp->v2 = v2;
4084
4085         if (v1 & 0x00000000ffffffffULL) {
4086                 u32 rx_vec = (v1 & 0xffffffff);
4087
4088                 for (i = 0; i < np->num_rx_rings; i++) {
4089                         struct rx_ring_info *rp = &np->rx_rings[i];
4090
4091                         if (rx_vec & (1 << rp->rx_channel)) {
4092                                 int r = niu_rx_error(np, rp);
4093                                 if (r) {
4094                                         err = r;
4095                                 } else {
4096                                         if (!v0)
4097                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4098                                                      RX_DMA_CTL_STAT_MEX);
4099                                 }
4100                         }
4101                 }
4102         }
4103         if (v1 & 0x7fffffff00000000ULL) {
4104                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4105
4106                 for (i = 0; i < np->num_tx_rings; i++) {
4107                         struct tx_ring_info *rp = &np->tx_rings[i];
4108
4109                         if (tx_vec & (1 << rp->tx_channel)) {
4110                                 int r = niu_tx_error(np, rp);
4111                                 if (r)
4112                                         err = r;
4113                         }
4114                 }
4115         }
4116         if ((v0 | v1) & 0x8000000000000000ULL) {
4117                 int r = niu_mif_interrupt(np);
4118                 if (r)
4119                         err = r;
4120         }
4121         if (v2) {
4122                 if (v2 & 0x01ef) {
4123                         int r = niu_mac_interrupt(np);
4124                         if (r)
4125                                 err = r;
4126                 }
4127                 if (v2 & 0x0210) {
4128                         int r = niu_device_error(np);
4129                         if (r)
4130                                 err = r;
4131                 }
4132         }
4133
4134         if (err)
4135                 niu_enable_interrupts(np, 0);
4136
4137         return err;
4138 }
4139
4140 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4141                             int ldn)
4142 {
4143         struct rxdma_mailbox *mbox = rp->mbox;
4144         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4145
4146         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4147                       RX_DMA_CTL_STAT_RCRTO);
4148         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4149
4150         niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
4151                np->dev->name, (unsigned long long) stat);
4152 }
4153
4154 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4155                             int ldn)
4156 {
4157         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4158
4159         niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
4160                np->dev->name, (unsigned long long) rp->tx_cs);
4161 }
4162
4163 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4164 {
4165         struct niu_parent *parent = np->parent;
4166         u32 rx_vec, tx_vec;
4167         int i;
4168
4169         tx_vec = (v0 >> 32);
4170         rx_vec = (v0 & 0xffffffff);
4171
4172         for (i = 0; i < np->num_rx_rings; i++) {
4173                 struct rx_ring_info *rp = &np->rx_rings[i];
4174                 int ldn = LDN_RXDMA(rp->rx_channel);
4175
4176                 if (parent->ldg_map[ldn] != ldg)
4177                         continue;
4178
4179                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4180                 if (rx_vec & (1 << rp->rx_channel))
4181                         niu_rxchan_intr(np, rp, ldn);
4182         }
4183
4184         for (i = 0; i < np->num_tx_rings; i++) {
4185                 struct tx_ring_info *rp = &np->tx_rings[i];
4186                 int ldn = LDN_TXDMA(rp->tx_channel);
4187
4188                 if (parent->ldg_map[ldn] != ldg)
4189                         continue;
4190
4191                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4192                 if (tx_vec & (1 << rp->tx_channel))
4193                         niu_txchan_intr(np, rp, ldn);
4194         }
4195 }
4196
4197 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4198                               u64 v0, u64 v1, u64 v2)
4199 {
4200         if (likely(napi_schedule_prep(&lp->napi))) {
4201                 lp->v0 = v0;
4202                 lp->v1 = v1;
4203                 lp->v2 = v2;
4204                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4205                 __napi_schedule(&lp->napi);
4206         }
4207 }
4208
4209 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4210 {
4211         struct niu_ldg *lp = dev_id;
4212         struct niu *np = lp->np;
4213         int ldg = lp->ldg_num;
4214         unsigned long flags;
4215         u64 v0, v1, v2;
4216
4217         if (netif_msg_intr(np))
4218                 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
4219                        lp, ldg);
4220
4221         spin_lock_irqsave(&np->lock, flags);
4222
4223         v0 = nr64(LDSV0(ldg));
4224         v1 = nr64(LDSV1(ldg));
4225         v2 = nr64(LDSV2(ldg));
4226
4227         if (netif_msg_intr(np))
4228                 printk("v0[%llx] v1[%llx] v2[%llx]\n",
4229                        (unsigned long long) v0,
4230                        (unsigned long long) v1,
4231                        (unsigned long long) v2);
4232
4233         if (unlikely(!v0 && !v1 && !v2)) {
4234                 spin_unlock_irqrestore(&np->lock, flags);
4235                 return IRQ_NONE;
4236         }
4237
4238         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4239                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4240                 if (err)
4241                         goto out;
4242         }
4243         if (likely(v0 & ~((u64)1 << LDN_MIF)))
4244                 niu_schedule_napi(np, lp, v0, v1, v2);
4245         else
4246                 niu_ldg_rearm(np, lp, 1);
4247 out:
4248         spin_unlock_irqrestore(&np->lock, flags);
4249
4250         return IRQ_HANDLED;
4251 }
4252
4253 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4254 {
4255         if (rp->mbox) {
4256                 np->ops->free_coherent(np->device,
4257                                        sizeof(struct rxdma_mailbox),
4258                                        rp->mbox, rp->mbox_dma);
4259                 rp->mbox = NULL;
4260         }
4261         if (rp->rcr) {
4262                 np->ops->free_coherent(np->device,
4263                                        MAX_RCR_RING_SIZE * sizeof(__le64),
4264                                        rp->rcr, rp->rcr_dma);
4265                 rp->rcr = NULL;
4266                 rp->rcr_table_size = 0;
4267                 rp->rcr_index = 0;
4268         }
4269         if (rp->rbr) {
4270                 niu_rbr_free(np, rp);
4271
4272                 np->ops->free_coherent(np->device,
4273                                        MAX_RBR_RING_SIZE * sizeof(__le32),
4274                                        rp->rbr, rp->rbr_dma);
4275                 rp->rbr = NULL;
4276                 rp->rbr_table_size = 0;
4277                 rp->rbr_index = 0;
4278         }
4279         kfree(rp->rxhash);
4280         rp->rxhash = NULL;
4281 }
4282
4283 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4284 {
4285         if (rp->mbox) {
4286                 np->ops->free_coherent(np->device,
4287                                        sizeof(struct txdma_mailbox),
4288                                        rp->mbox, rp->mbox_dma);
4289                 rp->mbox = NULL;
4290         }
4291         if (rp->descr) {
4292                 int i;
4293
4294                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4295                         if (rp->tx_buffs[i].skb)
4296                                 (void) release_tx_packet(np, rp, i);
4297                 }
4298
4299                 np->ops->free_coherent(np->device,
4300                                        MAX_TX_RING_SIZE * sizeof(__le64),
4301                                        rp->descr, rp->descr_dma);
4302                 rp->descr = NULL;
4303                 rp->pending = 0;
4304                 rp->prod = 0;
4305                 rp->cons = 0;
4306                 rp->wrap_bit = 0;
4307         }
4308 }
4309
4310 static void niu_free_channels(struct niu *np)
4311 {
4312         int i;
4313
4314         if (np->rx_rings) {
4315                 for (i = 0; i < np->num_rx_rings; i++) {
4316                         struct rx_ring_info *rp = &np->rx_rings[i];
4317
4318                         niu_free_rx_ring_info(np, rp);
4319                 }
4320                 kfree(np->rx_rings);
4321                 np->rx_rings = NULL;
4322                 np->num_rx_rings = 0;
4323         }
4324
4325         if (np->tx_rings) {
4326                 for (i = 0; i < np->num_tx_rings; i++) {
4327                         struct tx_ring_info *rp = &np->tx_rings[i];
4328
4329                         niu_free_tx_ring_info(np, rp);
4330                 }
4331                 kfree(np->tx_rings);
4332                 np->tx_rings = NULL;
4333                 np->num_tx_rings = 0;
4334         }
4335 }
4336
4337 static int niu_alloc_rx_ring_info(struct niu *np,
4338                                   struct rx_ring_info *rp)
4339 {
4340         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4341
4342         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4343                              GFP_KERNEL);
4344         if (!rp->rxhash)
4345                 return -ENOMEM;
4346
4347         rp->mbox = np->ops->alloc_coherent(np->device,
4348                                            sizeof(struct rxdma_mailbox),
4349                                            &rp->mbox_dma, GFP_KERNEL);
4350         if (!rp->mbox)
4351                 return -ENOMEM;
4352         if ((unsigned long)rp->mbox & (64UL - 1)) {
4353                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4354                         "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
4355                 return -EINVAL;
4356         }
4357
4358         rp->rcr = np->ops->alloc_coherent(np->device,
4359                                           MAX_RCR_RING_SIZE * sizeof(__le64),
4360                                           &rp->rcr_dma, GFP_KERNEL);
4361         if (!rp->rcr)
4362                 return -ENOMEM;
4363         if ((unsigned long)rp->rcr & (64UL - 1)) {
4364                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4365                         "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
4366                 return -EINVAL;
4367         }
4368         rp->rcr_table_size = MAX_RCR_RING_SIZE;
4369         rp->rcr_index = 0;
4370
4371         rp->rbr = np->ops->alloc_coherent(np->device,
4372                                           MAX_RBR_RING_SIZE * sizeof(__le32),
4373                                           &rp->rbr_dma, GFP_KERNEL);
4374         if (!rp->rbr)
4375                 return -ENOMEM;
4376         if ((unsigned long)rp->rbr & (64UL - 1)) {
4377                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4378                         "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
4379                 return -EINVAL;
4380         }
4381         rp->rbr_table_size = MAX_RBR_RING_SIZE;
4382         rp->rbr_index = 0;
4383         rp->rbr_pending = 0;
4384
4385         return 0;
4386 }
4387
4388 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4389 {
4390         int mtu = np->dev->mtu;
4391
4392         /* These values are recommended by the HW designers for fair
4393          * utilization of DRR amongst the rings.
4394          */
4395         rp->max_burst = mtu + 32;
4396         if (rp->max_burst > 4096)
4397                 rp->max_burst = 4096;
4398 }
4399
4400 static int niu_alloc_tx_ring_info(struct niu *np,
4401                                   struct tx_ring_info *rp)
4402 {
4403         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4404
4405         rp->mbox = np->ops->alloc_coherent(np->device,
4406                                            sizeof(struct txdma_mailbox),
4407                                            &rp->mbox_dma, GFP_KERNEL);
4408         if (!rp->mbox)
4409                 return -ENOMEM;
4410         if ((unsigned long)rp->mbox & (64UL - 1)) {
4411                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4412                         "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
4413                 return -EINVAL;
4414         }
4415
4416         rp->descr = np->ops->alloc_coherent(np->device,
4417                                             MAX_TX_RING_SIZE * sizeof(__le64),
4418                                             &rp->descr_dma, GFP_KERNEL);
4419         if (!rp->descr)
4420                 return -ENOMEM;
4421         if ((unsigned long)rp->descr & (64UL - 1)) {
4422                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4423                         "TXDMA descr table %p\n", np->dev->name, rp->descr);
4424                 return -EINVAL;
4425         }
4426
4427         rp->pending = MAX_TX_RING_SIZE;
4428         rp->prod = 0;
4429         rp->cons = 0;
4430         rp->wrap_bit = 0;
4431
4432         /* XXX make these configurable... XXX */
4433         rp->mark_freq = rp->pending / 4;
4434
4435         niu_set_max_burst(np, rp);
4436
4437         return 0;
4438 }
4439
4440 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4441 {
4442         u16 bss;
4443
4444         bss = min(PAGE_SHIFT, 15);
4445
4446         rp->rbr_block_size = 1 << bss;
4447         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4448
4449         rp->rbr_sizes[0] = 256;
4450         rp->rbr_sizes[1] = 1024;
4451         if (np->dev->mtu > ETH_DATA_LEN) {
4452                 switch (PAGE_SIZE) {
4453                 case 4 * 1024:
4454                         rp->rbr_sizes[2] = 4096;
4455                         break;
4456
4457                 default:
4458                         rp->rbr_sizes[2] = 8192;
4459                         break;
4460                 }
4461         } else {
4462                 rp->rbr_sizes[2] = 2048;
4463         }
4464         rp->rbr_sizes[3] = rp->rbr_block_size;
4465 }
4466
4467 static int niu_alloc_channels(struct niu *np)
4468 {
4469         struct niu_parent *parent = np->parent;
4470         int first_rx_channel, first_tx_channel;
4471         int i, port, err;
4472
4473         port = np->port;
4474         first_rx_channel = first_tx_channel = 0;
4475         for (i = 0; i < port; i++) {
4476                 first_rx_channel += parent->rxchan_per_port[i];
4477                 first_tx_channel += parent->txchan_per_port[i];
4478         }
4479
4480         np->num_rx_rings = parent->rxchan_per_port[port];
4481         np->num_tx_rings = parent->txchan_per_port[port];
4482
4483         np->dev->real_num_tx_queues = np->num_tx_rings;
4484
4485         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4486                                GFP_KERNEL);
4487         err = -ENOMEM;
4488         if (!np->rx_rings)
4489                 goto out_err;
4490
4491         for (i = 0; i < np->num_rx_rings; i++) {
4492                 struct rx_ring_info *rp = &np->rx_rings[i];
4493
4494                 rp->np = np;
4495                 rp->rx_channel = first_rx_channel + i;
4496
4497                 err = niu_alloc_rx_ring_info(np, rp);
4498                 if (err)
4499                         goto out_err;
4500
4501                 niu_size_rbr(np, rp);
4502
4503                 /* XXX better defaults, configurable, etc... XXX */
4504                 rp->nonsyn_window = 64;
4505                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4506                 rp->syn_window = 64;
4507                 rp->syn_threshold = rp->rcr_table_size - 64;
4508                 rp->rcr_pkt_threshold = 16;
4509                 rp->rcr_timeout = 8;
4510                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4511                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4512                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4513
4514                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4515                 if (err)
4516                         return err;
4517         }
4518
4519         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4520                                GFP_KERNEL);
4521         err = -ENOMEM;
4522         if (!np->tx_rings)
4523                 goto out_err;
4524
4525         for (i = 0; i < np->num_tx_rings; i++) {
4526                 struct tx_ring_info *rp = &np->tx_rings[i];
4527
4528                 rp->np = np;
4529                 rp->tx_channel = first_tx_channel + i;
4530
4531                 err = niu_alloc_tx_ring_info(np, rp);
4532                 if (err)
4533                         goto out_err;
4534         }
4535
4536         return 0;
4537
4538 out_err:
4539         niu_free_channels(np);
4540         return err;
4541 }
4542
4543 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4544 {
4545         int limit = 1000;
4546
4547         while (--limit > 0) {
4548                 u64 val = nr64(TX_CS(channel));
4549                 if (val & TX_CS_SNG_STATE)
4550                         return 0;
4551         }
4552         return -ENODEV;
4553 }
4554
4555 static int niu_tx_channel_stop(struct niu *np, int channel)
4556 {
4557         u64 val = nr64(TX_CS(channel));
4558
4559         val |= TX_CS_STOP_N_GO;
4560         nw64(TX_CS(channel), val);
4561
4562         return niu_tx_cs_sng_poll(np, channel);
4563 }
4564
4565 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4566 {
4567         int limit = 1000;
4568
4569         while (--limit > 0) {
4570                 u64 val = nr64(TX_CS(channel));
4571                 if (!(val & TX_CS_RST))
4572                         return 0;
4573         }
4574         return -ENODEV;
4575 }
4576
4577 static int niu_tx_channel_reset(struct niu *np, int channel)
4578 {
4579         u64 val = nr64(TX_CS(channel));
4580         int err;
4581
4582         val |= TX_CS_RST;
4583         nw64(TX_CS(channel), val);
4584
4585         err = niu_tx_cs_reset_poll(np, channel);
4586         if (!err)
4587                 nw64(TX_RING_KICK(channel), 0);
4588
4589         return err;
4590 }
4591
4592 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4593 {
4594         u64 val;
4595
4596         nw64(TX_LOG_MASK1(channel), 0);
4597         nw64(TX_LOG_VAL1(channel), 0);
4598         nw64(TX_LOG_MASK2(channel), 0);
4599         nw64(TX_LOG_VAL2(channel), 0);
4600         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4601         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4602         nw64(TX_LOG_PAGE_HDL(channel), 0);
4603
4604         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4605         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4606         nw64(TX_LOG_PAGE_VLD(channel), val);
4607
4608         /* XXX TXDMA 32bit mode? XXX */
4609
4610         return 0;
4611 }
4612
4613 static void niu_txc_enable_port(struct niu *np, int on)
4614 {
4615         unsigned long flags;
4616         u64 val, mask;
4617
4618         niu_lock_parent(np, flags);
4619         val = nr64(TXC_CONTROL);
4620         mask = (u64)1 << np->port;
4621         if (on) {
4622                 val |= TXC_CONTROL_ENABLE | mask;
4623         } else {
4624                 val &= ~mask;
4625                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4626                         val &= ~TXC_CONTROL_ENABLE;
4627         }
4628         nw64(TXC_CONTROL, val);
4629         niu_unlock_parent(np, flags);
4630 }
4631
4632 static void niu_txc_set_imask(struct niu *np, u64 imask)
4633 {
4634         unsigned long flags;
4635         u64 val;
4636
4637         niu_lock_parent(np, flags);
4638         val = nr64(TXC_INT_MASK);
4639         val &= ~TXC_INT_MASK_VAL(np->port);
4640         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4641         niu_unlock_parent(np, flags);
4642 }
4643
4644 static void niu_txc_port_dma_enable(struct niu *np, int on)
4645 {
4646         u64 val = 0;
4647
4648         if (on) {
4649                 int i;
4650
4651                 for (i = 0; i < np->num_tx_rings; i++)
4652                         val |= (1 << np->tx_rings[i].tx_channel);
4653         }
4654         nw64(TXC_PORT_DMA(np->port), val);
4655 }
4656
4657 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4658 {
4659         int err, channel = rp->tx_channel;
4660         u64 val, ring_len;
4661
4662         err = niu_tx_channel_stop(np, channel);
4663         if (err)
4664                 return err;
4665
4666         err = niu_tx_channel_reset(np, channel);
4667         if (err)
4668                 return err;
4669
4670         err = niu_tx_channel_lpage_init(np, channel);
4671         if (err)
4672                 return err;
4673
4674         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4675         nw64(TX_ENT_MSK(channel), 0);
4676
4677         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4678                               TX_RNG_CFIG_STADDR)) {
4679                 dev_err(np->device, PFX "%s: TX ring channel %d "
4680                         "DMA addr (%llx) is not aligned.\n",
4681                         np->dev->name, channel,
4682                         (unsigned long long) rp->descr_dma);
4683                 return -EINVAL;
4684         }
4685
4686         /* The length field in TX_RNG_CFIG is measured in 64-byte
4687          * blocks.  rp->pending is the number of TX descriptors in
4688          * our ring, 8 bytes each, thus we divide by 8 bytes more
4689          * to get the proper value the chip wants.
4690          */
4691         ring_len = (rp->pending / 8);
4692
4693         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4694                rp->descr_dma);
4695         nw64(TX_RNG_CFIG(channel), val);
4696
4697         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4698             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4699                 dev_err(np->device, PFX "%s: TX ring channel %d "
4700                         "MBOX addr (%llx) is has illegal bits.\n",
4701                         np->dev->name, channel,
4702                         (unsigned long long) rp->mbox_dma);
4703                 return -EINVAL;
4704         }
4705         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4706         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4707
4708         nw64(TX_CS(channel), 0);
4709
4710         rp->last_pkt_cnt = 0;
4711
4712         return 0;
4713 }
4714
4715 static void niu_init_rdc_groups(struct niu *np)
4716 {
4717         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4718         int i, first_table_num = tp->first_table_num;
4719
4720         for (i = 0; i < tp->num_tables; i++) {
4721                 struct rdc_table *tbl = &tp->tables[i];
4722                 int this_table = first_table_num + i;
4723                 int slot;
4724
4725                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4726                         nw64(RDC_TBL(this_table, slot),
4727                              tbl->rxdma_channel[slot]);
4728         }
4729
4730         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4731 }
4732
4733 static void niu_init_drr_weight(struct niu *np)
4734 {
4735         int type = phy_decode(np->parent->port_phy, np->port);
4736         u64 val;
4737
4738         switch (type) {
4739         case PORT_TYPE_10G:
4740                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4741                 break;
4742
4743         case PORT_TYPE_1G:
4744         default:
4745                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4746                 break;
4747         }
4748         nw64(PT_DRR_WT(np->port), val);
4749 }
4750
4751 static int niu_init_hostinfo(struct niu *np)
4752 {
4753         struct niu_parent *parent = np->parent;
4754         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4755         int i, err, num_alt = niu_num_alt_addr(np);
4756         int first_rdc_table = tp->first_table_num;
4757
4758         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4759         if (err)
4760                 return err;
4761
4762         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4763         if (err)
4764                 return err;
4765
4766         for (i = 0; i < num_alt; i++) {
4767                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4768                 if (err)
4769                         return err;
4770         }
4771
4772         return 0;
4773 }
4774
4775 static int niu_rx_channel_reset(struct niu *np, int channel)
4776 {
4777         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4778                                       RXDMA_CFIG1_RST, 1000, 10,
4779                                       "RXDMA_CFIG1");
4780 }
4781
4782 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4783 {
4784         u64 val;
4785
4786         nw64(RX_LOG_MASK1(channel), 0);
4787         nw64(RX_LOG_VAL1(channel), 0);
4788         nw64(RX_LOG_MASK2(channel), 0);
4789         nw64(RX_LOG_VAL2(channel), 0);
4790         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4791         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4792         nw64(RX_LOG_PAGE_HDL(channel), 0);
4793
4794         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4795         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4796         nw64(RX_LOG_PAGE_VLD(channel), val);
4797
4798         return 0;
4799 }
4800
4801 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4802 {
4803         u64 val;
4804
4805         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4806                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4807                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4808                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4809         nw64(RDC_RED_PARA(rp->rx_channel), val);
4810 }
4811
4812 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4813 {
4814         u64 val = 0;
4815
4816         switch (rp->rbr_block_size) {
4817         case 4 * 1024:
4818                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4819                 break;
4820         case 8 * 1024:
4821                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4822                 break;
4823         case 16 * 1024:
4824                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4825                 break;
4826         case 32 * 1024:
4827                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4828                 break;
4829         default:
4830                 return -EINVAL;
4831         }
4832         val |= RBR_CFIG_B_VLD2;
4833         switch (rp->rbr_sizes[2]) {
4834         case 2 * 1024:
4835                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4836                 break;
4837         case 4 * 1024:
4838                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4839                 break;
4840         case 8 * 1024:
4841                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4842                 break;
4843         case 16 * 1024:
4844                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4845                 break;
4846
4847         default:
4848                 return -EINVAL;
4849         }
4850         val |= RBR_CFIG_B_VLD1;
4851         switch (rp->rbr_sizes[1]) {
4852         case 1 * 1024:
4853                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4854                 break;
4855         case 2 * 1024:
4856                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4857                 break;
4858         case 4 * 1024:
4859                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4860                 break;
4861         case 8 * 1024:
4862                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4863                 break;
4864
4865         default:
4866                 return -EINVAL;
4867         }
4868         val |= RBR_CFIG_B_VLD0;
4869         switch (rp->rbr_sizes[0]) {
4870         case 256:
4871                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4872                 break;
4873         case 512:
4874                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4875                 break;
4876         case 1 * 1024:
4877                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4878                 break;
4879         case 2 * 1024:
4880                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4881                 break;
4882
4883         default:
4884                 return -EINVAL;
4885         }
4886
4887         *ret = val;
4888         return 0;
4889 }
4890
4891 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4892 {
4893         u64 val = nr64(RXDMA_CFIG1(channel));
4894         int limit;
4895
4896         if (on)
4897                 val |= RXDMA_CFIG1_EN;
4898         else
4899                 val &= ~RXDMA_CFIG1_EN;
4900         nw64(RXDMA_CFIG1(channel), val);
4901
4902         limit = 1000;
4903         while (--limit > 0) {
4904                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4905                         break;
4906                 udelay(10);
4907         }
4908         if (limit <= 0)
4909                 return -ENODEV;
4910         return 0;
4911 }
4912
4913 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4914 {
4915         int err, channel = rp->rx_channel;
4916         u64 val;
4917
4918         err = niu_rx_channel_reset(np, channel);
4919         if (err)
4920                 return err;
4921
4922         err = niu_rx_channel_lpage_init(np, channel);
4923         if (err)
4924                 return err;
4925
4926         niu_rx_channel_wred_init(np, rp);
4927
4928         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4929         nw64(RX_DMA_CTL_STAT(channel),
4930              (RX_DMA_CTL_STAT_MEX |
4931               RX_DMA_CTL_STAT_RCRTHRES |
4932               RX_DMA_CTL_STAT_RCRTO |
4933               RX_DMA_CTL_STAT_RBR_EMPTY));
4934         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4935         nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4936         nw64(RBR_CFIG_A(channel),
4937              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4938              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4939         err = niu_compute_rbr_cfig_b(rp, &val);
4940         if (err)
4941                 return err;
4942         nw64(RBR_CFIG_B(channel), val);
4943         nw64(RCRCFIG_A(channel),
4944              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4945              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4946         nw64(RCRCFIG_B(channel),
4947              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4948              RCRCFIG_B_ENTOUT |
4949              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4950
4951         err = niu_enable_rx_channel(np, channel, 1);
4952         if (err)
4953                 return err;
4954
4955         nw64(RBR_KICK(channel), rp->rbr_index);
4956
4957         val = nr64(RX_DMA_CTL_STAT(channel));
4958         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4959         nw64(RX_DMA_CTL_STAT(channel), val);
4960
4961         return 0;
4962 }
4963
4964 static int niu_init_rx_channels(struct niu *np)
4965 {
4966         unsigned long flags;
4967         u64 seed = jiffies_64;
4968         int err, i;
4969
4970         niu_lock_parent(np, flags);
4971         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4972         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4973         niu_unlock_parent(np, flags);
4974
4975         /* XXX RXDMA 32bit mode? XXX */
4976
4977         niu_init_rdc_groups(np);
4978         niu_init_drr_weight(np);
4979
4980         err = niu_init_hostinfo(np);
4981         if (err)
4982                 return err;
4983
4984         for (i = 0; i < np->num_rx_rings; i++) {
4985                 struct rx_ring_info *rp = &np->rx_rings[i];
4986
4987                 err = niu_init_one_rx_channel(np, rp);
4988                 if (err)
4989                         return err;
4990         }
4991
4992         return 0;
4993 }
4994
4995 static int niu_set_ip_frag_rule(struct niu *np)
4996 {
4997         struct niu_parent *parent = np->parent;
4998         struct niu_classifier *cp = &np->clas;
4999         struct niu_tcam_entry *tp;
5000         int index, err;
5001
5002         /* XXX fix this allocation scheme XXX */
5003         index = cp->tcam_index;
5004         tp = &parent->tcam[index];
5005
5006         /* Note that the noport bit is the same in both ipv4 and
5007          * ipv6 format TCAM entries.
5008          */
5009         memset(tp, 0, sizeof(*tp));
5010         tp->key[1] = TCAM_V4KEY1_NOPORT;
5011         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5012         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5013                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5014         err = tcam_write(np, index, tp->key, tp->key_mask);
5015         if (err)
5016                 return err;
5017         err = tcam_assoc_write(np, index, tp->assoc_data);
5018         if (err)
5019                 return err;
5020
5021         return 0;
5022 }
5023
5024 static int niu_init_classifier_hw(struct niu *np)
5025 {
5026         struct niu_parent *parent = np->parent;
5027         struct niu_classifier *cp = &np->clas;
5028         int i, err;
5029
5030         nw64(H1POLY, cp->h1_init);
5031         nw64(H2POLY, cp->h2_init);
5032
5033         err = niu_init_hostinfo(np);
5034         if (err)
5035                 return err;
5036
5037         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5038                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5039
5040                 vlan_tbl_write(np, i, np->port,
5041                                vp->vlan_pref, vp->rdc_num);
5042         }
5043
5044         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5045                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5046
5047                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5048                                                 ap->rdc_num, ap->mac_pref);
5049                 if (err)
5050                         return err;
5051         }
5052
5053         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5054                 int index = i - CLASS_CODE_USER_PROG1;
5055
5056                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5057                 if (err)
5058                         return err;
5059                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5060                 if (err)
5061                         return err;
5062         }
5063
5064         err = niu_set_ip_frag_rule(np);
5065         if (err)
5066                 return err;
5067
5068         tcam_enable(np, 1);
5069
5070         return 0;
5071 }
5072
5073 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5074 {
5075         nw64(ZCP_RAM_DATA0, data[0]);
5076         nw64(ZCP_RAM_DATA1, data[1]);
5077         nw64(ZCP_RAM_DATA2, data[2]);
5078         nw64(ZCP_RAM_DATA3, data[3]);
5079         nw64(ZCP_RAM_DATA4, data[4]);
5080         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5081         nw64(ZCP_RAM_ACC,
5082              (ZCP_RAM_ACC_WRITE |
5083               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5084               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5085
5086         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5087                                    1000, 100);
5088 }
5089
5090 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5091 {
5092         int err;
5093
5094         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5095                                   1000, 100);
5096         if (err) {
5097                 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
5098                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5099                         (unsigned long long) nr64(ZCP_RAM_ACC));
5100                 return err;
5101         }
5102
5103         nw64(ZCP_RAM_ACC,
5104              (ZCP_RAM_ACC_READ |
5105               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5106               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5107
5108         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5109                                   1000, 100);
5110         if (err) {
5111                 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
5112                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5113                         (unsigned long long) nr64(ZCP_RAM_ACC));
5114                 return err;
5115         }
5116
5117         data[0] = nr64(ZCP_RAM_DATA0);
5118         data[1] = nr64(ZCP_RAM_DATA1);
5119         data[2] = nr64(ZCP_RAM_DATA2);
5120         data[3] = nr64(ZCP_RAM_DATA3);
5121         data[4] = nr64(ZCP_RAM_DATA4);
5122
5123         return 0;
5124 }
5125
5126 static void niu_zcp_cfifo_reset(struct niu *np)
5127 {
5128         u64 val = nr64(RESET_CFIFO);
5129
5130         val |= RESET_CFIFO_RST(np->port);
5131         nw64(RESET_CFIFO, val);
5132         udelay(10);
5133
5134         val &= ~RESET_CFIFO_RST(np->port);
5135         nw64(RESET_CFIFO, val);
5136 }
5137
5138 static int niu_init_zcp(struct niu *np)
5139 {
5140         u64 data[5], rbuf[5];
5141         int i, max, err;
5142
5143         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5144                 if (np->port == 0 || np->port == 1)
5145                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
5146                 else
5147                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
5148         } else
5149                 max = NIU_CFIFO_ENTRIES;
5150
5151         data[0] = 0;
5152         data[1] = 0;
5153         data[2] = 0;
5154         data[3] = 0;
5155         data[4] = 0;
5156
5157         for (i = 0; i < max; i++) {
5158                 err = niu_zcp_write(np, i, data);
5159                 if (err)
5160                         return err;
5161                 err = niu_zcp_read(np, i, rbuf);
5162                 if (err)
5163                         return err;
5164         }
5165
5166         niu_zcp_cfifo_reset(np);
5167         nw64(CFIFO_ECC(np->port), 0);
5168         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5169         (void) nr64(ZCP_INT_STAT);
5170         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5171
5172         return 0;
5173 }
5174
5175 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5176 {
5177         u64 val = nr64_ipp(IPP_CFIG);
5178
5179         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5180         nw64_ipp(IPP_DFIFO_WR_PTR, index);
5181         nw64_ipp(IPP_DFIFO_WR0, data[0]);
5182         nw64_ipp(IPP_DFIFO_WR1, data[1]);
5183         nw64_ipp(IPP_DFIFO_WR2, data[2]);
5184         nw64_ipp(IPP_DFIFO_WR3, data[3]);
5185         nw64_ipp(IPP_DFIFO_WR4, data[4]);
5186         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5187 }
5188
5189 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5190 {
5191         nw64_ipp(IPP_DFIFO_RD_PTR, index);
5192         data[0] = nr64_ipp(IPP_DFIFO_RD0);
5193         data[1] = nr64_ipp(IPP_DFIFO_RD1);
5194         data[2] = nr64_ipp(IPP_DFIFO_RD2);
5195         data[3] = nr64_ipp(IPP_DFIFO_RD3);
5196         data[4] = nr64_ipp(IPP_DFIFO_RD4);
5197 }
5198
5199 static int niu_ipp_reset(struct niu *np)
5200 {
5201         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5202                                           1000, 100, "IPP_CFIG");
5203 }
5204
5205 static int niu_init_ipp(struct niu *np)
5206 {
5207         u64 data[5], rbuf[5], val;
5208         int i, max, err;
5209
5210         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5211                 if (np->port == 0 || np->port == 1)
5212                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
5213                 else
5214                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
5215         } else
5216                 max = NIU_DFIFO_ENTRIES;
5217
5218         data[0] = 0;
5219         data[1] = 0;
5220         data[2] = 0;
5221         data[3] = 0;
5222         data[4] = 0;
5223
5224         for (i = 0; i < max; i++) {
5225                 niu_ipp_write(np, i, data);
5226                 niu_ipp_read(np, i, rbuf);
5227         }
5228
5229         (void) nr64_ipp(IPP_INT_STAT);
5230         (void) nr64_ipp(IPP_INT_STAT);
5231
5232         err = niu_ipp_reset(np);
5233         if (err)
5234                 return err;
5235
5236         (void) nr64_ipp(IPP_PKT_DIS);
5237         (void) nr64_ipp(IPP_BAD_CS_CNT);
5238         (void) nr64_ipp(IPP_ECC);
5239
5240         (void) nr64_ipp(IPP_INT_STAT);
5241
5242         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5243
5244         val = nr64_ipp(IPP_CFIG);
5245         val &= ~IPP_CFIG_IP_MAX_PKT;
5246         val |= (IPP_CFIG_IPP_ENABLE |
5247                 IPP_CFIG_DFIFO_ECC_EN |
5248                 IPP_CFIG_DROP_BAD_CRC |
5249                 IPP_CFIG_CKSUM_EN |
5250                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5251         nw64_ipp(IPP_CFIG, val);
5252
5253         return 0;
5254 }
5255
5256 static void niu_handle_led(struct niu *np, int status)
5257 {
5258         u64 val;
5259         val = nr64_mac(XMAC_CONFIG);
5260
5261         if ((np->flags & NIU_FLAGS_10G) != 0 &&
5262             (np->flags & NIU_FLAGS_FIBER) != 0) {
5263                 if (status) {
5264                         val |= XMAC_CONFIG_LED_POLARITY;
5265                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
5266                 } else {
5267                         val |= XMAC_CONFIG_FORCE_LED_ON;
5268                         val &= ~XMAC_CONFIG_LED_POLARITY;
5269                 }
5270         }
5271
5272         nw64_mac(XMAC_CONFIG, val);
5273 }
5274
5275 static void niu_init_xif_xmac(struct niu *np)
5276 {
5277         struct niu_link_config *lp = &np->link_config;
5278         u64 val;
5279
5280         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5281                 val = nr64(MIF_CONFIG);
5282                 val |= MIF_CONFIG_ATCA_GE;
5283                 nw64(MIF_CONFIG, val);
5284         }
5285
5286         val = nr64_mac(XMAC_CONFIG);
5287         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5288
5289         val |= XMAC_CONFIG_TX_OUTPUT_EN;
5290
5291         if (lp->loopback_mode == LOOPBACK_MAC) {
5292                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5293                 val |= XMAC_CONFIG_LOOPBACK;
5294         } else {
5295                 val &= ~XMAC_CONFIG_LOOPBACK;
5296         }
5297
5298         if (np->flags & NIU_FLAGS_10G) {
5299                 val &= ~XMAC_CONFIG_LFS_DISABLE;
5300         } else {
5301                 val |= XMAC_CONFIG_LFS_DISABLE;
5302                 if (!(np->flags & NIU_FLAGS_FIBER) &&
5303                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
5304                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
5305                 else
5306                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5307         }
5308
5309         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5310
5311         if (lp->active_speed == SPEED_100)
5312                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5313         else
5314                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5315
5316         nw64_mac(XMAC_CONFIG, val);
5317
5318         val = nr64_mac(XMAC_CONFIG);
5319         val &= ~XMAC_CONFIG_MODE_MASK;
5320         if (np->flags & NIU_FLAGS_10G) {
5321                 val |= XMAC_CONFIG_MODE_XGMII;
5322         } else {
5323                 if (lp->active_speed == SPEED_1000)
5324                         val |= XMAC_CONFIG_MODE_GMII;
5325                 else
5326                         val |= XMAC_CONFIG_MODE_MII;
5327         }
5328
5329         nw64_mac(XMAC_CONFIG, val);
5330 }
5331
5332 static void niu_init_xif_bmac(struct niu *np)
5333 {
5334         struct niu_link_config *lp = &np->link_config;
5335         u64 val;
5336
5337         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5338
5339         if (lp->loopback_mode == LOOPBACK_MAC)
5340                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5341         else
5342                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5343
5344         if (lp->active_speed == SPEED_1000)
5345                 val |= BMAC_XIF_CONFIG_GMII_MODE;
5346         else
5347                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5348
5349         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5350                  BMAC_XIF_CONFIG_LED_POLARITY);
5351
5352         if (!(np->flags & NIU_FLAGS_10G) &&
5353             !(np->flags & NIU_FLAGS_FIBER) &&
5354             lp->active_speed == SPEED_100)
5355                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5356         else
5357                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5358
5359         nw64_mac(BMAC_XIF_CONFIG, val);
5360 }
5361
5362 static void niu_init_xif(struct niu *np)
5363 {
5364         if (np->flags & NIU_FLAGS_XMAC)
5365                 niu_init_xif_xmac(np);
5366         else
5367                 niu_init_xif_bmac(np);
5368 }
5369
5370 static void niu_pcs_mii_reset(struct niu *np)
5371 {
5372         int limit = 1000;
5373         u64 val = nr64_pcs(PCS_MII_CTL);
5374         val |= PCS_MII_CTL_RST;
5375         nw64_pcs(PCS_MII_CTL, val);
5376         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5377                 udelay(100);
5378                 val = nr64_pcs(PCS_MII_CTL);
5379         }
5380 }
5381
5382 static void niu_xpcs_reset(struct niu *np)
5383 {
5384         int limit = 1000;
5385         u64 val = nr64_xpcs(XPCS_CONTROL1);
5386         val |= XPCS_CONTROL1_RESET;
5387         nw64_xpcs(XPCS_CONTROL1, val);
5388         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5389                 udelay(100);
5390                 val = nr64_xpcs(XPCS_CONTROL1);
5391         }
5392 }
5393
5394 static int niu_init_pcs(struct niu *np)
5395 {
5396         struct niu_link_config *lp = &np->link_config;
5397         u64 val;
5398
5399         switch (np->flags & (NIU_FLAGS_10G |
5400                              NIU_FLAGS_FIBER |
5401                              NIU_FLAGS_XCVR_SERDES)) {
5402         case NIU_FLAGS_FIBER:
5403                 /* 1G fiber */
5404                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5405                 nw64_pcs(PCS_DPATH_MODE, 0);
5406                 niu_pcs_mii_reset(np);
5407                 break;
5408
5409         case NIU_FLAGS_10G:
5410         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5411         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5412                 /* 10G SERDES */
5413                 if (!(np->flags & NIU_FLAGS_XMAC))
5414                         return -EINVAL;
5415
5416                 /* 10G copper or fiber */
5417                 val = nr64_mac(XMAC_CONFIG);
5418                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5419                 nw64_mac(XMAC_CONFIG, val);
5420
5421                 niu_xpcs_reset(np);
5422
5423                 val = nr64_xpcs(XPCS_CONTROL1);
5424                 if (lp->loopback_mode == LOOPBACK_PHY)
5425                         val |= XPCS_CONTROL1_LOOPBACK;
5426                 else
5427                         val &= ~XPCS_CONTROL1_LOOPBACK;
5428                 nw64_xpcs(XPCS_CONTROL1, val);
5429
5430                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5431                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5432                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5433                 break;
5434
5435
5436         case NIU_FLAGS_XCVR_SERDES:
5437                 /* 1G SERDES */
5438                 niu_pcs_mii_reset(np);
5439                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5440                 nw64_pcs(PCS_DPATH_MODE, 0);
5441                 break;
5442
5443         case 0:
5444                 /* 1G copper */
5445         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5446                 /* 1G RGMII FIBER */
5447                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5448                 niu_pcs_mii_reset(np);
5449                 break;
5450
5451         default:
5452                 return -EINVAL;
5453         }
5454
5455         return 0;
5456 }
5457
5458 static int niu_reset_tx_xmac(struct niu *np)
5459 {
5460         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5461                                           (XTXMAC_SW_RST_REG_RS |
5462                                            XTXMAC_SW_RST_SOFT_RST),
5463                                           1000, 100, "XTXMAC_SW_RST");
5464 }
5465
5466 static int niu_reset_tx_bmac(struct niu *np)
5467 {
5468         int limit;
5469
5470         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5471         limit = 1000;
5472         while (--limit >= 0) {
5473                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5474                         break;
5475                 udelay(100);
5476         }
5477         if (limit < 0) {
5478                 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
5479                         "BTXMAC_SW_RST[%llx]\n",
5480                         np->port,
5481                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5482                 return -ENODEV;
5483         }
5484
5485         return 0;
5486 }
5487
5488 static int niu_reset_tx_mac(struct niu *np)
5489 {
5490         if (np->flags & NIU_FLAGS_XMAC)
5491                 return niu_reset_tx_xmac(np);
5492         else
5493                 return niu_reset_tx_bmac(np);
5494 }
5495
5496 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5497 {
5498         u64 val;
5499
5500         val = nr64_mac(XMAC_MIN);
5501         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5502                  XMAC_MIN_RX_MIN_PKT_SIZE);
5503         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5504         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5505         nw64_mac(XMAC_MIN, val);
5506
5507         nw64_mac(XMAC_MAX, max);
5508
5509         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5510
5511         val = nr64_mac(XMAC_IPG);
5512         if (np->flags & NIU_FLAGS_10G) {
5513                 val &= ~XMAC_IPG_IPG_XGMII;
5514                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5515         } else {
5516                 val &= ~XMAC_IPG_IPG_MII_GMII;
5517                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5518         }
5519         nw64_mac(XMAC_IPG, val);
5520
5521         val = nr64_mac(XMAC_CONFIG);
5522         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5523                  XMAC_CONFIG_STRETCH_MODE |
5524                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5525                  XMAC_CONFIG_TX_ENABLE);
5526         nw64_mac(XMAC_CONFIG, val);
5527
5528         nw64_mac(TXMAC_FRM_CNT, 0);
5529         nw64_mac(TXMAC_BYTE_CNT, 0);
5530 }
5531
5532 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5533 {
5534         u64 val;
5535
5536         nw64_mac(BMAC_MIN_FRAME, min);
5537         nw64_mac(BMAC_MAX_FRAME, max);
5538
5539         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5540         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5541         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5542
5543         val = nr64_mac(BTXMAC_CONFIG);
5544         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5545                  BTXMAC_CONFIG_ENABLE);
5546         nw64_mac(BTXMAC_CONFIG, val);
5547 }
5548
5549 static void niu_init_tx_mac(struct niu *np)
5550 {
5551         u64 min, max;
5552
5553         min = 64;
5554         if (np->dev->mtu > ETH_DATA_LEN)
5555                 max = 9216;
5556         else
5557                 max = 1522;
5558
5559         /* The XMAC_MIN register only accepts values for TX min which
5560          * have the low 3 bits cleared.
5561          */
5562         BUILD_BUG_ON(min & 0x7);
5563
5564         if (np->flags & NIU_FLAGS_XMAC)
5565                 niu_init_tx_xmac(np, min, max);
5566         else
5567                 niu_init_tx_bmac(np, min, max);
5568 }
5569
5570 static int niu_reset_rx_xmac(struct niu *np)
5571 {
5572         int limit;
5573
5574         nw64_mac(XRXMAC_SW_RST,
5575                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5576         limit = 1000;
5577         while (--limit >= 0) {
5578                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5579                                                  XRXMAC_SW_RST_SOFT_RST)))
5580                     break;
5581                 udelay(100);
5582         }
5583         if (limit < 0) {
5584                 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
5585                         "XRXMAC_SW_RST[%llx]\n",
5586                         np->port,
5587                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5588                 return -ENODEV;
5589         }
5590
5591         return 0;
5592 }
5593
5594 static int niu_reset_rx_bmac(struct niu *np)
5595 {
5596         int limit;
5597
5598         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5599         limit = 1000;
5600         while (--limit >= 0) {
5601                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5602                         break;
5603                 udelay(100);
5604         }
5605         if (limit < 0) {
5606                 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
5607                         "BRXMAC_SW_RST[%llx]\n",
5608                         np->port,
5609                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5610                 return -ENODEV;
5611         }
5612
5613         return 0;
5614 }
5615
5616 static int niu_reset_rx_mac(struct niu *np)
5617 {
5618         if (np->flags & NIU_FLAGS_XMAC)
5619                 return niu_reset_rx_xmac(np);
5620         else
5621                 return niu_reset_rx_bmac(np);
5622 }
5623
5624 static void niu_init_rx_xmac(struct niu *np)
5625 {
5626         struct niu_parent *parent = np->parent;
5627         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5628         int first_rdc_table = tp->first_table_num;
5629         unsigned long i;
5630         u64 val;
5631
5632         nw64_mac(XMAC_ADD_FILT0, 0);
5633         nw64_mac(XMAC_ADD_FILT1, 0);
5634         nw64_mac(XMAC_ADD_FILT2, 0);
5635         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5636         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5637         for (i = 0; i < MAC_NUM_HASH; i++)
5638                 nw64_mac(XMAC_HASH_TBL(i), 0);
5639         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5640         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5641         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5642
5643         val = nr64_mac(XMAC_CONFIG);
5644         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5645                  XMAC_CONFIG_PROMISCUOUS |
5646                  XMAC_CONFIG_PROMISC_GROUP |
5647                  XMAC_CONFIG_ERR_CHK_DIS |
5648                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5649                  XMAC_CONFIG_RESERVED_MULTICAST |
5650                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5651                  XMAC_CONFIG_ADDR_FILTER_EN |
5652                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5653                  XMAC_CONFIG_STRIP_CRC |
5654                  XMAC_CONFIG_PASS_FLOW_CTRL |
5655                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5656         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5657         nw64_mac(XMAC_CONFIG, val);
5658
5659         nw64_mac(RXMAC_BT_CNT, 0);
5660         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5661         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5662         nw64_mac(RXMAC_FRAG_CNT, 0);
5663         nw64_mac(RXMAC_HIST_CNT1, 0);
5664         nw64_mac(RXMAC_HIST_CNT2, 0);
5665         nw64_mac(RXMAC_HIST_CNT3, 0);
5666         nw64_mac(RXMAC_HIST_CNT4, 0);
5667         nw64_mac(RXMAC_HIST_CNT5, 0);
5668         nw64_mac(RXMAC_HIST_CNT6, 0);
5669         nw64_mac(RXMAC_HIST_CNT7, 0);
5670         nw64_mac(RXMAC_MPSZER_CNT, 0);
5671         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5672         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5673         nw64_mac(LINK_FAULT_CNT, 0);
5674 }
5675
5676 static void niu_init_rx_bmac(struct niu *np)
5677 {
5678         struct niu_parent *parent = np->parent;
5679         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5680         int first_rdc_table = tp->first_table_num;
5681         unsigned long i;
5682         u64 val;
5683
5684         nw64_mac(BMAC_ADD_FILT0, 0);
5685         nw64_mac(BMAC_ADD_FILT1, 0);
5686         nw64_mac(BMAC_ADD_FILT2, 0);
5687         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5688         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5689         for (i = 0; i < MAC_NUM_HASH; i++)
5690                 nw64_mac(BMAC_HASH_TBL(i), 0);
5691         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5692         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5693         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5694
5695         val = nr64_mac(BRXMAC_CONFIG);
5696         val &= ~(BRXMAC_CONFIG_ENABLE |
5697                  BRXMAC_CONFIG_STRIP_PAD |
5698                  BRXMAC_CONFIG_STRIP_FCS |
5699                  BRXMAC_CONFIG_PROMISC |
5700                  BRXMAC_CONFIG_PROMISC_GRP |
5701                  BRXMAC_CONFIG_ADDR_FILT_EN |
5702                  BRXMAC_CONFIG_DISCARD_DIS);
5703         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5704         nw64_mac(BRXMAC_CONFIG, val);
5705
5706         val = nr64_mac(BMAC_ADDR_CMPEN);
5707         val |= BMAC_ADDR_CMPEN_EN0;
5708         nw64_mac(BMAC_ADDR_CMPEN, val);
5709 }
5710
5711 static void niu_init_rx_mac(struct niu *np)
5712 {
5713         niu_set_primary_mac(np, np->dev->dev_addr);
5714
5715         if (np->flags & NIU_FLAGS_XMAC)
5716                 niu_init_rx_xmac(np);
5717         else
5718                 niu_init_rx_bmac(np);
5719 }
5720
5721 static void niu_enable_tx_xmac(struct niu *np, int on)
5722 {
5723         u64 val = nr64_mac(XMAC_CONFIG);
5724
5725         if (on)
5726                 val |= XMAC_CONFIG_TX_ENABLE;
5727         else
5728                 val &= ~XMAC_CONFIG_TX_ENABLE;
5729         nw64_mac(XMAC_CONFIG, val);
5730 }
5731
5732 static void niu_enable_tx_bmac(struct niu *np, int on)
5733 {
5734         u64 val = nr64_mac(BTXMAC_CONFIG);
5735
5736         if (on)
5737                 val |= BTXMAC_CONFIG_ENABLE;
5738         else
5739                 val &= ~BTXMAC_CONFIG_ENABLE;
5740         nw64_mac(BTXMAC_CONFIG, val);
5741 }
5742
5743 static void niu_enable_tx_mac(struct niu *np, int on)
5744 {
5745         if (np->flags & NIU_FLAGS_XMAC)
5746                 niu_enable_tx_xmac(np, on);
5747         else
5748                 niu_enable_tx_bmac(np, on);
5749 }
5750
5751 static void niu_enable_rx_xmac(struct niu *np, int on)
5752 {
5753         u64 val = nr64_mac(XMAC_CONFIG);
5754
5755         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5756                  XMAC_CONFIG_PROMISCUOUS);
5757
5758         if (np->flags & NIU_FLAGS_MCAST)
5759                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5760         if (np->flags & NIU_FLAGS_PROMISC)
5761                 val |= XMAC_CONFIG_PROMISCUOUS;
5762
5763         if (on)
5764                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5765         else
5766                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5767         nw64_mac(XMAC_CONFIG, val);
5768 }
5769
5770 static void niu_enable_rx_bmac(struct niu *np, int on)
5771 {
5772         u64 val = nr64_mac(BRXMAC_CONFIG);
5773
5774         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5775                  BRXMAC_CONFIG_PROMISC);
5776
5777         if (np->flags & NIU_FLAGS_MCAST)
5778                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5779         if (np->flags & NIU_FLAGS_PROMISC)
5780                 val |= BRXMAC_CONFIG_PROMISC;
5781
5782         if (on)
5783                 val |= BRXMAC_CONFIG_ENABLE;
5784         else
5785                 val &= ~BRXMAC_CONFIG_ENABLE;
5786         nw64_mac(BRXMAC_CONFIG, val);
5787 }
5788
5789 static void niu_enable_rx_mac(struct niu *np, int on)
5790 {
5791         if (np->flags & NIU_FLAGS_XMAC)
5792                 niu_enable_rx_xmac(np, on);
5793         else
5794                 niu_enable_rx_bmac(np, on);
5795 }
5796
5797 static int niu_init_mac(struct niu *np)
5798 {
5799         int err;
5800
5801         niu_init_xif(np);
5802         err = niu_init_pcs(np);
5803         if (err)
5804                 return err;
5805
5806         err = niu_reset_tx_mac(np);
5807         if (err)
5808                 return err;
5809         niu_init_tx_mac(np);
5810         err = niu_reset_rx_mac(np);
5811         if (err)
5812                 return err;
5813         niu_init_rx_mac(np);
5814
5815         /* This looks hookey but the RX MAC reset we just did will
5816          * undo some of the state we setup in niu_init_tx_mac() so we
5817          * have to call it again.  In particular, the RX MAC reset will
5818          * set the XMAC_MAX register back to it's default value.
5819          */
5820         niu_init_tx_mac(np);
5821         niu_enable_tx_mac(np, 1);
5822
5823         niu_enable_rx_mac(np, 1);
5824
5825         return 0;
5826 }
5827
5828 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5829 {
5830         (void) niu_tx_channel_stop(np, rp->tx_channel);
5831 }
5832
5833 static void niu_stop_tx_channels(struct niu *np)
5834 {
5835         int i;
5836
5837         for (i = 0; i < np->num_tx_rings; i++) {
5838                 struct tx_ring_info *rp = &np->tx_rings[i];
5839
5840                 niu_stop_one_tx_channel(np, rp);
5841         }
5842 }
5843
5844 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5845 {
5846         (void) niu_tx_channel_reset(np, rp->tx_channel);
5847 }
5848
5849 static void niu_reset_tx_channels(struct niu *np)
5850 {
5851         int i;
5852
5853         for (i = 0; i < np->num_tx_rings; i++) {
5854                 struct tx_ring_info *rp = &np->tx_rings[i];
5855
5856                 niu_reset_one_tx_channel(np, rp);
5857         }
5858 }
5859
5860 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5861 {
5862         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5863 }
5864
5865 static void niu_stop_rx_channels(struct niu *np)
5866 {
5867         int i;
5868
5869         for (i = 0; i < np->num_rx_rings; i++) {
5870                 struct rx_ring_info *rp = &np->rx_rings[i];
5871
5872                 niu_stop_one_rx_channel(np, rp);
5873         }
5874 }
5875
5876 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5877 {
5878         int channel = rp->rx_channel;
5879
5880         (void) niu_rx_channel_reset(np, channel);
5881         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5882         nw64(RX_DMA_CTL_STAT(channel), 0);
5883         (void) niu_enable_rx_channel(np, channel, 0);
5884 }
5885
5886 static void niu_reset_rx_channels(struct niu *np)
5887 {
5888         int i;
5889
5890         for (i = 0; i < np->num_rx_rings; i++) {
5891                 struct rx_ring_info *rp = &np->rx_rings[i];
5892
5893                 niu_reset_one_rx_channel(np, rp);
5894         }
5895 }
5896
5897 static void niu_disable_ipp(struct niu *np)
5898 {
5899         u64 rd, wr, val;
5900         int limit;
5901
5902         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5903         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5904         limit = 100;
5905         while (--limit >= 0 && (rd != wr)) {
5906                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5907                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5908         }
5909         if (limit < 0 &&
5910             (rd != 0 && wr != 1)) {
5911                 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5912                         "rd_ptr[%llx] wr_ptr[%llx]\n",
5913                         np->dev->name,
5914                         (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5915                         (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5916         }
5917
5918         val = nr64_ipp(IPP_CFIG);
5919         val &= ~(IPP_CFIG_IPP_ENABLE |
5920                  IPP_CFIG_DFIFO_ECC_EN |
5921                  IPP_CFIG_DROP_BAD_CRC |
5922                  IPP_CFIG_CKSUM_EN);
5923         nw64_ipp(IPP_CFIG, val);
5924
5925         (void) niu_ipp_reset(np);
5926 }
5927
5928 static int niu_init_hw(struct niu *np)
5929 {
5930         int i, err;
5931
5932         niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5933         niu_txc_enable_port(np, 1);
5934         niu_txc_port_dma_enable(np, 1);
5935         niu_txc_set_imask(np, 0);
5936
5937         niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5938         for (i = 0; i < np->num_tx_rings; i++) {
5939                 struct tx_ring_info *rp = &np->tx_rings[i];
5940
5941                 err = niu_init_one_tx_channel(np, rp);
5942                 if (err)
5943                         return err;
5944         }
5945
5946         niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
5947         err = niu_init_rx_channels(np);
5948         if (err)
5949                 goto out_uninit_tx_channels;
5950
5951         niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
5952         err = niu_init_classifier_hw(np);
5953         if (err)
5954                 goto out_uninit_rx_channels;
5955
5956         niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
5957         err = niu_init_zcp(np);
5958         if (err)
5959                 goto out_uninit_rx_channels;
5960
5961         niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
5962         err = niu_init_ipp(np);
5963         if (err)
5964                 goto out_uninit_rx_channels;
5965
5966         niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
5967         err = niu_init_mac(np);
5968         if (err)
5969                 goto out_uninit_ipp;
5970
5971         return 0;
5972
5973 out_uninit_ipp:
5974         niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
5975         niu_disable_ipp(np);
5976
5977 out_uninit_rx_channels:
5978         niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
5979         niu_stop_rx_channels(np);
5980         niu_reset_rx_channels(np);
5981
5982 out_uninit_tx_channels:
5983         niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
5984         niu_stop_tx_channels(np);
5985         niu_reset_tx_channels(np);
5986
5987         return err;
5988 }
5989
5990 static void niu_stop_hw(struct niu *np)
5991 {
5992         niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
5993         niu_enable_interrupts(np, 0);
5994
5995         niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
5996         niu_enable_rx_mac(np, 0);
5997
5998         niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
5999         niu_disable_ipp(np);
6000
6001         niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
6002         niu_stop_tx_channels(np);
6003
6004         niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
6005         niu_stop_rx_channels(np);
6006
6007         niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
6008         niu_reset_tx_channels(np);
6009
6010         niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
6011         niu_reset_rx_channels(np);
6012 }
6013
6014 static void niu_set_irq_name(struct niu *np)
6015 {
6016         int port = np->port;
6017         int i, j = 1;
6018
6019         sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6020
6021         if (port == 0) {
6022                 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6023                 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6024                 j = 3;
6025         }
6026
6027         for (i = 0; i < np->num_ldg - j; i++) {
6028                 if (i < np->num_rx_rings)
6029                         sprintf(np->irq_name[i+j], "%s-rx-%d",
6030                                 np->dev->name, i);
6031                 else if (i < np->num_tx_rings + np->num_rx_rings)
6032                         sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6033                                 i - np->num_rx_rings);
6034         }
6035 }
6036
6037 static int niu_request_irq(struct niu *np)
6038 {
6039         int i, j, err;
6040
6041         niu_set_irq_name(np);
6042
6043         err = 0;
6044         for (i = 0; i < np->num_ldg; i++) {
6045                 struct niu_ldg *lp = &np->ldg[i];
6046
6047                 err = request_irq(lp->irq, niu_interrupt,
6048                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6049                                   np->irq_name[i], lp);
6050                 if (err)
6051                         goto out_free_irqs;
6052
6053         }
6054
6055         return 0;
6056
6057 out_free_irqs:
6058         for (j = 0; j < i; j++) {
6059                 struct niu_ldg *lp = &np->ldg[j];
6060
6061                 free_irq(lp->irq, lp);
6062         }
6063         return err;
6064 }
6065
6066 static void niu_free_irq(struct niu *np)
6067 {
6068         int i;
6069
6070         for (i = 0; i < np->num_ldg; i++) {
6071                 struct niu_ldg *lp = &np->ldg[i];
6072
6073                 free_irq(lp->irq, lp);
6074         }
6075 }
6076
6077 static void niu_enable_napi(struct niu *np)
6078 {
6079         int i;
6080
6081         for (i = 0; i < np->num_ldg; i++)
6082                 napi_enable(&np->ldg[i].napi);
6083 }
6084
6085 static void niu_disable_napi(struct niu *np)
6086 {
6087         int i;
6088
6089         for (i = 0; i < np->num_ldg; i++)
6090                 napi_disable(&np->ldg[i].napi);
6091 }
6092
6093 static int niu_open(struct net_device *dev)
6094 {
6095         struct niu *np = netdev_priv(dev);
6096         int err;
6097
6098         netif_carrier_off(dev);
6099
6100         err = niu_alloc_channels(np);
6101         if (err)
6102                 goto out_err;
6103
6104         err = niu_enable_interrupts(np, 0);
6105         if (err)
6106                 goto out_free_channels;
6107
6108         err = niu_request_irq(np);
6109         if (err)
6110                 goto out_free_channels;
6111
6112         niu_enable_napi(np);
6113
6114         spin_lock_irq(&np->lock);
6115
6116         err = niu_init_hw(np);
6117         if (!err) {
6118                 init_timer(&np->timer);
6119                 np->timer.expires = jiffies + HZ;
6120                 np->timer.data = (unsigned long) np;
6121                 np->timer.function = niu_timer;
6122
6123                 err = niu_enable_interrupts(np, 1);
6124                 if (err)
6125                         niu_stop_hw(np);
6126         }
6127
6128         spin_unlock_irq(&np->lock);
6129
6130         if (err) {
6131                 niu_disable_napi(np);
6132                 goto out_free_irq;
6133         }
6134
6135         netif_tx_start_all_queues(dev);
6136
6137         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6138                 netif_carrier_on(dev);
6139
6140         add_timer(&np->timer);
6141
6142         return 0;
6143
6144 out_free_irq:
6145         niu_free_irq(np);
6146
6147 out_free_channels:
6148         niu_free_channels(np);
6149
6150 out_err:
6151         return err;
6152 }
6153
6154 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6155 {
6156         cancel_work_sync(&np->reset_task);
6157
6158         niu_disable_napi(np);
6159         netif_tx_stop_all_queues(dev);
6160
6161         del_timer_sync(&np->timer);
6162
6163         spin_lock_irq(&np->lock);
6164
6165         niu_stop_hw(np);
6166
6167         spin_unlock_irq(&np->lock);
6168 }
6169
6170 static int niu_close(struct net_device *dev)
6171 {
6172         struct niu *np = netdev_priv(dev);
6173
6174         niu_full_shutdown(np, dev);
6175
6176         niu_free_irq(np);
6177
6178         niu_free_channels(np);
6179
6180         niu_handle_led(np, 0);
6181
6182         return 0;
6183 }
6184
6185 static void niu_sync_xmac_stats(struct niu *np)
6186 {
6187         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6188
6189         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6190         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6191
6192         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6193         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6194         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6195         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6196         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6197         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6198         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6199         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6200         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6201         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6202         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6203         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6204         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6205         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6206         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6207         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6208 }
6209
6210 static void niu_sync_bmac_stats(struct niu *np)
6211 {
6212         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6213
6214         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6215         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6216
6217         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6218         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6219         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6220         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6221 }
6222
6223 static void niu_sync_mac_stats(struct niu *np)
6224 {
6225         if (np->flags & NIU_FLAGS_XMAC)
6226                 niu_sync_xmac_stats(np);
6227         else
6228                 niu_sync_bmac_stats(np);
6229 }
6230
6231 static void niu_get_rx_stats(struct niu *np)
6232 {
6233         unsigned long pkts, dropped, errors, bytes;
6234         int i;
6235
6236         pkts = dropped = errors = bytes = 0;
6237         for (i = 0; i < np->num_rx_rings; i++) {
6238                 struct rx_ring_info *rp = &np->rx_rings[i];
6239
6240                 niu_sync_rx_discard_stats(np, rp, 0);
6241
6242                 pkts += rp->rx_packets;
6243                 bytes += rp->rx_bytes;
6244                 dropped += rp->rx_dropped;
6245                 errors += rp->rx_errors;
6246         }
6247         np->dev->stats.rx_packets = pkts;
6248         np->dev->stats.rx_bytes = bytes;
6249         np->dev->stats.rx_dropped = dropped;
6250         np->dev->stats.rx_errors = errors;
6251 }
6252
6253 static void niu_get_tx_stats(struct niu *np)
6254 {
6255         unsigned long pkts, errors, bytes;
6256         int i;
6257
6258         pkts = errors = bytes = 0;
6259         for (i = 0; i < np->num_tx_rings; i++) {
6260                 struct tx_ring_info *rp = &np->tx_rings[i];
6261
6262                 pkts += rp->tx_packets;
6263                 bytes += rp->tx_bytes;
6264                 errors += rp->tx_errors;
6265         }
6266         np->dev->stats.tx_packets = pkts;
6267         np->dev->stats.tx_bytes = bytes;
6268         np->dev->stats.tx_errors = errors;
6269 }
6270
6271 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6272 {
6273         struct niu *np = netdev_priv(dev);
6274
6275         niu_get_rx_stats(np);
6276         niu_get_tx_stats(np);
6277
6278         return &dev->stats;
6279 }
6280
6281 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6282 {
6283         int i;
6284
6285         for (i = 0; i < 16; i++)
6286                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6287 }
6288
6289 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6290 {
6291         int i;
6292
6293         for (i = 0; i < 16; i++)
6294                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6295 }
6296
6297 static void niu_load_hash(struct niu *np, u16 *hash)
6298 {
6299         if (np->flags & NIU_FLAGS_XMAC)
6300                 niu_load_hash_xmac(np, hash);
6301         else
6302                 niu_load_hash_bmac(np, hash);
6303 }
6304
6305 static void niu_set_rx_mode(struct net_device *dev)
6306 {
6307         struct niu *np = netdev_priv(dev);
6308         int i, alt_cnt, err;
6309         struct dev_addr_list *addr;
6310         unsigned long flags;
6311         u16 hash[16] = { 0, };
6312
6313         spin_lock_irqsave(&np->lock, flags);
6314         niu_enable_rx_mac(np, 0);
6315
6316         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6317         if (dev->flags & IFF_PROMISC)
6318                 np->flags |= NIU_FLAGS_PROMISC;
6319         if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
6320                 np->flags |= NIU_FLAGS_MCAST;
6321
6322         alt_cnt = dev->uc_count;
6323         if (alt_cnt > niu_num_alt_addr(np)) {
6324                 alt_cnt = 0;
6325                 np->flags |= NIU_FLAGS_PROMISC;
6326         }
6327
6328         if (alt_cnt) {
6329                 int index = 0;
6330
6331                 for (addr = dev->uc_list; addr; addr = addr->next) {
6332                         err = niu_set_alt_mac(np, index,
6333                                               addr->da_addr);
6334                         if (err)
6335                                 printk(KERN_WARNING PFX "%s: Error %d "
6336                                        "adding alt mac %d\n",
6337                                        dev->name, err, index);
6338                         err = niu_enable_alt_mac(np, index, 1);
6339                         if (err)
6340                                 printk(KERN_WARNING PFX "%s: Error %d "
6341                                        "enabling alt mac %d\n",
6342                                        dev->name, err, index);
6343
6344                         index++;
6345                 }
6346         } else {
6347                 int alt_start;
6348                 if (np->flags & NIU_FLAGS_XMAC)
6349                         alt_start = 0;
6350                 else
6351                         alt_start = 1;
6352                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6353                         err = niu_enable_alt_mac(np, i, 0);
6354                         if (err)
6355                                 printk(KERN_WARNING PFX "%s: Error %d "
6356                                        "disabling alt mac %d\n",
6357                                        dev->name, err, i);
6358                 }
6359         }
6360         if (dev->flags & IFF_ALLMULTI) {
6361                 for (i = 0; i < 16; i++)
6362                         hash[i] = 0xffff;
6363         } else if (dev->mc_count > 0) {
6364                 for (addr = dev->mc_list; addr; addr = addr->next) {
6365                         u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
6366
6367                         crc >>= 24;
6368                         hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6369                 }
6370         }
6371
6372         if (np->flags & NIU_FLAGS_MCAST)
6373                 niu_load_hash(np, hash);
6374
6375         niu_enable_rx_mac(np, 1);
6376         spin_unlock_irqrestore(&np->lock, flags);
6377 }
6378
6379 static int niu_set_mac_addr(struct net_device *dev, void *p)
6380 {
6381         struct niu *np = netdev_priv(dev);
6382         struct sockaddr *addr = p;
6383         unsigned long flags;
6384
6385         if (!is_valid_ether_addr(addr->sa_data))
6386                 return -EINVAL;
6387
6388         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6389
6390         if (!netif_running(dev))
6391                 return 0;
6392
6393         spin_lock_irqsave(&np->lock, flags);
6394         niu_enable_rx_mac(np, 0);
6395         niu_set_primary_mac(np, dev->dev_addr);
6396         niu_enable_rx_mac(np, 1);
6397         spin_unlock_irqrestore(&np->lock, flags);
6398
6399         return 0;
6400 }
6401
6402 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6403 {
6404         return -EOPNOTSUPP;
6405 }
6406
6407 static void niu_netif_stop(struct niu *np)
6408 {
6409         np->dev->trans_start = jiffies; /* prevent tx timeout */
6410
6411         niu_disable_napi(np);
6412
6413         netif_tx_disable(np->dev);
6414 }
6415
6416 static void niu_netif_start(struct niu *np)
6417 {
6418         /* NOTE: unconditional netif_wake_queue is only appropriate
6419          * so long as all callers are assured to have free tx slots
6420          * (such as after niu_init_hw).
6421          */
6422         netif_tx_wake_all_queues(np->dev);
6423
6424         niu_enable_napi(np);
6425
6426         niu_enable_interrupts(np, 1);
6427 }
6428
6429 static void niu_reset_buffers(struct niu *np)
6430 {
6431         int i, j, k, err;
6432
6433         if (np->rx_rings) {
6434                 for (i = 0; i < np->num_rx_rings; i++) {
6435                         struct rx_ring_info *rp = &np->rx_rings[i];
6436
6437                         for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6438                                 struct page *page;
6439
6440                                 page = rp->rxhash[j];
6441                                 while (page) {
6442                                         struct page *next =
6443                                                 (struct page *) page->mapping;
6444                                         u64 base = page->index;
6445                                         base = base >> RBR_DESCR_ADDR_SHIFT;
6446                                         rp->rbr[k++] = cpu_to_le32(base);
6447                                         page = next;
6448                                 }
6449                         }
6450                         for (; k < MAX_RBR_RING_SIZE; k++) {
6451                                 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6452                                 if (unlikely(err))
6453                                         break;
6454                         }
6455
6456                         rp->rbr_index = rp->rbr_table_size - 1;
6457                         rp->rcr_index = 0;
6458                         rp->rbr_pending = 0;
6459                         rp->rbr_refill_pending = 0;
6460                 }
6461         }
6462         if (np->tx_rings) {
6463                 for (i = 0; i < np->num_tx_rings; i++) {
6464                         struct tx_ring_info *rp = &np->tx_rings[i];
6465
6466                         for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6467                                 if (rp->tx_buffs[j].skb)
6468                                         (void) release_tx_packet(np, rp, j);
6469                         }
6470
6471                         rp->pending = MAX_TX_RING_SIZE;
6472                         rp->prod = 0;
6473                         rp->cons = 0;
6474                         rp->wrap_bit = 0;
6475                 }
6476         }
6477 }
6478
6479 static void niu_reset_task(struct work_struct *work)
6480 {
6481         struct niu *np = container_of(work, struct niu, reset_task);
6482         unsigned long flags;
6483         int err;
6484
6485         spin_lock_irqsave(&np->lock, flags);
6486         if (!netif_running(np->dev)) {
6487                 spin_unlock_irqrestore(&np->lock, flags);
6488                 return;
6489         }
6490
6491         spin_unlock_irqrestore(&np->lock, flags);
6492
6493         del_timer_sync(&np->timer);
6494
6495         niu_netif_stop(np);
6496
6497         spin_lock_irqsave(&np->lock, flags);
6498
6499         niu_stop_hw(np);
6500
6501         spin_unlock_irqrestore(&np->lock, flags);
6502
6503         niu_reset_buffers(np);
6504
6505         spin_lock_irqsave(&np->lock, flags);
6506
6507         err = niu_init_hw(np);
6508         if (!err) {
6509                 np->timer.expires = jiffies + HZ;
6510                 add_timer(&np->timer);
6511                 niu_netif_start(np);
6512         }
6513
6514         spin_unlock_irqrestore(&np->lock, flags);
6515 }
6516
6517 static void niu_tx_timeout(struct net_device *dev)
6518 {
6519         struct niu *np = netdev_priv(dev);
6520
6521         dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
6522                 dev->name);
6523
6524         schedule_work(&np->reset_task);
6525 }
6526
6527 static void niu_set_txd(struct tx_ring_info *rp, int index,
6528                         u64 mapping, u64 len, u64 mark,
6529                         u64 n_frags)
6530 {
6531         __le64 *desc = &rp->descr[index];
6532
6533         *desc = cpu_to_le64(mark |
6534                             (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6535                             (len << TX_DESC_TR_LEN_SHIFT) |
6536                             (mapping & TX_DESC_SAD));
6537 }
6538
6539 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6540                                 u64 pad_bytes, u64 len)
6541 {
6542         u16 eth_proto, eth_proto_inner;
6543         u64 csum_bits, l3off, ihl, ret;
6544         u8 ip_proto;
6545         int ipv6;
6546
6547         eth_proto = be16_to_cpu(ehdr->h_proto);
6548         eth_proto_inner = eth_proto;
6549         if (eth_proto == ETH_P_8021Q) {
6550                 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6551                 __be16 val = vp->h_vlan_encapsulated_proto;
6552
6553                 eth_proto_inner = be16_to_cpu(val);
6554         }
6555
6556         ipv6 = ihl = 0;
6557         switch (skb->protocol) {
6558         case cpu_to_be16(ETH_P_IP):
6559                 ip_proto = ip_hdr(skb)->protocol;
6560                 ihl = ip_hdr(skb)->ihl;
6561                 break;
6562         case cpu_to_be16(ETH_P_IPV6):
6563                 ip_proto = ipv6_hdr(skb)->nexthdr;
6564                 ihl = (40 >> 2);
6565                 ipv6 = 1;
6566                 break;
6567         default:
6568                 ip_proto = ihl = 0;
6569                 break;
6570         }
6571
6572         csum_bits = TXHDR_CSUM_NONE;
6573         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6574                 u64 start, stuff;
6575
6576                 csum_bits = (ip_proto == IPPROTO_TCP ?
6577                              TXHDR_CSUM_TCP :
6578                              (ip_proto == IPPROTO_UDP ?
6579                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6580
6581                 start = skb_transport_offset(skb) -
6582                         (pad_bytes + sizeof(struct tx_pkt_hdr));
6583                 stuff = start + skb->csum_offset;
6584
6585                 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6586                 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6587         }
6588
6589         l3off = skb_network_offset(skb) -
6590                 (pad_bytes + sizeof(struct tx_pkt_hdr));
6591
6592         ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6593                (len << TXHDR_LEN_SHIFT) |
6594                ((l3off / 2) << TXHDR_L3START_SHIFT) |
6595                (ihl << TXHDR_IHL_SHIFT) |
6596                ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6597                ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6598                (ipv6 ? TXHDR_IP_VER : 0) |
6599                csum_bits);
6600
6601         return ret;
6602 }
6603
6604 static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6605 {
6606         struct niu *np = netdev_priv(dev);
6607         unsigned long align, headroom;
6608         struct netdev_queue *txq;
6609         struct tx_ring_info *rp;
6610         struct tx_pkt_hdr *tp;
6611         unsigned int len, nfg;
6612         struct ethhdr *ehdr;
6613         int prod, i, tlen;
6614         u64 mapping, mrk;
6615
6616         i = skb_get_queue_mapping(skb);
6617         rp = &np->tx_rings[i];
6618         txq = netdev_get_tx_queue(dev, i);
6619
6620         if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6621                 netif_tx_stop_queue(txq);
6622                 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
6623                         "queue awake!\n", dev->name);
6624                 rp->tx_errors++;
6625                 return NETDEV_TX_BUSY;
6626         }
6627
6628         if (skb->len < ETH_ZLEN) {
6629                 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6630
6631                 if (skb_pad(skb, pad_bytes))
6632                         goto out;
6633                 skb_put(skb, pad_bytes);
6634         }
6635
6636         len = sizeof(struct tx_pkt_hdr) + 15;
6637         if (skb_headroom(skb) < len) {
6638                 struct sk_buff *skb_new;
6639
6640                 skb_new = skb_realloc_headroom(skb, len);
6641                 if (!skb_new) {
6642                         rp->tx_errors++;
6643                         goto out_drop;
6644                 }
6645                 kfree_skb(skb);
6646                 skb = skb_new;
6647         } else
6648                 skb_orphan(skb);
6649
6650         align = ((unsigned long) skb->data & (16 - 1));
6651         headroom = align + sizeof(struct tx_pkt_hdr);
6652
6653         ehdr = (struct ethhdr *) skb->data;
6654         tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6655
6656         len = skb->len - sizeof(struct tx_pkt_hdr);
6657         tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6658         tp->resv = 0;
6659
6660         len = skb_headlen(skb);
6661         mapping = np->ops->map_single(np->device, skb->data,
6662                                       len, DMA_TO_DEVICE);
6663
6664         prod = rp->prod;
6665
6666         rp->tx_buffs[prod].skb = skb;
6667         rp->tx_buffs[prod].mapping = mapping;
6668
6669         mrk = TX_DESC_SOP;
6670         if (++rp->mark_counter == rp->mark_freq) {
6671                 rp->mark_counter = 0;
6672                 mrk |= TX_DESC_MARK;
6673                 rp->mark_pending++;
6674         }
6675
6676         tlen = len;
6677         nfg = skb_shinfo(skb)->nr_frags;
6678         while (tlen > 0) {
6679                 tlen -= MAX_TX_DESC_LEN;
6680                 nfg++;
6681         }
6682
6683         while (len > 0) {
6684                 unsigned int this_len = len;
6685
6686                 if (this_len > MAX_TX_DESC_LEN)
6687                         this_len = MAX_TX_DESC_LEN;
6688
6689                 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6690                 mrk = nfg = 0;
6691
6692                 prod = NEXT_TX(rp, prod);
6693                 mapping += this_len;
6694                 len -= this_len;
6695         }
6696
6697         for (i = 0; i <  skb_shinfo(skb)->nr_frags; i++) {
6698                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6699
6700                 len = frag->size;
6701                 mapping = np->ops->map_page(np->device, frag->page,
6702                                             frag->page_offset, len,
6703                                             DMA_TO_DEVICE);
6704
6705                 rp->tx_buffs[prod].skb = NULL;
6706                 rp->tx_buffs[prod].mapping = mapping;
6707
6708                 niu_set_txd(rp, prod, mapping, len, 0, 0);
6709
6710                 prod = NEXT_TX(rp, prod);
6711         }
6712
6713         if (prod < rp->prod)
6714                 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6715         rp->prod = prod;
6716
6717         nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6718
6719         if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6720                 netif_tx_stop_queue(txq);
6721                 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6722                         netif_tx_wake_queue(txq);
6723         }
6724
6725         dev->trans_start = jiffies;
6726
6727 out:
6728         return NETDEV_TX_OK;
6729
6730 out_drop:
6731         rp->tx_errors++;
6732         kfree_skb(skb);
6733         goto out;
6734 }
6735
6736 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6737 {
6738         struct niu *np = netdev_priv(dev);
6739         int err, orig_jumbo, new_jumbo;
6740
6741         if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6742                 return -EINVAL;
6743
6744         orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6745         new_jumbo = (new_mtu > ETH_DATA_LEN);
6746
6747         dev->mtu = new_mtu;
6748
6749         if (!netif_running(dev) ||
6750             (orig_jumbo == new_jumbo))
6751                 return 0;
6752
6753         niu_full_shutdown(np, dev);
6754
6755         niu_free_channels(np);
6756
6757         niu_enable_napi(np);
6758
6759         err = niu_alloc_channels(np);
6760         if (err)
6761                 return err;
6762
6763         spin_lock_irq(&np->lock);
6764
6765         err = niu_init_hw(np);
6766         if (!err) {
6767                 init_timer(&np->timer);
6768                 np->timer.expires = jiffies + HZ;
6769                 np->timer.data = (unsigned long) np;
6770                 np->timer.function = niu_timer;
6771
6772                 err = niu_enable_interrupts(np, 1);
6773                 if (err)
6774                         niu_stop_hw(np);
6775         }
6776
6777         spin_unlock_irq(&np->lock);
6778
6779         if (!err) {
6780                 netif_tx_start_all_queues(dev);
6781                 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6782                         netif_carrier_on(dev);
6783
6784                 add_timer(&np->timer);
6785         }
6786
6787         return err;
6788 }
6789
6790 static void niu_get_drvinfo(struct net_device *dev,
6791                             struct ethtool_drvinfo *info)
6792 {
6793         struct niu *np = netdev_priv(dev);
6794         struct niu_vpd *vpd = &np->vpd;
6795
6796         strcpy(info->driver, DRV_MODULE_NAME);
6797         strcpy(info->version, DRV_MODULE_VERSION);
6798         sprintf(info->fw_version, "%d.%d",
6799                 vpd->fcode_major, vpd->fcode_minor);
6800         if (np->parent->plat_type != PLAT_TYPE_NIU)
6801                 strcpy(info->bus_info, pci_name(np->pdev));
6802 }
6803
6804 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6805 {
6806         struct niu *np = netdev_priv(dev);
6807         struct niu_link_config *lp;
6808
6809         lp = &np->link_config;
6810
6811         memset(cmd, 0, sizeof(*cmd));
6812         cmd->phy_address = np->phy_addr;
6813         cmd->supported = lp->supported;
6814         cmd->advertising = lp->active_advertising;
6815         cmd->autoneg = lp->active_autoneg;
6816         cmd->speed = lp->active_speed;
6817         cmd->duplex = lp->active_duplex;
6818         cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6819         cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6820                 XCVR_EXTERNAL : XCVR_INTERNAL;
6821
6822         return 0;
6823 }
6824
6825 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6826 {
6827         struct niu *np = netdev_priv(dev);
6828         struct niu_link_config *lp = &np->link_config;
6829
6830         lp->advertising = cmd->advertising;
6831         lp->speed = cmd->speed;
6832         lp->duplex = cmd->duplex;
6833         lp->autoneg = cmd->autoneg;
6834         return niu_init_link(np);
6835 }
6836
6837 static u32 niu_get_msglevel(struct net_device *dev)
6838 {
6839         struct niu *np = netdev_priv(dev);
6840         return np->msg_enable;
6841 }
6842
6843 static void niu_set_msglevel(struct net_device *dev, u32 value)
6844 {
6845         struct niu *np = netdev_priv(dev);
6846         np->msg_enable = value;
6847 }
6848
6849 static int niu_nway_reset(struct net_device *dev)
6850 {
6851         struct niu *np = netdev_priv(dev);
6852
6853         if (np->link_config.autoneg)
6854                 return niu_init_link(np);
6855
6856         return 0;
6857 }
6858
6859 static int niu_get_eeprom_len(struct net_device *dev)
6860 {
6861         struct niu *np = netdev_priv(dev);
6862
6863         return np->eeprom_len;
6864 }
6865
6866 static int niu_get_eeprom(struct net_device *dev,
6867                           struct ethtool_eeprom *eeprom, u8 *data)
6868 {
6869         struct niu *np = netdev_priv(dev);
6870         u32 offset, len, val;
6871
6872         offset = eeprom->offset;
6873         len = eeprom->len;
6874
6875         if (offset + len < offset)
6876                 return -EINVAL;
6877         if (offset >= np->eeprom_len)
6878                 return -EINVAL;
6879         if (offset + len > np->eeprom_len)
6880                 len = eeprom->len = np->eeprom_len - offset;
6881
6882         if (offset & 3) {
6883                 u32 b_offset, b_count;
6884
6885                 b_offset = offset & 3;
6886                 b_count = 4 - b_offset;
6887                 if (b_count > len)
6888                         b_count = len;
6889
6890                 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6891                 memcpy(data, ((char *)&val) + b_offset, b_count);
6892                 data += b_count;
6893                 len -= b_count;
6894                 offset += b_count;
6895         }
6896         while (len >= 4) {
6897                 val = nr64(ESPC_NCR(offset / 4));
6898                 memcpy(data, &val, 4);
6899                 data += 4;
6900                 len -= 4;
6901                 offset += 4;
6902         }
6903         if (len) {
6904                 val = nr64(ESPC_NCR(offset / 4));
6905                 memcpy(data, &val, len);
6906         }
6907         return 0;
6908 }
6909
6910 static int niu_ethflow_to_class(int flow_type, u64 *class)
6911 {
6912         switch (flow_type) {
6913         case TCP_V4_FLOW:
6914                 *class = CLASS_CODE_TCP_IPV4;
6915                 break;
6916         case UDP_V4_FLOW:
6917                 *class = CLASS_CODE_UDP_IPV4;
6918                 break;
6919         case AH_ESP_V4_FLOW:
6920                 *class = CLASS_CODE_AH_ESP_IPV4;
6921                 break;
6922         case SCTP_V4_FLOW:
6923                 *class = CLASS_CODE_SCTP_IPV4;
6924                 break;
6925         case TCP_V6_FLOW:
6926                 *class = CLASS_CODE_TCP_IPV6;
6927                 break;
6928         case UDP_V6_FLOW:
6929                 *class = CLASS_CODE_UDP_IPV6;
6930                 break;
6931         case AH_ESP_V6_FLOW:
6932                 *class = CLASS_CODE_AH_ESP_IPV6;
6933                 break;
6934         case SCTP_V6_FLOW:
6935                 *class = CLASS_CODE_SCTP_IPV6;
6936                 break;
6937         default:
6938                 return 0;
6939         }
6940
6941         return 1;
6942 }
6943
6944 static u64 niu_flowkey_to_ethflow(u64 flow_key)
6945 {
6946         u64 ethflow = 0;
6947
6948         if (flow_key & FLOW_KEY_PORT)
6949                 ethflow |= RXH_DEV_PORT;
6950         if (flow_key & FLOW_KEY_L2DA)
6951                 ethflow |= RXH_L2DA;
6952         if (flow_key & FLOW_KEY_VLAN)
6953                 ethflow |= RXH_VLAN;
6954         if (flow_key & FLOW_KEY_IPSA)
6955                 ethflow |= RXH_IP_SRC;
6956         if (flow_key & FLOW_KEY_IPDA)
6957                 ethflow |= RXH_IP_DST;
6958         if (flow_key & FLOW_KEY_PROTO)
6959                 ethflow |= RXH_L3_PROTO;
6960         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
6961                 ethflow |= RXH_L4_B_0_1;
6962         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
6963                 ethflow |= RXH_L4_B_2_3;
6964
6965         return ethflow;
6966
6967 }
6968
6969 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
6970 {
6971         u64 key = 0;
6972
6973         if (ethflow & RXH_DEV_PORT)
6974                 key |= FLOW_KEY_PORT;
6975         if (ethflow & RXH_L2DA)
6976                 key |= FLOW_KEY_L2DA;
6977         if (ethflow & RXH_VLAN)
6978                 key |= FLOW_KEY_VLAN;
6979         if (ethflow & RXH_IP_SRC)
6980                 key |= FLOW_KEY_IPSA;
6981         if (ethflow & RXH_IP_DST)
6982                 key |= FLOW_KEY_IPDA;
6983         if (ethflow & RXH_L3_PROTO)
6984                 key |= FLOW_KEY_PROTO;
6985         if (ethflow & RXH_L4_B_0_1)
6986                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
6987         if (ethflow & RXH_L4_B_2_3)
6988                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
6989
6990         *flow_key = key;
6991
6992         return 1;
6993
6994 }
6995
6996 static int niu_get_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6997 {
6998         struct niu *np = netdev_priv(dev);
6999         u64 class;
7000
7001         cmd->data = 0;
7002
7003         if (!niu_ethflow_to_class(cmd->flow_type, &class))
7004                 return -EINVAL;
7005
7006         if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7007             TCAM_KEY_DISC)
7008                 cmd->data = RXH_DISCARD;
7009         else
7010
7011                 cmd->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7012                                                       CLASS_CODE_USER_PROG1]);
7013         return 0;
7014 }
7015
7016 static int niu_set_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
7017 {
7018         struct niu *np = netdev_priv(dev);
7019         u64 class;
7020         u64 flow_key = 0;
7021         unsigned long flags;
7022
7023         if (!niu_ethflow_to_class(cmd->flow_type, &class))
7024                 return -EINVAL;
7025
7026         if (class < CLASS_CODE_USER_PROG1 ||
7027             class > CLASS_CODE_SCTP_IPV6)
7028                 return -EINVAL;
7029
7030         if (cmd->data & RXH_DISCARD) {
7031                 niu_lock_parent(np, flags);
7032                 flow_key = np->parent->tcam_key[class -
7033                                                CLASS_CODE_USER_PROG1];
7034                 flow_key |= TCAM_KEY_DISC;
7035                 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7036                 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7037                 niu_unlock_parent(np, flags);
7038                 return 0;
7039         } else {
7040                 /* Discard was set before, but is not set now */
7041                 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7042                     TCAM_KEY_DISC) {
7043                         niu_lock_parent(np, flags);
7044                         flow_key = np->parent->tcam_key[class -
7045                                                CLASS_CODE_USER_PROG1];
7046                         flow_key &= ~TCAM_KEY_DISC;
7047                         nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7048                              flow_key);
7049                         np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7050                                 flow_key;
7051                         niu_unlock_parent(np, flags);
7052                 }
7053         }
7054
7055         if (!niu_ethflow_to_flowkey(cmd->data, &flow_key))
7056                 return -EINVAL;
7057
7058         niu_lock_parent(np, flags);
7059         nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7060         np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7061         niu_unlock_parent(np, flags);
7062
7063         return 0;
7064 }
7065
7066 static const struct {
7067         const char string[ETH_GSTRING_LEN];
7068 } niu_xmac_stat_keys[] = {
7069         { "tx_frames" },
7070         { "tx_bytes" },
7071         { "tx_fifo_errors" },
7072         { "tx_overflow_errors" },
7073         { "tx_max_pkt_size_errors" },
7074         { "tx_underflow_errors" },
7075         { "rx_local_faults" },
7076         { "rx_remote_faults" },
7077         { "rx_link_faults" },
7078         { "rx_align_errors" },
7079         { "rx_frags" },
7080         { "rx_mcasts" },
7081         { "rx_bcasts" },
7082         { "rx_hist_cnt1" },
7083         { "rx_hist_cnt2" },
7084         { "rx_hist_cnt3" },
7085         { "rx_hist_cnt4" },
7086         { "rx_hist_cnt5" },
7087         { "rx_hist_cnt6" },
7088         { "rx_hist_cnt7" },
7089         { "rx_octets" },
7090         { "rx_code_violations" },
7091         { "rx_len_errors" },
7092         { "rx_crc_errors" },
7093         { "rx_underflows" },
7094         { "rx_overflows" },
7095         { "pause_off_state" },
7096         { "pause_on_state" },
7097         { "pause_received" },
7098 };
7099
7100 #define NUM_XMAC_STAT_KEYS      ARRAY_SIZE(niu_xmac_stat_keys)
7101
7102 static const struct {
7103         const char string[ETH_GSTRING_LEN];
7104 } niu_bmac_stat_keys[] = {
7105         { "tx_underflow_errors" },
7106         { "tx_max_pkt_size_errors" },
7107         { "tx_bytes" },
7108         { "tx_frames" },
7109         { "rx_overflows" },
7110         { "rx_frames" },
7111         { "rx_align_errors" },
7112         { "rx_crc_errors" },
7113         { "rx_len_errors" },
7114         { "pause_off_state" },
7115         { "pause_on_state" },
7116         { "pause_received" },
7117 };
7118
7119 #define NUM_BMAC_STAT_KEYS      ARRAY_SIZE(niu_bmac_stat_keys)
7120
7121 static const struct {
7122         const char string[ETH_GSTRING_LEN];
7123 } niu_rxchan_stat_keys[] = {
7124         { "rx_channel" },
7125         { "rx_packets" },
7126         { "rx_bytes" },
7127         { "rx_dropped" },
7128         { "rx_errors" },
7129 };
7130
7131 #define NUM_RXCHAN_STAT_KEYS    ARRAY_SIZE(niu_rxchan_stat_keys)
7132
7133 static const struct {
7134         const char string[ETH_GSTRING_LEN];
7135 } niu_txchan_stat_keys[] = {
7136         { "tx_channel" },
7137         { "tx_packets" },
7138         { "tx_bytes" },
7139         { "tx_errors" },
7140 };
7141
7142 #define NUM_TXCHAN_STAT_KEYS    ARRAY_SIZE(niu_txchan_stat_keys)
7143
7144 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7145 {
7146         struct niu *np = netdev_priv(dev);
7147         int i;
7148
7149         if (stringset != ETH_SS_STATS)
7150                 return;
7151
7152         if (np->flags & NIU_FLAGS_XMAC) {
7153                 memcpy(data, niu_xmac_stat_keys,
7154                        sizeof(niu_xmac_stat_keys));
7155                 data += sizeof(niu_xmac_stat_keys);
7156         } else {
7157                 memcpy(data, niu_bmac_stat_keys,
7158                        sizeof(niu_bmac_stat_keys));
7159                 data += sizeof(niu_bmac_stat_keys);
7160         }
7161         for (i = 0; i < np->num_rx_rings; i++) {
7162                 memcpy(data, niu_rxchan_stat_keys,
7163                        sizeof(niu_rxchan_stat_keys));
7164                 data += sizeof(niu_rxchan_stat_keys);
7165         }
7166         for (i = 0; i < np->num_tx_rings; i++) {
7167                 memcpy(data, niu_txchan_stat_keys,
7168                        sizeof(niu_txchan_stat_keys));
7169                 data += sizeof(niu_txchan_stat_keys);
7170         }
7171 }
7172
7173 static int niu_get_stats_count(struct net_device *dev)
7174 {
7175         struct niu *np = netdev_priv(dev);
7176
7177         return ((np->flags & NIU_FLAGS_XMAC ?
7178                  NUM_XMAC_STAT_KEYS :
7179                  NUM_BMAC_STAT_KEYS) +
7180                 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7181                 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7182 }
7183
7184 static void niu_get_ethtool_stats(struct net_device *dev,
7185                                   struct ethtool_stats *stats, u64 *data)
7186 {
7187         struct niu *np = netdev_priv(dev);
7188         int i;
7189
7190         niu_sync_mac_stats(np);
7191         if (np->flags & NIU_FLAGS_XMAC) {
7192                 memcpy(data, &np->mac_stats.xmac,
7193                        sizeof(struct niu_xmac_stats));
7194                 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7195         } else {
7196                 memcpy(data, &np->mac_stats.bmac,
7197                        sizeof(struct niu_bmac_stats));
7198                 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7199         }
7200         for (i = 0; i < np->num_rx_rings; i++) {
7201                 struct rx_ring_info *rp = &np->rx_rings[i];
7202
7203                 niu_sync_rx_discard_stats(np, rp, 0);
7204
7205                 data[0] = rp->rx_channel;
7206                 data[1] = rp->rx_packets;
7207                 data[2] = rp->rx_bytes;
7208                 data[3] = rp->rx_dropped;
7209                 data[4] = rp->rx_errors;
7210                 data += 5;
7211         }
7212         for (i = 0; i < np->num_tx_rings; i++) {
7213                 struct tx_ring_info *rp = &np->tx_rings[i];
7214
7215                 data[0] = rp->tx_channel;
7216                 data[1] = rp->tx_packets;
7217                 data[2] = rp->tx_bytes;
7218                 data[3] = rp->tx_errors;
7219                 data += 4;
7220         }
7221 }
7222
7223 static u64 niu_led_state_save(struct niu *np)
7224 {
7225         if (np->flags & NIU_FLAGS_XMAC)
7226                 return nr64_mac(XMAC_CONFIG);
7227         else
7228                 return nr64_mac(BMAC_XIF_CONFIG);
7229 }
7230
7231 static void niu_led_state_restore(struct niu *np, u64 val)
7232 {
7233         if (np->flags & NIU_FLAGS_XMAC)
7234                 nw64_mac(XMAC_CONFIG, val);
7235         else
7236                 nw64_mac(BMAC_XIF_CONFIG, val);
7237 }
7238
7239 static void niu_force_led(struct niu *np, int on)
7240 {
7241         u64 val, reg, bit;
7242
7243         if (np->flags & NIU_FLAGS_XMAC) {
7244                 reg = XMAC_CONFIG;
7245                 bit = XMAC_CONFIG_FORCE_LED_ON;
7246         } else {
7247                 reg = BMAC_XIF_CONFIG;
7248                 bit = BMAC_XIF_CONFIG_LINK_LED;
7249         }
7250
7251         val = nr64_mac(reg);
7252         if (on)
7253                 val |= bit;
7254         else
7255                 val &= ~bit;
7256         nw64_mac(reg, val);
7257 }
7258
7259 static int niu_phys_id(struct net_device *dev, u32 data)
7260 {
7261         struct niu *np = netdev_priv(dev);
7262         u64 orig_led_state;
7263         int i;
7264
7265         if (!netif_running(dev))
7266                 return -EAGAIN;
7267
7268         if (data == 0)
7269                 data = 2;
7270
7271         orig_led_state = niu_led_state_save(np);
7272         for (i = 0; i < (data * 2); i++) {
7273                 int on = ((i % 2) == 0);
7274
7275                 niu_force_led(np, on);
7276
7277                 if (msleep_interruptible(500))
7278                         break;
7279         }
7280         niu_led_state_restore(np, orig_led_state);
7281
7282         return 0;
7283 }
7284
7285 static const struct ethtool_ops niu_ethtool_ops = {
7286         .get_drvinfo            = niu_get_drvinfo,
7287         .get_link               = ethtool_op_get_link,
7288         .get_msglevel           = niu_get_msglevel,
7289         .set_msglevel           = niu_set_msglevel,
7290         .nway_reset             = niu_nway_reset,
7291         .get_eeprom_len         = niu_get_eeprom_len,
7292         .get_eeprom             = niu_get_eeprom,
7293         .get_settings           = niu_get_settings,
7294         .set_settings           = niu_set_settings,
7295         .get_strings            = niu_get_strings,
7296         .get_stats_count        = niu_get_stats_count,
7297         .get_ethtool_stats      = niu_get_ethtool_stats,
7298         .phys_id                = niu_phys_id,
7299         .get_rxhash             = niu_get_hash_opts,
7300         .set_rxhash             = niu_set_hash_opts,
7301 };
7302
7303 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7304                               int ldg, int ldn)
7305 {
7306         if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7307                 return -EINVAL;
7308         if (ldn < 0 || ldn > LDN_MAX)
7309                 return -EINVAL;
7310
7311         parent->ldg_map[ldn] = ldg;
7312
7313         if (np->parent->plat_type == PLAT_TYPE_NIU) {
7314                 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7315                  * the firmware, and we're not supposed to change them.
7316                  * Validate the mapping, because if it's wrong we probably
7317                  * won't get any interrupts and that's painful to debug.
7318                  */
7319                 if (nr64(LDG_NUM(ldn)) != ldg) {
7320                         dev_err(np->device, PFX "Port %u, mis-matched "
7321                                 "LDG assignment "
7322                                 "for ldn %d, should be %d is %llu\n",
7323                                 np->port, ldn, ldg,
7324                                 (unsigned long long) nr64(LDG_NUM(ldn)));
7325                         return -EINVAL;
7326                 }
7327         } else
7328                 nw64(LDG_NUM(ldn), ldg);
7329
7330         return 0;
7331 }
7332
7333 static int niu_set_ldg_timer_res(struct niu *np, int res)
7334 {
7335         if (res < 0 || res > LDG_TIMER_RES_VAL)
7336                 return -EINVAL;
7337
7338
7339         nw64(LDG_TIMER_RES, res);
7340
7341         return 0;
7342 }
7343
7344 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7345 {
7346         if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7347             (func < 0 || func > 3) ||
7348             (vector < 0 || vector > 0x1f))
7349                 return -EINVAL;
7350
7351         nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7352
7353         return 0;
7354 }
7355
7356 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7357 {
7358         u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7359                                  (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7360         int limit;
7361
7362         if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7363                 return -EINVAL;
7364
7365         frame = frame_base;
7366         nw64(ESPC_PIO_STAT, frame);
7367         limit = 64;
7368         do {
7369                 udelay(5);
7370                 frame = nr64(ESPC_PIO_STAT);
7371                 if (frame & ESPC_PIO_STAT_READ_END)
7372                         break;
7373         } while (limit--);
7374         if (!(frame & ESPC_PIO_STAT_READ_END)) {
7375                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
7376                         (unsigned long long) frame);
7377                 return -ENODEV;
7378         }
7379
7380         frame = frame_base;
7381         nw64(ESPC_PIO_STAT, frame);
7382         limit = 64;
7383         do {
7384                 udelay(5);
7385                 frame = nr64(ESPC_PIO_STAT);
7386                 if (frame & ESPC_PIO_STAT_READ_END)
7387                         break;
7388         } while (limit--);
7389         if (!(frame & ESPC_PIO_STAT_READ_END)) {
7390                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
7391                         (unsigned long long) frame);
7392                 return -ENODEV;
7393         }
7394
7395         frame = nr64(ESPC_PIO_STAT);
7396         return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
7397 }
7398
7399 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
7400 {
7401         int err = niu_pci_eeprom_read(np, off);
7402         u16 val;
7403
7404         if (err < 0)
7405                 return err;
7406         val = (err << 8);
7407         err = niu_pci_eeprom_read(np, off + 1);
7408         if (err < 0)
7409                 return err;
7410         val |= (err & 0xff);
7411
7412         return val;
7413 }
7414
7415 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
7416 {
7417         int err = niu_pci_eeprom_read(np, off);
7418         u16 val;
7419
7420         if (err < 0)
7421                 return err;
7422
7423         val = (err & 0xff);
7424         err = niu_pci_eeprom_read(np, off + 1);
7425         if (err < 0)
7426                 return err;
7427
7428         val |= (err & 0xff) << 8;
7429
7430         return val;
7431 }
7432
7433 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
7434                                               u32 off,
7435                                               char *namebuf,
7436                                               int namebuf_len)
7437 {
7438         int i;
7439
7440         for (i = 0; i < namebuf_len; i++) {
7441                 int err = niu_pci_eeprom_read(np, off + i);
7442                 if (err < 0)
7443                         return err;
7444                 *namebuf++ = err;
7445                 if (!err)
7446                         break;
7447         }
7448         if (i >= namebuf_len)
7449                 return -EINVAL;
7450
7451         return i + 1;
7452 }
7453
7454 static void __devinit niu_vpd_parse_version(struct niu *np)
7455 {
7456         struct niu_vpd *vpd = &np->vpd;
7457         int len = strlen(vpd->version) + 1;
7458         const char *s = vpd->version;
7459         int i;
7460
7461         for (i = 0; i < len - 5; i++) {
7462                 if (!strncmp(s + i, "FCode ", 5))
7463                         break;
7464         }
7465         if (i >= len - 5)
7466                 return;
7467
7468         s += i + 5;
7469         sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
7470
7471         niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
7472                vpd->fcode_major, vpd->fcode_minor);
7473         if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
7474             (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
7475              vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
7476                 np->flags |= NIU_FLAGS_VPD_VALID;
7477 }
7478
7479 /* ESPC_PIO_EN_ENABLE must be set */
7480 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
7481                                             u32 start, u32 end)
7482 {
7483         unsigned int found_mask = 0;
7484 #define FOUND_MASK_MODEL        0x00000001
7485 #define FOUND_MASK_BMODEL       0x00000002
7486 #define FOUND_MASK_VERS         0x00000004
7487 #define FOUND_MASK_MAC          0x00000008
7488 #define FOUND_MASK_NMAC         0x00000010
7489 #define FOUND_MASK_PHY          0x00000020
7490 #define FOUND_MASK_ALL          0x0000003f
7491
7492         niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
7493                start, end);
7494         while (start < end) {
7495                 int len, err, instance, type, prop_len;
7496                 char namebuf[64];
7497                 u8 *prop_buf;
7498                 int max_len;
7499
7500                 if (found_mask == FOUND_MASK_ALL) {
7501                         niu_vpd_parse_version(np);
7502                         return 1;
7503                 }
7504
7505                 err = niu_pci_eeprom_read(np, start + 2);
7506                 if (err < 0)
7507                         return err;
7508                 len = err;
7509                 start += 3;
7510
7511                 instance = niu_pci_eeprom_read(np, start);
7512                 type = niu_pci_eeprom_read(np, start + 3);
7513                 prop_len = niu_pci_eeprom_read(np, start + 4);
7514                 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
7515                 if (err < 0)
7516                         return err;
7517
7518                 prop_buf = NULL;
7519                 max_len = 0;
7520                 if (!strcmp(namebuf, "model")) {
7521                         prop_buf = np->vpd.model;
7522                         max_len = NIU_VPD_MODEL_MAX;
7523                         found_mask |= FOUND_MASK_MODEL;
7524                 } else if (!strcmp(namebuf, "board-model")) {
7525                         prop_buf = np->vpd.board_model;
7526                         max_len = NIU_VPD_BD_MODEL_MAX;
7527                         found_mask |= FOUND_MASK_BMODEL;
7528                 } else if (!strcmp(namebuf, "version")) {
7529                         prop_buf = np->vpd.version;
7530                         max_len = NIU_VPD_VERSION_MAX;
7531                         found_mask |= FOUND_MASK_VERS;
7532                 } else if (!strcmp(namebuf, "local-mac-address")) {
7533                         prop_buf = np->vpd.local_mac;
7534                         max_len = ETH_ALEN;
7535                         found_mask |= FOUND_MASK_MAC;
7536                 } else if (!strcmp(namebuf, "num-mac-addresses")) {
7537                         prop_buf = &np->vpd.mac_num;
7538                         max_len = 1;
7539                         found_mask |= FOUND_MASK_NMAC;
7540                 } else if (!strcmp(namebuf, "phy-type")) {
7541                         prop_buf = np->vpd.phy_type;
7542                         max_len = NIU_VPD_PHY_TYPE_MAX;
7543                         found_mask |= FOUND_MASK_PHY;
7544                 }
7545
7546                 if (max_len && prop_len > max_len) {
7547                         dev_err(np->device, PFX "Property '%s' length (%d) is "
7548                                 "too long.\n", namebuf, prop_len);
7549                         return -EINVAL;
7550                 }
7551
7552                 if (prop_buf) {
7553                         u32 off = start + 5 + err;
7554                         int i;
7555
7556                         niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
7557                                "len[%d]\n", namebuf, prop_len);
7558                         for (i = 0; i < prop_len; i++)
7559                                 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
7560                 }
7561
7562                 start += len;
7563         }
7564
7565         return 0;
7566 }
7567
7568 /* ESPC_PIO_EN_ENABLE must be set */
7569 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
7570 {
7571         u32 offset;
7572         int err;
7573
7574         err = niu_pci_eeprom_read16_swp(np, start + 1);
7575         if (err < 0)
7576                 return;
7577
7578         offset = err + 3;
7579
7580         while (start + offset < ESPC_EEPROM_SIZE) {
7581                 u32 here = start + offset;
7582                 u32 end;
7583
7584                 err = niu_pci_eeprom_read(np, here);
7585                 if (err != 0x90)
7586                         return;
7587
7588                 err = niu_pci_eeprom_read16_swp(np, here + 1);
7589                 if (err < 0)
7590                         return;
7591
7592                 here = start + offset + 3;
7593                 end = start + offset + err;
7594
7595                 offset += err;
7596
7597                 err = niu_pci_vpd_scan_props(np, here, end);
7598                 if (err < 0 || err == 1)
7599                         return;
7600         }
7601 }
7602
7603 /* ESPC_PIO_EN_ENABLE must be set */
7604 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
7605 {
7606         u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
7607         int err;
7608
7609         while (start < end) {
7610                 ret = start;
7611
7612                 /* ROM header signature?  */
7613                 err = niu_pci_eeprom_read16(np, start +  0);
7614                 if (err != 0x55aa)
7615                         return 0;
7616
7617                 /* Apply offset to PCI data structure.  */
7618                 err = niu_pci_eeprom_read16(np, start + 23);
7619                 if (err < 0)
7620                         return 0;
7621                 start += err;
7622
7623                 /* Check for "PCIR" signature.  */
7624                 err = niu_pci_eeprom_read16(np, start +  0);
7625                 if (err != 0x5043)
7626                         return 0;
7627                 err = niu_pci_eeprom_read16(np, start +  2);
7628                 if (err != 0x4952)
7629                         return 0;
7630
7631                 /* Check for OBP image type.  */
7632                 err = niu_pci_eeprom_read(np, start + 20);
7633                 if (err < 0)
7634                         return 0;
7635                 if (err != 0x01) {
7636                         err = niu_pci_eeprom_read(np, ret + 2);
7637                         if (err < 0)
7638                                 return 0;
7639
7640                         start = ret + (err * 512);
7641                         continue;
7642                 }
7643
7644                 err = niu_pci_eeprom_read16_swp(np, start + 8);
7645                 if (err < 0)
7646                         return err;
7647                 ret += err;
7648
7649                 err = niu_pci_eeprom_read(np, ret + 0);
7650                 if (err != 0x82)
7651                         return 0;
7652
7653                 return ret;
7654         }
7655
7656         return 0;
7657 }
7658
7659 static int __devinit niu_phy_type_prop_decode(struct niu *np,
7660                                               const char *phy_prop)
7661 {
7662         if (!strcmp(phy_prop, "mif")) {
7663                 /* 1G copper, MII */
7664                 np->flags &= ~(NIU_FLAGS_FIBER |
7665                                NIU_FLAGS_10G);
7666                 np->mac_xcvr = MAC_XCVR_MII;
7667         } else if (!strcmp(phy_prop, "xgf")) {
7668                 /* 10G fiber, XPCS */
7669                 np->flags |= (NIU_FLAGS_10G |
7670                               NIU_FLAGS_FIBER);
7671                 np->mac_xcvr = MAC_XCVR_XPCS;
7672         } else if (!strcmp(phy_prop, "pcs")) {
7673                 /* 1G fiber, PCS */
7674                 np->flags &= ~NIU_FLAGS_10G;
7675                 np->flags |= NIU_FLAGS_FIBER;
7676                 np->mac_xcvr = MAC_XCVR_PCS;
7677         } else if (!strcmp(phy_prop, "xgc")) {
7678                 /* 10G copper, XPCS */
7679                 np->flags |= NIU_FLAGS_10G;
7680                 np->flags &= ~NIU_FLAGS_FIBER;
7681                 np->mac_xcvr = MAC_XCVR_XPCS;
7682         } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
7683                 /* 10G Serdes or 1G Serdes, default to 10G */
7684                 np->flags |= NIU_FLAGS_10G;
7685                 np->flags &= ~NIU_FLAGS_FIBER;
7686                 np->flags |= NIU_FLAGS_XCVR_SERDES;
7687                 np->mac_xcvr = MAC_XCVR_XPCS;
7688         } else {
7689                 return -EINVAL;
7690         }
7691         return 0;
7692 }
7693
7694 static int niu_pci_vpd_get_nports(struct niu *np)
7695 {
7696         int ports = 0;
7697
7698         if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
7699             (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
7700             (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
7701             (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
7702             (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7703                 ports = 4;
7704         } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
7705                    (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
7706                    (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
7707                    (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7708                 ports = 2;
7709         }
7710
7711         return ports;
7712 }
7713
7714 static void __devinit niu_pci_vpd_validate(struct niu *np)
7715 {
7716         struct net_device *dev = np->dev;
7717         struct niu_vpd *vpd = &np->vpd;
7718         u8 val8;
7719
7720         if (!is_valid_ether_addr(&vpd->local_mac[0])) {
7721                 dev_err(np->device, PFX "VPD MAC invalid, "
7722                         "falling back to SPROM.\n");
7723
7724                 np->flags &= ~NIU_FLAGS_VPD_VALID;
7725                 return;
7726         }
7727
7728         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
7729             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
7730                 np->flags |= NIU_FLAGS_10G;
7731                 np->flags &= ~NIU_FLAGS_FIBER;
7732                 np->flags |= NIU_FLAGS_XCVR_SERDES;
7733                 np->mac_xcvr = MAC_XCVR_PCS;
7734                 if (np->port > 1) {
7735                         np->flags |= NIU_FLAGS_FIBER;
7736                         np->flags &= ~NIU_FLAGS_10G;
7737                 }
7738                 if (np->flags & NIU_FLAGS_10G)
7739                          np->mac_xcvr = MAC_XCVR_XPCS;
7740         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
7741                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
7742                               NIU_FLAGS_HOTPLUG_PHY);
7743         } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
7744                 dev_err(np->device, PFX "Illegal phy string [%s].\n",
7745                         np->vpd.phy_type);
7746                 dev_err(np->device, PFX "Falling back to SPROM.\n");
7747                 np->flags &= ~NIU_FLAGS_VPD_VALID;
7748                 return;
7749         }
7750
7751         memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
7752
7753         val8 = dev->perm_addr[5];
7754         dev->perm_addr[5] += np->port;
7755         if (dev->perm_addr[5] < val8)
7756                 dev->perm_addr[4]++;
7757
7758         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7759 }
7760
7761 static int __devinit niu_pci_probe_sprom(struct niu *np)
7762 {
7763         struct net_device *dev = np->dev;
7764         int len, i;
7765         u64 val, sum;
7766         u8 val8;
7767
7768         val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
7769         val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
7770         len = val / 4;
7771
7772         np->eeprom_len = len;
7773
7774         niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
7775
7776         sum = 0;
7777         for (i = 0; i < len; i++) {
7778                 val = nr64(ESPC_NCR(i));
7779                 sum += (val >>  0) & 0xff;
7780                 sum += (val >>  8) & 0xff;
7781                 sum += (val >> 16) & 0xff;
7782                 sum += (val >> 24) & 0xff;
7783         }
7784         niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
7785         if ((sum & 0xff) != 0xab) {
7786                 dev_err(np->device, PFX "Bad SPROM checksum "
7787                         "(%x, should be 0xab)\n", (int) (sum & 0xff));
7788                 return -EINVAL;
7789         }
7790
7791         val = nr64(ESPC_PHY_TYPE);
7792         switch (np->port) {
7793         case 0:
7794                 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
7795                         ESPC_PHY_TYPE_PORT0_SHIFT;
7796                 break;
7797         case 1:
7798                 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
7799                         ESPC_PHY_TYPE_PORT1_SHIFT;
7800                 break;
7801         case 2:
7802                 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
7803                         ESPC_PHY_TYPE_PORT2_SHIFT;
7804                 break;
7805         case 3:
7806                 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
7807                         ESPC_PHY_TYPE_PORT3_SHIFT;
7808                 break;
7809         default:
7810                 dev_err(np->device, PFX "Bogus port number %u\n",
7811                         np->port);
7812                 return -EINVAL;
7813         }
7814         niudbg(PROBE, "SPROM: PHY type %x\n", val8);
7815
7816         switch (val8) {
7817         case ESPC_PHY_TYPE_1G_COPPER:
7818                 /* 1G copper, MII */
7819                 np->flags &= ~(NIU_FLAGS_FIBER |
7820                                NIU_FLAGS_10G);
7821                 np->mac_xcvr = MAC_XCVR_MII;
7822                 break;
7823
7824         case ESPC_PHY_TYPE_1G_FIBER:
7825                 /* 1G fiber, PCS */
7826                 np->flags &= ~NIU_FLAGS_10G;
7827                 np->flags |= NIU_FLAGS_FIBER;
7828                 np->mac_xcvr = MAC_XCVR_PCS;
7829                 break;
7830
7831         case ESPC_PHY_TYPE_10G_COPPER:
7832                 /* 10G copper, XPCS */
7833                 np->flags |= NIU_FLAGS_10G;
7834                 np->flags &= ~NIU_FLAGS_FIBER;
7835                 np->mac_xcvr = MAC_XCVR_XPCS;
7836                 break;
7837
7838         case ESPC_PHY_TYPE_10G_FIBER:
7839                 /* 10G fiber, XPCS */
7840                 np->flags |= (NIU_FLAGS_10G |
7841                               NIU_FLAGS_FIBER);
7842                 np->mac_xcvr = MAC_XCVR_XPCS;
7843                 break;
7844
7845         default:
7846                 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
7847                 return -EINVAL;
7848         }
7849
7850         val = nr64(ESPC_MAC_ADDR0);
7851         niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
7852                (unsigned long long) val);
7853         dev->perm_addr[0] = (val >>  0) & 0xff;
7854         dev->perm_addr[1] = (val >>  8) & 0xff;
7855         dev->perm_addr[2] = (val >> 16) & 0xff;
7856         dev->perm_addr[3] = (val >> 24) & 0xff;
7857
7858         val = nr64(ESPC_MAC_ADDR1);
7859         niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
7860                (unsigned long long) val);
7861         dev->perm_addr[4] = (val >>  0) & 0xff;
7862         dev->perm_addr[5] = (val >>  8) & 0xff;
7863
7864         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
7865                 dev_err(np->device, PFX "SPROM MAC address invalid\n");
7866                 dev_err(np->device, PFX "[ \n");
7867                 for (i = 0; i < 6; i++)
7868                         printk("%02x ", dev->perm_addr[i]);
7869                 printk("]\n");
7870                 return -EINVAL;
7871         }
7872
7873         val8 = dev->perm_addr[5];
7874         dev->perm_addr[5] += np->port;
7875         if (dev->perm_addr[5] < val8)
7876                 dev->perm_addr[4]++;
7877
7878         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7879
7880         val = nr64(ESPC_MOD_STR_LEN);
7881         niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
7882                (unsigned long long) val);
7883         if (val >= 8 * 4)
7884                 return -EINVAL;
7885
7886         for (i = 0; i < val; i += 4) {
7887                 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
7888
7889                 np->vpd.model[i + 3] = (tmp >>  0) & 0xff;
7890                 np->vpd.model[i + 2] = (tmp >>  8) & 0xff;
7891                 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
7892                 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
7893         }
7894         np->vpd.model[val] = '\0';
7895
7896         val = nr64(ESPC_BD_MOD_STR_LEN);
7897         niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
7898                (unsigned long long) val);
7899         if (val >= 4 * 4)
7900                 return -EINVAL;
7901
7902         for (i = 0; i < val; i += 4) {
7903                 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
7904
7905                 np->vpd.board_model[i + 3] = (tmp >>  0) & 0xff;
7906                 np->vpd.board_model[i + 2] = (tmp >>  8) & 0xff;
7907                 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
7908                 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
7909         }
7910         np->vpd.board_model[val] = '\0';
7911
7912         np->vpd.mac_num =
7913                 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
7914         niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
7915                np->vpd.mac_num);
7916
7917         return 0;
7918 }
7919
7920 static int __devinit niu_get_and_validate_port(struct niu *np)
7921 {
7922         struct niu_parent *parent = np->parent;
7923
7924         if (np->port <= 1)
7925                 np->flags |= NIU_FLAGS_XMAC;
7926
7927         if (!parent->num_ports) {
7928                 if (parent->plat_type == PLAT_TYPE_NIU) {
7929                         parent->num_ports = 2;
7930                 } else {
7931                         parent->num_ports = niu_pci_vpd_get_nports(np);
7932                         if (!parent->num_ports) {
7933                                 /* Fall back to SPROM as last resort.
7934                                  * This will fail on most cards.
7935                                  */
7936                                 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
7937                                         ESPC_NUM_PORTS_MACS_VAL;
7938
7939                                 /* All of the current probing methods fail on
7940                                  * Maramba on-board parts.
7941                                  */
7942                                 if (!parent->num_ports)
7943                                         parent->num_ports = 4;
7944                         }
7945                 }
7946         }
7947
7948         niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
7949                np->port, parent->num_ports);
7950         if (np->port >= parent->num_ports)
7951                 return -ENODEV;
7952
7953         return 0;
7954 }
7955
7956 static int __devinit phy_record(struct niu_parent *parent,
7957                                 struct phy_probe_info *p,
7958                                 int dev_id_1, int dev_id_2, u8 phy_port,
7959                                 int type)
7960 {
7961         u32 id = (dev_id_1 << 16) | dev_id_2;
7962         u8 idx;
7963
7964         if (dev_id_1 < 0 || dev_id_2 < 0)
7965                 return 0;
7966         if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
7967                 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
7968                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
7969                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
7970                         return 0;
7971         } else {
7972                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
7973                         return 0;
7974         }
7975
7976         pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
7977                 parent->index, id,
7978                 (type == PHY_TYPE_PMA_PMD ?
7979                  "PMA/PMD" :
7980                  (type == PHY_TYPE_PCS ?
7981                   "PCS" : "MII")),
7982                 phy_port);
7983
7984         if (p->cur[type] >= NIU_MAX_PORTS) {
7985                 printk(KERN_ERR PFX "Too many PHY ports.\n");
7986                 return -EINVAL;
7987         }
7988         idx = p->cur[type];
7989         p->phy_id[type][idx] = id;
7990         p->phy_port[type][idx] = phy_port;
7991         p->cur[type] = idx + 1;
7992         return 0;
7993 }
7994
7995 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
7996 {
7997         int i;
7998
7999         for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8000                 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8001                         return 1;
8002         }
8003         for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8004                 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8005                         return 1;
8006         }
8007
8008         return 0;
8009 }
8010
8011 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8012 {
8013         int port, cnt;
8014
8015         cnt = 0;
8016         *lowest = 32;
8017         for (port = 8; port < 32; port++) {
8018                 if (port_has_10g(p, port)) {
8019                         if (!cnt)
8020                                 *lowest = port;
8021                         cnt++;
8022                 }
8023         }
8024
8025         return cnt;
8026 }
8027
8028 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8029 {
8030         *lowest = 32;
8031         if (p->cur[PHY_TYPE_MII])
8032                 *lowest = p->phy_port[PHY_TYPE_MII][0];
8033
8034         return p->cur[PHY_TYPE_MII];
8035 }
8036
8037 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8038 {
8039         int num_ports = parent->num_ports;
8040         int i;
8041
8042         for (i = 0; i < num_ports; i++) {
8043                 parent->rxchan_per_port[i] = (16 / num_ports);
8044                 parent->txchan_per_port[i] = (16 / num_ports);
8045
8046                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
8047                         "[%u TX chans]\n",
8048                         parent->index, i,
8049                         parent->rxchan_per_port[i],
8050                         parent->txchan_per_port[i]);
8051         }
8052 }
8053
8054 static void __devinit niu_divide_channels(struct niu_parent *parent,
8055                                           int num_10g, int num_1g)
8056 {
8057         int num_ports = parent->num_ports;
8058         int rx_chans_per_10g, rx_chans_per_1g;
8059         int tx_chans_per_10g, tx_chans_per_1g;
8060         int i, tot_rx, tot_tx;
8061
8062         if (!num_10g || !num_1g) {
8063                 rx_chans_per_10g = rx_chans_per_1g =
8064                         (NIU_NUM_RXCHAN / num_ports);
8065                 tx_chans_per_10g = tx_chans_per_1g =
8066                         (NIU_NUM_TXCHAN / num_ports);
8067         } else {
8068                 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8069                 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8070                                     (rx_chans_per_1g * num_1g)) /
8071                         num_10g;
8072
8073                 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8074                 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8075                                     (tx_chans_per_1g * num_1g)) /
8076                         num_10g;
8077         }
8078
8079         tot_rx = tot_tx = 0;
8080         for (i = 0; i < num_ports; i++) {
8081                 int type = phy_decode(parent->port_phy, i);
8082
8083                 if (type == PORT_TYPE_10G) {
8084                         parent->rxchan_per_port[i] = rx_chans_per_10g;
8085                         parent->txchan_per_port[i] = tx_chans_per_10g;
8086                 } else {
8087                         parent->rxchan_per_port[i] = rx_chans_per_1g;
8088                         parent->txchan_per_port[i] = tx_chans_per_1g;
8089                 }
8090                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
8091                         "[%u TX chans]\n",
8092                         parent->index, i,
8093                         parent->rxchan_per_port[i],
8094                         parent->txchan_per_port[i]);
8095                 tot_rx += parent->rxchan_per_port[i];
8096                 tot_tx += parent->txchan_per_port[i];
8097         }
8098
8099         if (tot_rx > NIU_NUM_RXCHAN) {
8100                 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
8101                        "resetting to one per port.\n",
8102                        parent->index, tot_rx);
8103                 for (i = 0; i < num_ports; i++)
8104                         parent->rxchan_per_port[i] = 1;
8105         }
8106         if (tot_tx > NIU_NUM_TXCHAN) {
8107                 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
8108                        "resetting to one per port.\n",
8109                        parent->index, tot_tx);
8110                 for (i = 0; i < num_ports; i++)
8111                         parent->txchan_per_port[i] = 1;
8112         }
8113         if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8114                 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
8115                        "RX[%d] TX[%d]\n",
8116                        parent->index, tot_rx, tot_tx);
8117         }
8118 }
8119
8120 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8121                                             int num_10g, int num_1g)
8122 {
8123         int i, num_ports = parent->num_ports;
8124         int rdc_group, rdc_groups_per_port;
8125         int rdc_channel_base;
8126
8127         rdc_group = 0;
8128         rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8129
8130         rdc_channel_base = 0;
8131
8132         for (i = 0; i < num_ports; i++) {
8133                 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8134                 int grp, num_channels = parent->rxchan_per_port[i];
8135                 int this_channel_offset;
8136
8137                 tp->first_table_num = rdc_group;
8138                 tp->num_tables = rdc_groups_per_port;
8139                 this_channel_offset = 0;
8140                 for (grp = 0; grp < tp->num_tables; grp++) {
8141                         struct rdc_table *rt = &tp->tables[grp];
8142                         int slot;
8143
8144                         pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
8145                                 parent->index, i, tp->first_table_num + grp);
8146                         for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8147                                 rt->rxdma_channel[slot] =
8148                                         rdc_channel_base + this_channel_offset;
8149
8150                                 printk("%d ", rt->rxdma_channel[slot]);
8151
8152                                 if (++this_channel_offset == num_channels)
8153                                         this_channel_offset = 0;
8154                         }
8155                         printk("]\n");
8156                 }
8157
8158                 parent->rdc_default[i] = rdc_channel_base;
8159
8160                 rdc_channel_base += num_channels;
8161                 rdc_group += rdc_groups_per_port;
8162         }
8163 }
8164
8165 static int __devinit fill_phy_probe_info(struct niu *np,
8166                                          struct niu_parent *parent,
8167                                          struct phy_probe_info *info)
8168 {
8169         unsigned long flags;
8170         int port, err;
8171
8172         memset(info, 0, sizeof(*info));
8173
8174         /* Port 0 to 7 are reserved for onboard Serdes, probe the rest.  */
8175         niu_lock_parent(np, flags);
8176         err = 0;
8177         for (port = 8; port < 32; port++) {
8178                 int dev_id_1, dev_id_2;
8179
8180                 dev_id_1 = mdio_read(np, port,
8181                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8182                 dev_id_2 = mdio_read(np, port,
8183                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8184                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8185                                  PHY_TYPE_PMA_PMD);
8186                 if (err)
8187                         break;
8188                 dev_id_1 = mdio_read(np, port,
8189                                      NIU_PCS_DEV_ADDR, MII_PHYSID1);
8190                 dev_id_2 = mdio_read(np, port,
8191                                      NIU_PCS_DEV_ADDR, MII_PHYSID2);
8192                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8193                                  PHY_TYPE_PCS);
8194                 if (err)
8195                         break;
8196                 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8197                 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8198                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8199                                  PHY_TYPE_MII);
8200                 if (err)
8201                         break;
8202         }
8203         niu_unlock_parent(np, flags);
8204
8205         return err;
8206 }
8207
8208 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8209 {
8210         struct phy_probe_info *info = &parent->phy_probe_info;
8211         int lowest_10g, lowest_1g;
8212         int num_10g, num_1g;
8213         u32 val;
8214         int err;
8215
8216         num_10g = num_1g = 0;
8217
8218         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8219             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8220                 num_10g = 0;
8221                 num_1g = 2;
8222                 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8223                 parent->num_ports = 4;
8224                 val = (phy_encode(PORT_TYPE_1G, 0) |
8225                        phy_encode(PORT_TYPE_1G, 1) |
8226                        phy_encode(PORT_TYPE_1G, 2) |
8227                        phy_encode(PORT_TYPE_1G, 3));
8228         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8229                 num_10g = 2;
8230                 num_1g = 0;
8231                 parent->num_ports = 2;
8232                 val = (phy_encode(PORT_TYPE_10G, 0) |
8233                        phy_encode(PORT_TYPE_10G, 1));
8234         } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8235                    (parent->plat_type == PLAT_TYPE_NIU)) {
8236                 /* this is the Monza case */
8237                 if (np->flags & NIU_FLAGS_10G) {
8238                         val = (phy_encode(PORT_TYPE_10G, 0) |
8239                                phy_encode(PORT_TYPE_10G, 1));
8240                 } else {
8241                         val = (phy_encode(PORT_TYPE_1G, 0) |
8242                                phy_encode(PORT_TYPE_1G, 1));
8243                 }
8244         } else {
8245                 err = fill_phy_probe_info(np, parent, info);
8246                 if (err)
8247                         return err;
8248
8249                 num_10g = count_10g_ports(info, &lowest_10g);
8250                 num_1g = count_1g_ports(info, &lowest_1g);
8251
8252                 switch ((num_10g << 4) | num_1g) {
8253                 case 0x24:
8254                         if (lowest_1g == 10)
8255                                 parent->plat_type = PLAT_TYPE_VF_P0;
8256                         else if (lowest_1g == 26)
8257                                 parent->plat_type = PLAT_TYPE_VF_P1;
8258                         else
8259                                 goto unknown_vg_1g_port;
8260
8261                         /* fallthru */
8262                 case 0x22:
8263                         val = (phy_encode(PORT_TYPE_10G, 0) |
8264                                phy_encode(PORT_TYPE_10G, 1) |
8265                                phy_encode(PORT_TYPE_1G, 2) |
8266                                phy_encode(PORT_TYPE_1G, 3));
8267                         break;
8268
8269                 case 0x20:
8270                         val = (phy_encode(PORT_TYPE_10G, 0) |
8271                                phy_encode(PORT_TYPE_10G, 1));
8272                         break;
8273
8274                 case 0x10:
8275                         val = phy_encode(PORT_TYPE_10G, np->port);
8276                         break;
8277
8278                 case 0x14:
8279                         if (lowest_1g == 10)
8280                                 parent->plat_type = PLAT_TYPE_VF_P0;
8281                         else if (lowest_1g == 26)
8282                                 parent->plat_type = PLAT_TYPE_VF_P1;
8283                         else
8284                                 goto unknown_vg_1g_port;
8285
8286                         /* fallthru */
8287                 case 0x13:
8288                         if ((lowest_10g & 0x7) == 0)
8289                                 val = (phy_encode(PORT_TYPE_10G, 0) |
8290                                        phy_encode(PORT_TYPE_1G, 1) |
8291                                        phy_encode(PORT_TYPE_1G, 2) |
8292                                        phy_encode(PORT_TYPE_1G, 3));
8293                         else
8294                                 val = (phy_encode(PORT_TYPE_1G, 0) |
8295                                        phy_encode(PORT_TYPE_10G, 1) |
8296                                        phy_encode(PORT_TYPE_1G, 2) |
8297                                        phy_encode(PORT_TYPE_1G, 3));
8298                         break;
8299
8300                 case 0x04:
8301                         if (lowest_1g == 10)
8302                                 parent->plat_type = PLAT_TYPE_VF_P0;
8303                         else if (lowest_1g == 26)
8304                                 parent->plat_type = PLAT_TYPE_VF_P1;
8305                         else
8306                                 goto unknown_vg_1g_port;
8307
8308                         val = (phy_encode(PORT_TYPE_1G, 0) |
8309                                phy_encode(PORT_TYPE_1G, 1) |
8310                                phy_encode(PORT_TYPE_1G, 2) |
8311                                phy_encode(PORT_TYPE_1G, 3));
8312                         break;
8313
8314                 default:
8315                         printk(KERN_ERR PFX "Unsupported port config "
8316                                "10G[%d] 1G[%d]\n",
8317                                num_10g, num_1g);
8318                         return -EINVAL;
8319                 }
8320         }
8321
8322         parent->port_phy = val;
8323
8324         if (parent->plat_type == PLAT_TYPE_NIU)
8325                 niu_n2_divide_channels(parent);
8326         else
8327                 niu_divide_channels(parent, num_10g, num_1g);
8328
8329         niu_divide_rdc_groups(parent, num_10g, num_1g);
8330
8331         return 0;
8332
8333 unknown_vg_1g_port:
8334         printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
8335                lowest_1g);
8336         return -EINVAL;
8337 }
8338
8339 static int __devinit niu_probe_ports(struct niu *np)
8340 {
8341         struct niu_parent *parent = np->parent;
8342         int err, i;
8343
8344         niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
8345                parent->port_phy);
8346
8347         if (parent->port_phy == PORT_PHY_UNKNOWN) {
8348                 err = walk_phys(np, parent);
8349                 if (err)
8350                         return err;
8351
8352                 niu_set_ldg_timer_res(np, 2);
8353                 for (i = 0; i <= LDN_MAX; i++)
8354                         niu_ldn_irq_enable(np, i, 0);
8355         }
8356
8357         if (parent->port_phy == PORT_PHY_INVALID)
8358                 return -EINVAL;
8359
8360         return 0;
8361 }
8362
8363 static int __devinit niu_classifier_swstate_init(struct niu *np)
8364 {
8365         struct niu_classifier *cp = &np->clas;
8366
8367         niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
8368                np->parent->tcam_num_entries);
8369
8370         cp->tcam_index = (u16) np->port;
8371         cp->h1_init = 0xffffffff;
8372         cp->h2_init = 0xffff;
8373
8374         return fflp_early_init(np);
8375 }
8376
8377 static void __devinit niu_link_config_init(struct niu *np)
8378 {
8379         struct niu_link_config *lp = &np->link_config;
8380
8381         lp->advertising = (ADVERTISED_10baseT_Half |
8382                            ADVERTISED_10baseT_Full |
8383                            ADVERTISED_100baseT_Half |
8384                            ADVERTISED_100baseT_Full |
8385                            ADVERTISED_1000baseT_Half |
8386                            ADVERTISED_1000baseT_Full |
8387                            ADVERTISED_10000baseT_Full |
8388                            ADVERTISED_Autoneg);
8389         lp->speed = lp->active_speed = SPEED_INVALID;
8390         lp->duplex = DUPLEX_FULL;
8391         lp->active_duplex = DUPLEX_INVALID;
8392         lp->autoneg = 1;
8393 #if 0
8394         lp->loopback_mode = LOOPBACK_MAC;
8395         lp->active_speed = SPEED_10000;
8396         lp->active_duplex = DUPLEX_FULL;
8397 #else
8398         lp->loopback_mode = LOOPBACK_DISABLED;
8399 #endif
8400 }
8401
8402 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
8403 {
8404         switch (np->port) {
8405         case 0:
8406                 np->mac_regs = np->regs + XMAC_PORT0_OFF;
8407                 np->ipp_off  = 0x00000;
8408                 np->pcs_off  = 0x04000;
8409                 np->xpcs_off = 0x02000;
8410                 break;
8411
8412         case 1:
8413                 np->mac_regs = np->regs + XMAC_PORT1_OFF;
8414                 np->ipp_off  = 0x08000;
8415                 np->pcs_off  = 0x0a000;
8416                 np->xpcs_off = 0x08000;
8417                 break;
8418
8419         case 2:
8420                 np->mac_regs = np->regs + BMAC_PORT2_OFF;
8421                 np->ipp_off  = 0x04000;
8422                 np->pcs_off  = 0x0e000;
8423                 np->xpcs_off = ~0UL;
8424                 break;
8425
8426         case 3:
8427                 np->mac_regs = np->regs + BMAC_PORT3_OFF;
8428                 np->ipp_off  = 0x0c000;
8429                 np->pcs_off  = 0x12000;
8430                 np->xpcs_off = ~0UL;
8431                 break;
8432
8433         default:
8434                 dev_err(np->device, PFX "Port %u is invalid, cannot "
8435                         "compute MAC block offset.\n", np->port);
8436                 return -EINVAL;
8437         }
8438
8439         return 0;
8440 }
8441
8442 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
8443 {
8444         struct msix_entry msi_vec[NIU_NUM_LDG];
8445         struct niu_parent *parent = np->parent;
8446         struct pci_dev *pdev = np->pdev;
8447         int i, num_irqs, err;
8448         u8 first_ldg;
8449
8450         first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
8451         for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
8452                 ldg_num_map[i] = first_ldg + i;
8453
8454         num_irqs = (parent->rxchan_per_port[np->port] +
8455                     parent->txchan_per_port[np->port] +
8456                     (np->port == 0 ? 3 : 1));
8457         BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
8458
8459 retry:
8460         for (i = 0; i < num_irqs; i++) {
8461                 msi_vec[i].vector = 0;
8462                 msi_vec[i].entry = i;
8463         }
8464
8465         err = pci_enable_msix(pdev, msi_vec, num_irqs);
8466         if (err < 0) {
8467                 np->flags &= ~NIU_FLAGS_MSIX;
8468                 return;
8469         }
8470         if (err > 0) {
8471                 num_irqs = err;
8472                 goto retry;
8473         }
8474
8475         np->flags |= NIU_FLAGS_MSIX;
8476         for (i = 0; i < num_irqs; i++)
8477                 np->ldg[i].irq = msi_vec[i].vector;
8478         np->num_ldg = num_irqs;
8479 }
8480
8481 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
8482 {
8483 #ifdef CONFIG_SPARC64
8484         struct of_device *op = np->op;
8485         const u32 *int_prop;
8486         int i;
8487
8488         int_prop = of_get_property(op->node, "interrupts", NULL);
8489         if (!int_prop)
8490                 return -ENODEV;
8491
8492         for (i = 0; i < op->num_irqs; i++) {
8493                 ldg_num_map[i] = int_prop[i];
8494                 np->ldg[i].irq = op->irqs[i];
8495         }
8496
8497         np->num_ldg = op->num_irqs;
8498
8499         return 0;
8500 #else
8501         return -EINVAL;
8502 #endif
8503 }
8504
8505 static int __devinit niu_ldg_init(struct niu *np)
8506 {
8507         struct niu_parent *parent = np->parent;
8508         u8 ldg_num_map[NIU_NUM_LDG];
8509         int first_chan, num_chan;
8510         int i, err, ldg_rotor;
8511         u8 port;
8512
8513         np->num_ldg = 1;
8514         np->ldg[0].irq = np->dev->irq;
8515         if (parent->plat_type == PLAT_TYPE_NIU) {
8516                 err = niu_n2_irq_init(np, ldg_num_map);
8517                 if (err)
8518                         return err;
8519         } else
8520                 niu_try_msix(np, ldg_num_map);
8521
8522         port = np->port;
8523         for (i = 0; i < np->num_ldg; i++) {
8524                 struct niu_ldg *lp = &np->ldg[i];
8525
8526                 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
8527
8528                 lp->np = np;
8529                 lp->ldg_num = ldg_num_map[i];
8530                 lp->timer = 2; /* XXX */
8531
8532                 /* On N2 NIU the firmware has setup the SID mappings so they go
8533                  * to the correct values that will route the LDG to the proper
8534                  * interrupt in the NCU interrupt table.
8535                  */
8536                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
8537                         err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
8538                         if (err)
8539                                 return err;
8540                 }
8541         }
8542
8543         /* We adopt the LDG assignment ordering used by the N2 NIU
8544          * 'interrupt' properties because that simplifies a lot of
8545          * things.  This ordering is:
8546          *
8547          *      MAC
8548          *      MIF     (if port zero)
8549          *      SYSERR  (if port zero)
8550          *      RX channels
8551          *      TX channels
8552          */
8553
8554         ldg_rotor = 0;
8555
8556         err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
8557                                   LDN_MAC(port));
8558         if (err)
8559                 return err;
8560
8561         ldg_rotor++;
8562         if (ldg_rotor == np->num_ldg)
8563                 ldg_rotor = 0;
8564
8565         if (port == 0) {
8566                 err = niu_ldg_assign_ldn(np, parent,
8567                                          ldg_num_map[ldg_rotor],
8568                                          LDN_MIF);
8569                 if (err)
8570                         return err;
8571
8572                 ldg_rotor++;
8573                 if (ldg_rotor == np->num_ldg)
8574                         ldg_rotor = 0;
8575
8576                 err = niu_ldg_assign_ldn(np, parent,
8577                                          ldg_num_map[ldg_rotor],
8578                                          LDN_DEVICE_ERROR);
8579                 if (err)
8580                         return err;
8581
8582                 ldg_rotor++;
8583                 if (ldg_rotor == np->num_ldg)
8584                         ldg_rotor = 0;
8585
8586         }
8587
8588         first_chan = 0;
8589         for (i = 0; i < port; i++)
8590                 first_chan += parent->rxchan_per_port[port];
8591         num_chan = parent->rxchan_per_port[port];
8592
8593         for (i = first_chan; i < (first_chan + num_chan); i++) {
8594                 err = niu_ldg_assign_ldn(np, parent,
8595                                          ldg_num_map[ldg_rotor],
8596                                          LDN_RXDMA(i));
8597                 if (err)
8598                         return err;
8599                 ldg_rotor++;
8600                 if (ldg_rotor == np->num_ldg)
8601                         ldg_rotor = 0;
8602         }
8603
8604         first_chan = 0;
8605         for (i = 0; i < port; i++)
8606                 first_chan += parent->txchan_per_port[port];
8607         num_chan = parent->txchan_per_port[port];
8608         for (i = first_chan; i < (first_chan + num_chan); i++) {
8609                 err = niu_ldg_assign_ldn(np, parent,
8610                                          ldg_num_map[ldg_rotor],
8611                                          LDN_TXDMA(i));
8612                 if (err)
8613                         return err;
8614                 ldg_rotor++;
8615                 if (ldg_rotor == np->num_ldg)
8616                         ldg_rotor = 0;
8617         }
8618
8619         return 0;
8620 }
8621
8622 static void __devexit niu_ldg_free(struct niu *np)
8623 {
8624         if (np->flags & NIU_FLAGS_MSIX)
8625                 pci_disable_msix(np->pdev);
8626 }
8627
8628 static int __devinit niu_get_of_props(struct niu *np)
8629 {
8630 #ifdef CONFIG_SPARC64
8631         struct net_device *dev = np->dev;
8632         struct device_node *dp;
8633         const char *phy_type;
8634         const u8 *mac_addr;
8635         const char *model;
8636         int prop_len;
8637
8638         if (np->parent->plat_type == PLAT_TYPE_NIU)
8639                 dp = np->op->node;
8640         else
8641                 dp = pci_device_to_OF_node(np->pdev);
8642
8643         phy_type = of_get_property(dp, "phy-type", &prop_len);
8644         if (!phy_type) {
8645                 dev_err(np->device, PFX "%s: OF node lacks "
8646                         "phy-type property\n",
8647                         dp->full_name);
8648                 return -EINVAL;
8649         }
8650
8651         if (!strcmp(phy_type, "none"))
8652                 return -ENODEV;
8653
8654         strcpy(np->vpd.phy_type, phy_type);
8655
8656         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8657                 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
8658                         dp->full_name, np->vpd.phy_type);
8659                 return -EINVAL;
8660         }
8661
8662         mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
8663         if (!mac_addr) {
8664                 dev_err(np->device, PFX "%s: OF node lacks "
8665                         "local-mac-address property\n",
8666                         dp->full_name);
8667                 return -EINVAL;
8668         }
8669         if (prop_len != dev->addr_len) {
8670                 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
8671                         "is wrong.\n",
8672                         dp->full_name, prop_len);
8673         }
8674         memcpy(dev->perm_addr, mac_addr, dev->addr_len);
8675         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8676                 int i;
8677
8678                 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
8679                         dp->full_name);
8680                 dev_err(np->device, PFX "%s: [ \n",
8681                         dp->full_name);
8682                 for (i = 0; i < 6; i++)
8683                         printk("%02x ", dev->perm_addr[i]);
8684                 printk("]\n");
8685                 return -EINVAL;
8686         }
8687
8688         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8689
8690         model = of_get_property(dp, "model", &prop_len);
8691
8692         if (model)
8693                 strcpy(np->vpd.model, model);
8694
8695         return 0;
8696 #else
8697         return -EINVAL;
8698 #endif
8699 }
8700
8701 static int __devinit niu_get_invariants(struct niu *np)
8702 {
8703         int err, have_props;
8704         u32 offset;
8705
8706         err = niu_get_of_props(np);
8707         if (err == -ENODEV)
8708                 return err;
8709
8710         have_props = !err;
8711
8712         err = niu_init_mac_ipp_pcs_base(np);
8713         if (err)
8714                 return err;
8715
8716         if (have_props) {
8717                 err = niu_get_and_validate_port(np);
8718                 if (err)
8719                         return err;
8720
8721         } else  {
8722                 if (np->parent->plat_type == PLAT_TYPE_NIU)
8723                         return -EINVAL;
8724
8725                 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
8726                 offset = niu_pci_vpd_offset(np);
8727                 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
8728                        offset);
8729                 if (offset)
8730                         niu_pci_vpd_fetch(np, offset);
8731                 nw64(ESPC_PIO_EN, 0);
8732
8733                 if (np->flags & NIU_FLAGS_VPD_VALID) {
8734                         niu_pci_vpd_validate(np);
8735                         err = niu_get_and_validate_port(np);
8736                         if (err)
8737                                 return err;
8738                 }
8739
8740                 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
8741                         err = niu_get_and_validate_port(np);
8742                         if (err)
8743                                 return err;
8744                         err = niu_pci_probe_sprom(np);
8745                         if (err)
8746                                 return err;
8747                 }
8748         }
8749
8750         err = niu_probe_ports(np);
8751         if (err)
8752                 return err;
8753
8754         niu_ldg_init(np);
8755
8756         niu_classifier_swstate_init(np);
8757         niu_link_config_init(np);
8758
8759         err = niu_determine_phy_disposition(np);
8760         if (!err)
8761                 err = niu_init_link(np);
8762
8763         return err;
8764 }
8765
8766 static LIST_HEAD(niu_parent_list);
8767 static DEFINE_MUTEX(niu_parent_lock);
8768 static int niu_parent_index;
8769
8770 static ssize_t show_port_phy(struct device *dev,
8771                              struct device_attribute *attr, char *buf)
8772 {
8773         struct platform_device *plat_dev = to_platform_device(dev);
8774         struct niu_parent *p = plat_dev->dev.platform_data;
8775         u32 port_phy = p->port_phy;
8776         char *orig_buf = buf;
8777         int i;
8778
8779         if (port_phy == PORT_PHY_UNKNOWN ||
8780             port_phy == PORT_PHY_INVALID)
8781                 return 0;
8782
8783         for (i = 0; i < p->num_ports; i++) {
8784                 const char *type_str;
8785                 int type;
8786
8787                 type = phy_decode(port_phy, i);
8788                 if (type == PORT_TYPE_10G)
8789                         type_str = "10G";
8790                 else
8791                         type_str = "1G";
8792                 buf += sprintf(buf,
8793                                (i == 0) ? "%s" : " %s",
8794                                type_str);
8795         }
8796         buf += sprintf(buf, "\n");
8797         return buf - orig_buf;
8798 }
8799
8800 static ssize_t show_plat_type(struct device *dev,
8801                               struct device_attribute *attr, char *buf)
8802 {
8803         struct platform_device *plat_dev = to_platform_device(dev);
8804         struct niu_parent *p = plat_dev->dev.platform_data;
8805         const char *type_str;
8806
8807         switch (p->plat_type) {
8808         case PLAT_TYPE_ATLAS:
8809                 type_str = "atlas";
8810                 break;
8811         case PLAT_TYPE_NIU:
8812                 type_str = "niu";
8813                 break;
8814         case PLAT_TYPE_VF_P0:
8815                 type_str = "vf_p0";
8816                 break;
8817         case PLAT_TYPE_VF_P1:
8818                 type_str = "vf_p1";
8819                 break;
8820         default:
8821                 type_str = "unknown";
8822                 break;
8823         }
8824
8825         return sprintf(buf, "%s\n", type_str);
8826 }
8827
8828 static ssize_t __show_chan_per_port(struct device *dev,
8829                                     struct device_attribute *attr, char *buf,
8830                                     int rx)
8831 {
8832         struct platform_device *plat_dev = to_platform_device(dev);
8833         struct niu_parent *p = plat_dev->dev.platform_data;
8834         char *orig_buf = buf;
8835         u8 *arr;
8836         int i;
8837
8838         arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
8839
8840         for (i = 0; i < p->num_ports; i++) {
8841                 buf += sprintf(buf,
8842                                (i == 0) ? "%d" : " %d",
8843                                arr[i]);
8844         }
8845         buf += sprintf(buf, "\n");
8846
8847         return buf - orig_buf;
8848 }
8849
8850 static ssize_t show_rxchan_per_port(struct device *dev,
8851                                     struct device_attribute *attr, char *buf)
8852 {
8853         return __show_chan_per_port(dev, attr, buf, 1);
8854 }
8855
8856 static ssize_t show_txchan_per_port(struct device *dev,
8857                                     struct device_attribute *attr, char *buf)
8858 {
8859         return __show_chan_per_port(dev, attr, buf, 1);
8860 }
8861
8862 static ssize_t show_num_ports(struct device *dev,
8863                               struct device_attribute *attr, char *buf)
8864 {
8865         struct platform_device *plat_dev = to_platform_device(dev);
8866         struct niu_parent *p = plat_dev->dev.platform_data;
8867
8868         return sprintf(buf, "%d\n", p->num_ports);
8869 }
8870
8871 static struct device_attribute niu_parent_attributes[] = {
8872         __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
8873         __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
8874         __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
8875         __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
8876         __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
8877         {}
8878 };
8879
8880 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
8881                                                     union niu_parent_id *id,
8882                                                     u8 ptype)
8883 {
8884         struct platform_device *plat_dev;
8885         struct niu_parent *p;
8886         int i;
8887
8888         niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
8889
8890         plat_dev = platform_device_register_simple("niu", niu_parent_index,
8891                                                    NULL, 0);
8892         if (!plat_dev)
8893                 return NULL;
8894
8895         for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
8896                 int err = device_create_file(&plat_dev->dev,
8897                                              &niu_parent_attributes[i]);
8898                 if (err)
8899                         goto fail_unregister;
8900         }
8901
8902         p = kzalloc(sizeof(*p), GFP_KERNEL);
8903         if (!p)
8904                 goto fail_unregister;
8905
8906         p->index = niu_parent_index++;
8907
8908         plat_dev->dev.platform_data = p;
8909         p->plat_dev = plat_dev;
8910
8911         memcpy(&p->id, id, sizeof(*id));
8912         p->plat_type = ptype;
8913         INIT_LIST_HEAD(&p->list);
8914         atomic_set(&p->refcnt, 0);
8915         list_add(&p->list, &niu_parent_list);
8916         spin_lock_init(&p->lock);
8917
8918         p->rxdma_clock_divider = 7500;
8919
8920         p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
8921         if (p->plat_type == PLAT_TYPE_NIU)
8922                 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
8923
8924         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
8925                 int index = i - CLASS_CODE_USER_PROG1;
8926
8927                 p->tcam_key[index] = TCAM_KEY_TSEL;
8928                 p->flow_key[index] = (FLOW_KEY_IPSA |
8929                                       FLOW_KEY_IPDA |
8930                                       FLOW_KEY_PROTO |
8931                                       (FLOW_KEY_L4_BYTE12 <<
8932                                        FLOW_KEY_L4_0_SHIFT) |
8933                                       (FLOW_KEY_L4_BYTE12 <<
8934                                        FLOW_KEY_L4_1_SHIFT));
8935         }
8936
8937         for (i = 0; i < LDN_MAX + 1; i++)
8938                 p->ldg_map[i] = LDG_INVALID;
8939
8940         return p;
8941
8942 fail_unregister:
8943         platform_device_unregister(plat_dev);
8944         return NULL;
8945 }
8946
8947 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
8948                                                     union niu_parent_id *id,
8949                                                     u8 ptype)
8950 {
8951         struct niu_parent *p, *tmp;
8952         int port = np->port;
8953
8954         niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
8955                ptype, port);
8956
8957         mutex_lock(&niu_parent_lock);
8958         p = NULL;
8959         list_for_each_entry(tmp, &niu_parent_list, list) {
8960                 if (!memcmp(id, &tmp->id, sizeof(*id))) {
8961                         p = tmp;
8962                         break;
8963                 }
8964         }
8965         if (!p)
8966                 p = niu_new_parent(np, id, ptype);
8967
8968         if (p) {
8969                 char port_name[6];
8970                 int err;
8971
8972                 sprintf(port_name, "port%d", port);
8973                 err = sysfs_create_link(&p->plat_dev->dev.kobj,
8974                                         &np->device->kobj,
8975                                         port_name);
8976                 if (!err) {
8977                         p->ports[port] = np;
8978                         atomic_inc(&p->refcnt);
8979                 }
8980         }
8981         mutex_unlock(&niu_parent_lock);
8982
8983         return p;
8984 }
8985
8986 static void niu_put_parent(struct niu *np)
8987 {
8988         struct niu_parent *p = np->parent;
8989         u8 port = np->port;
8990         char port_name[6];
8991
8992         BUG_ON(!p || p->ports[port] != np);
8993
8994         niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
8995
8996         sprintf(port_name, "port%d", port);
8997
8998         mutex_lock(&niu_parent_lock);
8999
9000         sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9001
9002         p->ports[port] = NULL;
9003         np->parent = NULL;
9004
9005         if (atomic_dec_and_test(&p->refcnt)) {
9006                 list_del(&p->list);
9007                 platform_device_unregister(p->plat_dev);
9008         }
9009
9010         mutex_unlock(&niu_parent_lock);
9011 }
9012
9013 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9014                                     u64 *handle, gfp_t flag)
9015 {
9016         dma_addr_t dh;
9017         void *ret;
9018
9019         ret = dma_alloc_coherent(dev, size, &dh, flag);
9020         if (ret)
9021                 *handle = dh;
9022         return ret;
9023 }
9024
9025 static void niu_pci_free_coherent(struct device *dev, size_t size,
9026                                   void *cpu_addr, u64 handle)
9027 {
9028         dma_free_coherent(dev, size, cpu_addr, handle);
9029 }
9030
9031 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9032                             unsigned long offset, size_t size,
9033                             enum dma_data_direction direction)
9034 {
9035         return dma_map_page(dev, page, offset, size, direction);
9036 }
9037
9038 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9039                                size_t size, enum dma_data_direction direction)
9040 {
9041         dma_unmap_page(dev, dma_address, size, direction);
9042 }
9043
9044 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9045                               size_t size,
9046                               enum dma_data_direction direction)
9047 {
9048         return dma_map_single(dev, cpu_addr, size, direction);
9049 }
9050
9051 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9052                                  size_t size,
9053                                  enum dma_data_direction direction)
9054 {
9055         dma_unmap_single(dev, dma_address, size, direction);
9056 }
9057
9058 static const struct niu_ops niu_pci_ops = {
9059         .alloc_coherent = niu_pci_alloc_coherent,
9060         .free_coherent  = niu_pci_free_coherent,
9061         .map_page       = niu_pci_map_page,
9062         .unmap_page     = niu_pci_unmap_page,
9063         .map_single     = niu_pci_map_single,
9064         .unmap_single   = niu_pci_unmap_single,
9065 };
9066
9067 static void __devinit niu_driver_version(void)
9068 {
9069         static int niu_version_printed;
9070
9071         if (niu_version_printed++ == 0)
9072                 pr_info("%s", version);
9073 }
9074
9075 static struct net_device * __devinit niu_alloc_and_init(
9076         struct device *gen_dev, struct pci_dev *pdev,
9077         struct of_device *op, const struct niu_ops *ops,
9078         u8 port)
9079 {
9080         struct net_device *dev;
9081         struct niu *np;
9082
9083         dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9084         if (!dev) {
9085                 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
9086                 return NULL;
9087         }
9088
9089         SET_NETDEV_DEV(dev, gen_dev);
9090
9091         np = netdev_priv(dev);
9092         np->dev = dev;
9093         np->pdev = pdev;
9094         np->op = op;
9095         np->device = gen_dev;
9096         np->ops = ops;
9097
9098         np->msg_enable = niu_debug;
9099
9100         spin_lock_init(&np->lock);
9101         INIT_WORK(&np->reset_task, niu_reset_task);
9102
9103         np->port = port;
9104
9105         return dev;
9106 }
9107
9108 static const struct net_device_ops niu_netdev_ops = {
9109         .ndo_open               = niu_open,
9110         .ndo_stop               = niu_close,
9111         .ndo_start_xmit         = niu_start_xmit,
9112         .ndo_get_stats          = niu_get_stats,
9113         .ndo_set_multicast_list = niu_set_rx_mode,
9114         .ndo_validate_addr      = eth_validate_addr,
9115         .ndo_set_mac_address    = niu_set_mac_addr,
9116         .ndo_do_ioctl           = niu_ioctl,
9117         .ndo_tx_timeout         = niu_tx_timeout,
9118         .ndo_change_mtu         = niu_change_mtu,
9119 };
9120
9121 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9122 {
9123         dev->netdev_ops = &niu_netdev_ops;
9124         dev->ethtool_ops = &niu_ethtool_ops;
9125         dev->watchdog_timeo = NIU_TX_TIMEOUT;
9126 }
9127
9128 static void __devinit niu_device_announce(struct niu *np)
9129 {
9130         struct net_device *dev = np->dev;
9131
9132         pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9133
9134         if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9135                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9136                                 dev->name,
9137                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9138                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9139                                 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9140                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9141                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9142                                 np->vpd.phy_type);
9143         } else {
9144                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9145                                 dev->name,
9146                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9147                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9148                                 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9149                                  (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9150                                   "COPPER")),
9151                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9152                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9153                                 np->vpd.phy_type);
9154         }
9155 }
9156
9157 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9158                                       const struct pci_device_id *ent)
9159 {
9160         union niu_parent_id parent_id;
9161         struct net_device *dev;
9162         struct niu *np;
9163         int err, pos;
9164         u64 dma_mask;
9165         u16 val16;
9166
9167         niu_driver_version();
9168
9169         err = pci_enable_device(pdev);
9170         if (err) {
9171                 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
9172                         "aborting.\n");
9173                 return err;
9174         }
9175
9176         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9177             !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9178                 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
9179                         "base addresses, aborting.\n");
9180                 err = -ENODEV;
9181                 goto err_out_disable_pdev;
9182         }
9183
9184         err = pci_request_regions(pdev, DRV_MODULE_NAME);
9185         if (err) {
9186                 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
9187                         "aborting.\n");
9188                 goto err_out_disable_pdev;
9189         }
9190
9191         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9192         if (pos <= 0) {
9193                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
9194                         "aborting.\n");
9195                 goto err_out_free_res;
9196         }
9197
9198         dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9199                                  &niu_pci_ops, PCI_FUNC(pdev->devfn));
9200         if (!dev) {
9201                 err = -ENOMEM;
9202                 goto err_out_free_res;
9203         }
9204         np = netdev_priv(dev);
9205
9206         memset(&parent_id, 0, sizeof(parent_id));
9207         parent_id.pci.domain = pci_domain_nr(pdev->bus);
9208         parent_id.pci.bus = pdev->bus->number;
9209         parent_id.pci.device = PCI_SLOT(pdev->devfn);
9210
9211         np->parent = niu_get_parent(np, &parent_id,
9212                                     PLAT_TYPE_ATLAS);
9213         if (!np->parent) {
9214                 err = -ENOMEM;
9215                 goto err_out_free_dev;
9216         }
9217
9218         pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9219         val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9220         val16 |= (PCI_EXP_DEVCTL_CERE |
9221                   PCI_EXP_DEVCTL_NFERE |
9222                   PCI_EXP_DEVCTL_FERE |
9223                   PCI_EXP_DEVCTL_URRE |
9224                   PCI_EXP_DEVCTL_RELAX_EN);
9225         pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9226
9227         dma_mask = DMA_44BIT_MASK;
9228         err = pci_set_dma_mask(pdev, dma_mask);
9229         if (!err) {
9230                 dev->features |= NETIF_F_HIGHDMA;
9231                 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9232                 if (err) {
9233                         dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
9234                                 "DMA for consistent allocations, "
9235                                 "aborting.\n");
9236                         goto err_out_release_parent;
9237                 }
9238         }
9239         if (err || dma_mask == DMA_32BIT_MASK) {
9240                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
9241                 if (err) {
9242                         dev_err(&pdev->dev, PFX "No usable DMA configuration, "
9243                                 "aborting.\n");
9244                         goto err_out_release_parent;
9245                 }
9246         }
9247
9248         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9249
9250         np->regs = pci_ioremap_bar(pdev, 0);
9251         if (!np->regs) {
9252                 dev_err(&pdev->dev, PFX "Cannot map device registers, "
9253                         "aborting.\n");
9254                 err = -ENOMEM;
9255                 goto err_out_release_parent;
9256         }
9257
9258         pci_set_master(pdev);
9259         pci_save_state(pdev);
9260
9261         dev->irq = pdev->irq;
9262
9263         niu_assign_netdev_ops(dev);
9264
9265         err = niu_get_invariants(np);
9266         if (err) {
9267                 if (err != -ENODEV)
9268                         dev_err(&pdev->dev, PFX "Problem fetching invariants "
9269                                 "of chip, aborting.\n");
9270                 goto err_out_iounmap;
9271         }
9272
9273         err = register_netdev(dev);
9274         if (err) {
9275                 dev_err(&pdev->dev, PFX "Cannot register net device, "
9276                         "aborting.\n");
9277                 goto err_out_iounmap;
9278         }
9279
9280         pci_set_drvdata(pdev, dev);
9281
9282         niu_device_announce(np);
9283
9284         return 0;
9285
9286 err_out_iounmap:
9287         if (np->regs) {
9288                 iounmap(np->regs);
9289                 np->regs = NULL;
9290         }
9291
9292 err_out_release_parent:
9293         niu_put_parent(np);
9294
9295 err_out_free_dev:
9296         free_netdev(dev);
9297
9298 err_out_free_res:
9299         pci_release_regions(pdev);
9300
9301 err_out_disable_pdev:
9302         pci_disable_device(pdev);
9303         pci_set_drvdata(pdev, NULL);
9304
9305         return err;
9306 }
9307
9308 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9309 {
9310         struct net_device *dev = pci_get_drvdata(pdev);
9311
9312         if (dev) {
9313                 struct niu *np = netdev_priv(dev);
9314
9315                 unregister_netdev(dev);
9316                 if (np->regs) {
9317                         iounmap(np->regs);
9318                         np->regs = NULL;
9319                 }
9320
9321                 niu_ldg_free(np);
9322
9323                 niu_put_parent(np);
9324
9325                 free_netdev(dev);
9326                 pci_release_regions(pdev);
9327                 pci_disable_device(pdev);
9328                 pci_set_drvdata(pdev, NULL);
9329         }
9330 }
9331
9332 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9333 {
9334         struct net_device *dev = pci_get_drvdata(pdev);
9335         struct niu *np = netdev_priv(dev);
9336         unsigned long flags;
9337
9338         if (!netif_running(dev))
9339                 return 0;
9340
9341         flush_scheduled_work();
9342         niu_netif_stop(np);
9343
9344         del_timer_sync(&np->timer);
9345
9346         spin_lock_irqsave(&np->lock, flags);
9347         niu_enable_interrupts(np, 0);
9348         spin_unlock_irqrestore(&np->lock, flags);
9349
9350         netif_device_detach(dev);
9351
9352         spin_lock_irqsave(&np->lock, flags);
9353         niu_stop_hw(np);
9354         spin_unlock_irqrestore(&np->lock, flags);
9355
9356         pci_save_state(pdev);
9357
9358         return 0;
9359 }
9360
9361 static int niu_resume(struct pci_dev *pdev)
9362 {
9363         struct net_device *dev = pci_get_drvdata(pdev);
9364         struct niu *np = netdev_priv(dev);
9365         unsigned long flags;
9366         int err;
9367
9368         if (!netif_running(dev))
9369                 return 0;
9370
9371         pci_restore_state(pdev);
9372
9373         netif_device_attach(dev);
9374
9375         spin_lock_irqsave(&np->lock, flags);
9376
9377         err = niu_init_hw(np);
9378         if (!err) {
9379                 np->timer.expires = jiffies + HZ;
9380                 add_timer(&np->timer);
9381                 niu_netif_start(np);
9382         }
9383
9384         spin_unlock_irqrestore(&np->lock, flags);
9385
9386         return err;
9387 }
9388
9389 static struct pci_driver niu_pci_driver = {
9390         .name           = DRV_MODULE_NAME,
9391         .id_table       = niu_pci_tbl,
9392         .probe          = niu_pci_init_one,
9393         .remove         = __devexit_p(niu_pci_remove_one),
9394         .suspend        = niu_suspend,
9395         .resume         = niu_resume,
9396 };
9397
9398 #ifdef CONFIG_SPARC64
9399 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9400                                      u64 *dma_addr, gfp_t flag)
9401 {
9402         unsigned long order = get_order(size);
9403         unsigned long page = __get_free_pages(flag, order);
9404
9405         if (page == 0UL)
9406                 return NULL;
9407         memset((char *)page, 0, PAGE_SIZE << order);
9408         *dma_addr = __pa(page);
9409
9410         return (void *) page;
9411 }
9412
9413 static void niu_phys_free_coherent(struct device *dev, size_t size,
9414                                    void *cpu_addr, u64 handle)
9415 {
9416         unsigned long order = get_order(size);
9417
9418         free_pages((unsigned long) cpu_addr, order);
9419 }
9420
9421 static u64 niu_phys_map_page(struct device *dev, struct page *page,
9422                              unsigned long offset, size_t size,
9423                              enum dma_data_direction direction)
9424 {
9425         return page_to_phys(page) + offset;
9426 }
9427
9428 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
9429                                 size_t size, enum dma_data_direction direction)
9430 {
9431         /* Nothing to do.  */
9432 }
9433
9434 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
9435                                size_t size,
9436                                enum dma_data_direction direction)
9437 {
9438         return __pa(cpu_addr);
9439 }
9440
9441 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
9442                                   size_t size,
9443                                   enum dma_data_direction direction)
9444 {
9445         /* Nothing to do.  */
9446 }
9447
9448 static const struct niu_ops niu_phys_ops = {
9449         .alloc_coherent = niu_phys_alloc_coherent,
9450         .free_coherent  = niu_phys_free_coherent,
9451         .map_page       = niu_phys_map_page,
9452         .unmap_page     = niu_phys_unmap_page,
9453         .map_single     = niu_phys_map_single,
9454         .unmap_single   = niu_phys_unmap_single,
9455 };
9456
9457 static unsigned long res_size(struct resource *r)
9458 {
9459         return r->end - r->start + 1UL;
9460 }
9461
9462 static int __devinit niu_of_probe(struct of_device *op,
9463                                   const struct of_device_id *match)
9464 {
9465         union niu_parent_id parent_id;
9466         struct net_device *dev;
9467         struct niu *np;
9468         const u32 *reg;
9469         int err;
9470
9471         niu_driver_version();
9472
9473         reg = of_get_property(op->node, "reg", NULL);
9474         if (!reg) {
9475                 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
9476                         op->node->full_name);
9477                 return -ENODEV;
9478         }
9479
9480         dev = niu_alloc_and_init(&op->dev, NULL, op,
9481                                  &niu_phys_ops, reg[0] & 0x1);
9482         if (!dev) {
9483                 err = -ENOMEM;
9484                 goto err_out;
9485         }
9486         np = netdev_priv(dev);
9487
9488         memset(&parent_id, 0, sizeof(parent_id));
9489         parent_id.of = of_get_parent(op->node);
9490
9491         np->parent = niu_get_parent(np, &parent_id,
9492                                     PLAT_TYPE_NIU);
9493         if (!np->parent) {
9494                 err = -ENOMEM;
9495                 goto err_out_free_dev;
9496         }
9497
9498         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9499
9500         np->regs = of_ioremap(&op->resource[1], 0,
9501                               res_size(&op->resource[1]),
9502                               "niu regs");
9503         if (!np->regs) {
9504                 dev_err(&op->dev, PFX "Cannot map device registers, "
9505                         "aborting.\n");
9506                 err = -ENOMEM;
9507                 goto err_out_release_parent;
9508         }
9509
9510         np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
9511                                     res_size(&op->resource[2]),
9512                                     "niu vregs-1");
9513         if (!np->vir_regs_1) {
9514                 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
9515                         "aborting.\n");
9516                 err = -ENOMEM;
9517                 goto err_out_iounmap;
9518         }
9519
9520         np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
9521                                     res_size(&op->resource[3]),
9522                                     "niu vregs-2");
9523         if (!np->vir_regs_2) {
9524                 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
9525                         "aborting.\n");
9526                 err = -ENOMEM;
9527                 goto err_out_iounmap;
9528         }
9529
9530         niu_assign_netdev_ops(dev);
9531
9532         err = niu_get_invariants(np);
9533         if (err) {
9534                 if (err != -ENODEV)
9535                         dev_err(&op->dev, PFX "Problem fetching invariants "
9536                                 "of chip, aborting.\n");
9537                 goto err_out_iounmap;
9538         }
9539
9540         err = register_netdev(dev);
9541         if (err) {
9542                 dev_err(&op->dev, PFX "Cannot register net device, "
9543                         "aborting.\n");
9544                 goto err_out_iounmap;
9545         }
9546
9547         dev_set_drvdata(&op->dev, dev);
9548
9549         niu_device_announce(np);
9550
9551         return 0;
9552
9553 err_out_iounmap:
9554         if (np->vir_regs_1) {
9555                 of_iounmap(&op->resource[2], np->vir_regs_1,
9556                            res_size(&op->resource[2]));
9557                 np->vir_regs_1 = NULL;
9558         }
9559
9560         if (np->vir_regs_2) {
9561                 of_iounmap(&op->resource[3], np->vir_regs_2,
9562                            res_size(&op->resource[3]));
9563                 np->vir_regs_2 = NULL;
9564         }
9565
9566         if (np->regs) {
9567                 of_iounmap(&op->resource[1], np->regs,
9568                            res_size(&op->resource[1]));
9569                 np->regs = NULL;
9570         }
9571
9572 err_out_release_parent:
9573         niu_put_parent(np);
9574
9575 err_out_free_dev:
9576         free_netdev(dev);
9577
9578 err_out:
9579         return err;
9580 }
9581
9582 static int __devexit niu_of_remove(struct of_device *op)
9583 {
9584         struct net_device *dev = dev_get_drvdata(&op->dev);
9585
9586         if (dev) {
9587                 struct niu *np = netdev_priv(dev);
9588
9589                 unregister_netdev(dev);
9590
9591                 if (np->vir_regs_1) {
9592                         of_iounmap(&op->resource[2], np->vir_regs_1,
9593                                    res_size(&op->resource[2]));
9594                         np->vir_regs_1 = NULL;
9595                 }
9596
9597                 if (np->vir_regs_2) {
9598                         of_iounmap(&op->resource[3], np->vir_regs_2,
9599                                    res_size(&op->resource[3]));
9600                         np->vir_regs_2 = NULL;
9601                 }
9602
9603                 if (np->regs) {
9604                         of_iounmap(&op->resource[1], np->regs,
9605                                    res_size(&op->resource[1]));
9606                         np->regs = NULL;
9607                 }
9608
9609                 niu_ldg_free(np);
9610
9611                 niu_put_parent(np);
9612
9613                 free_netdev(dev);
9614                 dev_set_drvdata(&op->dev, NULL);
9615         }
9616         return 0;
9617 }
9618
9619 static const struct of_device_id niu_match[] = {
9620         {
9621                 .name = "network",
9622                 .compatible = "SUNW,niusl",
9623         },
9624         {},
9625 };
9626 MODULE_DEVICE_TABLE(of, niu_match);
9627
9628 static struct of_platform_driver niu_of_driver = {
9629         .name           = "niu",
9630         .match_table    = niu_match,
9631         .probe          = niu_of_probe,
9632         .remove         = __devexit_p(niu_of_remove),
9633 };
9634
9635 #endif /* CONFIG_SPARC64 */
9636
9637 static int __init niu_init(void)
9638 {
9639         int err = 0;
9640
9641         BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
9642
9643         niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
9644
9645 #ifdef CONFIG_SPARC64
9646         err = of_register_driver(&niu_of_driver, &of_bus_type);
9647 #endif
9648
9649         if (!err) {
9650                 err = pci_register_driver(&niu_pci_driver);
9651 #ifdef CONFIG_SPARC64
9652                 if (err)
9653                         of_unregister_driver(&niu_of_driver);
9654 #endif
9655         }
9656
9657         return err;
9658 }
9659
9660 static void __exit niu_exit(void)
9661 {
9662         pci_unregister_driver(&niu_pci_driver);
9663 #ifdef CONFIG_SPARC64
9664         of_unregister_driver(&niu_of_driver);
9665 #endif
9666 }
9667
9668 module_init(niu_init);
9669 module_exit(niu_exit);