Merge git://git.infradead.org/battery-2.6
[linux-2.6] / arch / powerpc / boot / dts / mpc832x_mds.dts
1 /*
2  * MPC8323E EMDS Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10
11  * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
12  * this:
13  *
14  * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
15  * 2) Solder a wire from U61-21 to P19A-23.  P19 is a grid of pins on the board
16  *    next to the serial ports.
17  * 3) Solder a wire from U61-22 to P19K-22.
18  *
19  * Note that there's a typo in the schematic.  The board labels the last column
20  * of pins "P19K", but in the schematic, that column is called "P19J".  So if
21  * you're going by the schematic, the pin is called "P19J-K22".
22  */
23
24 /dts-v1/;
25
26 / {
27         model = "MPC8323EMDS";
28         compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
29         #address-cells = <1>;
30         #size-cells = <1>;
31
32         aliases {
33                 ethernet0 = &enet0;
34                 ethernet1 = &enet1;
35                 serial0 = &serial0;
36                 serial1 = &serial1;
37                 pci0 = &pci0;
38         };
39
40         cpus {
41                 #address-cells = <1>;
42                 #size-cells = <0>;
43
44                 PowerPC,8323@0 {
45                         device_type = "cpu";
46                         reg = <0x0>;
47                         d-cache-line-size = <32>;       // 32 bytes
48                         i-cache-line-size = <32>;       // 32 bytes
49                         d-cache-size = <16384>;         // L1, 16K
50                         i-cache-size = <16384>;         // L1, 16K
51                         timebase-frequency = <0>;
52                         bus-frequency = <0>;
53                         clock-frequency = <0>;
54                 };
55         };
56
57         memory {
58                 device_type = "memory";
59                 reg = <0x00000000 0x08000000>;
60         };
61
62         bcsr@f8000000 {
63                 device_type = "board-control";
64                 reg = <0xf8000000 0x8000>;
65         };
66
67         soc8323@e0000000 {
68                 #address-cells = <1>;
69                 #size-cells = <1>;
70                 device_type = "soc";
71                 ranges = <0x0 0xe0000000 0x00100000>;
72                 reg = <0xe0000000 0x00000200>;
73                 bus-frequency = <132000000>;
74
75                 wdt@200 {
76                         device_type = "watchdog";
77                         compatible = "mpc83xx_wdt";
78                         reg = <0x200 0x100>;
79                 };
80
81                 i2c@3000 {
82                         #address-cells = <1>;
83                         #size-cells = <0>;
84                         cell-index = <0>;
85                         compatible = "fsl-i2c";
86                         reg = <0x3000 0x100>;
87                         interrupts = <14 0x8>;
88                         interrupt-parent = <&ipic>;
89                         dfsrr;
90
91                         rtc@68 {
92                                 compatible = "dallas,ds1374";
93                                 reg = <0x68>;
94                         };
95                 };
96
97                 serial0: serial@4500 {
98                         cell-index = <0>;
99                         device_type = "serial";
100                         compatible = "ns16550";
101                         reg = <0x4500 0x100>;
102                         clock-frequency = <0>;
103                         interrupts = <9 0x8>;
104                         interrupt-parent = <&ipic>;
105                 };
106
107                 serial1: serial@4600 {
108                         cell-index = <1>;
109                         device_type = "serial";
110                         compatible = "ns16550";
111                         reg = <0x4600 0x100>;
112                         clock-frequency = <0>;
113                         interrupts = <10 0x8>;
114                         interrupt-parent = <&ipic>;
115                 };
116
117                 crypto@30000 {
118                         device_type = "crypto";
119                         model = "SEC2";
120                         compatible = "talitos";
121                         reg = <0x30000 0x7000>;
122                         interrupts = <11 0x8>;
123                         interrupt-parent = <&ipic>;
124                         /* Rev. 2.2 */
125                         num-channels = <1>;
126                         channel-fifo-len = <24>;
127                         exec-units-mask = <0x0000004c>;
128                         descriptor-types-mask = <0x0122003f>;
129                 };
130
131                 ipic: pic@700 {
132                         interrupt-controller;
133                         #address-cells = <0>;
134                         #interrupt-cells = <2>;
135                         reg = <0x700 0x100>;
136                         device_type = "ipic";
137                 };
138
139                 par_io@1400 {
140                         reg = <0x1400 0x100>;
141                         device_type = "par_io";
142                         num-ports = <7>;
143
144                         pio3: ucc_pin@03 {
145                                 pio-map = <
146                         /* port  pin  dir  open_drain  assignment  has_irq */
147                                         3  4  3  0  2  0  /* MDIO */
148                                         3  5  1  0  2  0  /* MDC */
149                                         0 13  2  0  1  0        /* RX_CLK (CLK9) */
150                                         3 24  2  0  1  0        /* TX_CLK (CLK10) */
151                                         1  0  1  0  1  0        /* TxD0 */
152                                         1  1  1  0  1  0        /* TxD1 */
153                                         1  2  1  0  1  0        /* TxD2 */
154                                         1  3  1  0  1  0        /* TxD3 */
155                                         1  4  2  0  1  0        /* RxD0 */
156                                         1  5  2  0  1  0        /* RxD1 */
157                                         1  6  2  0  1  0        /* RxD2 */
158                                         1  7  2  0  1  0        /* RxD3 */
159                                         1  8  2  0  1  0        /* RX_ER */
160                                         1  9  1  0  1  0        /* TX_ER */
161                                         1 10  2  0  1  0        /* RX_DV */
162                                         1 11  2  0  1  0        /* COL */
163                                         1 12  1  0  1  0        /* TX_EN */
164                                         1 13  2  0  1  0>;      /* CRS */
165                         };
166                         pio4: ucc_pin@04 {
167                                 pio-map = <
168                         /* port  pin  dir  open_drain  assignment  has_irq */
169                                         3 31  2  0  1  0        /* RX_CLK (CLK7) */
170                                         3  6  2  0  1  0        /* TX_CLK (CLK8) */
171                                         1 18  1  0  1  0        /* TxD0 */
172                                         1 19  1  0  1  0        /* TxD1 */
173                                         1 20  1  0  1  0        /* TxD2 */
174                                         1 21  1  0  1  0        /* TxD3 */
175                                         1 22  2  0  1  0        /* RxD0 */
176                                         1 23  2  0  1  0        /* RxD1 */
177                                         1 24  2  0  1  0        /* RxD2 */
178                                         1 25  2  0  1  0        /* RxD3 */
179                                         1 26  2  0  1  0        /* RX_ER */
180                                         1 27  1  0  1  0        /* TX_ER */
181                                         1 28  2  0  1  0        /* RX_DV */
182                                         1 29  2  0  1  0        /* COL */
183                                         1 30  1  0  1  0        /* TX_EN */
184                                         1 31  2  0  1  0>;      /* CRS */
185                         };
186                         pio5: ucc_pin@05 {
187                                 pio-map = <
188                                 /*
189                                  *                    open       has
190                                  *   port  pin  dir  drain  sel  irq
191                                  */
192                                         2    0    1      0    2    0  /* TxD5 */
193                                         2    8    2      0    2    0  /* RxD5 */
194
195                                         2   29    2      0    0    0  /* CTS5 */
196                                         2   31    1      0    2    0  /* RTS5 */
197
198                                         2   24    2      0    0    0  /* CD */
199
200                                 >;
201                         };
202
203                 };
204         };
205
206         qe@e0100000 {
207                 #address-cells = <1>;
208                 #size-cells = <1>;
209                 device_type = "qe";
210                 compatible = "fsl,qe";
211                 ranges = <0x0 0xe0100000 0x00100000>;
212                 reg = <0xe0100000 0x480>;
213                 brg-frequency = <0>;
214                 bus-frequency = <198000000>;
215
216                 muram@10000 {
217                         #address-cells = <1>;
218                         #size-cells = <1>;
219                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
220                         ranges = <0x0 0x00010000 0x00004000>;
221
222                         data-only@0 {
223                                 compatible = "fsl,qe-muram-data",
224                                              "fsl,cpm-muram-data";
225                                 reg = <0x0 0x4000>;
226                         };
227                 };
228
229                 spi@4c0 {
230                         cell-index = <0>;
231                         compatible = "fsl,spi";
232                         reg = <0x4c0 0x40>;
233                         interrupts = <2>;
234                         interrupt-parent = <&qeic>;
235                         mode = "cpu";
236                 };
237
238                 spi@500 {
239                         cell-index = <1>;
240                         compatible = "fsl,spi";
241                         reg = <0x500 0x40>;
242                         interrupts = <1>;
243                         interrupt-parent = <&qeic>;
244                         mode = "cpu";
245                 };
246
247                 usb@6c0 {
248                         compatible = "qe_udc";
249                         reg = <0x6c0 0x40 0x8b00 0x100>;
250                         interrupts = <11>;
251                         interrupt-parent = <&qeic>;
252                         mode = "slave";
253                 };
254
255                 enet0: ucc@2200 {
256                         device_type = "network";
257                         compatible = "ucc_geth";
258                         cell-index = <3>;
259                         reg = <0x2200 0x200>;
260                         interrupts = <34>;
261                         interrupt-parent = <&qeic>;
262                         local-mac-address = [ 00 00 00 00 00 00 ];
263                         rx-clock-name = "clk9";
264                         tx-clock-name = "clk10";
265                         phy-handle = <&phy3>;
266                         pio-handle = <&pio3>;
267                 };
268
269                 enet1: ucc@3200 {
270                         device_type = "network";
271                         compatible = "ucc_geth";
272                         cell-index = <4>;
273                         reg = <0x3200 0x200>;
274                         interrupts = <35>;
275                         interrupt-parent = <&qeic>;
276                         local-mac-address = [ 00 00 00 00 00 00 ];
277                         rx-clock-name = "clk7";
278                         tx-clock-name = "clk8";
279                         phy-handle = <&phy4>;
280                         pio-handle = <&pio4>;
281                 };
282
283                 ucc@2400 {
284                         device_type = "serial";
285                         compatible = "ucc_uart";
286                         cell-index = <5>;       /* The UCC number, 1-7*/
287                         port-number = <0>;      /* Which ttyQEx device */
288                         soft-uart;              /* We need Soft-UART */
289                         reg = <0x2400 0x200>;
290                         interrupts = <40>;      /* From Table 18-12 */
291                         interrupt-parent = < &qeic >;
292                         /*
293                          * For Soft-UART, we need to set TX to 1X, which
294                          * means specifying separate clock sources.
295                          */
296                         rx-clock-name = "brg5";
297                         tx-clock-name = "brg6";
298                         pio-handle = < &pio5 >;
299                 };
300
301
302                 mdio@2320 {
303                         #address-cells = <1>;
304                         #size-cells = <0>;
305                         reg = <0x2320 0x18>;
306                         compatible = "fsl,ucc-mdio";
307
308                         phy3: ethernet-phy@03 {
309                                 interrupt-parent = <&ipic>;
310                                 interrupts = <17 0x8>;
311                                 reg = <0x3>;
312                                 device_type = "ethernet-phy";
313                         };
314                         phy4: ethernet-phy@04 {
315                                 interrupt-parent = <&ipic>;
316                                 interrupts = <18 0x8>;
317                                 reg = <0x4>;
318                                 device_type = "ethernet-phy";
319                         };
320                 };
321
322                 qeic: interrupt-controller@80 {
323                         interrupt-controller;
324                         compatible = "fsl,qe-ic";
325                         #address-cells = <0>;
326                         #interrupt-cells = <1>;
327                         reg = <0x80 0x80>;
328                         big-endian;
329                         interrupts = <32 0x8 33 0x8>; //high:32 low:33
330                         interrupt-parent = <&ipic>;
331                 };
332         };
333
334         pci0: pci@e0008500 {
335                 cell-index = <1>;
336                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
337                 interrupt-map = <
338                                 /* IDSEL 0x11 AD17 */
339                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
340                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
341                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
342                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
343
344                                 /* IDSEL 0x12 AD18 */
345                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
346                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
347                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
348                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
349
350                                 /* IDSEL 0x13 AD19 */
351                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
352                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
353                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
354                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
355
356                                 /* IDSEL 0x15 AD21*/
357                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
358                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
359                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
360                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
361
362                                 /* IDSEL 0x16 AD22*/
363                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
364                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
365                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
366                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
367
368                                 /* IDSEL 0x17 AD23*/
369                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
370                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
371                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
372                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
373
374                                 /* IDSEL 0x18 AD24*/
375                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
376                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
377                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
378                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
379                 interrupt-parent = <&ipic>;
380                 interrupts = <66 0x8>;
381                 bus-range = <0x0 0x0>;
382                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
383                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
384                           0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
385                 clock-frequency = <0>;
386                 #interrupt-cells = <1>;
387                 #size-cells = <2>;
388                 #address-cells = <3>;
389                 reg = <0xe0008500 0x100>;
390                 compatible = "fsl,mpc8349-pci";
391                 device_type = "pci";
392         };
393 };