2 * arch/s390/kernel/entry64.S
3 * S390 low-level entry points.
5 * Copyright (C) IBM Corp. 1999,2006
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/sys.h>
13 #include <linux/linkage.h>
14 #include <linux/init.h>
15 #include <asm/cache.h>
16 #include <asm/lowcore.h>
17 #include <asm/errno.h>
18 #include <asm/ptrace.h>
19 #include <asm/thread_info.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/unistd.h>
25 * Stack layout for the system_call stack entry.
26 * The first few entries are identical to the user_regs_struct.
28 SP_PTREGS = STACK_FRAME_OVERHEAD
29 SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
30 SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
31 SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
32 SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
33 SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
34 SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
35 SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
36 SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
37 SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
38 SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
39 SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64
40 SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72
41 SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80
42 SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88
43 SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96
44 SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104
45 SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112
46 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120
47 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
48 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
49 SP_TRAP = STACK_FRAME_OVERHEAD + __PT_TRAP
50 SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
52 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
53 STACK_SIZE = 1 << STACK_SHIFT
55 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
56 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
57 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
60 #define BASED(name) name-system_call(%r13)
62 #ifdef CONFIG_TRACE_IRQFLAGS
64 brasl %r14,trace_hardirqs_on
68 brasl %r14,trace_hardirqs_off
71 .macro TRACE_IRQS_CHECK
72 tm SP_PSW(%r15),0x03 # irqs enabled?
74 brasl %r14,trace_hardirqs_on
76 0: brasl %r14,trace_hardirqs_off
81 #define TRACE_IRQS_OFF
82 #define TRACE_IRQS_CHECK
86 .macro LOCKDEP_SYS_EXIT
87 tm SP_PSW+1(%r15),0x01 # returning to user ?
89 brasl %r14,lockdep_sys_exit
93 #define LOCKDEP_SYS_EXIT
96 .macro STORE_TIMER lc_offset
97 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
102 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
103 .macro UPDATE_VTIME lc_from,lc_to,lc_sum
112 * Register usage in interrupt handlers:
113 * R9 - pointer to current task structure
114 * R13 - pointer to literal pool
115 * R14 - return register for function calls
116 * R15 - kernel stack pointer
119 .macro SAVE_ALL_BASE savearea
120 stmg %r12,%r15,\savearea
121 larl %r13,system_call
124 .macro SAVE_ALL_SVC psworg,savearea
126 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
129 .macro SAVE_ALL_SYNC psworg,savearea
131 tm \psworg+1,0x01 # test problem state bit
132 jz 2f # skip stack setup save
133 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
134 #ifdef CONFIG_CHECK_STACK
136 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
143 .macro SAVE_ALL_ASYNC psworg,savearea
145 tm \psworg+1,0x01 # test problem state bit
146 jnz 1f # from user -> load kernel stack
147 clc \psworg+8(8),BASED(.Lcritical_end)
149 clc \psworg+8(8),BASED(.Lcritical_start)
151 brasl %r14,cleanup_critical
152 tm 1(%r12),0x01 # retest problem state after cleanup
154 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ?
156 srag %r14,%r14,STACK_SHIFT
158 1: lg %r15,__LC_ASYNC_STACK # load async stack
159 #ifdef CONFIG_CHECK_STACK
161 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
168 .macro CREATE_STACK_FRAME psworg,savearea
169 aghi %r15,-SP_SIZE # make room for registers & psw
170 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
172 stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
173 icm %r12,12,__LC_SVC_ILC
174 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
176 mvc SP_R12(32,%r15),\savearea # move %r12-%r15 to stack
178 stg %r12,__SF_BACKCHAIN(%r15)
181 .macro RESTORE_ALL psworg,sync
182 mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore
184 ni \psworg+1,0xfd # clear wait state bit
186 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 of user
187 STORE_TIMER __LC_EXIT_TIMER
188 lpswe \psworg # back to caller
192 * Scheduler resume function, called by switch_to
193 * gpr2 = (task_struct *) prev
194 * gpr3 = (task_struct *) next
200 tm __THREAD_per+4(%r3),0xe8 # is the new process using per ?
201 jz __switch_to_noper # if not we're fine
202 stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff
203 clc __THREAD_per(24,%r3),__SF_EMPTY(%r15)
204 je __switch_to_noper # we got away without bashing TLB's
205 lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't
207 lg %r4,__THREAD_info(%r2) # get thread_info of prev
208 tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending?
209 jz __switch_to_no_mcck
210 ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
211 lg %r4,__THREAD_info(%r3) # get thread_info of next
212 oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next
214 stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task
215 stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
216 lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
217 lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task
218 stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct
219 lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
220 lg %r3,__THREAD_info(%r3) # load thread_info from task struct
221 stg %r3,__LC_THREAD_INFO
223 stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
228 * SVC interrupt handler routine. System calls are synchronous events and
229 * are executed with interrupts enabled.
234 STORE_TIMER __LC_SYNC_ENTER_TIMER
236 SAVE_ALL_BASE __LC_SAVE_AREA
237 SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
238 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
239 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
240 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
242 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
244 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
246 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
249 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
250 slag %r7,%r7,2 # *4 and test for svc 0
252 # svc 0: system call number in %r1
253 cl %r1,BASED(.Lnr_syscalls)
255 lgfr %r7,%r1 # clear high word in r1
256 slag %r7,%r7,2 # svc 0: system call number in %r1
258 mvc SP_ARGS(8,%r15),SP_R7(%r15)
260 larl %r10,sys_call_table
262 tm __TI_flags+5(%r9),(_TIF_31BIT>>16) # running in 31 bit mode ?
264 larl %r10,sys_call_table_emu # use 31 bit emulation system calls
267 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
268 lgf %r8,0(%r7,%r10) # load address of system call routine
270 basr %r14,%r8 # call sys_xxxx
271 stg %r2,SP_R2(%r15) # store return value (change R2 on stack)
274 tm SP_PSW+1(%r15),0x01 # returning to user ?
276 tm __TI_flags+7(%r9),_TIF_WORK_SVC
277 jnz sysc_work # there is work to do (signals etc.)
279 #ifdef CONFIG_TRACE_IRQFLAGS
280 larl %r1,sysc_restore_trace_psw
287 RESTORE_ALL __LC_RETURN_PSW,1
290 #ifdef CONFIG_TRACE_IRQFLAGS
292 .globl sysc_restore_trace_psw
293 sysc_restore_trace_psw:
294 .quad 0, sysc_restore_trace
298 # recheck if there is more work to do
301 tm __TI_flags+7(%r9),_TIF_WORK_SVC
302 jz sysc_restore # there is no work to do
304 # One of the work bits is on. Find out which one.
307 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
309 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
311 tm __TI_flags+7(%r9),_TIF_SIGPENDING
313 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
315 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
321 # _TIF_NEED_RESCHED is set, call schedule
324 larl %r14,sysc_work_loop
325 jg schedule # return point is sysc_return
328 # _TIF_MCCK_PENDING is set, call handler
331 larl %r14,sysc_work_loop
332 jg s390_handle_mcck # TIF bit will be cleared by handler
335 # _TIF_SIGPENDING is set, call do_signal
338 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
339 la %r2,SP_PTREGS(%r15) # load pt_regs
340 brasl %r14,do_signal # call do_signal
341 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
343 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
348 # _TIF_RESTART_SVC is set, set up registers and restart svc
351 ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
352 lg %r7,SP_R2(%r15) # load new svc number
354 mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument
355 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
356 j sysc_do_restart # restart svc
359 # _TIF_SINGLE_STEP is set, call do_single_step
362 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
363 lhi %r0,__LC_PGM_OLD_PSW
364 sth %r0,SP_TRAP(%r15) # set trap indication to pgm check
365 la %r2,SP_PTREGS(%r15) # address of register-save area
366 larl %r14,sysc_return # load adr. of system return
367 jg do_single_step # branch to do_sigtrap
370 # call syscall_trace before and after system call
371 # special linkage: %r12 contains the return address for trace_svc
374 la %r2,SP_PTREGS(%r15) # load pt_regs
378 brasl %r14,syscall_trace
382 lg %r7,SP_R2(%r15) # strace might have changed the
383 sll %r7,2 # system call
386 lmg %r3,%r6,SP_R3(%r15)
387 lg %r2,SP_ORIG_R2(%r15)
388 basr %r14,%r8 # call sys_xxx
389 stg %r2,SP_R2(%r15) # store return value
391 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
393 la %r2,SP_PTREGS(%r15) # load pt_regs
395 larl %r14,sysc_return # return point is sysc_return
399 # a new process exits the kernel with ret_from_fork
403 lg %r13,__LC_SVC_NEW_PSW+8
404 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
405 tm SP_PSW+1(%r15),0x01 # forking a kernel thread ?
407 stg %r15,SP_R15(%r15) # store stack pointer for new kthread
408 0: brasl %r14,schedule_tail
410 stosm 24(%r15),0x03 # reenable interrupts
414 # kernel_execve function needs to deal with pt_regs that is not
419 stmg %r12,%r15,96(%r15)
422 stg %r14,__SF_BACKCHAIN(%r15)
423 la %r12,SP_PTREGS(%r15)
424 xc 0(__PT_SIZE,%r12),0(%r12)
430 lmg %r12,%r15,96(%r15)
433 0: stnsm __SF_EMPTY(%r15),0xfc # disable interrupts
434 lg %r15,__LC_KERNEL_STACK # load ksp
435 aghi %r15,-SP_SIZE # make room for registers & psw
436 lg %r13,__LC_SVC_NEW_PSW+8
437 lg %r9,__LC_THREAD_INFO
438 mvc SP_PTREGS(__PT_SIZE,%r15),0(%r12) # copy pt_regs
439 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
440 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
441 brasl %r14,execve_tail
445 * Program check handler routine
448 .globl pgm_check_handler
451 * First we need to check for a special case:
452 * Single stepping an instruction that disables the PER event mask will
453 * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
454 * For a single stepped SVC the program check handler gets control after
455 * the SVC new PSW has been loaded. But we want to execute the SVC first and
456 * then handle the PER event. Therefore we update the SVC old PSW to point
457 * to the pgm_check_handler and branch to the SVC handler after we checked
458 * if we have to load the kernel stack register.
459 * For every other possible cause for PER event without the PER mask set
460 * we just ignore the PER event (FIXME: is there anything we have to do
463 STORE_TIMER __LC_SYNC_ENTER_TIMER
464 SAVE_ALL_BASE __LC_SAVE_AREA
465 tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
466 jnz pgm_per # got per exception -> special case
467 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
468 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
469 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
470 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
472 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
473 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
474 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
477 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
478 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
480 lgf %r3,__LC_PGM_ILC # load program interruption code
485 larl %r1,pgm_check_table
486 lg %r1,0(%r8,%r1) # load address of handler routine
487 la %r2,SP_PTREGS(%r15) # address of register-save area
488 larl %r14,sysc_return
489 br %r1 # branch to interrupt-handler
492 # handle per exception
495 tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
496 jnz pgm_per_std # ok, normal per event from user space
497 # ok its one of the special cases, now we need to find out which one
498 clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
500 # no interesting special case, ignore PER event
501 lmg %r12,%r15,__LC_SAVE_AREA
502 lpswe __LC_PGM_OLD_PSW
505 # Normal per exception
508 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
509 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
510 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
511 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
513 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
514 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
515 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
518 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
520 lg %r1,__TI_task(%r9)
521 tm SP_PSW+1(%r15),0x01 # kernel per event ?
523 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
524 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
525 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
526 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
527 lgf %r3,__LC_PGM_ILC # load program interruption code
529 ngr %r8,%r3 # clear per-event-bit and ilc
534 # it was a single stepped SVC that is causing all the trouble
537 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
538 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
539 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
540 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
541 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
542 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
544 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
545 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
546 lg %r1,__TI_task(%r9)
547 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
548 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
549 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
550 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
552 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
556 # per was called from kernel, must be kprobes
559 lhi %r0,__LC_PGM_OLD_PSW
560 sth %r0,SP_TRAP(%r15) # set trap indication to pgm check
561 la %r2,SP_PTREGS(%r15) # address of register-save area
562 larl %r14,sysc_restore # load adr. of system ret, no work
563 jg do_single_step # branch to do_single_step
566 * IO interrupt handler routine
568 .globl io_int_handler
570 STORE_TIMER __LC_ASYNC_ENTER_TIMER
572 SAVE_ALL_BASE __LC_SAVE_AREA+32
573 SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
574 CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
575 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
576 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
578 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
579 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
580 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
583 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
585 la %r2,SP_PTREGS(%r15) # address of register-save area
586 brasl %r14,do_IRQ # call standard irq handler
588 tm SP_PSW+1(%r15),0x01 # returning to user ?
589 #ifdef CONFIG_PREEMPT
590 jno io_preempt # no -> check for preemptive scheduling
592 jno io_restore # no-> skip resched & signal
594 tm __TI_flags+7(%r9),_TIF_WORK_INT
595 jnz io_work # there is work to do (signals etc.)
597 #ifdef CONFIG_TRACE_IRQFLAGS
598 larl %r1,io_restore_trace_psw
605 RESTORE_ALL __LC_RETURN_PSW,0
608 #ifdef CONFIG_TRACE_IRQFLAGS
610 .globl io_restore_trace_psw
611 io_restore_trace_psw:
612 .quad 0, io_restore_trace
615 #ifdef CONFIG_PREEMPT
617 icm %r0,15,__TI_precount(%r9)
619 # switch to kernel stack
622 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
623 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
626 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
628 larl %r14,io_resume_loop
629 jg preempt_schedule_irq
633 # switch to kernel stack, then check TIF bits
636 lg %r1,__LC_KERNEL_STACK
638 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
639 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
642 # One of the work bits is on. Find out which one.
643 # Checked are: _TIF_SIGPENDING, _TIF_RESTORE_SIGPENDING, _TIF_NEED_RESCHED
644 # and _TIF_MCCK_PENDING
647 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
649 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
651 tm __TI_flags+7(%r9),_TIF_SIGPENDING
657 # _TIF_MCCK_PENDING is set, call handler
660 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
664 # _TIF_NEED_RESCHED is set, call schedule
668 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
669 brasl %r14,schedule # call scheduler
670 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
672 tm __TI_flags+7(%r9),_TIF_WORK_INT
673 jz io_restore # there is no work to do
677 # _TIF_SIGPENDING or is set, call do_signal
681 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
682 la %r2,SP_PTREGS(%r15) # load pt_regs
683 brasl %r14,do_signal # call do_signal
684 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
689 * External interrupt handler routine
691 .globl ext_int_handler
693 STORE_TIMER __LC_ASYNC_ENTER_TIMER
695 SAVE_ALL_BASE __LC_SAVE_AREA+32
696 SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
697 CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
698 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
699 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
701 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
702 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
703 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
706 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
708 la %r2,SP_PTREGS(%r15) # address of register-save area
709 llgh %r3,__LC_EXT_INT_CODE # get interruption code
716 * Machine check handler routines
718 .globl mcck_int_handler
720 la %r1,4095 # revalidate r1
721 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
722 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
723 SAVE_ALL_BASE __LC_SAVE_AREA+64
724 la %r12,__LC_MCK_OLD_PSW
725 tm __LC_MCCK_CODE,0x80 # system damage?
726 jo mcck_int_main # yes -> rest of mcck code invalid
727 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
729 mvc __LC_SAVE_AREA+104(8),__LC_ASYNC_ENTER_TIMER
730 mvc __LC_ASYNC_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14)
731 tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid?
733 la %r14,__LC_SYNC_ENTER_TIMER
734 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
736 la %r14,__LC_ASYNC_ENTER_TIMER
737 0: clc 0(8,%r14),__LC_EXIT_TIMER
739 la %r14,__LC_EXIT_TIMER
740 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
742 la %r14,__LC_LAST_UPDATE_TIMER
744 mvc __LC_ASYNC_ENTER_TIMER(8),0(%r14)
747 tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid?
748 jno mcck_int_main # no -> skip cleanup critical
749 tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit
750 jnz mcck_int_main # from user -> load kernel stack
751 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end)
753 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start)
755 brasl %r14,cleanup_critical
757 lg %r14,__LC_PANIC_STACK # are we already on the panic stack?
759 srag %r14,%r14,PAGE_SHIFT
761 lg %r15,__LC_PANIC_STACK # load panic stack
762 0: CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64
763 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
764 tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid?
765 jno mcck_no_vtime # no -> no timer update
766 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
768 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
769 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
770 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
773 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
774 la %r2,SP_PTREGS(%r15) # load pt_regs
775 brasl %r14,s390_do_machine_check
776 tm SP_PSW+1(%r15),0x01 # returning to user ?
778 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
780 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
781 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
783 stosm __SF_EMPTY(%r15),0x04 # turn dat on
784 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
787 brasl %r14,s390_handle_mcck
790 mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW
791 ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
792 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15
793 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
794 mvc __LC_ASYNC_ENTER_TIMER(8),__LC_SAVE_AREA+104
795 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
800 lpswe __LC_RETURN_MCCK_PSW # back to caller
803 * Restart interruption handler, kick starter for additional CPUs
807 .globl restart_int_handler
809 lg %r15,__LC_SAVE_AREA+120 # load ksp
810 lghi %r10,__LC_CREGS_SAVE_AREA
811 lctlg %c0,%c15,0(%r10) # get new ctl regs
812 lghi %r10,__LC_AREGS_SAVE_AREA
814 lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone
815 stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on
820 * If we do not run with SMP enabled, let the new CPU crash ...
822 .globl restart_int_handler
826 lpswe restart_crash-restart_base(%r1)
829 .long 0x000a0000,0x00000000,0x00000000,0x00000000
833 #ifdef CONFIG_CHECK_STACK
835 * The synchronous or the asynchronous stack overflowed. We are dead.
836 * No need to properly save the registers, we are going to panic anyway.
837 * Setup a pt_regs so that show_trace can provide a good call trace.
840 lg %r15,__LC_PANIC_STACK # change to panic stack
842 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
843 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
844 la %r1,__LC_SAVE_AREA
845 chi %r12,__LC_SVC_OLD_PSW
847 chi %r12,__LC_PGM_OLD_PSW
849 la %r1,__LC_SAVE_AREA+32
850 0: mvc SP_R12(32,%r15),0(%r1) # move %r12-%r15 to stack
851 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
852 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain
853 la %r2,SP_PTREGS(%r15) # load pt_regs
854 jg kernel_stack_overflow
857 cleanup_table_system_call:
858 .quad system_call, sysc_do_svc
859 cleanup_table_sysc_return:
860 .quad sysc_return, sysc_leave
861 cleanup_table_sysc_leave:
862 .quad sysc_leave, sysc_done
863 cleanup_table_sysc_work_loop:
864 .quad sysc_work_loop, sysc_work_done
865 cleanup_table_io_return:
866 .quad io_return, io_leave
867 cleanup_table_io_leave:
868 .quad io_leave, io_done
869 cleanup_table_io_work_loop:
870 .quad io_work_loop, io_work_done
873 clc 8(8,%r12),BASED(cleanup_table_system_call)
875 clc 8(8,%r12),BASED(cleanup_table_system_call+8)
876 jl cleanup_system_call
878 clc 8(8,%r12),BASED(cleanup_table_sysc_return)
880 clc 8(8,%r12),BASED(cleanup_table_sysc_return+8)
881 jl cleanup_sysc_return
883 clc 8(8,%r12),BASED(cleanup_table_sysc_leave)
885 clc 8(8,%r12),BASED(cleanup_table_sysc_leave+8)
886 jl cleanup_sysc_leave
888 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop)
890 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop+8)
891 jl cleanup_sysc_return
893 clc 8(8,%r12),BASED(cleanup_table_io_return)
895 clc 8(8,%r12),BASED(cleanup_table_io_return+8)
898 clc 8(8,%r12),BASED(cleanup_table_io_leave)
900 clc 8(8,%r12),BASED(cleanup_table_io_leave+8)
903 clc 8(8,%r12),BASED(cleanup_table_io_work_loop)
905 clc 8(8,%r12),BASED(cleanup_table_io_work_loop+8)
911 mvc __LC_RETURN_PSW(16),0(%r12)
912 cghi %r12,__LC_MCK_OLD_PSW
914 la %r12,__LC_SAVE_AREA+32
916 0: la %r12,__LC_SAVE_AREA+64
918 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
919 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8)
921 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
922 0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16)
925 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn)
927 mvc __LC_SAVE_AREA(32),0(%r12)
929 stg %r12,__LC_SAVE_AREA+96 # argh
930 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
931 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
932 lg %r12,__LC_SAVE_AREA+96 # argh
934 llgh %r7,__LC_SVC_INT_CODE
935 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
937 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24)
939 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
941 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32)
943 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
945 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
947 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)
948 la %r12,__LC_RETURN_PSW
950 cleanup_system_call_insn:
952 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
960 mvc __LC_RETURN_PSW(8),0(%r12)
961 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_return)
962 la %r12,__LC_RETURN_PSW
966 clc 8(8,%r12),BASED(cleanup_sysc_leave_insn)
968 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
969 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
970 clc 8(8,%r12),BASED(cleanup_sysc_leave_insn+8)
973 mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
974 cghi %r12,__LC_MCK_OLD_PSW
976 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
978 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
979 1: lmg %r0,%r11,SP_R0(%r15)
981 2: la %r12,__LC_RETURN_PSW
983 cleanup_sysc_leave_insn:
985 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
990 mvc __LC_RETURN_PSW(8),0(%r12)
991 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_work_loop)
992 la %r12,__LC_RETURN_PSW
996 clc 8(8,%r12),BASED(cleanup_io_leave_insn)
998 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
999 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1000 clc 8(8,%r12),BASED(cleanup_io_leave_insn+8)
1003 mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
1004 cghi %r12,__LC_MCK_OLD_PSW
1006 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
1008 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
1009 1: lmg %r0,%r11,SP_R0(%r15)
1010 lg %r15,SP_R15(%r15)
1011 2: la %r12,__LC_RETURN_PSW
1013 cleanup_io_leave_insn:
1015 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
1024 .Lnr_syscalls: .long NR_syscalls
1025 .L0x0130: .short 0x130
1026 .L0x0140: .short 0x140
1027 .L0x0150: .short 0x150
1028 .L0x0160: .short 0x160
1029 .L0x0170: .short 0x170
1031 .quad __critical_start
1033 .quad __critical_end
1035 .section .rodata, "a"
1036 #define SYSCALL(esa,esame,emu) .long esame
1038 #include "syscalls.S"
1041 #ifdef CONFIG_COMPAT
1043 #define SYSCALL(esa,esame,emu) .long emu
1045 #include "syscalls.S"