iwlwifi: kill struct iwl4965_lq_mngr
[linux-2.6] / drivers / net / sfc / falcon.c
1 /****************************************************************************
2  * Driver for Solarflare Solarstorm network controllers and boards
3  * Copyright 2005-2006 Fen Systems Ltd.
4  * Copyright 2006-2008 Solarflare Communications Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation, incorporated herein by reference.
9  */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include "net_driver.h"
19 #include "bitfield.h"
20 #include "efx.h"
21 #include "mac.h"
22 #include "gmii.h"
23 #include "spi.h"
24 #include "falcon.h"
25 #include "falcon_hwdefs.h"
26 #include "falcon_io.h"
27 #include "mdio_10g.h"
28 #include "phy.h"
29 #include "boards.h"
30 #include "workarounds.h"
31
32 /* Falcon hardware control.
33  * Falcon is the internal codename for the SFC4000 controller that is
34  * present in SFE400X evaluation boards
35  */
36
37 /**
38  * struct falcon_nic_data - Falcon NIC state
39  * @next_buffer_table: First available buffer table id
40  * @pci_dev2: The secondary PCI device if present
41  * @i2c_data: Operations and state for I2C bit-bashing algorithm
42  */
43 struct falcon_nic_data {
44         unsigned next_buffer_table;
45         struct pci_dev *pci_dev2;
46         struct i2c_algo_bit_data i2c_data;
47 };
48
49 /**************************************************************************
50  *
51  * Configurable values
52  *
53  **************************************************************************
54  */
55
56 static int disable_dma_stats;
57
58 /* This is set to 16 for a good reason.  In summary, if larger than
59  * 16, the descriptor cache holds more than a default socket
60  * buffer's worth of packets (for UDP we can only have at most one
61  * socket buffer's worth outstanding).  This combined with the fact
62  * that we only get 1 TX event per descriptor cache means the NIC
63  * goes idle.
64  */
65 #define TX_DC_ENTRIES 16
66 #define TX_DC_ENTRIES_ORDER 0
67 #define TX_DC_BASE 0x130000
68
69 #define RX_DC_ENTRIES 64
70 #define RX_DC_ENTRIES_ORDER 2
71 #define RX_DC_BASE 0x100000
72
73 /* RX FIFO XOFF watermark
74  *
75  * When the amount of the RX FIFO increases used increases past this
76  * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
77  * This also has an effect on RX/TX arbitration
78  */
79 static int rx_xoff_thresh_bytes = -1;
80 module_param(rx_xoff_thresh_bytes, int, 0644);
81 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
82
83 /* RX FIFO XON watermark
84  *
85  * When the amount of the RX FIFO used decreases below this
86  * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
87  * This also has an effect on RX/TX arbitration
88  */
89 static int rx_xon_thresh_bytes = -1;
90 module_param(rx_xon_thresh_bytes, int, 0644);
91 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
92
93 /* TX descriptor ring size - min 512 max 4k */
94 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
95 #define FALCON_TXD_RING_SIZE 1024
96 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
97
98 /* RX descriptor ring size - min 512 max 4k */
99 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
100 #define FALCON_RXD_RING_SIZE 1024
101 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
102
103 /* Event queue size - max 32k */
104 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
105 #define FALCON_EVQ_SIZE 4096
106 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
107
108 /* Max number of internal errors. After this resets will not be performed */
109 #define FALCON_MAX_INT_ERRORS 4
110
111 /* Maximum period that we wait for flush events. If the flush event
112  * doesn't arrive in this period of time then we check if the queue
113  * was disabled anyway. */
114 #define FALCON_FLUSH_TIMEOUT 10 /* 10ms */
115
116 /**************************************************************************
117  *
118  * Falcon constants
119  *
120  **************************************************************************
121  */
122
123 /* DMA address mask */
124 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
125
126 /* TX DMA length mask (13-bit) */
127 #define FALCON_TX_DMA_MASK (4096 - 1)
128
129 /* Size and alignment of special buffers (4KB) */
130 #define FALCON_BUF_SIZE 4096
131
132 /* Dummy SRAM size code */
133 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
134
135 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
136 #define PCI_EXP_DEVCAP_PWR_VAL_LBN      18
137 #define PCI_EXP_DEVCAP_PWR_SCL_LBN      26
138 #define PCI_EXP_DEVCTL_PAYLOAD_LBN      5
139 #define PCI_EXP_LNKSTA_LNK_WID          0x3f0
140 #define PCI_EXP_LNKSTA_LNK_WID_LBN      4
141
142 #define FALCON_IS_DUAL_FUNC(efx)                \
143         (falcon_rev(efx) < FALCON_REV_B0)
144
145 /**************************************************************************
146  *
147  * Falcon hardware access
148  *
149  **************************************************************************/
150
151 /* Read the current event from the event queue */
152 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
153                                         unsigned int index)
154 {
155         return (((efx_qword_t *) (channel->eventq.addr)) + index);
156 }
157
158 /* See if an event is present
159  *
160  * We check both the high and low dword of the event for all ones.  We
161  * wrote all ones when we cleared the event, and no valid event can
162  * have all ones in either its high or low dwords.  This approach is
163  * robust against reordering.
164  *
165  * Note that using a single 64-bit comparison is incorrect; even
166  * though the CPU read will be atomic, the DMA write may not be.
167  */
168 static inline int falcon_event_present(efx_qword_t *event)
169 {
170         return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
171                   EFX_DWORD_IS_ALL_ONES(event->dword[1])));
172 }
173
174 /**************************************************************************
175  *
176  * I2C bus - this is a bit-bashing interface using GPIO pins
177  * Note that it uses the output enables to tristate the outputs
178  * SDA is the data pin and SCL is the clock
179  *
180  **************************************************************************
181  */
182 static void falcon_setsda(void *data, int state)
183 {
184         struct efx_nic *efx = (struct efx_nic *)data;
185         efx_oword_t reg;
186
187         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
188         EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
189         falcon_write(efx, &reg, GPIO_CTL_REG_KER);
190 }
191
192 static void falcon_setscl(void *data, int state)
193 {
194         struct efx_nic *efx = (struct efx_nic *)data;
195         efx_oword_t reg;
196
197         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
198         EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
199         falcon_write(efx, &reg, GPIO_CTL_REG_KER);
200 }
201
202 static int falcon_getsda(void *data)
203 {
204         struct efx_nic *efx = (struct efx_nic *)data;
205         efx_oword_t reg;
206
207         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
208         return EFX_OWORD_FIELD(reg, GPIO3_IN);
209 }
210
211 static int falcon_getscl(void *data)
212 {
213         struct efx_nic *efx = (struct efx_nic *)data;
214         efx_oword_t reg;
215
216         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
217         return EFX_OWORD_FIELD(reg, GPIO0_IN);
218 }
219
220 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
221         .setsda         = falcon_setsda,
222         .setscl         = falcon_setscl,
223         .getsda         = falcon_getsda,
224         .getscl         = falcon_getscl,
225         .udelay         = 5,
226         /* Wait up to 50 ms for slave to let us pull SCL high */
227         .timeout        = DIV_ROUND_UP(HZ, 20),
228 };
229
230 /**************************************************************************
231  *
232  * Falcon special buffer handling
233  * Special buffers are used for event queues and the TX and RX
234  * descriptor rings.
235  *
236  *************************************************************************/
237
238 /*
239  * Initialise a Falcon special buffer
240  *
241  * This will define a buffer (previously allocated via
242  * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
243  * it to be used for event queues, descriptor rings etc.
244  */
245 static int
246 falcon_init_special_buffer(struct efx_nic *efx,
247                            struct efx_special_buffer *buffer)
248 {
249         efx_qword_t buf_desc;
250         int index;
251         dma_addr_t dma_addr;
252         int i;
253
254         EFX_BUG_ON_PARANOID(!buffer->addr);
255
256         /* Write buffer descriptors to NIC */
257         for (i = 0; i < buffer->entries; i++) {
258                 index = buffer->index + i;
259                 dma_addr = buffer->dma_addr + (i * 4096);
260                 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
261                         index, (unsigned long long)dma_addr);
262                 EFX_POPULATE_QWORD_4(buf_desc,
263                                      IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
264                                      BUF_ADR_REGION, 0,
265                                      BUF_ADR_FBUF, (dma_addr >> 12),
266                                      BUF_OWNER_ID_FBUF, 0);
267                 falcon_write_sram(efx, &buf_desc, index);
268         }
269
270         return 0;
271 }
272
273 /* Unmaps a buffer from Falcon and clears the buffer table entries */
274 static void
275 falcon_fini_special_buffer(struct efx_nic *efx,
276                            struct efx_special_buffer *buffer)
277 {
278         efx_oword_t buf_tbl_upd;
279         unsigned int start = buffer->index;
280         unsigned int end = (buffer->index + buffer->entries - 1);
281
282         if (!buffer->entries)
283                 return;
284
285         EFX_LOG(efx, "unmapping special buffers %d-%d\n",
286                 buffer->index, buffer->index + buffer->entries - 1);
287
288         EFX_POPULATE_OWORD_4(buf_tbl_upd,
289                              BUF_UPD_CMD, 0,
290                              BUF_CLR_CMD, 1,
291                              BUF_CLR_END_ID, end,
292                              BUF_CLR_START_ID, start);
293         falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
294 }
295
296 /*
297  * Allocate a new Falcon special buffer
298  *
299  * This allocates memory for a new buffer, clears it and allocates a
300  * new buffer ID range.  It does not write into Falcon's buffer table.
301  *
302  * This call will allocate 4KB buffers, since Falcon can't use 8KB
303  * buffers for event queues and descriptor rings.
304  */
305 static int falcon_alloc_special_buffer(struct efx_nic *efx,
306                                        struct efx_special_buffer *buffer,
307                                        unsigned int len)
308 {
309         struct falcon_nic_data *nic_data = efx->nic_data;
310
311         len = ALIGN(len, FALCON_BUF_SIZE);
312
313         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
314                                             &buffer->dma_addr);
315         if (!buffer->addr)
316                 return -ENOMEM;
317         buffer->len = len;
318         buffer->entries = len / FALCON_BUF_SIZE;
319         BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
320
321         /* All zeros is a potentially valid event so memset to 0xff */
322         memset(buffer->addr, 0xff, len);
323
324         /* Select new buffer ID */
325         buffer->index = nic_data->next_buffer_table;
326         nic_data->next_buffer_table += buffer->entries;
327
328         EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
329                 "(virt %p phys %lx)\n", buffer->index,
330                 buffer->index + buffer->entries - 1,
331                 (unsigned long long)buffer->dma_addr, len,
332                 buffer->addr, virt_to_phys(buffer->addr));
333
334         return 0;
335 }
336
337 static void falcon_free_special_buffer(struct efx_nic *efx,
338                                        struct efx_special_buffer *buffer)
339 {
340         if (!buffer->addr)
341                 return;
342
343         EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
344                 "(virt %p phys %lx)\n", buffer->index,
345                 buffer->index + buffer->entries - 1,
346                 (unsigned long long)buffer->dma_addr, buffer->len,
347                 buffer->addr, virt_to_phys(buffer->addr));
348
349         pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
350                             buffer->dma_addr);
351         buffer->addr = NULL;
352         buffer->entries = 0;
353 }
354
355 /**************************************************************************
356  *
357  * Falcon generic buffer handling
358  * These buffers are used for interrupt status and MAC stats
359  *
360  **************************************************************************/
361
362 static int falcon_alloc_buffer(struct efx_nic *efx,
363                                struct efx_buffer *buffer, unsigned int len)
364 {
365         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
366                                             &buffer->dma_addr);
367         if (!buffer->addr)
368                 return -ENOMEM;
369         buffer->len = len;
370         memset(buffer->addr, 0, len);
371         return 0;
372 }
373
374 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
375 {
376         if (buffer->addr) {
377                 pci_free_consistent(efx->pci_dev, buffer->len,
378                                     buffer->addr, buffer->dma_addr);
379                 buffer->addr = NULL;
380         }
381 }
382
383 /**************************************************************************
384  *
385  * Falcon TX path
386  *
387  **************************************************************************/
388
389 /* Returns a pointer to the specified transmit descriptor in the TX
390  * descriptor queue belonging to the specified channel.
391  */
392 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
393                                                unsigned int index)
394 {
395         return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
396 }
397
398 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
399 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
400 {
401         unsigned write_ptr;
402         efx_dword_t reg;
403
404         write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
405         EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
406         falcon_writel_page(tx_queue->efx, &reg,
407                            TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
408 }
409
410
411 /* For each entry inserted into the software descriptor ring, create a
412  * descriptor in the hardware TX descriptor ring (in host memory), and
413  * write a doorbell.
414  */
415 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
416 {
417
418         struct efx_tx_buffer *buffer;
419         efx_qword_t *txd;
420         unsigned write_ptr;
421
422         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
423
424         do {
425                 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
426                 buffer = &tx_queue->buffer[write_ptr];
427                 txd = falcon_tx_desc(tx_queue, write_ptr);
428                 ++tx_queue->write_count;
429
430                 /* Create TX descriptor ring entry */
431                 EFX_POPULATE_QWORD_5(*txd,
432                                      TX_KER_PORT, 0,
433                                      TX_KER_CONT, buffer->continuation,
434                                      TX_KER_BYTE_CNT, buffer->len,
435                                      TX_KER_BUF_REGION, 0,
436                                      TX_KER_BUF_ADR, buffer->dma_addr);
437         } while (tx_queue->write_count != tx_queue->insert_count);
438
439         wmb(); /* Ensure descriptors are written before they are fetched */
440         falcon_notify_tx_desc(tx_queue);
441 }
442
443 /* Allocate hardware resources for a TX queue */
444 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
445 {
446         struct efx_nic *efx = tx_queue->efx;
447         return falcon_alloc_special_buffer(efx, &tx_queue->txd,
448                                            FALCON_TXD_RING_SIZE *
449                                            sizeof(efx_qword_t));
450 }
451
452 int falcon_init_tx(struct efx_tx_queue *tx_queue)
453 {
454         efx_oword_t tx_desc_ptr;
455         struct efx_nic *efx = tx_queue->efx;
456         int rc;
457
458         /* Pin TX descriptor ring */
459         rc = falcon_init_special_buffer(efx, &tx_queue->txd);
460         if (rc)
461                 return rc;
462
463         /* Push TX descriptor ring to card */
464         EFX_POPULATE_OWORD_10(tx_desc_ptr,
465                               TX_DESCQ_EN, 1,
466                               TX_ISCSI_DDIG_EN, 0,
467                               TX_ISCSI_HDIG_EN, 0,
468                               TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
469                               TX_DESCQ_EVQ_ID, tx_queue->channel->evqnum,
470                               TX_DESCQ_OWNER_ID, 0,
471                               TX_DESCQ_LABEL, tx_queue->queue,
472                               TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
473                               TX_DESCQ_TYPE, 0,
474                               TX_NON_IP_DROP_DIS_B0, 1);
475
476         if (falcon_rev(efx) >= FALCON_REV_B0) {
477                 int csum = !(efx->net_dev->features & NETIF_F_IP_CSUM);
478                 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, csum);
479                 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, csum);
480         }
481
482         falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
483                            tx_queue->queue);
484
485         if (falcon_rev(efx) < FALCON_REV_B0) {
486                 efx_oword_t reg;
487
488                 BUG_ON(tx_queue->queue >= 128); /* HW limit */
489
490                 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
491                 if (efx->net_dev->features & NETIF_F_IP_CSUM)
492                         clear_bit_le(tx_queue->queue, (void *)&reg);
493                 else
494                         set_bit_le(tx_queue->queue, (void *)&reg);
495                 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
496         }
497
498         return 0;
499 }
500
501 static int falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
502 {
503         struct efx_nic *efx = tx_queue->efx;
504         struct efx_channel *channel = &efx->channel[0];
505         efx_oword_t tx_flush_descq;
506         unsigned int read_ptr, i;
507
508         /* Post a flush command */
509         EFX_POPULATE_OWORD_2(tx_flush_descq,
510                              TX_FLUSH_DESCQ_CMD, 1,
511                              TX_FLUSH_DESCQ, tx_queue->queue);
512         falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
513         msleep(FALCON_FLUSH_TIMEOUT);
514
515         if (EFX_WORKAROUND_7803(efx))
516                 return 0;
517
518         /* Look for a flush completed event */
519         read_ptr = channel->eventq_read_ptr;
520         for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
521                 efx_qword_t *event = falcon_event(channel, read_ptr);
522                 int ev_code, ev_sub_code, ev_queue;
523                 if (!falcon_event_present(event))
524                         break;
525
526                 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
527                 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
528                 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_TX_DESCQ_ID);
529                 if ((ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) &&
530                     (ev_queue == tx_queue->queue)) {
531                         EFX_LOG(efx, "tx queue %d flush command succesful\n",
532                                 tx_queue->queue);
533                         return 0;
534                 }
535
536                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
537         }
538
539         if (EFX_WORKAROUND_11557(efx)) {
540                 efx_oword_t reg;
541                 int enabled;
542
543                 falcon_read_table(efx, &reg, efx->type->txd_ptr_tbl_base,
544                                   tx_queue->queue);
545                 enabled = EFX_OWORD_FIELD(reg, TX_DESCQ_EN);
546                 if (!enabled) {
547                         EFX_LOG(efx, "tx queue %d disabled without a "
548                                 "flush event seen\n", tx_queue->queue);
549                         return 0;
550                 }
551         }
552
553         EFX_ERR(efx, "tx queue %d flush command timed out\n", tx_queue->queue);
554         return -ETIMEDOUT;
555 }
556
557 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
558 {
559         struct efx_nic *efx = tx_queue->efx;
560         efx_oword_t tx_desc_ptr;
561
562         /* Stop the hardware using the queue */
563         if (falcon_flush_tx_queue(tx_queue))
564                 EFX_ERR(efx, "failed to flush tx queue %d\n", tx_queue->queue);
565
566         /* Remove TX descriptor ring from card */
567         EFX_ZERO_OWORD(tx_desc_ptr);
568         falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
569                            tx_queue->queue);
570
571         /* Unpin TX descriptor ring */
572         falcon_fini_special_buffer(efx, &tx_queue->txd);
573 }
574
575 /* Free buffers backing TX queue */
576 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
577 {
578         falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
579 }
580
581 /**************************************************************************
582  *
583  * Falcon RX path
584  *
585  **************************************************************************/
586
587 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
588 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
589                                                unsigned int index)
590 {
591         return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
592 }
593
594 /* This creates an entry in the RX descriptor queue */
595 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
596                                         unsigned index)
597 {
598         struct efx_rx_buffer *rx_buf;
599         efx_qword_t *rxd;
600
601         rxd = falcon_rx_desc(rx_queue, index);
602         rx_buf = efx_rx_buffer(rx_queue, index);
603         EFX_POPULATE_QWORD_3(*rxd,
604                              RX_KER_BUF_SIZE,
605                              rx_buf->len -
606                              rx_queue->efx->type->rx_buffer_padding,
607                              RX_KER_BUF_REGION, 0,
608                              RX_KER_BUF_ADR, rx_buf->dma_addr);
609 }
610
611 /* This writes to the RX_DESC_WPTR register for the specified receive
612  * descriptor ring.
613  */
614 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
615 {
616         efx_dword_t reg;
617         unsigned write_ptr;
618
619         while (rx_queue->notified_count != rx_queue->added_count) {
620                 falcon_build_rx_desc(rx_queue,
621                                      rx_queue->notified_count &
622                                      FALCON_RXD_RING_MASK);
623                 ++rx_queue->notified_count;
624         }
625
626         wmb();
627         write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
628         EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
629         falcon_writel_page(rx_queue->efx, &reg,
630                            RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
631 }
632
633 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
634 {
635         struct efx_nic *efx = rx_queue->efx;
636         return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
637                                            FALCON_RXD_RING_SIZE *
638                                            sizeof(efx_qword_t));
639 }
640
641 int falcon_init_rx(struct efx_rx_queue *rx_queue)
642 {
643         efx_oword_t rx_desc_ptr;
644         struct efx_nic *efx = rx_queue->efx;
645         int rc;
646         int is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
647         int iscsi_digest_en = is_b0;
648
649         EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
650                 rx_queue->queue, rx_queue->rxd.index,
651                 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
652
653         /* Pin RX descriptor ring */
654         rc = falcon_init_special_buffer(efx, &rx_queue->rxd);
655         if (rc)
656                 return rc;
657
658         /* Push RX descriptor ring to card */
659         EFX_POPULATE_OWORD_10(rx_desc_ptr,
660                               RX_ISCSI_DDIG_EN, iscsi_digest_en,
661                               RX_ISCSI_HDIG_EN, iscsi_digest_en,
662                               RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
663                               RX_DESCQ_EVQ_ID, rx_queue->channel->evqnum,
664                               RX_DESCQ_OWNER_ID, 0,
665                               RX_DESCQ_LABEL, rx_queue->queue,
666                               RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
667                               RX_DESCQ_TYPE, 0 /* kernel queue */ ,
668                               /* For >=B0 this is scatter so disable */
669                               RX_DESCQ_JUMBO, !is_b0,
670                               RX_DESCQ_EN, 1);
671         falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
672                            rx_queue->queue);
673         return 0;
674 }
675
676 static int falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
677 {
678         struct efx_nic *efx = rx_queue->efx;
679         struct efx_channel *channel = &efx->channel[0];
680         unsigned int read_ptr, i;
681         efx_oword_t rx_flush_descq;
682
683         /* Post a flush command */
684         EFX_POPULATE_OWORD_2(rx_flush_descq,
685                              RX_FLUSH_DESCQ_CMD, 1,
686                              RX_FLUSH_DESCQ, rx_queue->queue);
687         falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
688         msleep(FALCON_FLUSH_TIMEOUT);
689
690         if (EFX_WORKAROUND_7803(efx))
691                 return 0;
692
693         /* Look for a flush completed event */
694         read_ptr = channel->eventq_read_ptr;
695         for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
696                 efx_qword_t *event = falcon_event(channel, read_ptr);
697                 int ev_code, ev_sub_code, ev_queue, ev_failed;
698                 if (!falcon_event_present(event))
699                         break;
700
701                 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
702                 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
703                 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_DESCQ_ID);
704                 ev_failed = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_FLUSH_FAIL);
705
706                 if ((ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) &&
707                     (ev_queue == rx_queue->queue)) {
708                         if (ev_failed) {
709                                 EFX_INFO(efx, "rx queue %d flush command "
710                                          "failed\n", rx_queue->queue);
711                                 return -EAGAIN;
712                         } else {
713                                 EFX_LOG(efx, "rx queue %d flush command "
714                                         "succesful\n", rx_queue->queue);
715                                 return 0;
716                         }
717                 }
718
719                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
720         }
721
722         if (EFX_WORKAROUND_11557(efx)) {
723                 efx_oword_t reg;
724                 int enabled;
725
726                 falcon_read_table(efx, &reg, efx->type->rxd_ptr_tbl_base,
727                                   rx_queue->queue);
728                 enabled = EFX_OWORD_FIELD(reg, RX_DESCQ_EN);
729                 if (!enabled) {
730                         EFX_LOG(efx, "rx queue %d disabled without a "
731                                 "flush event seen\n", rx_queue->queue);
732                         return 0;
733                 }
734         }
735
736         EFX_ERR(efx, "rx queue %d flush command timed out\n", rx_queue->queue);
737         return -ETIMEDOUT;
738 }
739
740 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
741 {
742         efx_oword_t rx_desc_ptr;
743         struct efx_nic *efx = rx_queue->efx;
744         int i, rc;
745
746         /* Try and flush the rx queue. This may need to be repeated */
747         for (i = 0; i < 5; i++) {
748                 rc = falcon_flush_rx_queue(rx_queue);
749                 if (rc == -EAGAIN)
750                         continue;
751                 break;
752         }
753         if (rc) {
754                 EFX_ERR(efx, "failed to flush rx queue %d\n", rx_queue->queue);
755                 efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
756         }
757
758         /* Remove RX descriptor ring from card */
759         EFX_ZERO_OWORD(rx_desc_ptr);
760         falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
761                            rx_queue->queue);
762
763         /* Unpin RX descriptor ring */
764         falcon_fini_special_buffer(efx, &rx_queue->rxd);
765 }
766
767 /* Free buffers backing RX queue */
768 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
769 {
770         falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
771 }
772
773 /**************************************************************************
774  *
775  * Falcon event queue processing
776  * Event queues are processed by per-channel tasklets.
777  *
778  **************************************************************************/
779
780 /* Update a channel's event queue's read pointer (RPTR) register
781  *
782  * This writes the EVQ_RPTR_REG register for the specified channel's
783  * event queue.
784  *
785  * Note that EVQ_RPTR_REG contains the index of the "last read" event,
786  * whereas channel->eventq_read_ptr contains the index of the "next to
787  * read" event.
788  */
789 void falcon_eventq_read_ack(struct efx_channel *channel)
790 {
791         efx_dword_t reg;
792         struct efx_nic *efx = channel->efx;
793
794         EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
795         falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
796                             channel->evqnum);
797 }
798
799 /* Use HW to insert a SW defined event */
800 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
801 {
802         efx_oword_t drv_ev_reg;
803
804         EFX_POPULATE_OWORD_2(drv_ev_reg,
805                              DRV_EV_QID, channel->evqnum,
806                              DRV_EV_DATA,
807                              EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
808         falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
809 }
810
811 /* Handle a transmit completion event
812  *
813  * Falcon batches TX completion events; the message we receive is of
814  * the form "complete all TX events up to this index".
815  */
816 static inline void falcon_handle_tx_event(struct efx_channel *channel,
817                                           efx_qword_t *event)
818 {
819         unsigned int tx_ev_desc_ptr;
820         unsigned int tx_ev_q_label;
821         struct efx_tx_queue *tx_queue;
822         struct efx_nic *efx = channel->efx;
823
824         if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
825                 /* Transmit completion */
826                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
827                 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
828                 tx_queue = &efx->tx_queue[tx_ev_q_label];
829                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
830         } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
831                 /* Rewrite the FIFO write pointer */
832                 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
833                 tx_queue = &efx->tx_queue[tx_ev_q_label];
834
835                 if (efx_dev_registered(efx))
836                         netif_tx_lock(efx->net_dev);
837                 falcon_notify_tx_desc(tx_queue);
838                 if (efx_dev_registered(efx))
839                         netif_tx_unlock(efx->net_dev);
840         } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
841                    EFX_WORKAROUND_10727(efx)) {
842                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
843         } else {
844                 EFX_ERR(efx, "channel %d unexpected TX event "
845                         EFX_QWORD_FMT"\n", channel->channel,
846                         EFX_QWORD_VAL(*event));
847         }
848 }
849
850 /* Check received packet's destination MAC address. */
851 static int check_dest_mac(struct efx_rx_queue *rx_queue,
852                           const efx_qword_t *event)
853 {
854         struct efx_rx_buffer *rx_buf;
855         struct efx_nic *efx = rx_queue->efx;
856         int rx_ev_desc_ptr;
857         struct ethhdr *eh;
858
859         if (efx->promiscuous)
860                 return 1;
861
862         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
863         rx_buf = efx_rx_buffer(rx_queue, rx_ev_desc_ptr);
864         eh = (struct ethhdr *)rx_buf->data;
865         if (memcmp(eh->h_dest, efx->net_dev->dev_addr, ETH_ALEN))
866                 return 0;
867         return 1;
868 }
869
870 /* Detect errors included in the rx_evt_pkt_ok bit. */
871 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
872                                     const efx_qword_t *event,
873                                     unsigned *rx_ev_pkt_ok,
874                                     int *discard, int byte_count)
875 {
876         struct efx_nic *efx = rx_queue->efx;
877         unsigned rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
878         unsigned rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
879         unsigned rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
880         unsigned rx_ev_pkt_type, rx_ev_other_err, rx_ev_pause_frm;
881         unsigned rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
882         int snap, non_ip;
883
884         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
885         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
886         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
887         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
888         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
889                                                  RX_EV_BUF_OWNER_ID_ERR);
890         rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
891         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
892                                                   RX_EV_IP_HDR_CHKSUM_ERR);
893         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
894                                                    RX_EV_TCP_UDP_CHKSUM_ERR);
895         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
896         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
897         rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
898                           0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
899         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
900
901         /* Every error apart from tobe_disc and pause_frm */
902         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
903                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
904                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
905
906         snap = (rx_ev_pkt_type == RX_EV_PKT_TYPE_LLC_DECODE) ||
907                 (rx_ev_pkt_type == RX_EV_PKT_TYPE_VLAN_LLC_DECODE);
908         non_ip = (rx_ev_hdr_type == RX_EV_HDR_TYPE_NON_IP_DECODE);
909
910         /* SFC bug 5475/8970: The Falcon XMAC incorrectly calculates the
911          * length field of an LLC frame, which sets TOBE_DISC. We could set
912          * PASS_LEN_ERR, but we want the MAC to filter out short frames (to
913          * protect the RX block).
914          *
915          * bug5475 - LLC/SNAP: Falcon identifies SNAP packets.
916          * bug8970 - LLC/noSNAP: Falcon does not provide an LLC flag.
917          *                       LLC can't encapsulate IP, so by definition
918          *                       these packets are NON_IP.
919          *
920          * Unicast mismatch will also cause TOBE_DISC, so the driver needs
921          * to check this.
922          */
923         if (EFX_WORKAROUND_5475(efx) && rx_ev_tobe_disc && (snap || non_ip)) {
924                 /* If all the other flags are zero then we can state the
925                  * entire packet is ok, which will flag to the kernel not
926                  * to recalculate checksums.
927                  */
928                 if (!(non_ip | rx_ev_other_err | rx_ev_pause_frm))
929                         *rx_ev_pkt_ok = 1;
930
931                 rx_ev_tobe_disc = 0;
932
933                 /* TOBE_DISC is set for unicast mismatch.  But given that
934                  * we can't trust TOBE_DISC here, we must validate the dest
935                  * MAC address ourselves.
936                  */
937                 if (!rx_ev_mcast_pkt && !check_dest_mac(rx_queue, event))
938                         rx_ev_tobe_disc = 1;
939         }
940
941         /* Count errors that are not in MAC stats. */
942         if (rx_ev_frm_trunc)
943                 ++rx_queue->channel->n_rx_frm_trunc;
944         else if (rx_ev_tobe_disc)
945                 ++rx_queue->channel->n_rx_tobe_disc;
946         else if (rx_ev_ip_hdr_chksum_err)
947                 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
948         else if (rx_ev_tcp_udp_chksum_err)
949                 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
950         if (rx_ev_ip_frag_err)
951                 ++rx_queue->channel->n_rx_ip_frag_err;
952
953         /* The frame must be discarded if any of these are true. */
954         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
955                     rx_ev_tobe_disc | rx_ev_pause_frm);
956
957         /* TOBE_DISC is expected on unicast mismatches; don't print out an
958          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
959          * to a FIFO overflow.
960          */
961 #ifdef EFX_ENABLE_DEBUG
962         if (rx_ev_other_err) {
963                 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
964                             EFX_QWORD_FMT "%s%s%s%s%s%s%s%s%s\n",
965                             rx_queue->queue, EFX_QWORD_VAL(*event),
966                             rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
967                             rx_ev_ip_hdr_chksum_err ?
968                             " [IP_HDR_CHKSUM_ERR]" : "",
969                             rx_ev_tcp_udp_chksum_err ?
970                             " [TCP_UDP_CHKSUM_ERR]" : "",
971                             rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
972                             rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
973                             rx_ev_drib_nib ? " [DRIB_NIB]" : "",
974                             rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
975                             rx_ev_pause_frm ? " [PAUSE]" : "",
976                             snap ? " [SNAP/LLC]" : "");
977         }
978 #endif
979
980         if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
981                      efx->phy_type == PHY_TYPE_10XPRESS))
982                 tenxpress_crc_err(efx);
983 }
984
985 /* Handle receive events that are not in-order. */
986 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
987                                        unsigned index)
988 {
989         struct efx_nic *efx = rx_queue->efx;
990         unsigned expected, dropped;
991
992         expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
993         dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
994                    FALCON_RXD_RING_MASK);
995         EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
996                 dropped, index, expected);
997
998         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
999                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1000 }
1001
1002 /* Handle a packet received event
1003  *
1004  * Falcon silicon gives a "discard" flag if it's a unicast packet with the
1005  * wrong destination address
1006  * Also "is multicast" and "matches multicast filter" flags can be used to
1007  * discard non-matching multicast packets.
1008  */
1009 static inline int falcon_handle_rx_event(struct efx_channel *channel,
1010                                          const efx_qword_t *event)
1011 {
1012         unsigned int rx_ev_q_label, rx_ev_desc_ptr, rx_ev_byte_cnt;
1013         unsigned int rx_ev_pkt_ok, rx_ev_hdr_type, rx_ev_mcast_pkt;
1014         unsigned expected_ptr;
1015         int discard = 0, checksummed;
1016         struct efx_rx_queue *rx_queue;
1017         struct efx_nic *efx = channel->efx;
1018
1019         /* Basic packet information */
1020         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
1021         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
1022         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
1023         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
1024         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
1025
1026         rx_ev_q_label = EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL);
1027         rx_queue = &efx->rx_queue[rx_ev_q_label];
1028
1029         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
1030         expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
1031         if (unlikely(rx_ev_desc_ptr != expected_ptr)) {
1032                 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
1033                 return rx_ev_q_label;
1034         }
1035
1036         if (likely(rx_ev_pkt_ok)) {
1037                 /* If packet is marked as OK and packet type is TCP/IPv4 or
1038                  * UDP/IPv4, then we can rely on the hardware checksum.
1039                  */
1040                 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
1041         } else {
1042                 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
1043                                         &discard, rx_ev_byte_cnt);
1044                 checksummed = 0;
1045         }
1046
1047         /* Detect multicast packets that didn't match the filter */
1048         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
1049         if (rx_ev_mcast_pkt) {
1050                 unsigned int rx_ev_mcast_hash_match =
1051                         EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
1052
1053                 if (unlikely(!rx_ev_mcast_hash_match))
1054                         discard = 1;
1055         }
1056
1057         /* Handle received packet */
1058         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
1059                       checksummed, discard);
1060
1061         return rx_ev_q_label;
1062 }
1063
1064 /* Global events are basically PHY events */
1065 static void falcon_handle_global_event(struct efx_channel *channel,
1066                                        efx_qword_t *event)
1067 {
1068         struct efx_nic *efx = channel->efx;
1069         int is_phy_event = 0, handled = 0;
1070
1071         /* Check for interrupt on either port.  Some boards have a
1072          * single PHY wired to the interrupt line for port 1. */
1073         if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
1074             EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
1075             EFX_QWORD_FIELD(*event, XG_PHY_INTR))
1076                 is_phy_event = 1;
1077
1078         if ((falcon_rev(efx) >= FALCON_REV_B0) &&
1079             EFX_OWORD_FIELD(*event, XG_MNT_INTR_B0))
1080                 is_phy_event = 1;
1081
1082         if (is_phy_event) {
1083                 efx->phy_op->clear_interrupt(efx);
1084                 queue_work(efx->workqueue, &efx->reconfigure_work);
1085                 handled = 1;
1086         }
1087
1088         if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
1089                 EFX_ERR(efx, "channel %d seen global RX_RESET "
1090                         "event. Resetting.\n", channel->channel);
1091
1092                 atomic_inc(&efx->rx_reset);
1093                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1094                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1095                 handled = 1;
1096         }
1097
1098         if (!handled)
1099                 EFX_ERR(efx, "channel %d unknown global event "
1100                         EFX_QWORD_FMT "\n", channel->channel,
1101                         EFX_QWORD_VAL(*event));
1102 }
1103
1104 static void falcon_handle_driver_event(struct efx_channel *channel,
1105                                        efx_qword_t *event)
1106 {
1107         struct efx_nic *efx = channel->efx;
1108         unsigned int ev_sub_code;
1109         unsigned int ev_sub_data;
1110
1111         ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1112         ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
1113
1114         switch (ev_sub_code) {
1115         case TX_DESCQ_FLS_DONE_EV_DECODE:
1116                 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
1117                           channel->channel, ev_sub_data);
1118                 break;
1119         case RX_DESCQ_FLS_DONE_EV_DECODE:
1120                 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
1121                           channel->channel, ev_sub_data);
1122                 break;
1123         case EVQ_INIT_DONE_EV_DECODE:
1124                 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
1125                         channel->channel, ev_sub_data);
1126                 break;
1127         case SRM_UPD_DONE_EV_DECODE:
1128                 EFX_TRACE(efx, "channel %d SRAM update done\n",
1129                           channel->channel);
1130                 break;
1131         case WAKE_UP_EV_DECODE:
1132                 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
1133                           channel->channel, ev_sub_data);
1134                 break;
1135         case TIMER_EV_DECODE:
1136                 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
1137                           channel->channel, ev_sub_data);
1138                 break;
1139         case RX_RECOVERY_EV_DECODE:
1140                 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
1141                         "Resetting.\n", channel->channel);
1142                 atomic_inc(&efx->rx_reset);
1143                 efx_schedule_reset(efx,
1144                                    EFX_WORKAROUND_6555(efx) ?
1145                                    RESET_TYPE_RX_RECOVERY :
1146                                    RESET_TYPE_DISABLE);
1147                 break;
1148         case RX_DSC_ERROR_EV_DECODE:
1149                 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
1150                         " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1151                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1152                 break;
1153         case TX_DSC_ERROR_EV_DECODE:
1154                 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1155                         " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1156                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1157                 break;
1158         default:
1159                 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1160                           "data %04x\n", channel->channel, ev_sub_code,
1161                           ev_sub_data);
1162                 break;
1163         }
1164 }
1165
1166 int falcon_process_eventq(struct efx_channel *channel, int *rx_quota)
1167 {
1168         unsigned int read_ptr;
1169         efx_qword_t event, *p_event;
1170         int ev_code;
1171         int rxq;
1172         int rxdmaqs = 0;
1173
1174         read_ptr = channel->eventq_read_ptr;
1175
1176         do {
1177                 p_event = falcon_event(channel, read_ptr);
1178                 event = *p_event;
1179
1180                 if (!falcon_event_present(&event))
1181                         /* End of events */
1182                         break;
1183
1184                 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1185                           channel->channel, EFX_QWORD_VAL(event));
1186
1187                 /* Clear this event by marking it all ones */
1188                 EFX_SET_QWORD(*p_event);
1189
1190                 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1191
1192                 switch (ev_code) {
1193                 case RX_IP_EV_DECODE:
1194                         rxq = falcon_handle_rx_event(channel, &event);
1195                         rxdmaqs |= (1 << rxq);
1196                         (*rx_quota)--;
1197                         break;
1198                 case TX_IP_EV_DECODE:
1199                         falcon_handle_tx_event(channel, &event);
1200                         break;
1201                 case DRV_GEN_EV_DECODE:
1202                         channel->eventq_magic
1203                                 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1204                         EFX_LOG(channel->efx, "channel %d received generated "
1205                                 "event "EFX_QWORD_FMT"\n", channel->channel,
1206                                 EFX_QWORD_VAL(event));
1207                         break;
1208                 case GLOBAL_EV_DECODE:
1209                         falcon_handle_global_event(channel, &event);
1210                         break;
1211                 case DRIVER_EV_DECODE:
1212                         falcon_handle_driver_event(channel, &event);
1213                         break;
1214                 default:
1215                         EFX_ERR(channel->efx, "channel %d unknown event type %d"
1216                                 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1217                                 ev_code, EFX_QWORD_VAL(event));
1218                 }
1219
1220                 /* Increment read pointer */
1221                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1222
1223         } while (*rx_quota);
1224
1225         channel->eventq_read_ptr = read_ptr;
1226         return rxdmaqs;
1227 }
1228
1229 void falcon_set_int_moderation(struct efx_channel *channel)
1230 {
1231         efx_dword_t timer_cmd;
1232         struct efx_nic *efx = channel->efx;
1233
1234         /* Set timer register */
1235         if (channel->irq_moderation) {
1236                 /* Round to resolution supported by hardware.  The value we
1237                  * program is based at 0.  So actual interrupt moderation
1238                  * achieved is ((x + 1) * res).
1239                  */
1240                 unsigned int res = 5;
1241                 channel->irq_moderation -= (channel->irq_moderation % res);
1242                 if (channel->irq_moderation < res)
1243                         channel->irq_moderation = res;
1244                 EFX_POPULATE_DWORD_2(timer_cmd,
1245                                      TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1246                                      TIMER_VAL,
1247                                      (channel->irq_moderation / res) - 1);
1248         } else {
1249                 EFX_POPULATE_DWORD_2(timer_cmd,
1250                                      TIMER_MODE, TIMER_MODE_DIS,
1251                                      TIMER_VAL, 0);
1252         }
1253         falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1254                                   channel->evqnum);
1255
1256 }
1257
1258 /* Allocate buffer table entries for event queue */
1259 int falcon_probe_eventq(struct efx_channel *channel)
1260 {
1261         struct efx_nic *efx = channel->efx;
1262         unsigned int evq_size;
1263
1264         evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1265         return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1266 }
1267
1268 int falcon_init_eventq(struct efx_channel *channel)
1269 {
1270         efx_oword_t evq_ptr;
1271         struct efx_nic *efx = channel->efx;
1272         int rc;
1273
1274         EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1275                 channel->channel, channel->eventq.index,
1276                 channel->eventq.index + channel->eventq.entries - 1);
1277
1278         /* Pin event queue buffer */
1279         rc = falcon_init_special_buffer(efx, &channel->eventq);
1280         if (rc)
1281                 return rc;
1282
1283         /* Fill event queue with all ones (i.e. empty events) */
1284         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1285
1286         /* Push event queue to card */
1287         EFX_POPULATE_OWORD_3(evq_ptr,
1288                              EVQ_EN, 1,
1289                              EVQ_SIZE, FALCON_EVQ_ORDER,
1290                              EVQ_BUF_BASE_ID, channel->eventq.index);
1291         falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1292                            channel->evqnum);
1293
1294         falcon_set_int_moderation(channel);
1295
1296         return 0;
1297 }
1298
1299 void falcon_fini_eventq(struct efx_channel *channel)
1300 {
1301         efx_oword_t eventq_ptr;
1302         struct efx_nic *efx = channel->efx;
1303
1304         /* Remove event queue from card */
1305         EFX_ZERO_OWORD(eventq_ptr);
1306         falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1307                            channel->evqnum);
1308
1309         /* Unpin event queue */
1310         falcon_fini_special_buffer(efx, &channel->eventq);
1311 }
1312
1313 /* Free buffers backing event queue */
1314 void falcon_remove_eventq(struct efx_channel *channel)
1315 {
1316         falcon_free_special_buffer(channel->efx, &channel->eventq);
1317 }
1318
1319
1320 /* Generates a test event on the event queue.  A subsequent call to
1321  * process_eventq() should pick up the event and place the value of
1322  * "magic" into channel->eventq_magic;
1323  */
1324 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1325 {
1326         efx_qword_t test_event;
1327
1328         EFX_POPULATE_QWORD_2(test_event,
1329                              EV_CODE, DRV_GEN_EV_DECODE,
1330                              EVQ_MAGIC, magic);
1331         falcon_generate_event(channel, &test_event);
1332 }
1333
1334
1335 /**************************************************************************
1336  *
1337  * Falcon hardware interrupts
1338  * The hardware interrupt handler does very little work; all the event
1339  * queue processing is carried out by per-channel tasklets.
1340  *
1341  **************************************************************************/
1342
1343 /* Enable/disable/generate Falcon interrupts */
1344 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1345                                      int force)
1346 {
1347         efx_oword_t int_en_reg_ker;
1348
1349         EFX_POPULATE_OWORD_2(int_en_reg_ker,
1350                              KER_INT_KER, force,
1351                              DRV_INT_EN_KER, enabled);
1352         falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1353 }
1354
1355 void falcon_enable_interrupts(struct efx_nic *efx)
1356 {
1357         efx_oword_t int_adr_reg_ker;
1358         struct efx_channel *channel;
1359
1360         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1361         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1362
1363         /* Program address */
1364         EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1365                              NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1366                              INT_ADR_KER, efx->irq_status.dma_addr);
1367         falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1368
1369         /* Enable interrupts */
1370         falcon_interrupts(efx, 1, 0);
1371
1372         /* Force processing of all the channels to get the EVQ RPTRs up to
1373            date */
1374         efx_for_each_channel_with_interrupt(channel, efx)
1375                 efx_schedule_channel(channel);
1376 }
1377
1378 void falcon_disable_interrupts(struct efx_nic *efx)
1379 {
1380         /* Disable interrupts */
1381         falcon_interrupts(efx, 0, 0);
1382 }
1383
1384 /* Generate a Falcon test interrupt
1385  * Interrupt must already have been enabled, otherwise nasty things
1386  * may happen.
1387  */
1388 void falcon_generate_interrupt(struct efx_nic *efx)
1389 {
1390         falcon_interrupts(efx, 1, 1);
1391 }
1392
1393 /* Acknowledge a legacy interrupt from Falcon
1394  *
1395  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1396  *
1397  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1398  * BIU. Interrupt acknowledge is read sensitive so must write instead
1399  * (then read to ensure the BIU collector is flushed)
1400  *
1401  * NB most hardware supports MSI interrupts
1402  */
1403 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1404 {
1405         efx_dword_t reg;
1406
1407         EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1408         falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1409         falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1410 }
1411
1412 /* Process a fatal interrupt
1413  * Disable bus mastering ASAP and schedule a reset
1414  */
1415 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1416 {
1417         struct falcon_nic_data *nic_data = efx->nic_data;
1418         efx_oword_t *int_ker = efx->irq_status.addr;
1419         efx_oword_t fatal_intr;
1420         int error, mem_perr;
1421         static int n_int_errors;
1422
1423         falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1424         error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1425
1426         EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1427                 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1428                 EFX_OWORD_VAL(fatal_intr),
1429                 error ? "disabling bus mastering" : "no recognised error");
1430         if (error == 0)
1431                 goto out;
1432
1433         /* If this is a memory parity error dump which blocks are offending */
1434         mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1435         if (mem_perr) {
1436                 efx_oword_t reg;
1437                 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1438                 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1439                         EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1440         }
1441
1442         /* Disable DMA bus mastering on both devices */
1443         pci_disable_device(efx->pci_dev);
1444         if (FALCON_IS_DUAL_FUNC(efx))
1445                 pci_disable_device(nic_data->pci_dev2);
1446
1447         if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1448                 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1449                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1450         } else {
1451                 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1452                         "NIC will be disabled\n");
1453                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1454         }
1455 out:
1456         return IRQ_HANDLED;
1457 }
1458
1459 /* Handle a legacy interrupt from Falcon
1460  * Acknowledges the interrupt and schedule event queue processing.
1461  */
1462 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1463 {
1464         struct efx_nic *efx = dev_id;
1465         efx_oword_t *int_ker = efx->irq_status.addr;
1466         struct efx_channel *channel;
1467         efx_dword_t reg;
1468         u32 queues;
1469         int syserr;
1470
1471         /* Read the ISR which also ACKs the interrupts */
1472         falcon_readl(efx, &reg, INT_ISR0_B0);
1473         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1474
1475         /* Check to see if we have a serious error condition */
1476         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1477         if (unlikely(syserr))
1478                 return falcon_fatal_interrupt(efx);
1479
1480         if (queues == 0)
1481                 return IRQ_NONE;
1482
1483         efx->last_irq_cpu = raw_smp_processor_id();
1484         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1485                   irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1486
1487         /* Schedule processing of any interrupting queues */
1488         channel = &efx->channel[0];
1489         while (queues) {
1490                 if (queues & 0x01)
1491                         efx_schedule_channel(channel);
1492                 channel++;
1493                 queues >>= 1;
1494         }
1495
1496         return IRQ_HANDLED;
1497 }
1498
1499
1500 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1501 {
1502         struct efx_nic *efx = dev_id;
1503         efx_oword_t *int_ker = efx->irq_status.addr;
1504         struct efx_channel *channel;
1505         int syserr;
1506         int queues;
1507
1508         /* Check to see if this is our interrupt.  If it isn't, we
1509          * exit without having touched the hardware.
1510          */
1511         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1512                 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1513                           raw_smp_processor_id());
1514                 return IRQ_NONE;
1515         }
1516         efx->last_irq_cpu = raw_smp_processor_id();
1517         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1518                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1519
1520         /* Check to see if we have a serious error condition */
1521         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1522         if (unlikely(syserr))
1523                 return falcon_fatal_interrupt(efx);
1524
1525         /* Determine interrupting queues, clear interrupt status
1526          * register and acknowledge the device interrupt.
1527          */
1528         BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1529         queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1530         EFX_ZERO_OWORD(*int_ker);
1531         wmb(); /* Ensure the vector is cleared before interrupt ack */
1532         falcon_irq_ack_a1(efx);
1533
1534         /* Schedule processing of any interrupting queues */
1535         channel = &efx->channel[0];
1536         while (queues) {
1537                 if (queues & 0x01)
1538                         efx_schedule_channel(channel);
1539                 channel++;
1540                 queues >>= 1;
1541         }
1542
1543         return IRQ_HANDLED;
1544 }
1545
1546 /* Handle an MSI interrupt from Falcon
1547  *
1548  * Handle an MSI hardware interrupt.  This routine schedules event
1549  * queue processing.  No interrupt acknowledgement cycle is necessary.
1550  * Also, we never need to check that the interrupt is for us, since
1551  * MSI interrupts cannot be shared.
1552  */
1553 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1554 {
1555         struct efx_channel *channel = dev_id;
1556         struct efx_nic *efx = channel->efx;
1557         efx_oword_t *int_ker = efx->irq_status.addr;
1558         int syserr;
1559
1560         efx->last_irq_cpu = raw_smp_processor_id();
1561         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1562                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1563
1564         /* Check to see if we have a serious error condition */
1565         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1566         if (unlikely(syserr))
1567                 return falcon_fatal_interrupt(efx);
1568
1569         /* Schedule processing of the channel */
1570         efx_schedule_channel(channel);
1571
1572         return IRQ_HANDLED;
1573 }
1574
1575
1576 /* Setup RSS indirection table.
1577  * This maps from the hash value of the packet to RXQ
1578  */
1579 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1580 {
1581         int i = 0;
1582         unsigned long offset;
1583         efx_dword_t dword;
1584
1585         if (falcon_rev(efx) < FALCON_REV_B0)
1586                 return;
1587
1588         for (offset = RX_RSS_INDIR_TBL_B0;
1589              offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1590              offset += 0x10) {
1591                 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1592                                      i % efx->rss_queues);
1593                 falcon_writel(efx, &dword, offset);
1594                 i++;
1595         }
1596 }
1597
1598 /* Hook interrupt handler(s)
1599  * Try MSI and then legacy interrupts.
1600  */
1601 int falcon_init_interrupt(struct efx_nic *efx)
1602 {
1603         struct efx_channel *channel;
1604         int rc;
1605
1606         if (!EFX_INT_MODE_USE_MSI(efx)) {
1607                 irq_handler_t handler;
1608                 if (falcon_rev(efx) >= FALCON_REV_B0)
1609                         handler = falcon_legacy_interrupt_b0;
1610                 else
1611                         handler = falcon_legacy_interrupt_a1;
1612
1613                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1614                                  efx->name, efx);
1615                 if (rc) {
1616                         EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1617                                 efx->pci_dev->irq);
1618                         goto fail1;
1619                 }
1620                 return 0;
1621         }
1622
1623         /* Hook MSI or MSI-X interrupt */
1624         efx_for_each_channel_with_interrupt(channel, efx) {
1625                 rc = request_irq(channel->irq, falcon_msi_interrupt,
1626                                  IRQF_PROBE_SHARED, /* Not shared */
1627                                  efx->name, channel);
1628                 if (rc) {
1629                         EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1630                         goto fail2;
1631                 }
1632         }
1633
1634         return 0;
1635
1636  fail2:
1637         efx_for_each_channel_with_interrupt(channel, efx)
1638                 free_irq(channel->irq, channel);
1639  fail1:
1640         return rc;
1641 }
1642
1643 void falcon_fini_interrupt(struct efx_nic *efx)
1644 {
1645         struct efx_channel *channel;
1646         efx_oword_t reg;
1647
1648         /* Disable MSI/MSI-X interrupts */
1649         efx_for_each_channel_with_interrupt(channel, efx) {
1650                 if (channel->irq)
1651                         free_irq(channel->irq, channel);
1652         }
1653
1654         /* ACK legacy interrupt */
1655         if (falcon_rev(efx) >= FALCON_REV_B0)
1656                 falcon_read(efx, &reg, INT_ISR0_B0);
1657         else
1658                 falcon_irq_ack_a1(efx);
1659
1660         /* Disable legacy interrupt */
1661         if (efx->legacy_irq)
1662                 free_irq(efx->legacy_irq, efx);
1663 }
1664
1665 /**************************************************************************
1666  *
1667  * EEPROM/flash
1668  *
1669  **************************************************************************
1670  */
1671
1672 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1673
1674 /* Wait for SPI command completion */
1675 static int falcon_spi_wait(struct efx_nic *efx)
1676 {
1677         efx_oword_t reg;
1678         int cmd_en, timer_active;
1679         int count;
1680
1681         count = 0;
1682         do {
1683                 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1684                 cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
1685                 timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
1686                 if (!cmd_en && !timer_active)
1687                         return 0;
1688                 udelay(10);
1689         } while (++count < 10000); /* wait upto 100msec */
1690         EFX_ERR(efx, "timed out waiting for SPI\n");
1691         return -ETIMEDOUT;
1692 }
1693
1694 static int
1695 falcon_spi_read(struct efx_nic *efx, int device_id, unsigned int command,
1696                 unsigned int address, unsigned int addr_len,
1697                 void *data, unsigned int len)
1698 {
1699         efx_oword_t reg;
1700         int rc;
1701
1702         BUG_ON(len > FALCON_SPI_MAX_LEN);
1703
1704         /* Check SPI not currently being accessed */
1705         rc = falcon_spi_wait(efx);
1706         if (rc)
1707                 return rc;
1708
1709         /* Program address register */
1710         EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1711         falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1712
1713         /* Issue read command */
1714         EFX_POPULATE_OWORD_7(reg,
1715                              EE_SPI_HCMD_CMD_EN, 1,
1716                              EE_SPI_HCMD_SF_SEL, device_id,
1717                              EE_SPI_HCMD_DABCNT, len,
1718                              EE_SPI_HCMD_READ, EE_SPI_READ,
1719                              EE_SPI_HCMD_DUBCNT, 0,
1720                              EE_SPI_HCMD_ADBCNT, addr_len,
1721                              EE_SPI_HCMD_ENC, command);
1722         falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1723
1724         /* Wait for read to complete */
1725         rc = falcon_spi_wait(efx);
1726         if (rc)
1727                 return rc;
1728
1729         /* Read data */
1730         falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1731         memcpy(data, &reg, len);
1732         return 0;
1733 }
1734
1735 /**************************************************************************
1736  *
1737  * MAC wrapper
1738  *
1739  **************************************************************************
1740  */
1741 void falcon_drain_tx_fifo(struct efx_nic *efx)
1742 {
1743         efx_oword_t temp;
1744         int count;
1745
1746         if ((falcon_rev(efx) < FALCON_REV_B0) ||
1747             (efx->loopback_mode != LOOPBACK_NONE))
1748                 return;
1749
1750         falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1751         /* There is no point in draining more than once */
1752         if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1753                 return;
1754
1755         /* MAC stats will fail whilst the TX fifo is draining. Serialise
1756          * the drain sequence with the statistics fetch */
1757         spin_lock(&efx->stats_lock);
1758
1759         EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
1760         falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
1761
1762         /* Reset the MAC and EM block. */
1763         falcon_read(efx, &temp, GLB_CTL_REG_KER);
1764         EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
1765         EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
1766         EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
1767         falcon_write(efx, &temp, GLB_CTL_REG_KER);
1768
1769         count = 0;
1770         while (1) {
1771                 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1772                 if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
1773                     !EFX_OWORD_FIELD(temp, RST_XGRX) &&
1774                     !EFX_OWORD_FIELD(temp, RST_EM)) {
1775                         EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1776                                 count);
1777                         break;
1778                 }
1779                 if (count > 20) {
1780                         EFX_ERR(efx, "MAC reset failed\n");
1781                         break;
1782                 }
1783                 count++;
1784                 udelay(10);
1785         }
1786
1787         spin_unlock(&efx->stats_lock);
1788
1789         /* If we've reset the EM block and the link is up, then
1790          * we'll have to kick the XAUI link so the PHY can recover */
1791         if (efx->link_up && EFX_WORKAROUND_5147(efx))
1792                 falcon_reset_xaui(efx);
1793 }
1794
1795 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1796 {
1797         efx_oword_t temp;
1798
1799         if (falcon_rev(efx) < FALCON_REV_B0)
1800                 return;
1801
1802         /* Isolate the MAC -> RX */
1803         falcon_read(efx, &temp, RX_CFG_REG_KER);
1804         EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
1805         falcon_write(efx, &temp, RX_CFG_REG_KER);
1806
1807         if (!efx->link_up)
1808                 falcon_drain_tx_fifo(efx);
1809 }
1810
1811 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1812 {
1813         efx_oword_t reg;
1814         int link_speed;
1815         unsigned int tx_fc;
1816
1817         if (efx->link_options & GM_LPA_10000)
1818                 link_speed = 0x3;
1819         else if (efx->link_options & GM_LPA_1000)
1820                 link_speed = 0x2;
1821         else if (efx->link_options & GM_LPA_100)
1822                 link_speed = 0x1;
1823         else
1824                 link_speed = 0x0;
1825         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1826          * as advertised.  Disable to ensure packets are not
1827          * indefinitely held and TX queue can be flushed at any point
1828          * while the link is down. */
1829         EFX_POPULATE_OWORD_5(reg,
1830                              MAC_XOFF_VAL, 0xffff /* max pause time */,
1831                              MAC_BCAD_ACPT, 1,
1832                              MAC_UC_PROM, efx->promiscuous,
1833                              MAC_LINK_STATUS, 1, /* always set */
1834                              MAC_SPEED, link_speed);
1835         /* On B0, MAC backpressure can be disabled and packets get
1836          * discarded. */
1837         if (falcon_rev(efx) >= FALCON_REV_B0) {
1838                 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1839                                     !efx->link_up);
1840         }
1841
1842         falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1843
1844         /* Restore the multicast hash registers. */
1845         falcon_set_multicast_hash(efx);
1846
1847         /* Transmission of pause frames when RX crosses the threshold is
1848          * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1849          * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1850         tx_fc = (efx->flow_control & EFX_FC_TX) ? 1 : 0;
1851         falcon_read(efx, &reg, RX_CFG_REG_KER);
1852         EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1853
1854         /* Unisolate the MAC -> RX */
1855         if (falcon_rev(efx) >= FALCON_REV_B0)
1856                 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
1857         falcon_write(efx, &reg, RX_CFG_REG_KER);
1858 }
1859
1860 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1861 {
1862         efx_oword_t reg;
1863         u32 *dma_done;
1864         int i;
1865
1866         if (disable_dma_stats)
1867                 return 0;
1868
1869         /* Statistics fetch will fail if the MAC is in TX drain */
1870         if (falcon_rev(efx) >= FALCON_REV_B0) {
1871                 efx_oword_t temp;
1872                 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1873                 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1874                         return 0;
1875         }
1876
1877         dma_done = (efx->stats_buffer.addr + done_offset);
1878         *dma_done = FALCON_STATS_NOT_DONE;
1879         wmb(); /* ensure done flag is clear */
1880
1881         /* Initiate DMA transfer of stats */
1882         EFX_POPULATE_OWORD_2(reg,
1883                              MAC_STAT_DMA_CMD, 1,
1884                              MAC_STAT_DMA_ADR,
1885                              efx->stats_buffer.dma_addr);
1886         falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
1887
1888         /* Wait for transfer to complete */
1889         for (i = 0; i < 400; i++) {
1890                 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE)
1891                         return 0;
1892                 udelay(10);
1893         }
1894
1895         EFX_ERR(efx, "timed out waiting for statistics\n");
1896         return -ETIMEDOUT;
1897 }
1898
1899 /**************************************************************************
1900  *
1901  * PHY access via GMII
1902  *
1903  **************************************************************************
1904  */
1905
1906 /* Use the top bit of the MII PHY id to indicate the PHY type
1907  * (1G/10G), with the remaining bits as the actual PHY id.
1908  *
1909  * This allows us to avoid leaking information from the mii_if_info
1910  * structure into other data structures.
1911  */
1912 #define FALCON_PHY_ID_ID_WIDTH  EFX_WIDTH(MD_PRT_DEV_ADR)
1913 #define FALCON_PHY_ID_ID_MASK   ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1914 #define FALCON_PHY_ID_WIDTH     (FALCON_PHY_ID_ID_WIDTH + 1)
1915 #define FALCON_PHY_ID_MASK      ((1 << FALCON_PHY_ID_WIDTH) - 1)
1916 #define FALCON_PHY_ID_10G       (1 << (FALCON_PHY_ID_WIDTH - 1))
1917
1918
1919 /* Packing the clause 45 port and device fields into a single value */
1920 #define MD_PRT_ADR_COMP_LBN   (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1921 #define MD_PRT_ADR_COMP_WIDTH  MD_PRT_ADR_WIDTH
1922 #define MD_DEV_ADR_COMP_LBN    0
1923 #define MD_DEV_ADR_COMP_WIDTH  MD_DEV_ADR_WIDTH
1924
1925
1926 /* Wait for GMII access to complete */
1927 static int falcon_gmii_wait(struct efx_nic *efx)
1928 {
1929         efx_dword_t md_stat;
1930         int count;
1931
1932         for (count = 0; count < 1000; count++) {        /* wait upto 10ms */
1933                 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
1934                 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
1935                         if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
1936                             EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
1937                                 EFX_ERR(efx, "error from GMII access "
1938                                         EFX_DWORD_FMT"\n",
1939                                         EFX_DWORD_VAL(md_stat));
1940                                 return -EIO;
1941                         }
1942                         return 0;
1943                 }
1944                 udelay(10);
1945         }
1946         EFX_ERR(efx, "timed out waiting for GMII\n");
1947         return -ETIMEDOUT;
1948 }
1949
1950 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
1951 static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
1952                               int addr, int value)
1953 {
1954         struct efx_nic *efx = net_dev->priv;
1955         unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
1956         efx_oword_t reg;
1957
1958         /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
1959          * chosen so that the only current user, Falcon, can take the
1960          * packed value and use them directly.
1961          * Fail to build if this assumption is broken.
1962          */
1963         BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
1964         BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
1965         BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
1966         BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
1967
1968         if (phy_id2 == PHY_ADDR_INVALID)
1969                 return;
1970
1971         /* See falcon_mdio_read for an explanation. */
1972         if (!(phy_id & FALCON_PHY_ID_10G)) {
1973                 int mmd = ffs(efx->phy_op->mmds) - 1;
1974                 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
1975                 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
1976                         & FALCON_PHY_ID_ID_MASK;
1977         }
1978
1979         EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
1980                     addr, value);
1981
1982         spin_lock_bh(&efx->phy_lock);
1983
1984         /* Check MII not currently being accessed */
1985         if (falcon_gmii_wait(efx) != 0)
1986                 goto out;
1987
1988         /* Write the address/ID register */
1989         EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
1990         falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
1991
1992         EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
1993         falcon_write(efx, &reg, MD_ID_REG_KER);
1994
1995         /* Write data */
1996         EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
1997         falcon_write(efx, &reg, MD_TXD_REG_KER);
1998
1999         EFX_POPULATE_OWORD_2(reg,
2000                              MD_WRC, 1,
2001                              MD_GC, 0);
2002         falcon_write(efx, &reg, MD_CS_REG_KER);
2003
2004         /* Wait for data to be written */
2005         if (falcon_gmii_wait(efx) != 0) {
2006                 /* Abort the write operation */
2007                 EFX_POPULATE_OWORD_2(reg,
2008                                      MD_WRC, 0,
2009                                      MD_GC, 1);
2010                 falcon_write(efx, &reg, MD_CS_REG_KER);
2011                 udelay(10);
2012         }
2013
2014  out:
2015         spin_unlock_bh(&efx->phy_lock);
2016 }
2017
2018 /* Reads a GMII register from a PHY connected to Falcon.  If no value
2019  * could be read, -1 will be returned. */
2020 static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2021 {
2022         struct efx_nic *efx = net_dev->priv;
2023         unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2024         efx_oword_t reg;
2025         int value = -1;
2026
2027         if (phy_addr == PHY_ADDR_INVALID)
2028                 return -1;
2029
2030         /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2031          * but the generic Linux code does not make any distinction or have
2032          * any state for this.
2033          * We spot the case where someone tried to talk 22 to a 45 PHY and
2034          * redirect the request to the lowest numbered MMD as a clause45
2035          * request. This is enough to allow simple queries like id and link
2036          * state to succeed. TODO: We may need to do more in future.
2037          */
2038         if (!(phy_id & FALCON_PHY_ID_10G)) {
2039                 int mmd = ffs(efx->phy_op->mmds) - 1;
2040                 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2041                 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2042                         & FALCON_PHY_ID_ID_MASK;
2043         }
2044
2045         spin_lock_bh(&efx->phy_lock);
2046
2047         /* Check MII not currently being accessed */
2048         if (falcon_gmii_wait(efx) != 0)
2049                 goto out;
2050
2051         EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2052         falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2053
2054         EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2055         falcon_write(efx, &reg, MD_ID_REG_KER);
2056
2057         /* Request data to be read */
2058         EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2059         falcon_write(efx, &reg, MD_CS_REG_KER);
2060
2061         /* Wait for data to become available */
2062         value = falcon_gmii_wait(efx);
2063         if (value == 0) {
2064                 falcon_read(efx, &reg, MD_RXD_REG_KER);
2065                 value = EFX_OWORD_FIELD(reg, MD_RXD);
2066                 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2067                             phy_id, addr, value);
2068         } else {
2069                 /* Abort the read operation */
2070                 EFX_POPULATE_OWORD_2(reg,
2071                                      MD_RIC, 0,
2072                                      MD_GC, 1);
2073                 falcon_write(efx, &reg, MD_CS_REG_KER);
2074
2075                 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2076                         "error %d\n", phy_id, addr, value);
2077         }
2078
2079  out:
2080         spin_unlock_bh(&efx->phy_lock);
2081
2082         return value;
2083 }
2084
2085 static void falcon_init_mdio(struct mii_if_info *gmii)
2086 {
2087         gmii->mdio_read = falcon_mdio_read;
2088         gmii->mdio_write = falcon_mdio_write;
2089         gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2090         gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2091 }
2092
2093 static int falcon_probe_phy(struct efx_nic *efx)
2094 {
2095         switch (efx->phy_type) {
2096         case PHY_TYPE_10XPRESS:
2097                 efx->phy_op = &falcon_tenxpress_phy_ops;
2098                 break;
2099         case PHY_TYPE_XFP:
2100                 efx->phy_op = &falcon_xfp_phy_ops;
2101                 break;
2102         default:
2103                 EFX_ERR(efx, "Unknown PHY type %d\n",
2104                         efx->phy_type);
2105                 return -1;
2106         }
2107
2108         efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
2109         return 0;
2110 }
2111
2112 /* This call is responsible for hooking in the MAC and PHY operations */
2113 int falcon_probe_port(struct efx_nic *efx)
2114 {
2115         int rc;
2116
2117         /* Hook in PHY operations table */
2118         rc = falcon_probe_phy(efx);
2119         if (rc)
2120                 return rc;
2121
2122         /* Set up GMII structure for PHY */
2123         efx->mii.supports_gmii = 1;
2124         falcon_init_mdio(&efx->mii);
2125
2126         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2127         if (falcon_rev(efx) >= FALCON_REV_B0)
2128                 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2129         else
2130                 efx->flow_control = EFX_FC_RX;
2131
2132         /* Allocate buffer for stats */
2133         rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2134                                  FALCON_MAC_STATS_SIZE);
2135         if (rc)
2136                 return rc;
2137         EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2138                 (unsigned long long)efx->stats_buffer.dma_addr,
2139                 efx->stats_buffer.addr,
2140                 virt_to_phys(efx->stats_buffer.addr));
2141
2142         return 0;
2143 }
2144
2145 void falcon_remove_port(struct efx_nic *efx)
2146 {
2147         falcon_free_buffer(efx, &efx->stats_buffer);
2148 }
2149
2150 /**************************************************************************
2151  *
2152  * Multicast filtering
2153  *
2154  **************************************************************************
2155  */
2156
2157 void falcon_set_multicast_hash(struct efx_nic *efx)
2158 {
2159         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2160
2161         /* Broadcast packets go through the multicast hash filter.
2162          * ether_crc_le() of the broadcast address is 0xbe2612ff
2163          * so we always add bit 0xff to the mask.
2164          */
2165         set_bit_le(0xff, mc_hash->byte);
2166
2167         falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2168         falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2169 }
2170
2171 /**************************************************************************
2172  *
2173  * Device reset
2174  *
2175  **************************************************************************
2176  */
2177
2178 /* Resets NIC to known state.  This routine must be called in process
2179  * context and is allowed to sleep. */
2180 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2181 {
2182         struct falcon_nic_data *nic_data = efx->nic_data;
2183         efx_oword_t glb_ctl_reg_ker;
2184         int rc;
2185
2186         EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2187
2188         /* Initiate device reset */
2189         if (method == RESET_TYPE_WORLD) {
2190                 rc = pci_save_state(efx->pci_dev);
2191                 if (rc) {
2192                         EFX_ERR(efx, "failed to backup PCI state of primary "
2193                                 "function prior to hardware reset\n");
2194                         goto fail1;
2195                 }
2196                 if (FALCON_IS_DUAL_FUNC(efx)) {
2197                         rc = pci_save_state(nic_data->pci_dev2);
2198                         if (rc) {
2199                                 EFX_ERR(efx, "failed to backup PCI state of "
2200                                         "secondary function prior to "
2201                                         "hardware reset\n");
2202                                 goto fail2;
2203                         }
2204                 }
2205
2206                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2207                                      EXT_PHY_RST_DUR, 0x7,
2208                                      SWRST, 1);
2209         } else {
2210                 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2211                                  EXCLUDE_FROM_RESET : 0);
2212
2213                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2214                                      EXT_PHY_RST_CTL, reset_phy,
2215                                      PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2216                                      PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2217                                      PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2218                                      EE_RST_CTL, EXCLUDE_FROM_RESET,
2219                                      EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2220                                      SWRST, 1);
2221         }
2222         falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2223
2224         EFX_LOG(efx, "waiting for hardware reset\n");
2225         schedule_timeout_uninterruptible(HZ / 20);
2226
2227         /* Restore PCI configuration if needed */
2228         if (method == RESET_TYPE_WORLD) {
2229                 if (FALCON_IS_DUAL_FUNC(efx)) {
2230                         rc = pci_restore_state(nic_data->pci_dev2);
2231                         if (rc) {
2232                                 EFX_ERR(efx, "failed to restore PCI config for "
2233                                         "the secondary function\n");
2234                                 goto fail3;
2235                         }
2236                 }
2237                 rc = pci_restore_state(efx->pci_dev);
2238                 if (rc) {
2239                         EFX_ERR(efx, "failed to restore PCI config for the "
2240                                 "primary function\n");
2241                         goto fail4;
2242                 }
2243                 EFX_LOG(efx, "successfully restored PCI config\n");
2244         }
2245
2246         /* Assert that reset complete */
2247         falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2248         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2249                 rc = -ETIMEDOUT;
2250                 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2251                 goto fail5;
2252         }
2253         EFX_LOG(efx, "hardware reset complete\n");
2254
2255         return 0;
2256
2257         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2258 fail2:
2259 fail3:
2260         pci_restore_state(efx->pci_dev);
2261 fail1:
2262 fail4:
2263 fail5:
2264         return rc;
2265 }
2266
2267 /* Zeroes out the SRAM contents.  This routine must be called in
2268  * process context and is allowed to sleep.
2269  */
2270 static int falcon_reset_sram(struct efx_nic *efx)
2271 {
2272         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2273         int count;
2274
2275         /* Set the SRAM wake/sleep GPIO appropriately. */
2276         falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2277         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2278         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2279         falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2280
2281         /* Initiate SRAM reset */
2282         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2283                              SRAM_OOB_BT_INIT_EN, 1,
2284                              SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2285         falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2286
2287         /* Wait for SRAM reset to complete */
2288         count = 0;
2289         do {
2290                 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2291
2292                 /* SRAM reset is slow; expect around 16ms */
2293                 schedule_timeout_uninterruptible(HZ / 50);
2294
2295                 /* Check for reset complete */
2296                 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2297                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2298                         EFX_LOG(efx, "SRAM reset complete\n");
2299
2300                         return 0;
2301                 }
2302         } while (++count < 20); /* wait upto 0.4 sec */
2303
2304         EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2305         return -ETIMEDOUT;
2306 }
2307
2308 /* Extract non-volatile configuration */
2309 static int falcon_probe_nvconfig(struct efx_nic *efx)
2310 {
2311         struct falcon_nvconfig *nvconfig;
2312         efx_oword_t nic_stat;
2313         int device_id;
2314         unsigned addr_len;
2315         size_t offset, len;
2316         int magic_num, struct_ver, board_rev;
2317         int rc;
2318
2319         /* Find the boot device. */
2320         falcon_read(efx, &nic_stat, NIC_STAT_REG);
2321         if (EFX_OWORD_FIELD(nic_stat, SF_PRST)) {
2322                 device_id = EE_SPI_FLASH;
2323                 addr_len = 3;
2324         } else if (EFX_OWORD_FIELD(nic_stat, EE_PRST)) {
2325                 device_id = EE_SPI_EEPROM;
2326                 addr_len = 2;
2327         } else {
2328                 return -ENODEV;
2329         }
2330
2331         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2332
2333         /* Read the whole configuration structure into memory. */
2334         for (offset = 0; offset < sizeof(*nvconfig); offset += len) {
2335                 len = min(sizeof(*nvconfig) - offset,
2336                           (size_t) FALCON_SPI_MAX_LEN);
2337                 rc = falcon_spi_read(efx, device_id, SPI_READ,
2338                                      NVCONFIG_BASE + offset, addr_len,
2339                                      (char *)nvconfig + offset, len);
2340                 if (rc)
2341                         goto out;
2342         }
2343
2344         /* Read the MAC addresses */
2345         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2346
2347         /* Read the board configuration. */
2348         magic_num = le16_to_cpu(nvconfig->board_magic_num);
2349         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2350
2351         if (magic_num != NVCONFIG_BOARD_MAGIC_NUM || struct_ver < 2) {
2352                 EFX_ERR(efx, "Non volatile memory bad magic=%x ver=%x "
2353                         "therefore using defaults\n", magic_num, struct_ver);
2354                 efx->phy_type = PHY_TYPE_NONE;
2355                 efx->mii.phy_id = PHY_ADDR_INVALID;
2356                 board_rev = 0;
2357         } else {
2358                 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2359
2360                 efx->phy_type = v2->port0_phy_type;
2361                 efx->mii.phy_id = v2->port0_phy_addr;
2362                 board_rev = le16_to_cpu(v2->board_revision);
2363         }
2364
2365         EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2366
2367         efx_set_board_info(efx, board_rev);
2368
2369  out:
2370         kfree(nvconfig);
2371         return rc;
2372 }
2373
2374 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2375  * count, port speed).  Set workaround and feature flags accordingly.
2376  */
2377 static int falcon_probe_nic_variant(struct efx_nic *efx)
2378 {
2379         efx_oword_t altera_build;
2380
2381         falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2382         if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2383                 EFX_ERR(efx, "Falcon FPGA not supported\n");
2384                 return -ENODEV;
2385         }
2386
2387         switch (falcon_rev(efx)) {
2388         case FALCON_REV_A0:
2389         case 0xff:
2390                 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2391                 return -ENODEV;
2392
2393         case FALCON_REV_A1:{
2394                 efx_oword_t nic_stat;
2395
2396                 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2397
2398                 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2399                         EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2400                         return -ENODEV;
2401                 }
2402                 if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
2403                         EFX_ERR(efx, "1G mode not supported\n");
2404                         return -ENODEV;
2405                 }
2406                 break;
2407         }
2408
2409         case FALCON_REV_B0:
2410                 break;
2411
2412         default:
2413                 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2414                 return -ENODEV;
2415         }
2416
2417         return 0;
2418 }
2419
2420 int falcon_probe_nic(struct efx_nic *efx)
2421 {
2422         struct falcon_nic_data *nic_data;
2423         int rc;
2424
2425         /* Allocate storage for hardware specific data */
2426         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2427         efx->nic_data = nic_data;
2428
2429         /* Determine number of ports etc. */
2430         rc = falcon_probe_nic_variant(efx);
2431         if (rc)
2432                 goto fail1;
2433
2434         /* Probe secondary function if expected */
2435         if (FALCON_IS_DUAL_FUNC(efx)) {
2436                 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2437
2438                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2439                                              dev))) {
2440                         if (dev->bus == efx->pci_dev->bus &&
2441                             dev->devfn == efx->pci_dev->devfn + 1) {
2442                                 nic_data->pci_dev2 = dev;
2443                                 break;
2444                         }
2445                 }
2446                 if (!nic_data->pci_dev2) {
2447                         EFX_ERR(efx, "failed to find secondary function\n");
2448                         rc = -ENODEV;
2449                         goto fail2;
2450                 }
2451         }
2452
2453         /* Now we can reset the NIC */
2454         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2455         if (rc) {
2456                 EFX_ERR(efx, "failed to reset NIC\n");
2457                 goto fail3;
2458         }
2459
2460         /* Allocate memory for INT_KER */
2461         rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2462         if (rc)
2463                 goto fail4;
2464         BUG_ON(efx->irq_status.dma_addr & 0x0f);
2465
2466         EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2467                 (unsigned long long)efx->irq_status.dma_addr,
2468                 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2469
2470         /* Read in the non-volatile configuration */
2471         rc = falcon_probe_nvconfig(efx);
2472         if (rc)
2473                 goto fail5;
2474
2475         /* Initialise I2C adapter */
2476         efx->i2c_adap.owner = THIS_MODULE;
2477         nic_data->i2c_data = falcon_i2c_bit_operations;
2478         nic_data->i2c_data.data = efx;
2479         efx->i2c_adap.algo_data = &nic_data->i2c_data;
2480         efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2481         strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2482         rc = i2c_bit_add_bus(&efx->i2c_adap);
2483         if (rc)
2484                 goto fail5;
2485
2486         return 0;
2487
2488  fail5:
2489         falcon_free_buffer(efx, &efx->irq_status);
2490  fail4:
2491  fail3:
2492         if (nic_data->pci_dev2) {
2493                 pci_dev_put(nic_data->pci_dev2);
2494                 nic_data->pci_dev2 = NULL;
2495         }
2496  fail2:
2497  fail1:
2498         kfree(efx->nic_data);
2499         return rc;
2500 }
2501
2502 /* This call performs hardware-specific global initialisation, such as
2503  * defining the descriptor cache sizes and number of RSS channels.
2504  * It does not set up any buffers, descriptor rings or event queues.
2505  */
2506 int falcon_init_nic(struct efx_nic *efx)
2507 {
2508         efx_oword_t temp;
2509         unsigned thresh;
2510         int rc;
2511
2512         /* Set up the address region register. This is only needed
2513          * for the B0 FPGA, but since we are just pushing in the
2514          * reset defaults this may as well be unconditional. */
2515         EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0,
2516                                    ADR_REGION1, (1 << 16),
2517                                    ADR_REGION2, (2 << 16),
2518                                    ADR_REGION3, (3 << 16));
2519         falcon_write(efx, &temp, ADR_REGION_REG_KER);
2520
2521         /* Use on-chip SRAM */
2522         falcon_read(efx, &temp, NIC_STAT_REG);
2523         EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2524         falcon_write(efx, &temp, NIC_STAT_REG);
2525
2526         /* Set buffer table mode */
2527         EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2528         falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2529
2530         rc = falcon_reset_sram(efx);
2531         if (rc)
2532                 return rc;
2533
2534         /* Set positions of descriptor caches in SRAM. */
2535         EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2536         falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2537         EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2538         falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2539
2540         /* Set TX descriptor cache size. */
2541         BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2542         EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2543         falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2544
2545         /* Set RX descriptor cache size.  Set low watermark to size-8, as
2546          * this allows most efficient prefetching.
2547          */
2548         BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2549         EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2550         falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2551         EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2552         falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2553
2554         /* Clear the parity enables on the TX data fifos as
2555          * they produce false parity errors because of timing issues
2556          */
2557         if (EFX_WORKAROUND_5129(efx)) {
2558                 falcon_read(efx, &temp, SPARE_REG_KER);
2559                 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2560                 falcon_write(efx, &temp, SPARE_REG_KER);
2561         }
2562
2563         /* Enable all the genuinely fatal interrupts.  (They are still
2564          * masked by the overall interrupt mask, controlled by
2565          * falcon_interrupts()).
2566          *
2567          * Note: All other fatal interrupts are enabled
2568          */
2569         EFX_POPULATE_OWORD_3(temp,
2570                              ILL_ADR_INT_KER_EN, 1,
2571                              RBUF_OWN_INT_KER_EN, 1,
2572                              TBUF_OWN_INT_KER_EN, 1);
2573         EFX_INVERT_OWORD(temp);
2574         falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2575
2576         /* Set number of RSS queues for receive path. */
2577         falcon_read(efx, &temp, RX_FILTER_CTL_REG);
2578         if (falcon_rev(efx) >= FALCON_REV_B0)
2579                 EFX_SET_OWORD_FIELD(temp, NUM_KER, 0);
2580         else
2581                 EFX_SET_OWORD_FIELD(temp, NUM_KER, efx->rss_queues - 1);
2582         if (EFX_WORKAROUND_7244(efx)) {
2583                 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2584                 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2585                 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2586                 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
2587         }
2588         falcon_write(efx, &temp, RX_FILTER_CTL_REG);
2589
2590         falcon_setup_rss_indir_table(efx);
2591
2592         /* Setup RX.  Wait for descriptor is broken and must
2593          * be disabled.  RXDP recovery shouldn't be needed, but is.
2594          */
2595         falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
2596         EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
2597         EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
2598         if (EFX_WORKAROUND_5583(efx))
2599                 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
2600         falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
2601
2602         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2603          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2604          */
2605         falcon_read(efx, &temp, TX_CFG2_REG_KER);
2606         EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
2607         EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
2608         EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
2609         EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
2610         EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
2611         /* Enable SW_EV to inherit in char driver - assume harmless here */
2612         EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
2613         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2614         EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
2615         /* Squash TX of packets of 16 bytes or less */
2616         if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
2617                 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
2618         falcon_write(efx, &temp, TX_CFG2_REG_KER);
2619
2620         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2621          * descriptors (which is bad).
2622          */
2623         falcon_read(efx, &temp, TX_CFG_REG_KER);
2624         EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
2625         falcon_write(efx, &temp, TX_CFG_REG_KER);
2626
2627         /* RX config */
2628         falcon_read(efx, &temp, RX_CFG_REG_KER);
2629         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
2630         if (EFX_WORKAROUND_7575(efx))
2631                 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
2632                                         (3 * 4096) / 32);
2633         if (falcon_rev(efx) >= FALCON_REV_B0)
2634                 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
2635
2636         /* RX FIFO flow control thresholds */
2637         thresh = ((rx_xon_thresh_bytes >= 0) ?
2638                   rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
2639         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
2640         thresh = ((rx_xoff_thresh_bytes >= 0) ?
2641                   rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
2642         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
2643         /* RX control FIFO thresholds [32 entries] */
2644         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 25);
2645         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 20);
2646         falcon_write(efx, &temp, RX_CFG_REG_KER);
2647
2648         /* Set destination of both TX and RX Flush events */
2649         if (falcon_rev(efx) >= FALCON_REV_B0) {
2650                 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
2651                 falcon_write(efx, &temp, DP_CTRL_REG);
2652         }
2653
2654         return 0;
2655 }
2656
2657 void falcon_remove_nic(struct efx_nic *efx)
2658 {
2659         struct falcon_nic_data *nic_data = efx->nic_data;
2660         int rc;
2661
2662         rc = i2c_del_adapter(&efx->i2c_adap);
2663         BUG_ON(rc);
2664
2665         falcon_free_buffer(efx, &efx->irq_status);
2666
2667         falcon_reset_hw(efx, RESET_TYPE_ALL);
2668
2669         /* Release the second function after the reset */
2670         if (nic_data->pci_dev2) {
2671                 pci_dev_put(nic_data->pci_dev2);
2672                 nic_data->pci_dev2 = NULL;
2673         }
2674
2675         /* Tear down the private nic state */
2676         kfree(efx->nic_data);
2677         efx->nic_data = NULL;
2678 }
2679
2680 void falcon_update_nic_stats(struct efx_nic *efx)
2681 {
2682         efx_oword_t cnt;
2683
2684         falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
2685         efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
2686 }
2687
2688 /**************************************************************************
2689  *
2690  * Revision-dependent attributes used by efx.c
2691  *
2692  **************************************************************************
2693  */
2694
2695 struct efx_nic_type falcon_a_nic_type = {
2696         .mem_bar = 2,
2697         .mem_map_size = 0x20000,
2698         .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
2699         .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
2700         .buf_tbl_base = BUF_TBL_KER_A1,
2701         .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
2702         .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
2703         .txd_ring_mask = FALCON_TXD_RING_MASK,
2704         .rxd_ring_mask = FALCON_RXD_RING_MASK,
2705         .evq_size = FALCON_EVQ_SIZE,
2706         .max_dma_mask = FALCON_DMA_MASK,
2707         .tx_dma_mask = FALCON_TX_DMA_MASK,
2708         .bug5391_mask = 0xf,
2709         .rx_xoff_thresh = 2048,
2710         .rx_xon_thresh = 512,
2711         .rx_buffer_padding = 0x24,
2712         .max_interrupt_mode = EFX_INT_MODE_MSI,
2713         .phys_addr_channels = 4,
2714 };
2715
2716 struct efx_nic_type falcon_b_nic_type = {
2717         .mem_bar = 2,
2718         /* Map everything up to and including the RSS indirection
2719          * table.  Don't map MSI-X table, MSI-X PBA since Linux
2720          * requires that they not be mapped.  */
2721         .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
2722         .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
2723         .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
2724         .buf_tbl_base = BUF_TBL_KER_B0,
2725         .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
2726         .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
2727         .txd_ring_mask = FALCON_TXD_RING_MASK,
2728         .rxd_ring_mask = FALCON_RXD_RING_MASK,
2729         .evq_size = FALCON_EVQ_SIZE,
2730         .max_dma_mask = FALCON_DMA_MASK,
2731         .tx_dma_mask = FALCON_TX_DMA_MASK,
2732         .bug5391_mask = 0,
2733         .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
2734         .rx_xon_thresh = 27648,  /* ~3*max MTU */
2735         .rx_buffer_padding = 0,
2736         .max_interrupt_mode = EFX_INT_MODE_MSIX,
2737         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
2738                                    * interrupt handler only supports 32
2739                                    * channels */
2740 };
2741