2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
20 #define ATH_PCI_VERSION "0.1"
22 static char *dev_info = "ath9k";
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
29 /* We use the hw_value as an index into our private channel structure */
31 #define CHAN2G(_freq, _idx) { \
32 .center_freq = (_freq), \
37 #define CHAN5G(_freq, _idx) { \
38 .band = IEEE80211_BAND_5GHZ, \
39 .center_freq = (_freq), \
44 /* Some 2 GHz radios are actually tunable on 2312-2732
45 * on 5 MHz steps, we support the channels which we know
46 * we have calibration data for all cards though to make
48 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
49 CHAN2G(2412, 0), /* Channel 1 */
50 CHAN2G(2417, 1), /* Channel 2 */
51 CHAN2G(2422, 2), /* Channel 3 */
52 CHAN2G(2427, 3), /* Channel 4 */
53 CHAN2G(2432, 4), /* Channel 5 */
54 CHAN2G(2437, 5), /* Channel 6 */
55 CHAN2G(2442, 6), /* Channel 7 */
56 CHAN2G(2447, 7), /* Channel 8 */
57 CHAN2G(2452, 8), /* Channel 9 */
58 CHAN2G(2457, 9), /* Channel 10 */
59 CHAN2G(2462, 10), /* Channel 11 */
60 CHAN2G(2467, 11), /* Channel 12 */
61 CHAN2G(2472, 12), /* Channel 13 */
62 CHAN2G(2484, 13), /* Channel 14 */
65 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
66 * on 5 MHz steps, we support the channels which we know
67 * we have calibration data for all cards though to make
69 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
70 /* _We_ call this UNII 1 */
71 CHAN5G(5180, 14), /* Channel 36 */
72 CHAN5G(5200, 15), /* Channel 40 */
73 CHAN5G(5220, 16), /* Channel 44 */
74 CHAN5G(5240, 17), /* Channel 48 */
75 /* _We_ call this UNII 2 */
76 CHAN5G(5260, 18), /* Channel 52 */
77 CHAN5G(5280, 19), /* Channel 56 */
78 CHAN5G(5300, 20), /* Channel 60 */
79 CHAN5G(5320, 21), /* Channel 64 */
80 /* _We_ call this "Middle band" */
81 CHAN5G(5500, 22), /* Channel 100 */
82 CHAN5G(5520, 23), /* Channel 104 */
83 CHAN5G(5540, 24), /* Channel 108 */
84 CHAN5G(5560, 25), /* Channel 112 */
85 CHAN5G(5580, 26), /* Channel 116 */
86 CHAN5G(5600, 27), /* Channel 120 */
87 CHAN5G(5620, 28), /* Channel 124 */
88 CHAN5G(5640, 29), /* Channel 128 */
89 CHAN5G(5660, 30), /* Channel 132 */
90 CHAN5G(5680, 31), /* Channel 136 */
91 CHAN5G(5700, 32), /* Channel 140 */
92 /* _We_ call this UNII 3 */
93 CHAN5G(5745, 33), /* Channel 149 */
94 CHAN5G(5765, 34), /* Channel 153 */
95 CHAN5G(5785, 35), /* Channel 157 */
96 CHAN5G(5805, 36), /* Channel 161 */
97 CHAN5G(5825, 37), /* Channel 165 */
100 static void ath_cache_conf_rate(struct ath_softc *sc,
101 struct ieee80211_conf *conf)
103 switch (conf->channel->band) {
104 case IEEE80211_BAND_2GHZ:
105 if (conf_is_ht20(conf))
107 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
108 else if (conf_is_ht40_minus(conf))
110 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
111 else if (conf_is_ht40_plus(conf))
113 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
116 sc->hw_rate_table[ATH9K_MODE_11G];
118 case IEEE80211_BAND_5GHZ:
119 if (conf_is_ht20(conf))
121 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
122 else if (conf_is_ht40_minus(conf))
124 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
125 else if (conf_is_ht40_plus(conf))
127 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130 sc->hw_rate_table[ATH9K_MODE_11A];
138 static void ath_update_txpow(struct ath_softc *sc)
140 struct ath_hal *ah = sc->sc_ah;
143 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
144 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
145 /* read back in case value is clamped */
146 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
147 sc->sc_curtxpow = txpow;
151 static u8 parse_mpdudensity(u8 mpdudensity)
154 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
155 * 0 for no restriction
164 switch (mpdudensity) {
170 /* Our lower layer calculations limit our precision to
186 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
188 struct ath_rate_table *rate_table = NULL;
189 struct ieee80211_supported_band *sband;
190 struct ieee80211_rate *rate;
194 case IEEE80211_BAND_2GHZ:
195 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
197 case IEEE80211_BAND_5GHZ:
198 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
204 if (rate_table == NULL)
207 sband = &sc->sbands[band];
208 rate = sc->rates[band];
210 if (rate_table->rate_cnt > ATH_RATE_MAX)
211 maxrates = ATH_RATE_MAX;
213 maxrates = rate_table->rate_cnt;
215 for (i = 0; i < maxrates; i++) {
216 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
217 rate[i].hw_value = rate_table->info[i].ratecode;
218 if (rate_table->info[i].short_preamble) {
219 rate[i].hw_value_short = rate_table->info[i].ratecode |
220 rate_table->info[i].short_preamble;
221 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
225 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
226 rate[i].bitrate / 10, rate[i].hw_value);
231 * Set/change channels. If the channel is really being changed, it's done
232 * by reseting the chip. To accomplish this we must first cleanup any pending
233 * DMA, then restart stuff.
235 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
237 struct ath_hal *ah = sc->sc_ah;
238 bool fastcc = true, stopped;
239 struct ieee80211_hw *hw = sc->hw;
240 struct ieee80211_channel *channel = hw->conf.channel;
243 if (sc->sc_flags & SC_OP_INVALID)
249 * This is only performed if the channel settings have
252 * To switch channels clear any pending DMA operations;
253 * wait long enough for the RX fifo to drain, reset the
254 * hardware at the new frequency, and then re-enable
255 * the relevant bits of the h/w.
257 ath9k_hw_set_interrupts(ah, 0);
258 ath_drain_all_txq(sc, false);
259 stopped = ath_stoprecv(sc);
261 /* XXX: do not flush receive queue here. We don't want
262 * to flush data frames already in queue because of
263 * changing channel. */
265 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
268 DPRINTF(sc, ATH_DBG_CONFIG,
269 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
270 sc->sc_ah->ah_curchan->channel,
271 channel->center_freq, sc->tx_chan_width);
273 spin_lock_bh(&sc->sc_resetlock);
275 r = ath9k_hw_reset(ah, hchan, fastcc);
277 DPRINTF(sc, ATH_DBG_FATAL,
278 "Unable to reset channel (%u Mhz) "
280 channel->center_freq, r);
281 spin_unlock_bh(&sc->sc_resetlock);
284 spin_unlock_bh(&sc->sc_resetlock);
286 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
287 sc->sc_flags &= ~SC_OP_FULL_RESET;
289 if (ath_startrecv(sc) != 0) {
290 DPRINTF(sc, ATH_DBG_FATAL,
291 "Unable to restart recv logic\n");
295 ath_cache_conf_rate(sc, &hw->conf);
296 ath_update_txpow(sc);
297 ath9k_hw_set_interrupts(ah, sc->sc_imask);
298 ath9k_ps_restore(sc);
303 * This routine performs the periodic noise floor calibration function
304 * that is used to adjust and optimize the chip performance. This
305 * takes environmental changes (location, temperature) into account.
306 * When the task is complete, it reschedules itself depending on the
307 * appropriate interval that was calculated.
309 static void ath_ani_calibrate(unsigned long data)
311 struct ath_softc *sc;
313 bool longcal = false;
314 bool shortcal = false;
315 bool aniflag = false;
316 unsigned int timestamp = jiffies_to_msecs(jiffies);
319 sc = (struct ath_softc *)data;
323 * don't calibrate when we're scanning.
324 * we are most likely not on our home channel.
326 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
329 /* Long calibration runs independently of short calibration. */
330 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
332 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
333 sc->sc_ani.sc_longcal_timer = timestamp;
336 /* Short calibration applies only while sc_caldone is false */
337 if (!sc->sc_ani.sc_caldone) {
338 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
339 ATH_SHORT_CALINTERVAL) {
341 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
342 sc->sc_ani.sc_shortcal_timer = timestamp;
343 sc->sc_ani.sc_resetcal_timer = timestamp;
346 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
347 ATH_RESTART_CALINTERVAL) {
348 sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
349 if (sc->sc_ani.sc_caldone)
350 sc->sc_ani.sc_resetcal_timer = timestamp;
354 /* Verify whether we must check ANI */
355 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
356 ATH_ANI_POLLINTERVAL) {
358 sc->sc_ani.sc_checkani_timer = timestamp;
361 /* Skip all processing if there's nothing to do. */
362 if (longcal || shortcal || aniflag) {
363 /* Call ANI routine if necessary */
365 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
368 /* Perform calibration if necessary */
369 if (longcal || shortcal) {
370 bool iscaldone = false;
372 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
373 sc->sc_rx_chainmask, longcal,
376 sc->sc_ani.sc_noise_floor =
377 ath9k_hw_getchan_noise(ah,
380 DPRINTF(sc, ATH_DBG_ANI,
381 "calibrate chan %u/%x nf: %d\n",
382 ah->ah_curchan->channel,
383 ah->ah_curchan->channelFlags,
384 sc->sc_ani.sc_noise_floor);
386 DPRINTF(sc, ATH_DBG_ANY,
387 "calibrate chan %u/%x failed\n",
388 ah->ah_curchan->channel,
389 ah->ah_curchan->channelFlags);
391 sc->sc_ani.sc_caldone = iscaldone;
396 * Set timer interval based on previous results.
397 * The interval must be the shortest necessary to satisfy ANI,
398 * short calibration and long calibration.
400 cal_interval = ATH_LONG_CALINTERVAL;
401 if (sc->sc_ah->ah_config.enable_ani)
402 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
403 if (!sc->sc_ani.sc_caldone)
404 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
406 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
410 * Update tx/rx chainmask. For legacy association,
411 * hard code chainmask to 1x1, for 11n association, use
412 * the chainmask configuration, for bt coexistence, use
413 * the chainmask configuration even in legacy mode.
415 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
417 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
419 (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
420 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
421 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
423 sc->sc_tx_chainmask = 1;
424 sc->sc_rx_chainmask = 1;
427 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
428 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
431 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
435 an = (struct ath_node *)sta->drv_priv;
437 if (sc->sc_flags & SC_OP_TXAGGR)
438 ath_tx_node_init(sc, an);
440 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
441 sta->ht_cap.ampdu_factor);
442 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
447 struct ath_node *an = (struct ath_node *)sta->drv_priv;
449 if (sc->sc_flags & SC_OP_TXAGGR)
450 ath_tx_node_cleanup(sc, an);
453 static void ath9k_tasklet(unsigned long data)
455 struct ath_softc *sc = (struct ath_softc *)data;
456 u32 status = sc->sc_intrstatus;
458 if (status & ATH9K_INT_FATAL) {
459 /* need a chip reset */
460 ath_reset(sc, false);
465 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
466 spin_lock_bh(&sc->rx.rxflushlock);
467 ath_rx_tasklet(sc, 0);
468 spin_unlock_bh(&sc->rx.rxflushlock);
470 /* XXX: optimize this */
471 if (status & ATH9K_INT_TX)
475 /* re-enable hardware interrupt */
476 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
479 irqreturn_t ath_isr(int irq, void *dev)
481 struct ath_softc *sc = dev;
482 struct ath_hal *ah = sc->sc_ah;
483 enum ath9k_int status;
487 if (sc->sc_flags & SC_OP_INVALID) {
489 * The hardware is not ready/present, don't
490 * touch anything. Note this can happen early
491 * on if the IRQ is shared.
495 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
500 * Figure out the reason(s) for the interrupt. Note
501 * that the hal returns a pseudo-ISR that may include
502 * bits we haven't explicitly enabled so we mask the
503 * value to insure we only process bits we requested.
505 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
507 status &= sc->sc_imask; /* discard unasked-for bits */
510 * If there are no status bits set, then this interrupt was not
511 * for me (should have been caught above).
516 sc->sc_intrstatus = status;
518 if (status & ATH9K_INT_FATAL) {
519 /* need a chip reset */
521 } else if (status & ATH9K_INT_RXORN) {
522 /* need a chip reset */
525 if (status & ATH9K_INT_SWBA) {
526 /* schedule a tasklet for beacon handling */
527 tasklet_schedule(&sc->bcon_tasklet);
529 if (status & ATH9K_INT_RXEOL) {
531 * NB: the hardware should re-read the link when
532 * RXE bit is written, but it doesn't work
533 * at least on older hardware revs.
538 if (status & ATH9K_INT_TXURN)
539 /* bump tx trigger level */
540 ath9k_hw_updatetxtriglevel(ah, true);
541 /* XXX: optimize this */
542 if (status & ATH9K_INT_RX)
544 if (status & ATH9K_INT_TX)
546 if (status & ATH9K_INT_BMISS)
548 /* carrier sense timeout */
549 if (status & ATH9K_INT_CST)
551 if (status & ATH9K_INT_MIB) {
553 * Disable interrupts until we service the MIB
554 * interrupt; otherwise it will continue to
557 ath9k_hw_set_interrupts(ah, 0);
559 * Let the hal handle the event. We assume
560 * it will clear whatever condition caused
563 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
564 ath9k_hw_set_interrupts(ah, sc->sc_imask);
566 if (status & ATH9K_INT_TIM_TIMER) {
567 if (!(ah->ah_caps.hw_caps &
568 ATH9K_HW_CAP_AUTOSLEEP)) {
569 /* Clear RxAbort bit so that we can
571 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
572 ath9k_hw_setrxabort(ah, 0);
574 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
580 ath_debug_stat_interrupt(sc, status);
583 /* turn off every interrupt except SWBA */
584 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
585 tasklet_schedule(&sc->intr_tq);
591 static u32 ath_get_extchanmode(struct ath_softc *sc,
592 struct ieee80211_channel *chan,
593 enum nl80211_channel_type channel_type)
597 switch (chan->band) {
598 case IEEE80211_BAND_2GHZ:
599 switch(channel_type) {
600 case NL80211_CHAN_NO_HT:
601 case NL80211_CHAN_HT20:
602 chanmode = CHANNEL_G_HT20;
604 case NL80211_CHAN_HT40PLUS:
605 chanmode = CHANNEL_G_HT40PLUS;
607 case NL80211_CHAN_HT40MINUS:
608 chanmode = CHANNEL_G_HT40MINUS;
612 case IEEE80211_BAND_5GHZ:
613 switch(channel_type) {
614 case NL80211_CHAN_NO_HT:
615 case NL80211_CHAN_HT20:
616 chanmode = CHANNEL_A_HT20;
618 case NL80211_CHAN_HT40PLUS:
619 chanmode = CHANNEL_A_HT40PLUS;
621 case NL80211_CHAN_HT40MINUS:
622 chanmode = CHANNEL_A_HT40MINUS;
633 static int ath_keyset(struct ath_softc *sc, u16 keyix,
634 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
638 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
639 keyix, hk, mac, false);
641 return status != false;
644 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
645 struct ath9k_keyval *hk,
651 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
652 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
655 /* Group key installation */
656 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
657 return ath_keyset(sc, keyix, hk, addr);
659 if (!sc->sc_splitmic) {
661 * data key goes at first index,
662 * the hal handles the MIC keys at index+64.
664 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
665 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
666 return ath_keyset(sc, keyix, hk, addr);
669 * TX key goes at first index, RX key at +32.
670 * The hal handles the MIC keys at index+64.
672 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
673 if (!ath_keyset(sc, keyix, hk, NULL)) {
674 /* Txmic entry failed. No need to proceed further */
675 DPRINTF(sc, ATH_DBG_KEYCACHE,
676 "Setting TX MIC Key Failed\n");
680 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
681 /* XXX delete tx key on failure? */
682 return ath_keyset(sc, keyix + 32, hk, addr);
685 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
689 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
690 if (test_bit(i, sc->sc_keymap) ||
691 test_bit(i + 64, sc->sc_keymap))
692 continue; /* At least one part of TKIP key allocated */
693 if (sc->sc_splitmic &&
694 (test_bit(i + 32, sc->sc_keymap) ||
695 test_bit(i + 64 + 32, sc->sc_keymap)))
696 continue; /* At least one part of TKIP key allocated */
698 /* Found a free slot for a TKIP key */
704 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
708 /* First, try to find slots that would not be available for TKIP. */
709 if (sc->sc_splitmic) {
710 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
711 if (!test_bit(i, sc->sc_keymap) &&
712 (test_bit(i + 32, sc->sc_keymap) ||
713 test_bit(i + 64, sc->sc_keymap) ||
714 test_bit(i + 64 + 32, sc->sc_keymap)))
716 if (!test_bit(i + 32, sc->sc_keymap) &&
717 (test_bit(i, sc->sc_keymap) ||
718 test_bit(i + 64, sc->sc_keymap) ||
719 test_bit(i + 64 + 32, sc->sc_keymap)))
721 if (!test_bit(i + 64, sc->sc_keymap) &&
722 (test_bit(i , sc->sc_keymap) ||
723 test_bit(i + 32, sc->sc_keymap) ||
724 test_bit(i + 64 + 32, sc->sc_keymap)))
726 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
727 (test_bit(i, sc->sc_keymap) ||
728 test_bit(i + 32, sc->sc_keymap) ||
729 test_bit(i + 64, sc->sc_keymap)))
733 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
734 if (!test_bit(i, sc->sc_keymap) &&
735 test_bit(i + 64, sc->sc_keymap))
737 if (test_bit(i, sc->sc_keymap) &&
738 !test_bit(i + 64, sc->sc_keymap))
743 /* No partially used TKIP slots, pick any available slot */
744 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
745 /* Do not allow slots that could be needed for TKIP group keys
746 * to be used. This limitation could be removed if we know that
747 * TKIP will not be used. */
748 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
750 if (sc->sc_splitmic) {
751 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
753 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
757 if (!test_bit(i, sc->sc_keymap))
758 return i; /* Found a free slot for a key */
761 /* No free slot found */
765 static int ath_key_config(struct ath_softc *sc,
766 struct ieee80211_sta *sta,
767 struct ieee80211_key_conf *key)
769 struct ath9k_keyval hk;
770 const u8 *mac = NULL;
774 memset(&hk, 0, sizeof(hk));
778 hk.kv_type = ATH9K_CIPHER_WEP;
781 hk.kv_type = ATH9K_CIPHER_TKIP;
784 hk.kv_type = ATH9K_CIPHER_AES_CCM;
790 hk.kv_len = key->keylen;
791 memcpy(hk.kv_val, key->key, key->keylen);
793 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
794 /* For now, use the default keys for broadcast keys. This may
795 * need to change with virtual interfaces. */
797 } else if (key->keyidx) {
798 struct ieee80211_vif *vif;
804 vif = sc->sc_vaps[0];
805 if (vif->type != NL80211_IFTYPE_AP) {
806 /* Only keyidx 0 should be used with unicast key, but
807 * allow this for client mode for now. */
816 if (key->alg == ALG_TKIP)
817 idx = ath_reserve_key_cache_slot_tkip(sc);
819 idx = ath_reserve_key_cache_slot(sc);
821 return -ENOSPC; /* no free key cache entries */
824 if (key->alg == ALG_TKIP)
825 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
827 ret = ath_keyset(sc, idx, &hk, mac);
832 set_bit(idx, sc->sc_keymap);
833 if (key->alg == ALG_TKIP) {
834 set_bit(idx + 64, sc->sc_keymap);
835 if (sc->sc_splitmic) {
836 set_bit(idx + 32, sc->sc_keymap);
837 set_bit(idx + 64 + 32, sc->sc_keymap);
844 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
846 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
847 if (key->hw_key_idx < IEEE80211_WEP_NKID)
850 clear_bit(key->hw_key_idx, sc->sc_keymap);
851 if (key->alg != ALG_TKIP)
854 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
855 if (sc->sc_splitmic) {
856 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
857 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
861 static void setup_ht_cap(struct ath_softc *sc,
862 struct ieee80211_sta_ht_cap *ht_info)
864 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
865 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
867 ht_info->ht_supported = true;
868 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
869 IEEE80211_HT_CAP_SM_PS |
870 IEEE80211_HT_CAP_SGI_40 |
871 IEEE80211_HT_CAP_DSSSCCK40;
873 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
874 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
876 /* set up supported mcs set */
877 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
879 switch(sc->sc_rx_chainmask) {
881 ht_info->mcs.rx_mask[0] = 0xff;
887 ht_info->mcs.rx_mask[0] = 0xff;
888 ht_info->mcs.rx_mask[1] = 0xff;
892 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
895 static void ath9k_bss_assoc_info(struct ath_softc *sc,
896 struct ieee80211_vif *vif,
897 struct ieee80211_bss_conf *bss_conf)
899 struct ath_vap *avp = (void *)vif->drv_priv;
901 if (bss_conf->assoc) {
902 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
903 bss_conf->aid, sc->sc_curbssid);
905 /* New association, store aid */
906 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
907 sc->sc_curaid = bss_conf->aid;
908 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
912 /* Configure the beacon */
913 ath_beacon_config(sc, 0);
914 sc->sc_flags |= SC_OP_BEACONS;
916 /* Reset rssi stats */
917 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
918 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
919 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
920 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
923 mod_timer(&sc->sc_ani.timer,
924 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
927 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
932 /********************************/
934 /********************************/
936 static void ath_led_blink_work(struct work_struct *work)
938 struct ath_softc *sc = container_of(work, struct ath_softc,
939 ath_led_blink_work.work);
941 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
943 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
944 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
946 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
947 (sc->sc_flags & SC_OP_LED_ON) ?
948 msecs_to_jiffies(sc->led_off_duration) :
949 msecs_to_jiffies(sc->led_on_duration));
951 sc->led_on_duration =
952 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
953 sc->led_off_duration =
954 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
955 sc->led_on_cnt = sc->led_off_cnt = 0;
956 if (sc->sc_flags & SC_OP_LED_ON)
957 sc->sc_flags &= ~SC_OP_LED_ON;
959 sc->sc_flags |= SC_OP_LED_ON;
962 static void ath_led_brightness(struct led_classdev *led_cdev,
963 enum led_brightness brightness)
965 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
966 struct ath_softc *sc = led->sc;
968 switch (brightness) {
970 if (led->led_type == ATH_LED_ASSOC ||
971 led->led_type == ATH_LED_RADIO) {
972 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
973 (led->led_type == ATH_LED_RADIO));
974 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
975 if (led->led_type == ATH_LED_RADIO)
976 sc->sc_flags &= ~SC_OP_LED_ON;
982 if (led->led_type == ATH_LED_ASSOC) {
983 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
984 queue_delayed_work(sc->hw->workqueue,
985 &sc->ath_led_blink_work, 0);
986 } else if (led->led_type == ATH_LED_RADIO) {
987 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
988 sc->sc_flags |= SC_OP_LED_ON;
998 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1004 led->led_cdev.name = led->name;
1005 led->led_cdev.default_trigger = trigger;
1006 led->led_cdev.brightness_set = ath_led_brightness;
1008 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1010 DPRINTF(sc, ATH_DBG_FATAL,
1011 "Failed to register led:%s", led->name);
1013 led->registered = 1;
1017 static void ath_unregister_led(struct ath_led *led)
1019 if (led->registered) {
1020 led_classdev_unregister(&led->led_cdev);
1021 led->registered = 0;
1025 static void ath_deinit_leds(struct ath_softc *sc)
1027 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1028 ath_unregister_led(&sc->assoc_led);
1029 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1030 ath_unregister_led(&sc->tx_led);
1031 ath_unregister_led(&sc->rx_led);
1032 ath_unregister_led(&sc->radio_led);
1033 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1036 static void ath_init_leds(struct ath_softc *sc)
1041 /* Configure gpio 1 for output */
1042 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1043 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1044 /* LED off, active low */
1045 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1047 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1049 trigger = ieee80211_get_radio_led_name(sc->hw);
1050 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1051 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1052 ret = ath_register_led(sc, &sc->radio_led, trigger);
1053 sc->radio_led.led_type = ATH_LED_RADIO;
1057 trigger = ieee80211_get_assoc_led_name(sc->hw);
1058 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1059 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1060 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1061 sc->assoc_led.led_type = ATH_LED_ASSOC;
1065 trigger = ieee80211_get_tx_led_name(sc->hw);
1066 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1067 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1068 ret = ath_register_led(sc, &sc->tx_led, trigger);
1069 sc->tx_led.led_type = ATH_LED_TX;
1073 trigger = ieee80211_get_rx_led_name(sc->hw);
1074 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1075 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1076 ret = ath_register_led(sc, &sc->rx_led, trigger);
1077 sc->rx_led.led_type = ATH_LED_RX;
1084 ath_deinit_leds(sc);
1087 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1089 /*******************/
1091 /*******************/
1093 static void ath_radio_enable(struct ath_softc *sc)
1095 struct ath_hal *ah = sc->sc_ah;
1096 struct ieee80211_channel *channel = sc->hw->conf.channel;
1099 ath9k_ps_wakeup(sc);
1100 spin_lock_bh(&sc->sc_resetlock);
1102 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1105 DPRINTF(sc, ATH_DBG_FATAL,
1106 "Unable to reset channel %u (%uMhz) ",
1107 "reset status %u\n",
1108 channel->center_freq, r);
1110 spin_unlock_bh(&sc->sc_resetlock);
1112 ath_update_txpow(sc);
1113 if (ath_startrecv(sc) != 0) {
1114 DPRINTF(sc, ATH_DBG_FATAL,
1115 "Unable to restart recv logic\n");
1119 if (sc->sc_flags & SC_OP_BEACONS)
1120 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1122 /* Re-Enable interrupts */
1123 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1126 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1127 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1128 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1130 ieee80211_wake_queues(sc->hw);
1131 ath9k_ps_restore(sc);
1134 static void ath_radio_disable(struct ath_softc *sc)
1136 struct ath_hal *ah = sc->sc_ah;
1137 struct ieee80211_channel *channel = sc->hw->conf.channel;
1140 ath9k_ps_wakeup(sc);
1141 ieee80211_stop_queues(sc->hw);
1144 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1145 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1147 /* Disable interrupts */
1148 ath9k_hw_set_interrupts(ah, 0);
1150 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1151 ath_stoprecv(sc); /* turn off frame recv */
1152 ath_flushrecv(sc); /* flush recv queue */
1154 spin_lock_bh(&sc->sc_resetlock);
1155 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1157 DPRINTF(sc, ATH_DBG_FATAL,
1158 "Unable to reset channel %u (%uMhz) "
1159 "reset status %u\n",
1160 channel->center_freq, r);
1162 spin_unlock_bh(&sc->sc_resetlock);
1164 ath9k_hw_phy_disable(ah);
1165 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1166 ath9k_ps_restore(sc);
1169 static bool ath_is_rfkill_set(struct ath_softc *sc)
1171 struct ath_hal *ah = sc->sc_ah;
1173 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1174 ah->ah_rfkill_polarity;
1177 /* h/w rfkill poll function */
1178 static void ath_rfkill_poll(struct work_struct *work)
1180 struct ath_softc *sc = container_of(work, struct ath_softc,
1181 rf_kill.rfkill_poll.work);
1184 if (sc->sc_flags & SC_OP_INVALID)
1187 radio_on = !ath_is_rfkill_set(sc);
1190 * enable/disable radio only when there is a
1191 * state change in RF switch
1193 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1194 enum rfkill_state state;
1196 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1197 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1198 : RFKILL_STATE_HARD_BLOCKED;
1199 } else if (radio_on) {
1200 ath_radio_enable(sc);
1201 state = RFKILL_STATE_UNBLOCKED;
1203 ath_radio_disable(sc);
1204 state = RFKILL_STATE_HARD_BLOCKED;
1207 if (state == RFKILL_STATE_HARD_BLOCKED)
1208 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1210 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1212 rfkill_force_state(sc->rf_kill.rfkill, state);
1215 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1216 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1219 /* s/w rfkill handler */
1220 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1222 struct ath_softc *sc = data;
1225 case RFKILL_STATE_SOFT_BLOCKED:
1226 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1227 SC_OP_RFKILL_SW_BLOCKED)))
1228 ath_radio_disable(sc);
1229 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1231 case RFKILL_STATE_UNBLOCKED:
1232 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1233 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1234 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1235 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1236 "radio as it is disabled by h/w\n");
1239 ath_radio_enable(sc);
1247 /* Init s/w rfkill */
1248 static int ath_init_sw_rfkill(struct ath_softc *sc)
1250 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1252 if (!sc->rf_kill.rfkill) {
1253 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1257 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1258 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1259 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1260 sc->rf_kill.rfkill->data = sc;
1261 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1262 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1263 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1268 /* Deinitialize rfkill */
1269 static void ath_deinit_rfkill(struct ath_softc *sc)
1271 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1272 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1274 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1275 rfkill_unregister(sc->rf_kill.rfkill);
1276 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1277 sc->rf_kill.rfkill = NULL;
1281 static int ath_start_rfkill_poll(struct ath_softc *sc)
1283 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1284 queue_delayed_work(sc->hw->workqueue,
1285 &sc->rf_kill.rfkill_poll, 0);
1287 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1288 if (rfkill_register(sc->rf_kill.rfkill)) {
1289 DPRINTF(sc, ATH_DBG_FATAL,
1290 "Unable to register rfkill\n");
1291 rfkill_free(sc->rf_kill.rfkill);
1293 /* Deinitialize the device */
1297 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1303 #endif /* CONFIG_RFKILL */
1305 void ath_cleanup(struct ath_softc *sc)
1308 free_irq(sc->irq, sc);
1309 ath_bus_cleanup(sc);
1310 ieee80211_free_hw(sc->hw);
1313 void ath_detach(struct ath_softc *sc)
1315 struct ieee80211_hw *hw = sc->hw;
1318 ath9k_ps_wakeup(sc);
1320 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1322 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1323 ath_deinit_rfkill(sc);
1325 ath_deinit_leds(sc);
1327 ieee80211_unregister_hw(hw);
1331 tasklet_kill(&sc->intr_tq);
1332 tasklet_kill(&sc->bcon_tasklet);
1334 if (!(sc->sc_flags & SC_OP_INVALID))
1335 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1337 /* cleanup tx queues */
1338 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1339 if (ATH_TXQ_SETUP(sc, i))
1340 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1342 ath9k_hw_detach(sc->sc_ah);
1343 ath9k_exit_debug(sc);
1344 ath9k_ps_restore(sc);
1347 static int ath_init(u16 devid, struct ath_softc *sc)
1349 struct ath_hal *ah = NULL;
1354 /* XXX: hardware will not be ready until ath_open() being called */
1355 sc->sc_flags |= SC_OP_INVALID;
1357 if (ath9k_init_debug(sc) < 0)
1358 printk(KERN_ERR "Unable to create debugfs files\n");
1360 spin_lock_init(&sc->sc_resetlock);
1361 mutex_init(&sc->mutex);
1362 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1363 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1367 * Cache line size is used to size and align various
1368 * structures used to communicate with the hardware.
1370 ath_read_cachesize(sc, &csz);
1371 /* XXX assert csz is non-zero */
1372 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1374 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1376 DPRINTF(sc, ATH_DBG_FATAL,
1377 "Unable to attach hardware; HAL status %d\n", status);
1383 /* Get the hardware key cache size. */
1384 sc->sc_keymax = ah->ah_caps.keycache_size;
1385 if (sc->sc_keymax > ATH_KEYMAX) {
1386 DPRINTF(sc, ATH_DBG_KEYCACHE,
1387 "Warning, using only %u entries in %u key cache\n",
1388 ATH_KEYMAX, sc->sc_keymax);
1389 sc->sc_keymax = ATH_KEYMAX;
1393 * Reset the key cache since some parts do not
1394 * reset the contents on initial power up.
1396 for (i = 0; i < sc->sc_keymax; i++)
1397 ath9k_hw_keyreset(ah, (u16) i);
1399 if (ath9k_regd_init(sc->sc_ah))
1402 /* default to MONITOR mode */
1403 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1405 /* Setup rate tables */
1407 ath_rate_attach(sc);
1408 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1409 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1412 * Allocate hardware transmit queues: one queue for
1413 * beacon frames and one data queue for each QoS
1414 * priority. Note that the hal handles reseting
1415 * these queues at the needed time.
1417 sc->beacon.beaconq = ath_beaconq_setup(ah);
1418 if (sc->beacon.beaconq == -1) {
1419 DPRINTF(sc, ATH_DBG_FATAL,
1420 "Unable to setup a beacon xmit queue\n");
1424 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1425 if (sc->beacon.cabq == NULL) {
1426 DPRINTF(sc, ATH_DBG_FATAL,
1427 "Unable to setup CAB xmit queue\n");
1432 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1433 ath_cabq_update(sc);
1435 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1436 sc->tx.hwq_map[i] = -1;
1438 /* Setup data queues */
1439 /* NB: ensure BK queue is the lowest priority h/w queue */
1440 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1441 DPRINTF(sc, ATH_DBG_FATAL,
1442 "Unable to setup xmit queue for BK traffic\n");
1447 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1448 DPRINTF(sc, ATH_DBG_FATAL,
1449 "Unable to setup xmit queue for BE traffic\n");
1453 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1454 DPRINTF(sc, ATH_DBG_FATAL,
1455 "Unable to setup xmit queue for VI traffic\n");
1459 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1460 DPRINTF(sc, ATH_DBG_FATAL,
1461 "Unable to setup xmit queue for VO traffic\n");
1466 /* Initializes the noise floor to a reasonable default value.
1467 * Later on this will be updated during ANI processing. */
1469 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1470 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1472 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1473 ATH9K_CIPHER_TKIP, NULL)) {
1475 * Whether we should enable h/w TKIP MIC.
1476 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1477 * report WMM capable, so it's always safe to turn on
1478 * TKIP MIC in this case.
1480 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1485 * Check whether the separate key cache entries
1486 * are required to handle both tx+rx MIC keys.
1487 * With split mic keys the number of stations is limited
1488 * to 27 otherwise 59.
1490 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1491 ATH9K_CIPHER_TKIP, NULL)
1492 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1493 ATH9K_CIPHER_MIC, NULL)
1494 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1496 sc->sc_splitmic = 1;
1498 /* turn on mcast key search if possible */
1499 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1500 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1503 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1505 /* 11n Capabilities */
1506 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1507 sc->sc_flags |= SC_OP_TXAGGR;
1508 sc->sc_flags |= SC_OP_RXAGGR;
1511 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1512 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1514 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1515 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1517 ath9k_hw_getmac(ah, sc->sc_myaddr);
1518 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1519 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1520 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1521 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1524 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1526 /* initialize beacon slots */
1527 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1528 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1530 /* save MISC configurations */
1531 sc->sc_config.swBeaconProcess = 1;
1533 /* setup channels and rates */
1535 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1536 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1537 sc->rates[IEEE80211_BAND_2GHZ];
1538 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1539 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1540 ARRAY_SIZE(ath9k_2ghz_chantable);
1542 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1543 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1544 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1545 sc->rates[IEEE80211_BAND_5GHZ];
1546 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1547 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1548 ARRAY_SIZE(ath9k_5ghz_chantable);
1551 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1552 ath9k_hw_btcoex_enable(sc->sc_ah);
1556 /* cleanup tx queues */
1557 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1558 if (ATH_TXQ_SETUP(sc, i))
1559 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1562 ath9k_hw_detach(ah);
1567 int ath_attach(u16 devid, struct ath_softc *sc)
1569 struct ieee80211_hw *hw = sc->hw;
1572 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1574 error = ath_init(devid, sc);
1578 /* get mac address from hardware and set in mac80211 */
1580 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1582 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1583 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1584 IEEE80211_HW_SIGNAL_DBM |
1585 IEEE80211_HW_AMPDU_AGGREGATION |
1586 IEEE80211_HW_SUPPORTS_PS |
1587 IEEE80211_HW_PS_NULLFUNC_STACK;
1589 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1590 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1592 hw->wiphy->interface_modes =
1593 BIT(NL80211_IFTYPE_AP) |
1594 BIT(NL80211_IFTYPE_STATION) |
1595 BIT(NL80211_IFTYPE_ADHOC);
1597 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1598 hw->wiphy->strict_regulatory = true;
1602 hw->max_rate_tries = ATH_11N_TXMAXTRY;
1603 hw->sta_data_size = sizeof(struct ath_node);
1604 hw->vif_data_size = sizeof(struct ath_vap);
1606 hw->rate_control_algorithm = "ath9k_rate_control";
1608 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1609 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1610 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1611 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1614 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1615 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1616 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1617 &sc->sbands[IEEE80211_BAND_5GHZ];
1619 /* initialize tx/rx engine */
1620 error = ath_tx_init(sc, ATH_TXBUF);
1624 error = ath_rx_init(sc, ATH_RXBUF);
1628 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1629 /* Initialze h/w Rfkill */
1630 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1631 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1633 /* Initialize s/w rfkill */
1634 if (ath_init_sw_rfkill(sc))
1638 if (ath9k_is_world_regd(sc->sc_ah)) {
1639 /* Anything applied here (prior to wiphy registratoin) gets
1640 * saved on the wiphy orig_* parameters */
1641 const struct ieee80211_regdomain *regd =
1642 ath9k_world_regdomain(sc->sc_ah);
1643 hw->wiphy->custom_regulatory = true;
1644 hw->wiphy->strict_regulatory = false;
1645 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1646 ath9k_reg_apply_radar_flags(hw->wiphy);
1647 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1649 /* This gets applied in the case of the absense of CRDA,
1650 * its our own custom world regulatory domain, similar to
1651 * cfg80211's but we enable passive scanning */
1652 const struct ieee80211_regdomain *regd =
1653 ath9k_default_world_regdomain();
1654 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1655 ath9k_reg_apply_radar_flags(hw->wiphy);
1656 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1659 error = ieee80211_register_hw(hw);
1661 if (!ath9k_is_world_regd(sc->sc_ah))
1662 regulatory_hint(hw->wiphy, sc->sc_ah->alpha2);
1664 /* Initialize LED control */
1674 int ath_reset(struct ath_softc *sc, bool retry_tx)
1676 struct ath_hal *ah = sc->sc_ah;
1677 struct ieee80211_hw *hw = sc->hw;
1680 ath9k_hw_set_interrupts(ah, 0);
1681 ath_drain_all_txq(sc, retry_tx);
1685 spin_lock_bh(&sc->sc_resetlock);
1686 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1688 DPRINTF(sc, ATH_DBG_FATAL,
1689 "Unable to reset hardware; reset status %u\n", r);
1690 spin_unlock_bh(&sc->sc_resetlock);
1692 if (ath_startrecv(sc) != 0)
1693 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1696 * We may be doing a reset in response to a request
1697 * that changes the channel so update any state that
1698 * might change as a result.
1700 ath_cache_conf_rate(sc, &hw->conf);
1702 ath_update_txpow(sc);
1704 if (sc->sc_flags & SC_OP_BEACONS)
1705 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1707 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1711 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1712 if (ATH_TXQ_SETUP(sc, i)) {
1713 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1714 ath_txq_schedule(sc, &sc->tx.txq[i]);
1715 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1724 * This function will allocate both the DMA descriptor structure, and the
1725 * buffers it contains. These are used to contain the descriptors used
1728 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1729 struct list_head *head, const char *name,
1730 int nbuf, int ndesc)
1732 #define DS2PHYS(_dd, _ds) \
1733 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1734 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1735 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1737 struct ath_desc *ds;
1739 int i, bsize, error;
1741 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1744 /* ath_desc must be a multiple of DWORDs */
1745 if ((sizeof(struct ath_desc) % 4) != 0) {
1746 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1747 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1753 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1756 * Need additional DMA memory because we can't use
1757 * descriptors that cross the 4K page boundary. Assume
1758 * one skipped descriptor per 4K page.
1760 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1762 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1765 while (ndesc_skipped) {
1766 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1767 dd->dd_desc_len += dma_len;
1769 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1773 /* allocate descriptors */
1774 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1775 &dd->dd_desc_paddr, GFP_ATOMIC);
1776 if (dd->dd_desc == NULL) {
1781 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1782 dd->dd_name, ds, (u32) dd->dd_desc_len,
1783 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1785 /* allocate buffers */
1786 bsize = sizeof(struct ath_buf) * nbuf;
1787 bf = kmalloc(bsize, GFP_KERNEL);
1792 memset(bf, 0, bsize);
1795 INIT_LIST_HEAD(head);
1796 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1798 bf->bf_daddr = DS2PHYS(dd, ds);
1800 if (!(sc->sc_ah->ah_caps.hw_caps &
1801 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1803 * Skip descriptor addresses which can cause 4KB
1804 * boundary crossing (addr + length) with a 32 dword
1807 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1808 ASSERT((caddr_t) bf->bf_desc <
1809 ((caddr_t) dd->dd_desc +
1814 bf->bf_daddr = DS2PHYS(dd, ds);
1817 list_add_tail(&bf->list, head);
1821 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1824 memset(dd, 0, sizeof(*dd));
1826 #undef ATH_DESC_4KB_BOUND_CHECK
1827 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1831 void ath_descdma_cleanup(struct ath_softc *sc,
1832 struct ath_descdma *dd,
1833 struct list_head *head)
1835 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1838 INIT_LIST_HEAD(head);
1839 kfree(dd->dd_bufptr);
1840 memset(dd, 0, sizeof(*dd));
1843 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1849 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1852 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1855 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1858 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1861 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1868 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1873 case ATH9K_WME_AC_VO:
1876 case ATH9K_WME_AC_VI:
1879 case ATH9K_WME_AC_BE:
1882 case ATH9K_WME_AC_BK:
1893 /* XXX: Remove me once we don't depend on ath9k_channel for all
1894 * this redundant data */
1895 static void ath9k_update_ichannel(struct ath_softc *sc,
1896 struct ath9k_channel *ichan)
1898 struct ieee80211_hw *hw = sc->hw;
1899 struct ieee80211_channel *chan = hw->conf.channel;
1900 struct ieee80211_conf *conf = &hw->conf;
1902 ichan->channel = chan->center_freq;
1905 if (chan->band == IEEE80211_BAND_2GHZ) {
1906 ichan->chanmode = CHANNEL_G;
1907 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1909 ichan->chanmode = CHANNEL_A;
1910 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1913 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1915 if (conf_is_ht(conf)) {
1916 if (conf_is_ht40(conf))
1917 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1919 ichan->chanmode = ath_get_extchanmode(sc, chan,
1920 conf->channel_type);
1924 /**********************/
1925 /* mac80211 callbacks */
1926 /**********************/
1928 static int ath9k_start(struct ieee80211_hw *hw)
1930 struct ath_softc *sc = hw->priv;
1931 struct ieee80211_channel *curchan = hw->conf.channel;
1932 struct ath9k_channel *init_channel;
1935 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1936 "initial channel: %d MHz\n", curchan->center_freq);
1938 mutex_lock(&sc->mutex);
1940 /* setup initial channel */
1942 pos = curchan->hw_value;
1944 init_channel = &sc->sc_ah->ah_channels[pos];
1945 ath9k_update_ichannel(sc, init_channel);
1947 /* Reset SERDES registers */
1948 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1951 * The basic interface to setting the hardware in a good
1952 * state is ``reset''. On return the hardware is known to
1953 * be powered up and with interrupts disabled. This must
1954 * be followed by initialization of the appropriate bits
1955 * and then setup of the interrupt mask.
1957 spin_lock_bh(&sc->sc_resetlock);
1958 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1960 DPRINTF(sc, ATH_DBG_FATAL,
1961 "Unable to reset hardware; reset status %u "
1962 "(freq %u MHz)\n", r,
1963 curchan->center_freq);
1964 spin_unlock_bh(&sc->sc_resetlock);
1967 spin_unlock_bh(&sc->sc_resetlock);
1970 * This is needed only to setup initial state
1971 * but it's best done after a reset.
1973 ath_update_txpow(sc);
1976 * Setup the hardware after reset:
1977 * The receive engine is set going.
1978 * Frame transmit is handled entirely
1979 * in the frame output path; there's nothing to do
1980 * here except setup the interrupt mask.
1982 if (ath_startrecv(sc) != 0) {
1983 DPRINTF(sc, ATH_DBG_FATAL,
1984 "Unable to start recv logic\n");
1989 /* Setup our intr mask. */
1990 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1991 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1992 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1994 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1995 sc->sc_imask |= ATH9K_INT_GTT;
1997 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1998 sc->sc_imask |= ATH9K_INT_CST;
2000 ath_cache_conf_rate(sc, &hw->conf);
2002 sc->sc_flags &= ~SC_OP_INVALID;
2004 /* Disable BMISS interrupt when we're not associated */
2005 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2006 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
2008 ieee80211_wake_queues(sc->hw);
2010 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2011 r = ath_start_rfkill_poll(sc);
2015 mutex_unlock(&sc->mutex);
2020 static int ath9k_tx(struct ieee80211_hw *hw,
2021 struct sk_buff *skb)
2023 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2024 struct ath_softc *sc = hw->priv;
2025 struct ath_tx_control txctl;
2026 int hdrlen, padsize;
2028 memset(&txctl, 0, sizeof(struct ath_tx_control));
2031 * As a temporary workaround, assign seq# here; this will likely need
2032 * to be cleaned up to work better with Beacon transmission and virtual
2035 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2036 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2037 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2038 sc->tx.seq_no += 0x10;
2039 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2040 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2043 /* Add the padding after the header if this is not already done */
2044 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2046 padsize = hdrlen % 4;
2047 if (skb_headroom(skb) < padsize)
2049 skb_push(skb, padsize);
2050 memmove(skb->data, skb->data + padsize, hdrlen);
2053 /* Check if a tx queue is available */
2055 txctl.txq = ath_test_get_txq(sc, skb);
2059 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2061 if (ath_tx_start(sc, skb, &txctl) != 0) {
2062 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2068 dev_kfree_skb_any(skb);
2072 static void ath9k_stop(struct ieee80211_hw *hw)
2074 struct ath_softc *sc = hw->priv;
2076 if (sc->sc_flags & SC_OP_INVALID) {
2077 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2081 mutex_lock(&sc->mutex);
2083 ieee80211_stop_queues(sc->hw);
2085 /* make sure h/w will not generate any interrupt
2086 * before setting the invalid flag. */
2087 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2089 if (!(sc->sc_flags & SC_OP_INVALID)) {
2090 ath_drain_all_txq(sc, false);
2092 ath9k_hw_phy_disable(sc->sc_ah);
2094 sc->rx.rxlink = NULL;
2096 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2097 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2098 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2100 /* disable HAL and put h/w to sleep */
2101 ath9k_hw_disable(sc->sc_ah);
2102 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2104 sc->sc_flags |= SC_OP_INVALID;
2106 mutex_unlock(&sc->mutex);
2108 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2111 static int ath9k_add_interface(struct ieee80211_hw *hw,
2112 struct ieee80211_if_init_conf *conf)
2114 struct ath_softc *sc = hw->priv;
2115 struct ath_vap *avp = (void *)conf->vif->drv_priv;
2116 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2118 /* Support only vap for now */
2123 mutex_lock(&sc->mutex);
2125 switch (conf->type) {
2126 case NL80211_IFTYPE_STATION:
2127 ic_opmode = NL80211_IFTYPE_STATION;
2129 case NL80211_IFTYPE_ADHOC:
2130 ic_opmode = NL80211_IFTYPE_ADHOC;
2132 case NL80211_IFTYPE_AP:
2133 ic_opmode = NL80211_IFTYPE_AP;
2136 DPRINTF(sc, ATH_DBG_FATAL,
2137 "Interface type %d not yet supported\n", conf->type);
2141 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2143 /* Set the VAP opmode */
2144 avp->av_opmode = ic_opmode;
2147 if (ic_opmode == NL80211_IFTYPE_AP)
2148 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2150 sc->sc_vaps[0] = conf->vif;
2153 /* Set the device opmode */
2154 sc->sc_ah->ah_opmode = ic_opmode;
2157 * Enable MIB interrupts when there are hardware phy counters.
2158 * Note we only do this (at the moment) for station mode.
2160 if (ath9k_hw_phycounters(sc->sc_ah) &&
2161 ((conf->type == NL80211_IFTYPE_STATION) ||
2162 (conf->type == NL80211_IFTYPE_ADHOC)))
2163 sc->sc_imask |= ATH9K_INT_MIB;
2165 * Some hardware processes the TIM IE and fires an
2166 * interrupt when the TIM bit is set. For hardware
2167 * that does, if not overridden by configuration,
2168 * enable the TIM interrupt when operating as station.
2170 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2171 (conf->type == NL80211_IFTYPE_STATION) &&
2172 !sc->sc_config.swBeaconProcess)
2173 sc->sc_imask |= ATH9K_INT_TIM;
2175 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
2177 if (conf->type == NL80211_IFTYPE_AP) {
2178 /* TODO: is this a suitable place to start ANI for AP mode? */
2180 mod_timer(&sc->sc_ani.timer,
2181 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2184 mutex_unlock(&sc->mutex);
2189 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2190 struct ieee80211_if_init_conf *conf)
2192 struct ath_softc *sc = hw->priv;
2193 struct ath_vap *avp = (void *)conf->vif->drv_priv;
2195 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2197 mutex_lock(&sc->mutex);
2200 del_timer_sync(&sc->sc_ani.timer);
2202 /* Reclaim beacon resources */
2203 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2204 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2205 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2206 ath_beacon_return(sc, avp);
2209 sc->sc_flags &= ~SC_OP_BEACONS;
2211 sc->sc_vaps[0] = NULL;
2214 mutex_unlock(&sc->mutex);
2217 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2219 struct ath_softc *sc = hw->priv;
2220 struct ieee80211_conf *conf = &hw->conf;
2222 mutex_lock(&sc->mutex);
2224 if (changed & IEEE80211_CONF_CHANGE_PS) {
2225 if (conf->flags & IEEE80211_CONF_PS) {
2226 if ((sc->sc_imask & ATH9K_INT_TIM_TIMER) == 0) {
2227 sc->sc_imask |= ATH9K_INT_TIM_TIMER;
2228 ath9k_hw_set_interrupts(sc->sc_ah,
2231 ath9k_hw_setrxabort(sc->sc_ah, 1);
2232 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2234 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2235 ath9k_hw_setrxabort(sc->sc_ah, 0);
2236 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2237 if (sc->sc_imask & ATH9K_INT_TIM_TIMER) {
2238 sc->sc_imask &= ~ATH9K_INT_TIM_TIMER;
2239 ath9k_hw_set_interrupts(sc->sc_ah,
2245 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2246 struct ieee80211_channel *curchan = hw->conf.channel;
2247 int pos = curchan->hw_value;
2249 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2250 curchan->center_freq);
2252 /* XXX: remove me eventualy */
2253 ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]);
2255 ath_update_chainmask(sc, conf_is_ht(conf));
2257 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2258 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2259 mutex_unlock(&sc->mutex);
2264 if (changed & IEEE80211_CONF_CHANGE_POWER)
2265 sc->sc_config.txpowlimit = 2 * conf->power_level;
2267 mutex_unlock(&sc->mutex);
2272 static int ath9k_config_interface(struct ieee80211_hw *hw,
2273 struct ieee80211_vif *vif,
2274 struct ieee80211_if_conf *conf)
2276 struct ath_softc *sc = hw->priv;
2277 struct ath_hal *ah = sc->sc_ah;
2278 struct ath_vap *avp = (void *)vif->drv_priv;
2282 /* TODO: Need to decide which hw opmode to use for multi-interface
2284 if (vif->type == NL80211_IFTYPE_AP &&
2285 ah->ah_opmode != NL80211_IFTYPE_AP) {
2286 ah->ah_opmode = NL80211_IFTYPE_STATION;
2287 ath9k_hw_setopmode(ah);
2288 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2289 /* Request full reset to get hw opmode changed properly */
2290 sc->sc_flags |= SC_OP_FULL_RESET;
2293 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2294 !is_zero_ether_addr(conf->bssid)) {
2295 switch (vif->type) {
2296 case NL80211_IFTYPE_STATION:
2297 case NL80211_IFTYPE_ADHOC:
2299 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2301 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2304 /* Set aggregation protection mode parameters */
2305 sc->sc_config.ath_aggr_prot = 0;
2307 DPRINTF(sc, ATH_DBG_CONFIG,
2308 "RX filter 0x%x bssid %pM aid 0x%x\n",
2309 rfilt, sc->sc_curbssid, sc->sc_curaid);
2311 /* need to reconfigure the beacon */
2312 sc->sc_flags &= ~SC_OP_BEACONS ;
2320 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2321 (vif->type == NL80211_IFTYPE_AP)) {
2322 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2323 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2324 conf->enable_beacon)) {
2326 * Allocate and setup the beacon frame.
2328 * Stop any previous beacon DMA. This may be
2329 * necessary, for example, when an ibss merge
2330 * causes reconfiguration; we may be called
2331 * with beacon transmission active.
2333 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2335 error = ath_beacon_alloc(sc, 0);
2339 ath_beacon_sync(sc, 0);
2343 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2344 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2345 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2346 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2347 ath9k_hw_keysetmac(sc->sc_ah,
2352 /* Only legacy IBSS for now */
2353 if (vif->type == NL80211_IFTYPE_ADHOC)
2354 ath_update_chainmask(sc, 0);
2359 #define SUPPORTED_FILTERS \
2360 (FIF_PROMISC_IN_BSS | \
2364 FIF_BCN_PRBRESP_PROMISC | \
2367 /* FIXME: sc->sc_full_reset ? */
2368 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2369 unsigned int changed_flags,
2370 unsigned int *total_flags,
2372 struct dev_mc_list *mclist)
2374 struct ath_softc *sc = hw->priv;
2377 changed_flags &= SUPPORTED_FILTERS;
2378 *total_flags &= SUPPORTED_FILTERS;
2380 sc->rx.rxfilter = *total_flags;
2381 rfilt = ath_calcrxfilter(sc);
2382 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2384 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2385 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2386 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2389 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2392 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2393 struct ieee80211_vif *vif,
2394 enum sta_notify_cmd cmd,
2395 struct ieee80211_sta *sta)
2397 struct ath_softc *sc = hw->priv;
2400 case STA_NOTIFY_ADD:
2401 ath_node_attach(sc, sta);
2403 case STA_NOTIFY_REMOVE:
2404 ath_node_detach(sc, sta);
2411 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2412 const struct ieee80211_tx_queue_params *params)
2414 struct ath_softc *sc = hw->priv;
2415 struct ath9k_tx_queue_info qi;
2418 if (queue >= WME_NUM_AC)
2421 mutex_lock(&sc->mutex);
2423 qi.tqi_aifs = params->aifs;
2424 qi.tqi_cwmin = params->cw_min;
2425 qi.tqi_cwmax = params->cw_max;
2426 qi.tqi_burstTime = params->txop;
2427 qnum = ath_get_hal_qnum(queue, sc);
2429 DPRINTF(sc, ATH_DBG_CONFIG,
2430 "Configure tx [queue/halq] [%d/%d], "
2431 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2432 queue, qnum, params->aifs, params->cw_min,
2433 params->cw_max, params->txop);
2435 ret = ath_txq_update(sc, qnum, &qi);
2437 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2439 mutex_unlock(&sc->mutex);
2444 static int ath9k_set_key(struct ieee80211_hw *hw,
2445 enum set_key_cmd cmd,
2446 struct ieee80211_vif *vif,
2447 struct ieee80211_sta *sta,
2448 struct ieee80211_key_conf *key)
2450 struct ath_softc *sc = hw->priv;
2453 mutex_lock(&sc->mutex);
2454 ath9k_ps_wakeup(sc);
2455 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2459 ret = ath_key_config(sc, sta, key);
2461 key->hw_key_idx = ret;
2462 /* push IV and Michael MIC generation to stack */
2463 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2464 if (key->alg == ALG_TKIP)
2465 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2466 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2467 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2472 ath_key_delete(sc, key);
2478 ath9k_ps_restore(sc);
2479 mutex_unlock(&sc->mutex);
2484 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2485 struct ieee80211_vif *vif,
2486 struct ieee80211_bss_conf *bss_conf,
2489 struct ath_softc *sc = hw->priv;
2491 mutex_lock(&sc->mutex);
2493 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2494 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2495 bss_conf->use_short_preamble);
2496 if (bss_conf->use_short_preamble)
2497 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2499 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2502 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2503 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2504 bss_conf->use_cts_prot);
2505 if (bss_conf->use_cts_prot &&
2506 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2507 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2509 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2512 if (changed & BSS_CHANGED_ASSOC) {
2513 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2515 ath9k_bss_assoc_info(sc, vif, bss_conf);
2518 mutex_unlock(&sc->mutex);
2521 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2524 struct ath_softc *sc = hw->priv;
2526 mutex_lock(&sc->mutex);
2527 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2528 mutex_unlock(&sc->mutex);
2533 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2535 struct ath_softc *sc = hw->priv;
2537 mutex_lock(&sc->mutex);
2538 ath9k_hw_settsf64(sc->sc_ah, tsf);
2539 mutex_unlock(&sc->mutex);
2542 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2544 struct ath_softc *sc = hw->priv;
2546 mutex_lock(&sc->mutex);
2547 ath9k_hw_reset_tsf(sc->sc_ah);
2548 mutex_unlock(&sc->mutex);
2551 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2552 enum ieee80211_ampdu_mlme_action action,
2553 struct ieee80211_sta *sta,
2556 struct ath_softc *sc = hw->priv;
2560 case IEEE80211_AMPDU_RX_START:
2561 if (!(sc->sc_flags & SC_OP_RXAGGR))
2564 case IEEE80211_AMPDU_RX_STOP:
2566 case IEEE80211_AMPDU_TX_START:
2567 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2569 DPRINTF(sc, ATH_DBG_FATAL,
2570 "Unable to start TX aggregation\n");
2572 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2574 case IEEE80211_AMPDU_TX_STOP:
2575 ret = ath_tx_aggr_stop(sc, sta, tid);
2577 DPRINTF(sc, ATH_DBG_FATAL,
2578 "Unable to stop TX aggregation\n");
2580 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2582 case IEEE80211_AMPDU_TX_RESUME:
2583 ath_tx_aggr_resume(sc, sta, tid);
2586 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2592 struct ieee80211_ops ath9k_ops = {
2594 .start = ath9k_start,
2596 .add_interface = ath9k_add_interface,
2597 .remove_interface = ath9k_remove_interface,
2598 .config = ath9k_config,
2599 .config_interface = ath9k_config_interface,
2600 .configure_filter = ath9k_configure_filter,
2601 .sta_notify = ath9k_sta_notify,
2602 .conf_tx = ath9k_conf_tx,
2603 .bss_info_changed = ath9k_bss_info_changed,
2604 .set_key = ath9k_set_key,
2605 .get_tsf = ath9k_get_tsf,
2606 .set_tsf = ath9k_set_tsf,
2607 .reset_tsf = ath9k_reset_tsf,
2608 .ampdu_action = ath9k_ampdu_action,
2614 } ath_mac_bb_names[] = {
2615 { AR_SREV_VERSION_5416_PCI, "5416" },
2616 { AR_SREV_VERSION_5416_PCIE, "5418" },
2617 { AR_SREV_VERSION_9100, "9100" },
2618 { AR_SREV_VERSION_9160, "9160" },
2619 { AR_SREV_VERSION_9280, "9280" },
2620 { AR_SREV_VERSION_9285, "9285" }
2626 } ath_rf_names[] = {
2628 { AR_RAD5133_SREV_MAJOR, "5133" },
2629 { AR_RAD5122_SREV_MAJOR, "5122" },
2630 { AR_RAD2133_SREV_MAJOR, "2133" },
2631 { AR_RAD2122_SREV_MAJOR, "2122" }
2635 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2638 ath_mac_bb_name(u32 mac_bb_version)
2642 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2643 if (ath_mac_bb_names[i].version == mac_bb_version) {
2644 return ath_mac_bb_names[i].name;
2652 * Return the RF name. "????" is returned if the RF is unknown.
2655 ath_rf_name(u16 rf_version)
2659 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2660 if (ath_rf_names[i].version == rf_version) {
2661 return ath_rf_names[i].name;
2668 static int __init ath9k_init(void)
2672 /* Register rate control algorithm */
2673 error = ath_rate_control_register();
2676 "ath9k: Unable to register rate control "
2682 error = ath_pci_init();
2685 "ath9k: No PCI devices found, driver not installed.\n");
2687 goto err_rate_unregister;
2690 error = ath_ahb_init();
2701 err_rate_unregister:
2702 ath_rate_control_unregister();
2706 module_init(ath9k_init);
2708 static void __exit ath9k_exit(void)
2712 ath_rate_control_unregister();
2713 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2715 module_exit(ath9k_exit);