1 /* linux/arch/arm/plat-s3c24xx/dma.c
3 * Copyright (c) 2003-2005,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
16 #ifdef CONFIG_S3C2410_DMA_DEBUG
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/sched.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysdev.h>
26 #include <linux/slab.h>
27 #include <linux/errno.h>
28 #include <linux/delay.h>
30 #include <asm/system.h>
32 #include <asm/hardware.h>
36 #include <asm/mach/dma.h>
37 #include <asm/arch/map.h>
39 #include <asm/plat-s3c24xx/dma.h>
42 static void __iomem *dma_base;
43 static struct kmem_cache *dma_kmem;
45 static int dma_channels;
47 static struct s3c24xx_dma_selection dma_sel;
49 /* dma channel state information */
50 struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
52 /* debugging functions */
54 #define BUF_MAGIC (0xcafebabe)
56 #define dmawarn(fmt...) printk(KERN_DEBUG fmt)
58 #define dma_regaddr(chan, reg) ((chan)->regs + (reg))
61 #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
64 dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
66 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
67 writel(val, dma_regaddr(chan, reg));
71 #define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
73 /* captured register state for debug */
75 struct s3c2410_dma_regstate {
80 unsigned long dmsktrig;
83 #ifdef CONFIG_S3C2410_DMA_DEBUG
87 * simple debug routine to print the current state of the dma registers
91 dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
93 regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC);
94 regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC);
95 regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT);
96 regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON);
97 regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
101 dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
102 struct s3c2410_dma_regstate *regs)
104 printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
105 chan->number, fname, line,
106 regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
111 dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
113 struct s3c2410_dma_regstate state;
115 dmadbg_capture(chan, &state);
117 printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
118 chan->number, fname, line, chan->load_state,
119 chan->curr, chan->next, chan->end);
121 dmadbg_dumpregs(fname, line, chan, &state);
125 dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
127 struct s3c2410_dma_regstate state;
129 dmadbg_capture(chan, &state);
130 dmadbg_dumpregs(fname, line, chan, &state);
133 #define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan))
134 #define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan))
136 #define dbg_showregs(chan) do { } while(0)
137 #define dbg_showchan(chan) do { } while(0)
138 #endif /* CONFIG_S3C2410_DMA_DEBUG */
140 static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
142 /* lookup_dma_channel
144 * change the dma channel number given into a real dma channel id
147 static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
149 if (channel & DMACH_LOW_LEVEL)
150 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
152 return dma_chan_map[channel];
155 /* s3c2410_dma_stats_timeout
157 * Update DMA stats from timeout info
161 s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
166 if (val > stats->timeout_longest)
167 stats->timeout_longest = val;
168 if (val < stats->timeout_shortest)
169 stats->timeout_shortest = val;
171 stats->timeout_avg += val;
174 /* s3c2410_dma_waitforload
176 * wait for the DMA engine to load a buffer, and update the state accordingly
180 s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
182 int timeout = chan->load_timeout;
185 if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
186 printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
190 if (chan->stats != NULL)
191 chan->stats->loads++;
193 while (--timeout > 0) {
194 if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
195 took = chan->load_timeout - timeout;
197 s3c2410_dma_stats_timeout(chan->stats, took);
199 switch (chan->load_state) {
200 case S3C2410_DMALOAD_1LOADED:
201 chan->load_state = S3C2410_DMALOAD_1RUNNING;
205 printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
212 if (chan->stats != NULL) {
213 chan->stats->timeout_failed++;
221 /* s3c2410_dma_loadbuffer
223 * load a buffer, and update the channel state
227 s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
228 struct s3c2410_dma_buf *buf)
230 unsigned long reload;
232 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
233 buf, (unsigned long)buf->data, buf->size);
236 dmawarn("buffer is NULL\n");
240 /* check the state of the channel before we do anything */
242 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
243 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
246 if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
247 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
250 /* it would seem sensible if we are the last buffer to not bother
251 * with the auto-reload bit, so that the DMA engine will not try
252 * and load another transfer after this one has finished...
254 if (chan->load_state == S3C2410_DMALOAD_NONE) {
255 pr_debug("load_state is none, checking for noreload (next=%p)\n",
257 reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
259 //pr_debug("load_state is %d => autoreload\n", chan->load_state);
260 reload = S3C2410_DCON_AUTORELOAD;
263 if ((buf->data & 0xf0000000) != 0x30000000) {
264 dmawarn("dmaload: buffer is %p\n", (void *)buf->data);
267 writel(buf->data, chan->addr_reg);
269 dma_wrreg(chan, S3C2410_DMA_DCON,
270 chan->dcon | reload | (buf->size/chan->xfer_unit));
272 chan->next = buf->next;
274 /* update the state of the channel */
276 switch (chan->load_state) {
277 case S3C2410_DMALOAD_NONE:
278 chan->load_state = S3C2410_DMALOAD_1LOADED;
281 case S3C2410_DMALOAD_1RUNNING:
282 chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
286 dmawarn("dmaload: unknown state %d in loadbuffer\n",
294 /* s3c2410_dma_call_op
296 * small routine to call the op routine with the given op if it has been
301 s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
303 if (chan->op_fn != NULL) {
304 (chan->op_fn)(chan, op);
308 /* s3c2410_dma_buffdone
310 * small wrapper to check if callback routine needs to be called, and
315 s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
316 enum s3c2410_dma_buffresult result)
319 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
320 chan->callback_fn, buf, buf->id, buf->size, result);
323 if (chan->callback_fn != NULL) {
324 (chan->callback_fn)(chan, buf->id, buf->size, result);
330 * start a dma channel going
333 static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
338 pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
340 local_irq_save(flags);
342 if (chan->state == S3C2410_DMA_RUNNING) {
343 pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
344 local_irq_restore(flags);
348 chan->state = S3C2410_DMA_RUNNING;
350 /* check wether there is anything to load, and if not, see
351 * if we can find anything to load
354 if (chan->load_state == S3C2410_DMALOAD_NONE) {
355 if (chan->next == NULL) {
356 printk(KERN_ERR "dma%d: channel has nothing loaded\n",
358 chan->state = S3C2410_DMA_IDLE;
359 local_irq_restore(flags);
363 s3c2410_dma_loadbuffer(chan, chan->next);
368 /* enable the channel */
370 if (!chan->irq_enabled) {
371 enable_irq(chan->irq);
372 chan->irq_enabled = 1;
375 /* start the channel going */
377 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
378 tmp &= ~S3C2410_DMASKTRIG_STOP;
379 tmp |= S3C2410_DMASKTRIG_ON;
380 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
382 pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp);
385 /* the dma buffer loads should take care of clearing the AUTO
386 * reloading feature */
387 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
388 tmp &= ~S3C2410_DCON_NORELOAD;
389 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
392 s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
396 /* if we've only loaded one buffer onto the channel, then chec
397 * to see if we have another, and if so, try and load it so when
398 * the first buffer is finished, the new one will be loaded onto
401 if (chan->next != NULL) {
402 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
404 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
405 pr_debug("%s: buff not yet loaded, no more todo\n",
408 chan->load_state = S3C2410_DMALOAD_1RUNNING;
409 s3c2410_dma_loadbuffer(chan, chan->next);
412 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
413 s3c2410_dma_loadbuffer(chan, chan->next);
418 local_irq_restore(flags);
423 /* s3c2410_dma_canload
425 * work out if we can queue another buffer into the DMA engine
429 s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
431 if (chan->load_state == S3C2410_DMALOAD_NONE ||
432 chan->load_state == S3C2410_DMALOAD_1RUNNING)
438 /* s3c2410_dma_enqueue
440 * queue an given buffer for dma transfer.
442 * id the device driver's id information for this buffer
443 * data the physical address of the buffer data
444 * size the size of the buffer in bytes
446 * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
447 * is checked, and if set, the channel is started. If this flag isn't set,
448 * then an error will be returned.
450 * It is possible to queue more than one DMA buffer onto a channel at
451 * once, and the code will deal with the re-loading of the next buffer
455 int s3c2410_dma_enqueue(unsigned int channel, void *id,
456 dma_addr_t data, int size)
458 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
459 struct s3c2410_dma_buf *buf;
465 pr_debug("%s: id=%p, data=%08x, size=%d\n",
466 __func__, id, (unsigned int)data, size);
468 buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
470 pr_debug("%s: out of memory (%ld alloc)\n",
471 __func__, (long)sizeof(*buf));
475 //pr_debug("%s: new buffer %p\n", __func__, buf);
476 //dbg_showchan(chan);
479 buf->data = buf->ptr = data;
482 buf->magic = BUF_MAGIC;
484 local_irq_save(flags);
486 if (chan->curr == NULL) {
487 /* we've got nothing loaded... */
488 pr_debug("%s: buffer %p queued onto empty channel\n",
495 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
496 chan->number, __func__, buf);
498 if (chan->end == NULL)
499 pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
500 chan->number, __func__, chan);
502 chan->end->next = buf;
506 /* if necessary, update the next buffer field */
507 if (chan->next == NULL)
510 /* check to see if we can load a buffer */
511 if (chan->state == S3C2410_DMA_RUNNING) {
512 if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
513 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
514 printk(KERN_ERR "dma%d: loadbuffer:"
515 "timeout loading buffer\n",
518 local_irq_restore(flags);
523 while (s3c2410_dma_canload(chan) && chan->next != NULL) {
524 s3c2410_dma_loadbuffer(chan, chan->next);
526 } else if (chan->state == S3C2410_DMA_IDLE) {
527 if (chan->flags & S3C2410_DMAF_AUTOSTART) {
528 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
529 S3C2410_DMAOP_START);
533 local_irq_restore(flags);
537 EXPORT_SYMBOL(s3c2410_dma_enqueue);
540 s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
542 int magicok = (buf->magic == BUF_MAGIC);
547 kmem_cache_free(dma_kmem, buf);
549 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
553 /* s3c2410_dma_lastxfer
555 * called when the system is out of buffers, to ensure that the channel
556 * is prepared for shutdown.
560 s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
563 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
564 chan->number, chan->load_state);
567 switch (chan->load_state) {
568 case S3C2410_DMALOAD_NONE:
571 case S3C2410_DMALOAD_1LOADED:
572 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
574 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
575 chan->number, __func__);
580 case S3C2410_DMALOAD_1LOADED_1RUNNING:
581 /* I belive in this case we do not have anything to do
582 * until the next buffer comes along, and we turn off the
587 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
588 chan->number, chan->load_state);
593 /* hopefully this'll shut the damned thing up after the transfer... */
594 dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
598 #define dmadbg2(x...)
601 s3c2410_dma_irq(int irq, void *devpw)
603 struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
604 struct s3c2410_dma_buf *buf;
610 /* modify the channel state */
612 switch (chan->load_state) {
613 case S3C2410_DMALOAD_1RUNNING:
614 /* TODO - if we are running only one buffer, we probably
615 * want to reload here, and then worry about the buffer
618 chan->load_state = S3C2410_DMALOAD_NONE;
621 case S3C2410_DMALOAD_1LOADED:
622 /* iirc, we should go back to NONE loaded here, we
623 * had a buffer, and it was never verified as being
627 chan->load_state = S3C2410_DMALOAD_NONE;
630 case S3C2410_DMALOAD_1LOADED_1RUNNING:
631 /* we'll worry about checking to see if another buffer is
632 * ready after we've called back the owner. This should
633 * ensure we do not wait around too long for the DMA
634 * engine to start the next transfer
637 chan->load_state = S3C2410_DMALOAD_1LOADED;
640 case S3C2410_DMALOAD_NONE:
641 printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
646 printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
647 chan->number, chan->load_state);
652 /* update the chain to make sure that if we load any more
653 * buffers when we call the callback function, things should
656 chan->curr = buf->next;
659 if (buf->magic != BUF_MAGIC) {
660 printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
661 chan->number, __func__, buf);
665 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
668 s3c2410_dma_freebuf(buf);
672 /* only reload if the channel is still running... our buffer done
673 * routine may have altered the state by requesting the dma channel
674 * to stop or shutdown... */
676 /* todo: check that when the channel is shut-down from inside this
677 * function, we cope with unsetting reload, etc */
679 if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) {
682 switch (chan->load_state) {
683 case S3C2410_DMALOAD_1RUNNING:
684 /* don't need to do anything for this state */
687 case S3C2410_DMALOAD_NONE:
688 /* can load buffer immediately */
691 case S3C2410_DMALOAD_1LOADED:
692 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
694 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
695 chan->number, __func__);
701 case S3C2410_DMALOAD_1LOADED_1RUNNING:
705 printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
706 chan->number, chan->load_state);
710 local_irq_save(flags);
711 s3c2410_dma_loadbuffer(chan, chan->next);
712 local_irq_restore(flags);
714 s3c2410_dma_lastxfer(chan);
716 /* see if we can stop this channel.. */
717 if (chan->load_state == S3C2410_DMALOAD_NONE) {
718 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
719 chan->number, jiffies);
720 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
729 static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
731 /* s3c2410_request_dma
733 * get control of an dma channel
736 int s3c2410_dma_request(unsigned int channel,
737 struct s3c2410_dma_client *client,
740 struct s3c2410_dma_chan *chan;
744 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
745 channel, client->name, dev);
747 local_irq_save(flags);
749 chan = s3c2410_dma_map_channel(channel);
751 local_irq_restore(flags);
757 chan->client = client;
760 if (!chan->irq_claimed) {
761 pr_debug("dma%d: %s : requesting irq %d\n",
762 channel, __func__, chan->irq);
764 chan->irq_claimed = 1;
765 local_irq_restore(flags);
767 err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED,
768 client->name, (void *)chan);
770 local_irq_save(flags);
774 chan->irq_claimed = 0;
775 local_irq_restore(flags);
777 printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
778 client->name, chan->irq, chan->number);
782 chan->irq_enabled = 1;
785 local_irq_restore(flags);
789 pr_debug("%s: channel initialised, %p\n", __func__, chan);
791 return chan->number | DMACH_LOW_LEVEL;
794 EXPORT_SYMBOL(s3c2410_dma_request);
798 * release the given channel back to the system, will stop and flush
799 * any outstanding transfers, and ensure the channel is ready for the
802 * Note, although a warning is currently printed if the freeing client
803 * info is not the same as the registrant's client info, the free is still
804 * allowed to go through.
807 int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client)
809 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
815 local_irq_save(flags);
817 if (chan->client != client) {
818 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
819 channel, chan->client, client);
822 /* sort out stopping and freeing the channel */
824 if (chan->state != S3C2410_DMA_IDLE) {
825 pr_debug("%s: need to stop dma channel %p\n",
828 /* possibly flush the channel */
829 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
835 if (chan->irq_claimed)
836 free_irq(chan->irq, (void *)chan);
838 chan->irq_claimed = 0;
840 if (!(channel & DMACH_LOW_LEVEL))
841 dma_chan_map[channel] = NULL;
843 local_irq_restore(flags);
848 EXPORT_SYMBOL(s3c2410_dma_free);
850 static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
855 pr_debug("%s:\n", __func__);
859 local_irq_save(flags);
861 s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP);
863 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
864 tmp |= S3C2410_DMASKTRIG_STOP;
865 //tmp &= ~S3C2410_DMASKTRIG_ON;
866 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
869 /* should also clear interrupts, according to WinCE BSP */
870 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
871 tmp |= S3C2410_DCON_NORELOAD;
872 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
875 /* should stop do this, or should we wait for flush? */
876 chan->state = S3C2410_DMA_IDLE;
877 chan->load_state = S3C2410_DMALOAD_NONE;
879 local_irq_restore(flags);
884 static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
887 unsigned int timeout = 0x10000;
889 while (timeout-- > 0) {
890 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
892 if (!(tmp & S3C2410_DMASKTRIG_ON))
896 pr_debug("dma%d: failed to stop?\n", chan->number);
902 * stop the channel, and remove all current and pending transfers
905 static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
907 struct s3c2410_dma_buf *buf, *next;
910 pr_debug("%s: chan %p (%d)\n", __func__, chan, chan->number);
914 local_irq_save(flags);
916 if (chan->state != S3C2410_DMA_IDLE) {
917 pr_debug("%s: stopping channel...\n", __func__ );
918 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
925 chan->curr = chan->next = chan->end = NULL;
928 for ( ; buf != NULL; buf = next) {
931 pr_debug("%s: free buffer %p, next %p\n",
932 __func__, buf, buf->next);
934 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
935 s3c2410_dma_freebuf(buf);
941 s3c2410_dma_waitforstop(chan);
944 /* should also clear interrupts, according to WinCE BSP */
948 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
949 tmp |= S3C2410_DCON_NORELOAD;
950 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
956 local_irq_restore(flags);
961 static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
965 local_irq_save(flags);
969 /* if we've only loaded one buffer onto the channel, then chec
970 * to see if we have another, and if so, try and load it so when
971 * the first buffer is finished, the new one will be loaded onto
974 if (chan->next != NULL) {
975 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
977 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
978 pr_debug("%s: buff not yet loaded, no more todo\n",
981 chan->load_state = S3C2410_DMALOAD_1RUNNING;
982 s3c2410_dma_loadbuffer(chan, chan->next);
985 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
986 s3c2410_dma_loadbuffer(chan, chan->next);
991 local_irq_restore(flags);
998 s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op)
1000 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1006 case S3C2410_DMAOP_START:
1007 return s3c2410_dma_start(chan);
1009 case S3C2410_DMAOP_STOP:
1010 return s3c2410_dma_dostop(chan);
1012 case S3C2410_DMAOP_PAUSE:
1013 case S3C2410_DMAOP_RESUME:
1016 case S3C2410_DMAOP_FLUSH:
1017 return s3c2410_dma_flush(chan);
1019 case S3C2410_DMAOP_STARTED:
1020 return s3c2410_dma_started(chan);
1022 case S3C2410_DMAOP_TIMEOUT:
1027 return -ENOENT; /* unknown, don't bother */
1030 EXPORT_SYMBOL(s3c2410_dma_ctrl);
1032 /* DMA configuration for each channel
1034 * DISRCC -> source of the DMA (AHB,APB)
1035 * DISRC -> source address of the DMA
1036 * DIDSTC -> destination of the DMA (AHB,APD)
1037 * DIDST -> destination address of the DMA
1040 /* s3c2410_dma_config
1042 * xfersize: size of unit in bytes (1,2,4)
1043 * dcon: base value of the DCONx register
1046 int s3c2410_dma_config(dmach_t channel,
1050 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1052 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
1053 __func__, channel, xferunit, dcon);
1058 pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
1060 dcon |= chan->dcon & dma_sel.dcon_mask;
1062 pr_debug("%s: New dcon is %08x\n", __func__, dcon);
1066 dcon |= S3C2410_DCON_BYTE;
1070 dcon |= S3C2410_DCON_HALFWORD;
1074 dcon |= S3C2410_DCON_WORD;
1078 pr_debug("%s: bad transfer size %d\n", __func__, xferunit);
1082 dcon |= S3C2410_DCON_HWTRIG;
1083 dcon |= S3C2410_DCON_INTREQ;
1085 pr_debug("%s: dcon now %08x\n", __func__, dcon);
1088 chan->xfer_unit = xferunit;
1093 EXPORT_SYMBOL(s3c2410_dma_config);
1095 int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
1097 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1102 pr_debug("%s: chan=%p, flags=%08x\n", __func__, chan, flags);
1104 chan->flags = flags;
1109 EXPORT_SYMBOL(s3c2410_dma_setflags);
1112 /* do we need to protect the settings of the fields from
1116 int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
1118 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1123 pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
1130 EXPORT_SYMBOL(s3c2410_dma_set_opfn);
1132 int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
1134 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1139 pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
1141 chan->callback_fn = rtn;
1146 EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1148 /* s3c2410_dma_devconfig
1150 * configure the dma source/destination hardware type and address
1152 * source: S3C2410_DMASRC_HW: source is hardware
1153 * S3C2410_DMASRC_MEM: source is memory
1155 * hwcfg: the value for xxxSTCn register,
1156 * bit 0: 0=increment pointer, 1=leave pointer
1157 * bit 1: 0=source is AHB, 1=source is APB
1159 * devaddr: physical address of the source
1162 int s3c2410_dma_devconfig(int channel,
1163 enum s3c2410_dmasrc source,
1165 unsigned long devaddr)
1167 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1172 pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
1173 __func__, (int)source, hwcfg, devaddr);
1175 chan->source = source;
1176 chan->dev_addr = devaddr;
1177 chan->hw_cfg = hwcfg;
1180 case S3C2410_DMASRC_HW:
1181 /* source is hardware */
1182 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1183 __func__, devaddr, hwcfg);
1184 dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
1185 dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr);
1186 dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
1188 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
1191 case S3C2410_DMASRC_MEM:
1192 /* source is memory */
1193 pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1194 __func__, devaddr, hwcfg);
1195 dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
1196 dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr);
1197 dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
1199 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
1203 printk(KERN_ERR "dma%d: invalid source type (%d)\n",
1209 if (dma_sel.direction != NULL)
1210 (dma_sel.direction)(chan, chan->map, source);
1215 EXPORT_SYMBOL(s3c2410_dma_devconfig);
1217 /* s3c2410_dma_getposition
1219 * returns the current transfer points for the dma source and destination
1222 int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst)
1224 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1230 *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
1233 *dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
1238 EXPORT_SYMBOL(s3c2410_dma_getposition);
1240 static struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev)
1242 return container_of(dev, struct s3c2410_dma_chan, dev);
1245 /* system device class */
1249 static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state)
1251 struct s3c2410_dma_chan *cp = to_dma_chan(dev);
1253 printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
1255 if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
1256 /* the dma channel is still working, which is probably
1257 * a bad thing to do over suspend/resume. We stop the
1258 * channel and assume that the client is either going to
1259 * retry after resume, or that it is broken.
1262 printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
1265 s3c2410_dma_dostop(cp);
1271 static int s3c2410_dma_resume(struct sys_device *dev)
1273 struct s3c2410_dma_chan *cp = to_dma_chan(dev);
1274 unsigned int no = cp->number | DMACH_LOW_LEVEL;
1276 /* restore channel's hardware configuration */
1281 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
1283 s3c2410_dma_config(no, cp->xfer_unit, cp->dcon);
1284 s3c2410_dma_devconfig(no, cp->source, cp->hw_cfg, cp->dev_addr);
1286 /* re-select the dma source for this channel */
1288 if (cp->map != NULL)
1289 dma_sel.select(cp, cp->map);
1295 #define s3c2410_dma_suspend NULL
1296 #define s3c2410_dma_resume NULL
1297 #endif /* CONFIG_PM */
1299 struct sysdev_class dma_sysclass = {
1300 .name = "s3c24xx-dma",
1301 .suspend = s3c2410_dma_suspend,
1302 .resume = s3c2410_dma_resume,
1305 /* kmem cache implementation */
1307 static void s3c2410_dma_cache_ctor(struct kmem_cache *c, void *p)
1309 memset(p, 0, sizeof(struct s3c2410_dma_buf));
1312 /* initialisation code */
1314 static int __init s3c24xx_dma_sysclass_init(void)
1316 int ret = sysdev_class_register(&dma_sysclass);
1319 printk(KERN_ERR "dma sysclass registration failed\n");
1324 core_initcall(s3c24xx_dma_sysclass_init);
1326 static int __init s3c24xx_dma_sysdev_register(void)
1328 struct s3c2410_dma_chan *cp = s3c2410_chans;
1331 for (channel = 0; channel < dma_channels; cp++, channel++) {
1332 cp->dev.cls = &dma_sysclass;
1333 cp->dev.id = channel;
1334 ret = sysdev_register(&cp->dev);
1337 printk(KERN_ERR "error registering dev for dma %d\n",
1346 late_initcall(s3c24xx_dma_sysdev_register);
1348 int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
1349 unsigned int stride)
1351 struct s3c2410_dma_chan *cp;
1355 printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n");
1357 dma_channels = channels;
1359 dma_base = ioremap(S3C24XX_PA_DMA, stride * channels);
1360 if (dma_base == NULL) {
1361 printk(KERN_ERR "dma failed to remap register block\n");
1365 dma_kmem = kmem_cache_create("dma_desc",
1366 sizeof(struct s3c2410_dma_buf), 0,
1368 s3c2410_dma_cache_ctor);
1370 if (dma_kmem == NULL) {
1371 printk(KERN_ERR "dma failed to make kmem cache\n");
1376 for (channel = 0; channel < channels; channel++) {
1377 cp = &s3c2410_chans[channel];
1379 memset(cp, 0, sizeof(struct s3c2410_dma_chan));
1381 /* dma channel irqs are in order.. */
1382 cp->number = channel;
1383 cp->irq = channel + irq;
1384 cp->regs = dma_base + (channel * stride);
1386 /* point current stats somewhere */
1387 cp->stats = &cp->stats_store;
1388 cp->stats_store.timeout_shortest = LONG_MAX;
1390 /* basic channel configuration */
1392 cp->load_timeout = 1<<18;
1394 printk("DMA channel %d at %p, irq %d\n",
1395 cp->number, cp->regs, cp->irq);
1401 kmem_cache_destroy(dma_kmem);
1407 int __init s3c2410_dma_init(void)
1409 return s3c24xx_dma_init(4, IRQ_DMA0, 0x40);
1412 static inline int is_channel_valid(unsigned int channel)
1414 return (channel & DMA_CH_VALID);
1417 static struct s3c24xx_dma_order *dma_order;
1420 /* s3c2410_dma_map_channel()
1422 * turn the virtual channel number into a real, and un-used hardware
1425 * first, try the dma ordering given to us by either the relevant
1426 * dma code, or the board. Then just find the first usable free
1430 static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
1432 struct s3c24xx_dma_order_ch *ord = NULL;
1433 struct s3c24xx_dma_map *ch_map;
1434 struct s3c2410_dma_chan *dmach;
1437 if (dma_sel.map == NULL || channel > dma_sel.map_size)
1440 ch_map = dma_sel.map + channel;
1442 /* first, try the board mapping */
1445 ord = &dma_order->channels[channel];
1447 for (ch = 0; ch < dma_channels; ch++) {
1448 if (!is_channel_valid(ord->list[ch]))
1451 if (s3c2410_chans[ord->list[ch]].in_use == 0) {
1452 ch = ord->list[ch] & ~DMA_CH_VALID;
1457 if (ord->flags & DMA_CH_NEVER)
1461 /* second, search the channel map for first free */
1463 for (ch = 0; ch < dma_channels; ch++) {
1464 if (!is_channel_valid(ch_map->channels[ch]))
1467 if (s3c2410_chans[ch].in_use == 0) {
1468 printk("mapped channel %d to %d\n", channel, ch);
1473 if (ch >= dma_channels)
1476 /* update our channel mapping */
1479 dmach = &s3c2410_chans[ch];
1480 dmach->map = ch_map;
1481 dma_chan_map[channel] = dmach;
1483 /* select the channel */
1485 (dma_sel.select)(dmach, ch_map);
1490 static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
1495 int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
1497 struct s3c24xx_dma_map *nmap;
1498 size_t map_sz = sizeof(*nmap) * sel->map_size;
1501 nmap = kmalloc(map_sz, GFP_KERNEL);
1505 memcpy(nmap, sel->map, map_sz);
1506 memcpy(&dma_sel, sel, sizeof(*sel));
1510 for (ptr = 0; ptr < sel->map_size; ptr++)
1511 s3c24xx_dma_check_entry(nmap+ptr, ptr);
1516 int __init s3c24xx_dma_order_set(struct s3c24xx_dma_order *ord)
1518 struct s3c24xx_dma_order *nord = dma_order;
1521 nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
1524 printk(KERN_ERR "no memory to store dma channel order\n");
1529 memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));