git.oblomov.eu Git - linux-2.6/blob - drivers/net/ixgbe/ixgbe_82599.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34
  35 #define IXGBE_82599_MAX_TX_QUEUES 128
  36 #define IXGBE_82599_MAX_RX_QUEUES 128
  37 #define IXGBE_82599_RAR_ENTRIES   128
  38 #define IXGBE_82599_MC_TBL_SIZE   128
  39 #define IXGBE_82599_VFT_TBL_SIZE  128
  40
  41 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
  42                                       ixgbe_link_speed *speed,
  43                                       bool *autoneg);
  44 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
  45 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
  46 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
  47                                      ixgbe_link_speed speed, bool autoneg,
  48                                      bool autoneg_wait_to_complete);
  49 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
  50 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
  51                                ixgbe_link_speed *speed,
  52                                bool *link_up, bool link_up_wait_to_complete);
  53 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
  54                                      ixgbe_link_speed speed,
  55                                      bool autoneg,
  56                                      bool autoneg_wait_to_complete);
  57 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
  58                                              ixgbe_link_speed *speed,
  59                                              bool *autoneg);
  60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
  61 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
  62                                                ixgbe_link_speed speed,
  63                                                bool autoneg,
  64                                                bool autoneg_wait_to_complete);
  65 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
  66 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
  67 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
  68 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
  69                          u32 vind, bool vlan_on);
  70 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
  71 s32 ixgbe_blink_led_stop_82599(struct ixgbe_hw *hw, u32 index);
  72 s32 ixgbe_blink_led_start_82599(struct ixgbe_hw *hw, u32 index);
  73 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
  74 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
  75 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
  76 s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
  77 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
  78 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
  79 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
  80
  81 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
  82 {
  83         struct ixgbe_mac_info *mac = &hw->mac;
  84         if (hw->phy.multispeed_fiber) {
  85                 /* Set up dual speed SFP+ support */
  86                 mac->ops.setup_link =
  87                           &ixgbe_setup_mac_link_multispeed_fiber;
  88                 mac->ops.setup_link_speed =
  89                           &ixgbe_setup_mac_link_speed_multispeed_fiber;
  90         } else {
  91                 mac->ops.setup_link =
  92                           &ixgbe_setup_mac_link_82599;
  93                 mac->ops.setup_link_speed =
  94                           &ixgbe_setup_mac_link_speed_82599;
  95         }
  96 }
  97
  98 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
  99 {
 100         s32 ret_val = 0;
 101         u16 list_offset, data_offset, data_value;
 102
 103         if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
 104                 ixgbe_init_mac_link_ops_82599(hw);
 105                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 106                                                               &data_offset);
 107
 108                 if (ret_val != 0)
 109                         goto setup_sfp_out;
 110
 111                 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 112                 while (data_value != 0xffff) {
 113                         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
 114                         IXGBE_WRITE_FLUSH(hw);
 115                         hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 116                 }
 117                 /* Now restart DSP */
 118                 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102);
 119                 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d);
 120                 IXGBE_WRITE_FLUSH(hw);
 121         }
 122
 123 setup_sfp_out:
 124         return ret_val;
 125 }
 126
 127 /**
 128  *  ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
 129  *  @hw: pointer to hardware structure
 130  *
 131  *  Read PCIe configuration space, and get the MSI-X vector count from
 132  *  the capabilities table.
 133  **/
 134 u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
 135 {
 136         struct ixgbe_adapter *adapter = hw->back;
 137         u16 msix_count;
 138         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
 139                              &msix_count);
 140         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
 141
 142         /* MSI-X count is zero-based in HW, so increment to give proper value */
 143         msix_count++;
 144
 145         return msix_count;
 146 }
 147
 148 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
 149 {
 150         struct ixgbe_mac_info *mac = &hw->mac;
 151         struct ixgbe_phy_info *phy = &hw->phy;
 152         s32 ret_val;
 153
 154         /* Set the bus information prior to PHY identification */
 155         mac->ops.get_bus_info(hw);
 156
 157         /* Call PHY identify routine to get the Cu or SFI phy type */
 158         ret_val = phy->ops.identify(hw);
 159
 160         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
 161                 goto get_invariants_out;
 162
 163         ixgbe_init_mac_link_ops_82599(hw);
 164
 165         /* Setup SFP module if there is one present. */
 166         ret_val = mac->ops.setup_sfp(hw);
 167
 168         /* If copper media, overwrite with copper function pointers */
 169         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 170                 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
 171                 mac->ops.setup_link_speed =
 172                                   &ixgbe_setup_copper_link_speed_82599;
 173                 mac->ops.get_link_capabilities =
 174                                   &ixgbe_get_copper_link_capabilities_82599;
 175         }
 176
 177         /* PHY Init */
 178         switch (hw->phy.type) {
 179         case ixgbe_phy_tn:
 180                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
 181                 phy->ops.get_firmware_version =
 182                                   &ixgbe_get_phy_firmware_version_tnx;
 183                 break;
 184         default:
 185                 break;
 186         }
 187
 188         mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
 189         mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
 190         mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
 191         mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
 192         mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
 193         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
 194
 195 get_invariants_out:
 196         return ret_val;
 197 }
 198
 199 /**
 200  *  ixgbe_get_link_capabilities_82599 - Determines link capabilities
 201  *  @hw: pointer to hardware structure
 202  *  @speed: pointer to link speed
 203  *  @negotiation: true when autoneg or autotry is enabled
 204  *
 205  *  Determines the link capabilities by reading the AUTOC register.
 206  **/
 207 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
 208                                       ixgbe_link_speed *speed,
 209                                       bool *negotiation)
 210 {
 211         s32 status = 0;
 212
 213         switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
 214         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 215                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 216                 *negotiation = false;
 217                 break;
 218
 219         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 220                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 221                 *negotiation = false;
 222                 break;
 223
 224         case IXGBE_AUTOC_LMS_1G_AN:
 225                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 226                 *negotiation = true;
 227                 break;
 228
 229         case IXGBE_AUTOC_LMS_10G_SERIAL:
 230                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 231                 *negotiation = false;
 232                 break;
 233
 234         case IXGBE_AUTOC_LMS_KX4_KX_KR:
 235         case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
 236                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
 237                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
 238                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 239                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 240                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 241                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
 242                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 243                 *negotiation = true;
 244                 break;
 245
 246         case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
 247                 *speed = IXGBE_LINK_SPEED_100_FULL;
 248                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
 249                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 250                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 251                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 252                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
 253                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 254                 *negotiation = true;
 255                 break;
 256
 257         case IXGBE_AUTOC_LMS_SGMII_1G_100M:
 258                 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
 259                 *negotiation = false;
 260                 break;
 261
 262         default:
 263                 status = IXGBE_ERR_LINK_SETUP;
 264                 goto out;
 265                 break;
 266         }
 267
 268         if (hw->phy.multispeed_fiber) {
 269                 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
 270                           IXGBE_LINK_SPEED_1GB_FULL;
 271                 *negotiation = true;
 272         }
 273
 274 out:
 275         return status;
 276 }
 277
 278 /**
 279  *  ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
 280  *  @hw: pointer to hardware structure
 281  *  @speed: pointer to link speed
 282  *  @autoneg: boolean auto-negotiation value
 283  *
 284  *  Determines the link capabilities by reading the AUTOC register.
 285  **/
 286 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
 287                                                     ixgbe_link_speed *speed,
 288                                                     bool *autoneg)
 289 {
 290         s32 status = IXGBE_ERR_LINK_SETUP;
 291         u16 speed_ability;
 292
 293         *speed = 0;
 294         *autoneg = true;
 295
 296         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 297                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 298                                       &speed_ability);
 299
 300         if (status == 0) {
 301                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 302                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 303                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 304                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 305         }
 306
 307         return status;
 308 }
 309
 310 /**
 311  *  ixgbe_get_media_type_82599 - Get media type
 312  *  @hw: pointer to hardware structure
 313  *
 314  *  Returns the media type (fiber, copper, backplane)
 315  **/
 316 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
 317 {
 318         enum ixgbe_media_type media_type;
 319
 320         /* Detect if there is a copper PHY attached. */
 321         if (hw->phy.type == ixgbe_phy_cu_unknown ||
 322             hw->phy.type == ixgbe_phy_tn) {
 323                 media_type = ixgbe_media_type_copper;
 324                 goto out;
 325         }
 326
 327         switch (hw->device_id) {
 328         case IXGBE_DEV_ID_82599:
 329         case IXGBE_DEV_ID_82599_KX4:
 330                 /* Default device ID is mezzanine card KX/KX4 */
 331                 media_type = ixgbe_media_type_backplane;
 332                 break;
 333         case IXGBE_DEV_ID_82599_SFP:
 334                 media_type = ixgbe_media_type_fiber;
 335                 break;
 336         default:
 337                 media_type = ixgbe_media_type_unknown;
 338                 break;
 339         }
 340 out:
 341         return media_type;
 342 }
 343
 344 /**
 345  *  ixgbe_setup_mac_link_82599 - Setup MAC link settings
 346  *  @hw: pointer to hardware structure
 347  *
 348  *  Configures link settings based on values in the ixgbe_hw struct.
 349  *  Restarts the link.  Performs autonegotiation if needed.
 350  **/
 351 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
 352 {
 353         u32 autoc_reg;
 354         u32 links_reg;
 355         u32 i;
 356         s32 status = 0;
 357
 358         /* Restart link */
 359         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 360         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 361         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 362
 363         /* Only poll for autoneg to complete if specified to do so */
 364         if (hw->phy.autoneg_wait_to_complete) {
 365                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 366                      IXGBE_AUTOC_LMS_KX4_KX_KR ||
 367                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 368                      IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 369                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 370                      IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 371                         links_reg = 0; /* Just in case Autoneg time = 0 */
 372                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 373                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 374                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 375                                         break;
 376                                 msleep(100);
 377                         }
 378                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 379                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 380                                 hw_dbg(hw, "Autoneg did not complete.\n");
 381                         }
 382                 }
 383         }
 384
 385         /* Set up flow control */
 386         status = ixgbe_setup_fc_generic(hw, 0);
 387
 388         /* Add delay to filter out noises during initial link setup */
 389         msleep(50);
 390
 391         return status;
 392 }
 393
 394 /**
 395  *  ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
 396  *  @hw: pointer to hardware structure
 397  *
 398  *  Configures link settings based on values in the ixgbe_hw struct.
 399  *  Restarts the link for multi-speed fiber at 1G speed, if link
 400  *  fails at 10G.
 401  *  Performs autonegotiation if needed.
 402  **/
 403 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
 404 {
 405         s32 status = 0;
 406         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
 407         status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
 408                                                              link_speed,
 409                                                              true, true);
 410         return status;
 411 }
 412
 413 /**
 414  *  ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
 415  *  @hw: pointer to hardware structure
 416  *  @speed: new link speed
 417  *  @autoneg: true if autonegotiation enabled
 418  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 419  *
 420  *  Set the link speed in the AUTOC register and restarts link.
 421  **/
 422 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
 423                                                 ixgbe_link_speed speed,
 424                                                 bool autoneg,
 425                                                 bool autoneg_wait_to_complete)
 426 {
 427         s32 status = 0;
 428         ixgbe_link_speed phy_link_speed;
 429         ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 430         u32 speedcnt = 0;
 431         u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
 432         bool link_up = false;
 433         bool negotiation;
 434
 435         /* Mask off requested but non-supported speeds */
 436         hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
 437         speed &= phy_link_speed;
 438
 439         /*
 440          * Try each speed one by one, highest priority first.  We do this in
 441          * software because 10gb fiber doesn't support speed autonegotiation.
 442          */
 443         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 444                 speedcnt++;
 445                 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
 446
 447                 /* Set hardware SDP's */
 448                 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
 449                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 450
 451                 ixgbe_setup_mac_link_speed_82599(hw,
 452                                                  IXGBE_LINK_SPEED_10GB_FULL,
 453                                                  autoneg,
 454                                                  autoneg_wait_to_complete);
 455
 456                 msleep(50);
 457
 458                 /* If we have link, just jump out */
 459                 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
 460                 if (link_up)
 461                         goto out;
 462         }
 463
 464         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 465                 speedcnt++;
 466                 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
 467                         highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
 468
 469                 /* Set hardware SDP's */
 470                 esdp_reg &= ~IXGBE_ESDP_SDP5;
 471                 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
 472                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 473
 474                 ixgbe_setup_mac_link_speed_82599(
 475                         hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
 476                         autoneg_wait_to_complete);
 477
 478                 msleep(50);
 479
 480                 /* If we have link, just jump out */
 481                 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
 482                 if (link_up)
 483                         goto out;
 484         }
 485
 486         /*
 487          * We didn't get link.  Configure back to the highest speed we tried,
 488          * (if there was more than one).  We call ourselves back with just the
 489          * single highest speed that the user requested.
 490          */
 491         if (speedcnt > 1)
 492                 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
 493                                                      highest_link_speed,
 494                                                      autoneg,
 495                                                      autoneg_wait_to_complete);
 496
 497 out:
 498         return status;
 499 }
 500
 501 /**
 502  *  ixgbe_check_mac_link_82599 - Determine link and speed status
 503  *  @hw: pointer to hardware structure
 504  *  @speed: pointer to link speed
 505  *  @link_up: true when link is up
 506  *  @link_up_wait_to_complete: bool used to wait for link up or not
 507  *
 508  *  Reads the links register to determine if link is up and the current speed
 509  **/
 510 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 511                                bool *link_up, bool link_up_wait_to_complete)
 512 {
 513         u32 links_reg;
 514         u32 i;
 515
 516         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 517         if (link_up_wait_to_complete) {
 518                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 519                         if (links_reg & IXGBE_LINKS_UP) {
 520                                 *link_up = true;
 521                                 break;
 522                         } else {
 523                                 *link_up = false;
 524                         }
 525                         msleep(100);
 526                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 527                 }
 528         } else {
 529                 if (links_reg & IXGBE_LINKS_UP)
 530                         *link_up = true;
 531                 else
 532                         *link_up = false;
 533         }
 534
 535         if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
 536             IXGBE_LINKS_SPEED_10G_82599)
 537                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 538         else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
 539                  IXGBE_LINKS_SPEED_1G_82599)
 540                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 541         else
 542                 *speed = IXGBE_LINK_SPEED_100_FULL;
 543
 544
 545         return 0;
 546 }
 547
 548 /**
 549  *  ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
 550  *  @hw: pointer to hardware structure
 551  *  @speed: new link speed
 552  *  @autoneg: true if autonegotiation enabled
 553  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 554  *
 555  *  Set the link speed in the AUTOC register and restarts link.
 556  **/
 557 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
 558                                      ixgbe_link_speed speed, bool autoneg,
 559                                      bool autoneg_wait_to_complete)
 560 {
 561         s32 status = 0;
 562         u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 563         u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 564         u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
 565         u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
 566         u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
 567         u32 links_reg;
 568         u32 i;
 569         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 570
 571         /* Check to see if speed passed in is supported. */
 572         hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
 573         speed &= link_capabilities;
 574
 575         if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
 576                 status = IXGBE_ERR_LINK_SETUP;
 577         } else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
 578                    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 579                    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 580                 /* Set KX4/KX/KR support according to speed requested */
 581                 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
 582                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 583                         if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 584                                 autoc |= IXGBE_AUTOC_KX4_SUPP;
 585                         if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
 586                                 autoc |= IXGBE_AUTOC_KR_SUPP;
 587                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 588                         autoc |= IXGBE_AUTOC_KX_SUPP;
 589         } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
 590                    (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
 591                     link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
 592                 /* Switch from 1G SFI to 10G SFI if requested */
 593                 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
 594                     (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
 595                         autoc &= ~IXGBE_AUTOC_LMS_MASK;
 596                         autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
 597                 }
 598         } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
 599                    (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
 600                 /* Switch from 10G SFI to 1G SFI if requested */
 601                 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
 602                     (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
 603                         autoc &= ~IXGBE_AUTOC_LMS_MASK;
 604                         if (autoneg)
 605                                 autoc |= IXGBE_AUTOC_LMS_1G_AN;
 606                         else
 607                                 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
 608                 }
 609         }
 610
 611         if (status == 0) {
 612                 /* Restart link */
 613                 autoc |= IXGBE_AUTOC_AN_RESTART;
 614                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
 615
 616                 /* Only poll for autoneg to complete if specified to do so */
 617                 if (autoneg_wait_to_complete) {
 618                         if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
 619                             link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 620                             link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 621                                 links_reg = 0; /*Just in case Autoneg time=0*/
 622                                 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 623                                         links_reg =
 624                                                IXGBE_READ_REG(hw, IXGBE_LINKS);
 625                                         if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 626                                                 break;
 627                                         msleep(100);
 628                                 }
 629                                 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 630                                         status =
 631                                                 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 632                                         hw_dbg(hw, "Autoneg did not "
 633                                                "complete.\n");
 634                                 }
 635                         }
 636                 }
 637
 638                 /* Set up flow control */
 639                 status = ixgbe_setup_fc_generic(hw, 0);
 640
 641                 /* Add delay to filter out noises during initial link setup */
 642                 msleep(50);
 643         }
 644
 645         return status;
 646 }
 647
 648 /**
 649  *  ixgbe_setup_copper_link_82599 - Setup copper link settings
 650  *  @hw: pointer to hardware structure
 651  *
 652  *  Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
 653  **/
 654 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
 655 {
 656         s32 status;
 657
 658         /* Restart autonegotiation on PHY */
 659         status = hw->phy.ops.setup_link(hw);
 660
 661         /* Set up MAC */
 662         ixgbe_setup_mac_link_82599(hw);
 663
 664         return status;
 665 }
 666
 667 /**
 668  *  ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
 669  *  @hw: pointer to hardware structure
 670  *  @speed: new link speed
 671  *  @autoneg: true if autonegotiation enabled
 672  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 673  *
 674  *  Restarts link on PHY and MAC based on settings passed in.
 675  **/
 676 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
 677                                                ixgbe_link_speed speed,
 678                                                bool autoneg,
 679                                                bool autoneg_wait_to_complete)
 680 {
 681         s32 status;
 682
 683         /* Setup the PHY according to input speed */
 684         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 685                                               autoneg_wait_to_complete);
 686         /* Set up MAC */
 687         ixgbe_setup_mac_link_82599(hw);
 688
 689         return status;
 690 }
 691
 692 /**
 693  *  ixgbe_reset_hw_82599 - Perform hardware reset
 694  *  @hw: pointer to hardware structure
 695  *
 696  *  Resets the hardware by resetting the transmit and receive units, masks
 697  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 698  *  reset.
 699  **/
 700 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
 701 {
 702         s32 status = 0;
 703         u32 ctrl, ctrl_ext;
 704         u32 i;
 705         u32 autoc;
 706         u32 autoc2;
 707
 708         /* Call adapter stop to disable tx/rx and clear interrupts */
 709         hw->mac.ops.stop_adapter(hw);
 710
 711         /* Reset PHY */
 712         hw->phy.ops.reset(hw);
 713
 714         /*
 715          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 716          * access and verify no pending requests before reset
 717          */
 718         if (ixgbe_disable_pcie_master(hw) != 0) {
 719                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 720                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 721         }
 722
 723         /*
 724          * Issue global reset to the MAC.  This needs to be a SW reset.
 725          * If link reset is used, it might reset the MAC when mng is using it
 726          */
 727         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 728         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
 729         IXGBE_WRITE_FLUSH(hw);
 730
 731         /* Poll for reset bit to self-clear indicating reset is complete */
 732         for (i = 0; i < 10; i++) {
 733                 udelay(1);
 734                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 735                 if (!(ctrl & IXGBE_CTRL_RST))
 736                         break;
 737         }
 738         if (ctrl & IXGBE_CTRL_RST) {
 739                 status = IXGBE_ERR_RESET_FAILED;
 740                 hw_dbg(hw, "Reset polling failed to complete.\n");
 741         }
 742         /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
 743         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 744         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 745         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 746
 747         msleep(50);
 748
 749
 750
 751         /*
 752          * Store the original AUTOC/AUTOC2 values if they have not been
 753          * stored off yet.  Otherwise restore the stored original
 754          * values since the reset operation sets back to defaults.
 755          */
 756         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 757         autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 758         if (hw->mac.orig_link_settings_stored == false) {
 759                 hw->mac.orig_autoc = autoc;
 760                 hw->mac.orig_autoc2 = autoc2;
 761                 hw->mac.orig_link_settings_stored = true;
 762         } else  {
 763                 if (autoc != hw->mac.orig_autoc)
 764                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
 765                                         IXGBE_AUTOC_AN_RESTART));
 766
 767                 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
 768                     (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
 769                         autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
 770                         autoc2 |= (hw->mac.orig_autoc2 &
 771                                    IXGBE_AUTOC2_UPPER_MASK);
 772                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
 773                 }
 774         }
 775
 776         /* Store the permanent mac address */
 777         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 778
 779         return status;
 780 }
 781
 782 /**
 783  *  ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
 784  *  @hw: pointer to hardware struct
 785  *  @rar: receive address register index to disassociate
 786  *  @vmdq: VMDq pool index to remove from the rar
 787  **/
 788 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 789 {
 790         u32 mpsar_lo, mpsar_hi;
 791         u32 rar_entries = hw->mac.num_rar_entries;
 792
 793         if (rar < rar_entries) {
 794                 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
 795                 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
 796
 797                 if (!mpsar_lo && !mpsar_hi)
 798                         goto done;
 799
 800                 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
 801                         if (mpsar_lo) {
 802                                 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
 803                                 mpsar_lo = 0;
 804                         }
 805                         if (mpsar_hi) {
 806                                 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
 807                                 mpsar_hi = 0;
 808                         }
 809                 } else if (vmdq < 32) {
 810                         mpsar_lo &= ~(1 << vmdq);
 811                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
 812                 } else {
 813                         mpsar_hi &= ~(1 << (vmdq - 32));
 814                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
 815                 }
 816
 817                 /* was that the last pool using this rar? */
 818                 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
 819                         hw->mac.ops.clear_rar(hw, rar);
 820         } else {
 821                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 822         }
 823
 824 done:
 825         return 0;
 826 }
 827
 828 /**
 829  *  ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
 830  *  @hw: pointer to hardware struct
 831  *  @rar: receive address register index to associate with a VMDq index
 832  *  @vmdq: VMDq pool index
 833  **/
 834 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 835 {
 836         u32 mpsar;
 837         u32 rar_entries = hw->mac.num_rar_entries;
 838
 839         if (rar < rar_entries) {
 840                 if (vmdq < 32) {
 841                         mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
 842                         mpsar |= 1 << vmdq;
 843                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
 844                 } else {
 845                         mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
 846                         mpsar |= 1 << (vmdq - 32);
 847                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
 848                 }
 849         } else {
 850                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 851         }
 852         return 0;
 853 }
 854
 855 /**
 856  *  ixgbe_set_vfta_82599 - Set VLAN filter table
 857  *  @hw: pointer to hardware structure
 858  *  @vlan: VLAN id to write to VLAN filter
 859  *  @vind: VMDq output index that maps queue to VLAN id in VFVFB
 860  *  @vlan_on: boolean flag to turn on/off VLAN in VFVF
 861  *
 862  *  Turn on/off specified VLAN in the VLAN filter table.
 863  **/
 864 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
 865                          bool vlan_on)
 866 {
 867         u32 regindex;
 868         u32 bitindex;
 869         u32 bits;
 870         u32 first_empty_slot;
 871
 872         if (vlan > 4095)
 873                 return IXGBE_ERR_PARAM;
 874
 875         /*
 876          * this is a 2 part operation - first the VFTA, then the
 877          * VLVF and VLVFB if vind is set
 878          */
 879
 880         /* Part 1
 881          * The VFTA is a bitstring made up of 128 32-bit registers
 882          * that enable the particular VLAN id, much like the MTA:
 883          *    bits[11-5]: which register
 884          *    bits[4-0]:  which bit in the register
 885          */
 886         regindex = (vlan >> 5) & 0x7F;
 887         bitindex = vlan & 0x1F;
 888         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
 889         if (vlan_on)
 890                 bits |= (1 << bitindex);
 891         else
 892                 bits &= ~(1 << bitindex);
 893         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
 894
 895
 896         /* Part 2
 897          * If the vind is set
 898          *   Either vlan_on
 899          *     make sure the vlan is in VLVF
 900          *     set the vind bit in the matching VLVFB
 901          *   Or !vlan_on
 902          *     clear the pool bit and possibly the vind
 903          */
 904         if (vind) {
 905                 /* find the vlanid or the first empty slot */
 906                 first_empty_slot = 0;
 907
 908                 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
 909                         bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
 910                         if (!bits && !first_empty_slot)
 911                                 first_empty_slot = regindex;
 912                         else if ((bits & 0x0FFF) == vlan)
 913                                 break;
 914                 }
 915
 916                 if (regindex >= IXGBE_VLVF_ENTRIES) {
 917                         if (first_empty_slot)
 918                                 regindex = first_empty_slot;
 919                         else {
 920                                 hw_dbg(hw, "No space in VLVF.\n");
 921                                 goto out;
 922                         }
 923                 }
 924
 925                 if (vlan_on) {
 926                         /* set the pool bit */
 927                         if (vind < 32) {
 928                                 bits = IXGBE_READ_REG(hw,
 929                                                     IXGBE_VLVFB(regindex * 2));
 930                                 bits |= (1 << vind);
 931                                 IXGBE_WRITE_REG(hw,
 932                                               IXGBE_VLVFB(regindex * 2), bits);
 933                         } else {
 934                                 bits = IXGBE_READ_REG(hw,
 935                                               IXGBE_VLVFB((regindex * 2) + 1));
 936                                 bits |= (1 << vind);
 937                                 IXGBE_WRITE_REG(hw,
 938                                         IXGBE_VLVFB((regindex * 2) + 1), bits);
 939                         }
 940                 } else {
 941                         /* clear the pool bit */
 942                         if (vind < 32) {
 943                                 bits = IXGBE_READ_REG(hw,
 944                                      IXGBE_VLVFB(regindex * 2));
 945                         bits &= ~(1 << vind);
 946                                 IXGBE_WRITE_REG(hw,
 947                                               IXGBE_VLVFB(regindex * 2), bits);
 948                                 bits |= IXGBE_READ_REG(hw,
 949                                               IXGBE_VLVFB((regindex * 2) + 1));
 950                         } else {
 951                                 bits = IXGBE_READ_REG(hw,
 952                                               IXGBE_VLVFB((regindex * 2) + 1));
 953                                 bits &= ~(1 << vind);
 954                                 IXGBE_WRITE_REG(hw,
 955                                         IXGBE_VLVFB((regindex * 2) + 1), bits);
 956                                 bits |= IXGBE_READ_REG(hw,
 957                                                     IXGBE_VLVFB(regindex * 2));
 958                         }
 959                 }
 960
 961                 if (bits)
 962                         IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
 963                                         (IXGBE_VLVF_VIEN | vlan));
 964                 else
 965                         IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
 966         }
 967
 968 out:
 969         return 0;
 970 }
 971
 972 /**
 973  *  ixgbe_clear_vfta_82599 - Clear VLAN filter table
 974  *  @hw: pointer to hardware structure
 975  *
 976  *  Clears the VLAN filer table, and the VMDq index associated with the filter
 977  **/
 978 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
 979 {
 980         u32 offset;
 981
 982         for (offset = 0; offset < hw->mac.vft_size; offset++)
 983                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
 984
 985         for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
 986                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
 987                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
 988                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
 989         }
 990
 991         return 0;
 992 }
 993
 994 /**
 995  *  ixgbe_blink_led_start_82599 - Blink LED based on index.
 996  *  @hw: pointer to hardware structure
 997  *  @index: led number to blink
 998  **/
 999 s32 ixgbe_blink_led_start_82599(struct ixgbe_hw *hw, u32 index)
1000 {
1001         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1002
1003         led_reg &= ~IXGBE_LED_MODE_MASK(index);
1004         led_reg |= IXGBE_LED_BLINK(index);
1005         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1006         IXGBE_WRITE_FLUSH(hw);
1007
1008         return 0;
1009 }
1010
1011 /**
1012  *  ixgbe_blink_led_stop_82599 - Stop blinking LED based on index.
1013  *  @hw: pointer to hardware structure
1014  *  @index: led number to stop blinking
1015  **/
1016 s32 ixgbe_blink_led_stop_82599(struct ixgbe_hw *hw, u32 index)
1017 {
1018         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1019
1020         led_reg &= ~IXGBE_LED_MODE_MASK(index);
1021         led_reg &= ~IXGBE_LED_BLINK(index);
1022         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1023         IXGBE_WRITE_FLUSH(hw);
1024
1025         return 0;
1026 }
1027
1028 /**
1029  *  ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1030  *  @hw: pointer to hardware structure
1031  **/
1032 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1033 {
1034         int i;
1035         hw_dbg(hw, " Clearing UTA\n");
1036
1037         for (i = 0; i < 128; i++)
1038                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1039
1040         return 0;
1041 }
1042
1043 /**
1044  *  ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1045  *  @hw: pointer to hardware structure
1046  *  @reg: analog register to read
1047  *  @val: read value
1048  *
1049  *  Performs read operation to Omer analog register specified.
1050  **/
1051 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1052 {
1053         u32  core_ctl;
1054
1055         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1056                         (reg << 8));
1057         IXGBE_WRITE_FLUSH(hw);
1058         udelay(10);
1059         core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1060         *val = (u8)core_ctl;
1061
1062         return 0;
1063 }
1064
1065 /**
1066  *  ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1067  *  @hw: pointer to hardware structure
1068  *  @reg: atlas register to write
1069  *  @val: value to write
1070  *
1071  *  Performs write operation to Omer analog register specified.
1072  **/
1073 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1074 {
1075         u32  core_ctl;
1076
1077         core_ctl = (reg << 8) | val;
1078         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1079         IXGBE_WRITE_FLUSH(hw);
1080         udelay(10);
1081
1082         return 0;
1083 }
1084
1085 /**
1086  *  ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1087  *  @hw: pointer to hardware structure
1088  *
1089  *  Starts the hardware using the generic start_hw function.
1090  *  Then performs device-specific:
1091  *  Clears the rate limiter registers.
1092  **/
1093 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1094 {
1095         u32 q_num;
1096
1097         ixgbe_start_hw_generic(hw);
1098
1099         /* Clear the rate limiters */
1100         for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1101                 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1102                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1103         }
1104         IXGBE_WRITE_FLUSH(hw);
1105
1106         return 0;
1107 }
1108
1109 /**
1110  *  ixgbe_identify_phy_82599 - Get physical layer module
1111  *  @hw: pointer to hardware structure
1112  *
1113  *  Determines the physical layer module found on the current adapter.
1114  **/
1115 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1116 {
1117         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1118         status = ixgbe_identify_phy_generic(hw);
1119         if (status != 0)
1120                 status = ixgbe_identify_sfp_module_generic(hw);
1121         return status;
1122 }
1123
1124 /**
1125  *  ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1126  *  @hw: pointer to hardware structure
1127  *
1128  *  Determines physical layer capabilities of the current configuration.
1129  **/
1130 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1131 {
1132         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1133
1134         switch (hw->device_id) {
1135         case IXGBE_DEV_ID_82599:
1136         case IXGBE_DEV_ID_82599_KX4:
1137                 /* Default device ID is mezzanine card KX/KX4 */
1138                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1139                                   IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1140                 break;
1141         case IXGBE_DEV_ID_82599_SFP:
1142                 hw->phy.ops.identify_sfp(hw);
1143
1144                 switch (hw->phy.sfp_type) {
1145                 case ixgbe_sfp_type_da_cu:
1146                         physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1147                         break;
1148                 case ixgbe_sfp_type_sr:
1149                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1150                         break;
1151                 case ixgbe_sfp_type_lr:
1152                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1153                         break;
1154                 default:
1155                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1156                         break;
1157                 }
1158                 break;
1159         default:
1160                 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1161                 break;
1162         }
1163
1164         return physical_layer;
1165 }
1166
1167 /**
1168  *  ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1169  *  @hw: pointer to hardware structure
1170  *  @regval: register value to write to RXCTRL
1171  *
1172  *  Enables the Rx DMA unit for 82599
1173  **/
1174 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1175 {
1176 #define IXGBE_MAX_SECRX_POLL 30
1177         int i;
1178         int secrxreg;
1179
1180         /*
1181          * Workaround for 82599 silicon errata when enabling the Rx datapath.
1182          * If traffic is incoming before we enable the Rx unit, it could hang
1183          * the Rx DMA unit.  Therefore, make sure the security engine is
1184          * completely disabled prior to enabling the Rx unit.
1185          */
1186         secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1187         secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1188         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1189         for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1190                 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1191                 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1192                         break;
1193                 else
1194                         udelay(10);
1195         }
1196
1197         /* For informational purposes only */
1198         if (i >= IXGBE_MAX_SECRX_POLL)
1199                 hw_dbg(hw, "Rx unit being enabled before security "
1200                        "path fully disabled.  Continuing with init.\n");
1201
1202         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1203         secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1204         secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1205         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1206         IXGBE_WRITE_FLUSH(hw);
1207
1208         return 0;
1209 }
1210
1211 static struct ixgbe_mac_operations mac_ops_82599 = {
1212         .init_hw                = &ixgbe_init_hw_generic,
1213         .reset_hw               = &ixgbe_reset_hw_82599,
1214         .start_hw               = &ixgbe_start_hw_82599,
1215         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1216         .get_media_type         = &ixgbe_get_media_type_82599,
1217         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1218         .enable_rx_dma          = &ixgbe_enable_rx_dma_82599,
1219         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1220         .stop_adapter           = &ixgbe_stop_adapter_generic,
1221         .get_bus_info           = &ixgbe_get_bus_info_generic,
1222         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
1223         .read_analog_reg8       = &ixgbe_read_analog_reg8_82599,
1224         .write_analog_reg8      = &ixgbe_write_analog_reg8_82599,
1225         .setup_link             = &ixgbe_setup_mac_link_82599,
1226         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82599,
1227         .check_link             = &ixgbe_check_mac_link_82599,
1228         .get_link_capabilities  = &ixgbe_get_link_capabilities_82599,
1229         .led_on                 = &ixgbe_led_on_generic,
1230         .led_off                = &ixgbe_led_off_generic,
1231         .blink_led_start        = &ixgbe_blink_led_start_82599,
1232         .blink_led_stop         = &ixgbe_blink_led_stop_82599,
1233         .set_rar                = &ixgbe_set_rar_generic,
1234         .clear_rar              = &ixgbe_clear_rar_generic,
1235         .set_vmdq               = &ixgbe_set_vmdq_82599,
1236         .clear_vmdq             = &ixgbe_clear_vmdq_82599,
1237         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1238         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1239         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1240         .enable_mc              = &ixgbe_enable_mc_generic,
1241         .disable_mc             = &ixgbe_disable_mc_generic,
1242         .clear_vfta             = &ixgbe_clear_vfta_82599,
1243         .set_vfta               = &ixgbe_set_vfta_82599,
1244         .setup_fc               = &ixgbe_setup_fc_generic,
1245         .init_uta_tables        = &ixgbe_init_uta_tables_82599,
1246         .setup_sfp              = &ixgbe_setup_sfp_modules_82599,
1247 };
1248
1249 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1250         .init_params            = &ixgbe_init_eeprom_params_generic,
1251         .read                   = &ixgbe_read_eeprom_generic,
1252         .write                  = &ixgbe_write_eeprom_generic,
1253         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1254         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1255 };
1256
1257 static struct ixgbe_phy_operations phy_ops_82599 = {
1258         .identify               = &ixgbe_identify_phy_82599,
1259         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1260         .reset                  = &ixgbe_reset_phy_generic,
1261         .read_reg               = &ixgbe_read_phy_reg_generic,
1262         .write_reg              = &ixgbe_write_phy_reg_generic,
1263         .setup_link             = &ixgbe_setup_phy_link_generic,
1264         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1265         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic,
1266         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic,
1267         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic,
1268         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic,
1269 };
1270
1271 struct ixgbe_info ixgbe_82599_info = {
1272         .mac                    = ixgbe_mac_82599EB,
1273         .get_invariants         = &ixgbe_get_invariants_82599,
1274         .mac_ops                = &mac_ops_82599,
1275         .eeprom_ops             = &eeprom_ops_82599,
1276         .phy_ops                = &phy_ops_82599,
1277 };