2 * Driver for the Conexant CX23885 PCIe bridge
4 * Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/kmod.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <asm/div64.h>
35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
37 MODULE_LICENSE("GPL");
39 static unsigned int debug = 0;
40 module_param(debug,int,0644);
41 MODULE_PARM_DESC(debug,"enable debug messages");
43 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
44 module_param_array(card, int, NULL, 0444);
45 MODULE_PARM_DESC(card,"card type");
47 #define dprintk(level,fmt, arg...) if (debug >= level) \
48 printk(KERN_DEBUG "%s/0: " fmt, dev->name , ## arg)
50 static unsigned int cx23885_devcount;
52 static DEFINE_MUTEX(devlist);
53 static LIST_HEAD(cx23885_devlist);
55 #define NO_SYNC_LINE (-1U)
59 * 1 line = 16 bytes of CDT
61 * cdt size = 16 * linesize
66 * 0x00000000 0x00008fff FIFO clusters
67 * 0x00010000 0x000104af Channel Management Data Structures
68 * 0x000104b0 0x000104ff Free
69 * 0x00010500 0x000108bf 15 channels * iqsize
70 * 0x000108c0 0x000108ff Free
71 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
72 * 15 channels * (iqsize + (maxlines * linesize))
73 * 0x00010ea0 0x00010xxx Free
76 static struct sram_channel cx23885_sram_channels[] = {
79 .cmds_start = 0x10000,
80 .ctrl_start = 0x10500,
84 .ptr1_reg = DMA1_PTR1,
85 .ptr2_reg = DMA1_PTR2,
86 .cnt1_reg = DMA1_CNT1,
87 .cnt2_reg = DMA1_CNT2,
97 .ptr1_reg = DMA2_PTR1,
98 .ptr2_reg = DMA2_PTR2,
99 .cnt1_reg = DMA2_CNT1,
100 .cnt2_reg = DMA2_CNT2,
104 .cmds_start = 0x100A0,
105 .ctrl_start = 0x10780,
107 .fifo_start = 0x5000,
109 .ptr1_reg = DMA3_PTR1,
110 .ptr2_reg = DMA3_PTR2,
111 .cnt1_reg = DMA3_CNT1,
112 .cnt2_reg = DMA3_CNT2,
121 .ptr1_reg = DMA4_PTR1,
122 .ptr2_reg = DMA4_PTR2,
123 .cnt1_reg = DMA4_CNT1,
124 .cnt2_reg = DMA4_CNT2,
133 .ptr1_reg = DMA5_PTR1,
134 .ptr2_reg = DMA5_PTR2,
135 .cnt1_reg = DMA5_CNT1,
136 .cnt2_reg = DMA5_CNT2,
140 .cmds_start = 0x10140,
141 .ctrl_start = 0x10680,
143 .fifo_start = 0x6000,
145 .ptr1_reg = DMA5_PTR1,
146 .ptr2_reg = DMA5_PTR2,
147 .cnt1_reg = DMA5_CNT1,
148 .cnt2_reg = DMA5_CNT2,
157 .ptr1_reg = DMA6_PTR1,
158 .ptr2_reg = DMA6_PTR2,
159 .cnt1_reg = DMA6_CNT1,
160 .cnt2_reg = DMA6_CNT2,
169 .ptr1_reg = DMA7_PTR1,
170 .ptr2_reg = DMA7_PTR2,
171 .cnt1_reg = DMA7_CNT1,
172 .cnt2_reg = DMA7_CNT2,
181 .ptr1_reg = DMA8_PTR1,
182 .ptr2_reg = DMA8_PTR2,
183 .cnt1_reg = DMA8_CNT1,
184 .cnt2_reg = DMA8_CNT2,
188 /* FIXME, these allocations will change when
189 * analog arrives. The be reviewed.
190 * CX23887 Assumptions
191 * 1 line = 16 bytes of CDT
193 * cdt size = 16 * linesize
198 * 0x00000000 0x00008fff FIFO clusters
199 * 0x00010000 0x000104af Channel Management Data Structures
200 * 0x000104b0 0x000104ff Free
201 * 0x00010500 0x000108bf 15 channels * iqsize
202 * 0x000108c0 0x000108ff Free
203 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
204 * 15 channels * (iqsize + (maxlines * linesize))
205 * 0x00010ea0 0x00010xxx Free
208 static struct sram_channel cx23887_sram_channels[] = {
216 .ptr1_reg = DMA1_PTR1,
217 .ptr2_reg = DMA1_PTR2,
218 .cnt1_reg = DMA1_CNT1,
219 .cnt2_reg = DMA1_CNT2,
228 .ptr1_reg = DMA2_PTR1,
229 .ptr2_reg = DMA2_PTR2,
230 .cnt1_reg = DMA2_CNT1,
231 .cnt2_reg = DMA2_CNT2,
240 .ptr1_reg = DMA3_PTR1,
241 .ptr2_reg = DMA3_PTR2,
242 .cnt1_reg = DMA3_CNT1,
243 .cnt2_reg = DMA3_CNT2,
252 .ptr1_reg = DMA4_PTR1,
253 .ptr2_reg = DMA4_PTR2,
254 .cnt1_reg = DMA4_CNT1,
255 .cnt2_reg = DMA4_CNT2,
264 .ptr1_reg = DMA5_PTR1,
265 .ptr2_reg = DMA5_PTR2,
266 .cnt1_reg = DMA5_CNT1,
267 .cnt2_reg = DMA5_CNT2,
271 .cmds_start = 0x10140,
272 .ctrl_start = 0x10680,
274 .fifo_start = 0x6000,
276 .ptr1_reg = DMA5_PTR1,
277 .ptr2_reg = DMA5_PTR2,
278 .cnt1_reg = DMA5_CNT1,
279 .cnt2_reg = DMA5_CNT2,
288 .ptr1_reg = DMA6_PTR1,
289 .ptr2_reg = DMA6_PTR2,
290 .cnt1_reg = DMA6_CNT1,
291 .cnt2_reg = DMA6_CNT2,
300 .ptr1_reg = DMA7_PTR1,
301 .ptr2_reg = DMA7_PTR2,
302 .cnt1_reg = DMA7_CNT1,
303 .cnt2_reg = DMA7_CNT2,
312 .ptr1_reg = DMA8_PTR1,
313 .ptr2_reg = DMA8_PTR2,
314 .cnt1_reg = DMA8_CNT1,
315 .cnt2_reg = DMA8_CNT2,
319 static int cx23885_risc_decode(u32 risc)
321 static char *instr[16] = {
322 [ RISC_SYNC >> 28 ] = "sync",
323 [ RISC_WRITE >> 28 ] = "write",
324 [ RISC_WRITEC >> 28 ] = "writec",
325 [ RISC_READ >> 28 ] = "read",
326 [ RISC_READC >> 28 ] = "readc",
327 [ RISC_JUMP >> 28 ] = "jump",
328 [ RISC_SKIP >> 28 ] = "skip",
329 [ RISC_WRITERM >> 28 ] = "writerm",
330 [ RISC_WRITECM >> 28 ] = "writecm",
331 [ RISC_WRITECR >> 28 ] = "writecr",
333 static int incr[16] = {
334 [ RISC_WRITE >> 28 ] = 3,
335 [ RISC_JUMP >> 28 ] = 3,
336 [ RISC_SKIP >> 28 ] = 1,
337 [ RISC_SYNC >> 28 ] = 1,
338 [ RISC_WRITERM >> 28 ] = 3,
339 [ RISC_WRITECM >> 28 ] = 3,
340 [ RISC_WRITECR >> 28 ] = 4,
342 static char *bits[] = {
343 "12", "13", "14", "resync",
344 "cnt0", "cnt1", "18", "19",
345 "20", "21", "22", "23",
346 "irq1", "irq2", "eol", "sol",
350 printk("0x%08x [ %s", risc,
351 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
352 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
353 if (risc & (1 << (i + 12)))
354 printk(" %s", bits[i]);
355 printk(" count=%d ]\n", risc & 0xfff);
356 return incr[risc >> 28] ? incr[risc >> 28] : 1;
359 static void cx23885_wakeup(struct cx23885_tsport *port,
360 struct cx23885_dmaqueue *q, u32 count)
362 struct cx23885_dev *dev = port->dev;
363 struct cx23885_buffer *buf;
366 for (bc = 0;; bc++) {
367 if (list_empty(&q->active))
369 buf = list_entry(q->active.next,
370 struct cx23885_buffer, vb.queue);
372 /* count comes from the hw and is is 16bit wide --
373 * this trick handles wrap-arounds correctly for
374 * up to 32767 buffers in flight... */
375 if ((s16) (count - buf->count) < 0)
378 do_gettimeofday(&buf->vb.ts);
379 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
381 buf->vb.state = STATE_DONE;
382 list_del(&buf->vb.queue);
383 wake_up(&buf->vb.done);
385 if (list_empty(&q->active)) {
386 del_timer(&q->timeout);
388 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
391 printk("%s: %d buffers handled (should be 1)\n",
395 static int cx23885_sram_channel_setup(struct cx23885_dev *dev,
396 struct sram_channel *ch,
397 unsigned int bpl, u32 risc)
399 unsigned int i, lines;
402 if (ch->cmds_start == 0)
404 dprintk(1, "%s() Erasing channel [%s]\n", __FUNCTION__,
406 cx_write(ch->ptr1_reg, 0);
407 cx_write(ch->ptr2_reg, 0);
408 cx_write(ch->cnt2_reg, 0);
409 cx_write(ch->cnt1_reg, 0);
412 dprintk(1, "%s() Configuring channel [%s]\n", __FUNCTION__,
416 bpl = (bpl + 7) & ~7; /* alignment */
418 lines = ch->fifo_size / bpl;
423 cx_write(8 + 0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
424 cx_write(8 + 4, cpu_to_le32(8) );
425 cx_write(8 + 8, cpu_to_le32(0) );
428 for (i = 0; i < lines; i++) {
429 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __FUNCTION__, cdt + 16*i,
430 ch->fifo_start + bpl*i);
431 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
432 cx_write(cdt + 16*i + 4, 0);
433 cx_write(cdt + 16*i + 8, 0);
434 cx_write(cdt + 16*i + 12, 0);
439 cx_write(ch->cmds_start + 0, 8);
441 cx_write(ch->cmds_start + 0, risc);
442 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
443 cx_write(ch->cmds_start + 8, cdt);
444 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
445 cx_write(ch->cmds_start + 16, ch->ctrl_start);
447 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
449 cx_write(ch->cmds_start + 20, 64 >> 2);
450 for (i = 24; i < 80; i += 4)
451 cx_write(ch->cmds_start + i, 0);
454 cx_write(ch->ptr1_reg, ch->fifo_start);
455 cx_write(ch->ptr2_reg, cdt);
456 cx_write(ch->cnt2_reg, (lines*16) >> 3);
457 cx_write(ch->cnt1_reg, (bpl >> 3) -1);
459 dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
468 static void cx23885_sram_channel_dump(struct cx23885_dev *dev,
469 struct sram_channel *ch)
471 static char *name[] = {
488 unsigned int i, j, n;
490 printk("%s: %s - dma channel status dump\n",
491 dev->name, ch->name);
492 for (i = 0; i < ARRAY_SIZE(name); i++)
493 printk("%s: cmds: %-15s: 0x%08x\n",
495 cx_read(ch->cmds_start + 4*i));
497 for (i = 0; i < 4; i++) {
498 risc = cx_read(ch->cmds_start + 4 * (i + 14));
499 printk("%s: risc%d: ", dev->name, i);
500 cx23885_risc_decode(risc);
502 for (i = 0; i < (64 >> 2); i += n) {
503 risc = cx_read(ch->ctrl_start + 4 * i);
504 /* No consideration for bits 63-32 */
506 printk("%s: (0x%08x) iq %x: ", dev->name,
507 ch->ctrl_start + 4 * i, i);
508 n = cx23885_risc_decode(risc);
509 for (j = 1; j < n; j++) {
510 risc = cx_read(ch->ctrl_start + 4 * (i + j));
511 printk("%s: iq %x: 0x%08x [ arg #%d ]\n",
512 dev->name, i+j, risc, j);
516 printk("%s: fifo: 0x%08x -> 0x%x\n",
517 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
518 printk("%s: ctrl: 0x%08x -> 0x%x\n",
519 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
520 printk("%s: ptr1_reg: 0x%08x\n",
521 dev->name, cx_read(ch->ptr1_reg));
522 printk("%s: ptr2_reg: 0x%08x\n",
523 dev->name, cx_read(ch->ptr2_reg));
524 printk("%s: cnt1_reg: 0x%08x\n",
525 dev->name, cx_read(ch->cnt1_reg));
526 printk("%s: cnt2_reg: 0x%08x\n",
527 dev->name, cx_read(ch->cnt2_reg));
530 static void cx23885_risc_disasm(struct cx23885_tsport *port,
531 struct btcx_riscmem *risc)
533 struct cx23885_dev *dev = port->dev;
534 unsigned int i, j, n;
536 printk("%s: risc disasm: %p [dma=0x%08lx]\n",
537 dev->name, risc->cpu, (unsigned long)risc->dma);
538 for (i = 0; i < (risc->size >> 2); i += n) {
539 printk("%s: %04d: ", dev->name, i);
540 n = cx23885_risc_decode(risc->cpu[i]);
541 for (j = 1; j < n; j++)
542 printk("%s: %04d: 0x%08x [ arg #%d ]\n",
543 dev->name, i + j, risc->cpu[i + j], j);
544 if (risc->cpu[i] == RISC_JUMP)
549 static void cx23885_shutdown(struct cx23885_dev *dev)
551 /* disable RISC controller */
552 cx_write(DEV_CNTRL2, 0);
554 /* Disable all IR activity */
555 cx_write(IR_CNTRL_REG, 0);
557 /* Disable Video A/B activity */
558 cx_write(VID_A_DMA_CTL, 0);
559 cx_write(VID_B_DMA_CTL, 0);
560 cx_write(VID_C_DMA_CTL, 0);
562 /* Disable Audio activity */
563 cx_write(AUD_INT_DMA_CTL, 0);
564 cx_write(AUD_EXT_DMA_CTL, 0);
566 /* Disable Serial port */
567 cx_write(UART_CTL, 0);
569 /* Disable Interrupts */
570 cx_write(PCI_INT_MSK, 0);
571 cx_write(VID_A_INT_MSK, 0);
572 cx_write(VID_B_INT_MSK, 0);
573 cx_write(VID_C_INT_MSK, 0);
574 cx_write(AUDIO_INT_INT_MSK, 0);
575 cx_write(AUDIO_EXT_INT_MSK, 0);
579 static void cx23885_reset(struct cx23885_dev *dev)
581 dprintk(1, "%s()\n", __FUNCTION__);
583 cx23885_shutdown(dev);
585 cx_write(PCI_INT_STAT, 0xffffffff);
586 cx_write(VID_A_INT_STAT, 0xffffffff);
587 cx_write(VID_B_INT_STAT, 0xffffffff);
588 cx_write(VID_C_INT_STAT, 0xffffffff);
589 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
590 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
591 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
595 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH01 ], 188*4, 0);
596 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH02 ], 128, 0);
597 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH03 ], 188*4, 0);
598 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH04 ], 128, 0);
599 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH05 ], 128, 0);
600 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH06 ], 188*4, 0);
601 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH07 ], 128, 0);
602 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH08 ], 128, 0);
603 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH09 ], 128, 0);
605 cx23885_gpio_setup(dev);
609 static int cx23885_pci_quirks(struct cx23885_dev *dev)
611 dprintk(1, "%s()\n", __FUNCTION__);
613 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
614 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
615 * occur on the cx23887 bridge.
617 if(dev->bridge == CX23885_BRIDGE_885)
618 cx_clear(RDR_TLCTL0, 1 << 4);
623 static int get_resources(struct cx23885_dev *dev)
625 if (request_mem_region(pci_resource_start(dev->pci,0),
626 pci_resource_len(dev->pci,0),
630 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
631 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
636 static void cx23885_timeout(unsigned long data);
637 static int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
638 u32 reg, u32 mask, u32 value);
640 static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno)
642 dprintk(1, "%s(portno=%d)\n", __FUNCTION__, portno);
644 /* Transport bus init dma queue - Common settings */
645 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
646 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
648 spin_lock_init(&port->slock);
652 INIT_LIST_HEAD(&port->mpegq.active);
653 INIT_LIST_HEAD(&port->mpegq.queued);
654 port->mpegq.timeout.function = cx23885_timeout;
655 port->mpegq.timeout.data = (unsigned long)port;
656 init_timer(&port->mpegq.timeout);
660 port->reg_gpcnt = VID_B_GPCNT;
661 port->reg_gpcnt_ctl = VID_B_GPCNT_CTL;
662 port->reg_dma_ctl = VID_B_DMA_CTL;
663 port->reg_lngth = VID_B_LNGTH;
664 port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL;
665 port->reg_gen_ctrl = VID_B_GEN_CTL;
666 port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS;
667 port->reg_sop_status = VID_B_SOP_STATUS;
668 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
669 port->reg_vld_misc = VID_B_VLD_MISC;
670 port->reg_ts_clk_en = VID_B_TS_CLK_EN;
671 port->reg_src_sel = VID_B_SRC_SEL;
672 port->reg_ts_int_msk = VID_B_INT_MSK;
673 port->reg_ts_int_stat = VID_B_INT_STAT;
674 port->sram_chno = SRAM_CH03; /* VID_B */
675 port->pci_irqmask = 0x02; /* VID_B bit1 */
678 port->reg_gpcnt = VID_C_GPCNT;
679 port->reg_gpcnt_ctl = VID_C_GPCNT_CTL;
680 port->reg_dma_ctl = VID_C_DMA_CTL;
681 port->reg_lngth = VID_C_LNGTH;
682 port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
683 port->reg_gen_ctrl = VID_C_GEN_CTL;
684 port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
685 port->reg_sop_status = VID_C_SOP_STATUS;
686 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
687 port->reg_vld_misc = VID_C_VLD_MISC;
688 port->reg_ts_clk_en = VID_C_TS_CLK_EN;
689 port->reg_src_sel = 0;
690 port->reg_ts_int_msk = VID_C_INT_MSK;
691 port->reg_ts_int_stat = VID_C_INT_STAT;
692 port->sram_chno = SRAM_CH06; /* VID_C */
693 port->pci_irqmask = 0x04; /* VID_C bit2 */
699 cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
700 port->reg_dma_ctl, port->dma_ctl_val, 0x00);
705 static int cx23885_dev_setup(struct cx23885_dev *dev)
709 mutex_init(&dev->lock);
711 atomic_inc(&dev->refcount);
713 dev->nr = cx23885_devcount++;
714 sprintf(dev->name, "cx23885[%d]", dev->nr);
716 mutex_lock(&devlist);
717 list_add_tail(&dev->devlist, &cx23885_devlist);
718 mutex_unlock(&devlist);
720 /* Configure the internal memory */
721 if(dev->pci->device == 0x8880) {
722 dev->bridge = CX23885_BRIDGE_887;
723 dev->sram_channels = cx23887_sram_channels;
725 if(dev->pci->device == 0x8852) {
726 dev->bridge = CX23885_BRIDGE_885;
727 dev->sram_channels = cx23885_sram_channels;
731 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
732 __FUNCTION__, dev->bridge);
736 if (card[dev->nr] < cx23885_bcount)
737 dev->board = card[dev->nr];
738 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
739 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
740 dev->pci->subsystem_device == cx23885_subids[i].subdevice)
741 dev->board = cx23885_subids[i].card;
742 if (UNSET == dev->board) {
743 dev->board = CX23885_BOARD_UNKNOWN;
744 cx23885_card_list(dev);
747 dev->pci_bus = dev->pci->bus->number;
748 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
749 dev->pci_irqmask = 0x001f00;
751 /* External Master 1 Bus */
752 dev->i2c_bus[0].nr = 0;
753 dev->i2c_bus[0].dev = dev;
754 dev->i2c_bus[0].reg_stat = I2C1_STAT;
755 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
756 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
757 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
758 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
759 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
761 /* External Master 2 Bus */
762 dev->i2c_bus[1].nr = 1;
763 dev->i2c_bus[1].dev = dev;
764 dev->i2c_bus[1].reg_stat = I2C2_STAT;
765 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
766 dev->i2c_bus[1].reg_addr = I2C2_ADDR;
767 dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
768 dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
769 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
771 /* Internal Master 3 Bus */
772 dev->i2c_bus[2].nr = 2;
773 dev->i2c_bus[2].dev = dev;
774 dev->i2c_bus[2].reg_stat = I2C3_STAT;
775 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
776 dev->i2c_bus[2].reg_addr = I2C3_ADDR;
777 dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
778 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
779 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
781 if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
782 cx23885_init_tsport(dev, &dev->ts1, 1);
784 if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
785 cx23885_init_tsport(dev, &dev->ts2, 2);
787 if (get_resources(dev) < 0) {
788 printk(KERN_ERR "CORE %s No more PCIe resources for "
789 "subsystem: %04x:%04x\n",
790 dev->name, dev->pci->subsystem_vendor,
791 dev->pci->subsystem_device);
798 dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
799 pci_resource_len(dev->pci,0));
801 dev->bmmio = (u8 __iomem *)dev->lmmio;
803 printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
804 dev->name, dev->pci->subsystem_vendor,
805 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
806 dev->board, card[dev->nr] == dev->board ?
807 "insmod option" : "autodetected");
809 cx23885_pci_quirks(dev);
814 cx23885_i2c_register(&dev->i2c_bus[0]);
815 cx23885_i2c_register(&dev->i2c_bus[1]);
816 cx23885_i2c_register(&dev->i2c_bus[2]);
817 cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
818 cx23885_card_setup(dev);
819 cx23885_ir_init(dev);
821 if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
822 if (cx23885_dvb_register(&dev->ts1) < 0) {
823 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
828 if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
829 if (cx23885_dvb_register(&dev->ts2) < 0) {
830 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_C\n",
838 static void cx23885_dev_unregister(struct cx23885_dev *dev)
840 release_mem_region(pci_resource_start(dev->pci,0),
841 pci_resource_len(dev->pci,0));
843 if (!atomic_dec_and_test(&dev->refcount))
846 if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
847 cx23885_dvb_unregister(&dev->ts1);
849 if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
850 cx23885_dvb_unregister(&dev->ts2);
852 cx23885_i2c_unregister(&dev->i2c_bus[2]);
853 cx23885_i2c_unregister(&dev->i2c_bus[1]);
854 cx23885_i2c_unregister(&dev->i2c_bus[0]);
859 static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
860 unsigned int offset, u32 sync_line,
861 unsigned int bpl, unsigned int padding,
864 struct scatterlist *sg;
865 unsigned int line, todo;
867 /* sync instruction */
868 if (sync_line != NO_SYNC_LINE)
869 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
873 for (line = 0; line < lines; line++) {
874 while (offset && offset >= sg_dma_len(sg)) {
875 offset -= sg_dma_len(sg);
878 if (bpl <= sg_dma_len(sg)-offset) {
879 /* fits into current chunk */
880 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
881 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
882 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
885 /* scanline needs to be split */
887 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
888 (sg_dma_len(sg)-offset));
889 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
890 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
891 todo -= (sg_dma_len(sg)-offset);
894 while (todo > sg_dma_len(sg)) {
895 *(rp++)=cpu_to_le32(RISC_WRITE|
897 *(rp++)=cpu_to_le32(sg_dma_address(sg));
898 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
899 todo -= sg_dma_len(sg);
902 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
903 *(rp++)=cpu_to_le32(sg_dma_address(sg));
904 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
914 static int cx23885_risc_databuffer(struct pci_dev *pci,
915 struct btcx_riscmem *risc,
916 struct scatterlist *sglist,
924 /* estimate risc mem: worst case is one write per page border +
925 one write per scan line + syncs + jump (all 2 dwords). Here
926 there is no padding and no sync. First DMA region may be smaller
928 /* Jump and write need an extra dword */
929 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
932 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
935 /* write risc instructions */
937 rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
939 /* save pointer to jmp instruction address */
941 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
945 static int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
946 u32 reg, u32 mask, u32 value)
951 if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
954 /* write risc instructions */
956 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
957 *(rp++) = cpu_to_le32(reg);
958 *(rp++) = cpu_to_le32(value);
959 *(rp++) = cpu_to_le32(mask);
960 *(rp++) = cpu_to_le32(RISC_JUMP);
961 *(rp++) = cpu_to_le32(risc->dma);
962 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
966 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
968 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
970 BUG_ON(in_interrupt());
971 videobuf_waiton(&buf->vb, 0, 0);
972 videobuf_dma_unmap(q, dma);
973 videobuf_dma_free(dma);
974 btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc);
975 buf->vb.state = STATE_NEEDS_INIT;
978 static int cx23885_start_dma(struct cx23885_tsport *port,
979 struct cx23885_dmaqueue *q,
980 struct cx23885_buffer *buf)
982 struct cx23885_dev *dev = port->dev;
984 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __FUNCTION__,
985 buf->vb.width, buf->vb.height, buf->vb.field);
987 /* setup fifo + format */
988 cx23885_sram_channel_setup(dev,
989 &dev->sram_channels[ port->sram_chno ],
990 port->ts_packet_size, buf->risc.dma);
992 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
993 cx23885_risc_disasm(port, &buf->risc);
996 /* write TS length to chip */
997 cx_write(port->reg_lngth, buf->vb.width);
999 if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1000 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
1001 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
1003 cx23885_boards[dev->board].portb,
1004 cx23885_boards[dev->board].portc );
1010 /* If the port supports SRC SELECT, configure it */
1011 if(port->reg_src_sel)
1012 cx_write(port->reg_src_sel, port->src_sel_val);
1014 cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
1015 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1016 cx_write(port->reg_vld_misc, 0x00);
1017 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1020 // NOTE: this is 2 (reserved) for portb, does it matter?
1021 /* reset counter to zero */
1022 cx_write(port->reg_gpcnt_ctl, 3);
1025 switch(dev->bridge) {
1026 case CX23885_BRIDGE_885:
1027 case CX23885_BRIDGE_887:
1029 dprintk(1, "%s() enabling TS int's and DMA\n", __FUNCTION__ );
1030 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1031 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1032 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1038 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1043 static int cx23885_stop_dma(struct cx23885_tsport *port)
1045 struct cx23885_dev *dev = port->dev;
1046 dprintk(1, "%s()\n", __FUNCTION__);
1048 /* Stop interrupts and DMA */
1049 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1050 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1055 static int cx23885_restart_queue(struct cx23885_tsport *port,
1056 struct cx23885_dmaqueue *q)
1058 struct cx23885_dev *dev = port->dev;
1059 struct cx23885_buffer *buf;
1061 dprintk(5, "%s()\n", __FUNCTION__);
1062 if (list_empty(&q->active))
1064 struct cx23885_buffer *prev;
1067 dprintk(5, "%s() queue is empty\n", __FUNCTION__);
1070 if (list_empty(&q->queued))
1072 buf = list_entry(q->queued.next, struct cx23885_buffer,
1075 list_del(&buf->vb.queue);
1076 list_add_tail(&buf->vb.queue, &q->active);
1077 cx23885_start_dma(port, q, buf);
1078 buf->vb.state = STATE_ACTIVE;
1079 buf->count = q->count++;
1080 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1081 dprintk(5, "[%p/%d] restart_queue - first active\n",
1084 } else if (prev->vb.width == buf->vb.width &&
1085 prev->vb.height == buf->vb.height &&
1086 prev->fmt == buf->fmt) {
1087 list_del(&buf->vb.queue);
1088 list_add_tail(&buf->vb.queue, &q->active);
1089 buf->vb.state = STATE_ACTIVE;
1090 buf->count = q->count++;
1091 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1092 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1093 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1103 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1104 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1106 cx23885_start_dma(port, q, buf);
1107 list_for_each_entry(buf, &q->active, vb.queue)
1108 buf->count = q->count++;
1109 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1113 /* ------------------------------------------------------------------ */
1115 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1116 struct cx23885_buffer *buf, enum v4l2_field field)
1118 struct cx23885_dev *dev = port->dev;
1119 int size = port->ts_packet_size * port->ts_packet_count;
1122 dprintk(1, "%s: %p\n", __FUNCTION__, buf);
1123 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1126 if (STATE_NEEDS_INIT == buf->vb.state) {
1127 buf->vb.width = port->ts_packet_size;
1128 buf->vb.height = port->ts_packet_count;
1129 buf->vb.size = size;
1130 buf->vb.field = field /*V4L2_FIELD_TOP*/;
1132 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
1134 cx23885_risc_databuffer(dev->pci, &buf->risc,
1135 videobuf_to_dma(&buf->vb)->sglist,
1136 buf->vb.width, buf->vb.height);
1138 buf->vb.state = STATE_PREPARED;
1142 cx23885_free_buffer(q, buf);
1146 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1148 struct cx23885_buffer *prev;
1149 struct cx23885_dev *dev = port->dev;
1150 struct cx23885_dmaqueue *cx88q = &port->mpegq;
1152 /* add jump to stopper */
1153 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1154 buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1155 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1157 if (list_empty(&cx88q->active)) {
1158 dprintk( 1, "queue is empty - first active\n" );
1159 list_add_tail(&buf->vb.queue, &cx88q->active);
1160 cx23885_start_dma(port, cx88q, buf);
1161 buf->vb.state = STATE_ACTIVE;
1162 buf->count = cx88q->count++;
1163 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1164 dprintk(1, "[%p/%d] %s - first active\n",
1165 buf, buf->vb.i, __FUNCTION__);
1167 dprintk( 1, "queue is not empty - append to active\n" );
1168 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1170 list_add_tail(&buf->vb.queue, &cx88q->active);
1171 buf->vb.state = STATE_ACTIVE;
1172 buf->count = cx88q->count++;
1173 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1174 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1175 dprintk( 1, "[%p/%d] %s - append to active\n",
1176 buf, buf->vb.i, __FUNCTION__);
1180 /* ----------------------------------------------------------- */
1182 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1185 struct cx23885_dev *dev = port->dev;
1186 struct cx23885_dmaqueue *q = &port->mpegq;
1187 struct cx23885_buffer *buf;
1188 unsigned long flags;
1190 spin_lock_irqsave(&port->slock, flags);
1191 while (!list_empty(&q->active)) {
1192 buf = list_entry(q->active.next, struct cx23885_buffer,
1194 list_del(&buf->vb.queue);
1195 buf->vb.state = STATE_ERROR;
1196 wake_up(&buf->vb.done);
1197 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1198 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1201 dprintk(1, "restarting queue\n" );
1202 cx23885_restart_queue(port, q);
1204 spin_unlock_irqrestore(&port->slock, flags);
1208 static void cx23885_timeout(unsigned long data)
1210 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1211 struct cx23885_dev *dev = port->dev;
1213 dprintk(1, "%s()\n",__FUNCTION__);
1216 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1218 cx23885_stop_dma(port);
1219 do_cancel_buffers(port, "timeout", 1);
1222 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1224 struct cx23885_dev *dev = port->dev;
1228 if ( (status & VID_BC_MSK_OPC_ERR) ||
1229 (status & VID_BC_MSK_BAD_PKT) ||
1230 (status & VID_BC_MSK_SYNC) ||
1231 (status & VID_BC_MSK_OF))
1233 if (status & VID_BC_MSK_OPC_ERR)
1234 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR);
1235 if (status & VID_BC_MSK_BAD_PKT)
1236 dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n", VID_BC_MSK_BAD_PKT);
1237 if (status & VID_BC_MSK_SYNC)
1238 dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n", VID_BC_MSK_SYNC);
1239 if (status & VID_BC_MSK_OF)
1240 dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n", VID_BC_MSK_OF);
1242 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1244 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1245 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1247 } else if (status & VID_BC_MSK_RISCI1) {
1249 dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1);
1251 spin_lock(&port->slock);
1252 count = cx_read(port->reg_gpcnt);
1253 cx23885_wakeup(port, &port->mpegq, count);
1254 spin_unlock(&port->slock);
1256 } else if (status & VID_BC_MSK_RISCI2) {
1258 dprintk(7, " (RISCI2 0x%08x)\n", VID_BC_MSK_RISCI2);
1260 spin_lock(&port->slock);
1261 cx23885_restart_queue(port, &port->mpegq);
1262 spin_unlock(&port->slock);
1266 cx_write(port->reg_ts_int_stat, status);
1273 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1275 struct cx23885_dev *dev = dev_id;
1276 struct cx23885_tsport *ts1 = &dev->ts1;
1277 struct cx23885_tsport *ts2 = &dev->ts2;
1278 u32 pci_status, pci_mask;
1279 u32 ts1_status, ts1_mask;
1280 u32 ts2_status, ts2_mask;
1281 int ts1_count = 0, ts2_count = 0, handled = 0;
1283 pci_status = cx_read(PCI_INT_STAT);
1284 pci_mask = cx_read(PCI_INT_MSK);
1285 ts1_status = cx_read(VID_B_INT_STAT);
1286 ts1_mask = cx_read(VID_B_INT_MSK);
1287 ts2_status = cx_read(VID_C_INT_STAT);
1288 ts2_mask = cx_read(VID_C_INT_MSK);
1290 if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
1293 ts1_count = cx_read(ts1->reg_gpcnt);
1294 ts2_count = cx_read(ts2->reg_gpcnt);
1295 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n", pci_status, pci_mask );
1296 dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n", ts1_status, ts1_mask, ts1_count );
1297 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n", ts2_status, ts2_mask, ts2_count );
1299 if ( (pci_status & PCI_MSK_RISC_RD) ||
1300 (pci_status & PCI_MSK_RISC_WR) ||
1301 (pci_status & PCI_MSK_AL_RD) ||
1302 (pci_status & PCI_MSK_AL_WR) ||
1303 (pci_status & PCI_MSK_APB_DMA) ||
1304 (pci_status & PCI_MSK_VID_C) ||
1305 (pci_status & PCI_MSK_VID_B) ||
1306 (pci_status & PCI_MSK_VID_A) ||
1307 (pci_status & PCI_MSK_AUD_INT) ||
1308 (pci_status & PCI_MSK_AUD_EXT) )
1311 if (pci_status & PCI_MSK_RISC_RD)
1312 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n", PCI_MSK_RISC_RD);
1313 if (pci_status & PCI_MSK_RISC_WR)
1314 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n", PCI_MSK_RISC_WR);
1315 if (pci_status & PCI_MSK_AL_RD)
1316 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n", PCI_MSK_AL_RD);
1317 if (pci_status & PCI_MSK_AL_WR)
1318 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n", PCI_MSK_AL_WR);
1319 if (pci_status & PCI_MSK_APB_DMA)
1320 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n", PCI_MSK_APB_DMA);
1321 if (pci_status & PCI_MSK_VID_C)
1322 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n", PCI_MSK_VID_C);
1323 if (pci_status & PCI_MSK_VID_B)
1324 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n", PCI_MSK_VID_B);
1325 if (pci_status & PCI_MSK_VID_A)
1326 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n", PCI_MSK_VID_A);
1327 if (pci_status & PCI_MSK_AUD_INT)
1328 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n", PCI_MSK_AUD_INT);
1329 if (pci_status & PCI_MSK_AUD_EXT)
1330 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n", PCI_MSK_AUD_EXT);
1335 handled += cx23885_irq_ts(ts1, ts1_status);
1338 handled += cx23885_irq_ts(ts2, ts2_status);
1341 cx_write(PCI_INT_STAT, pci_status);
1343 return IRQ_RETVAL(handled);
1346 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1347 const struct pci_device_id *pci_id)
1349 struct cx23885_dev *dev;
1352 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1358 if (pci_enable_device(pci_dev)) {
1363 if (cx23885_dev_setup(dev) < 0) {
1368 /* print pci info */
1369 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1370 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1371 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1372 "latency: %d, mmio: 0x%llx\n", dev->name,
1373 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1374 dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0));
1376 pci_set_master(pci_dev);
1377 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1378 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1383 err = request_irq(pci_dev->irq, cx23885_irq,
1384 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1386 printk(KERN_ERR "%s: can't get IRQ %d\n",
1387 dev->name, pci_dev->irq);
1391 pci_set_drvdata(pci_dev, dev);
1395 cx23885_dev_unregister(dev);
1401 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1403 struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1405 cx23885_shutdown(dev);
1407 pci_disable_device(pci_dev);
1409 /* unregister stuff */
1410 free_irq(pci_dev->irq, dev);
1411 pci_set_drvdata(pci_dev, NULL);
1413 mutex_lock(&devlist);
1414 list_del(&dev->devlist);
1415 mutex_unlock(&devlist);
1417 cx23885_dev_unregister(dev);
1421 static struct pci_device_id cx23885_pci_tbl[] = {
1426 .subvendor = PCI_ANY_ID,
1427 .subdevice = PCI_ANY_ID,
1432 .subvendor = PCI_ANY_ID,
1433 .subdevice = PCI_ANY_ID,
1435 /* --- end of list --- */
1438 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1440 static struct pci_driver cx23885_pci_driver = {
1442 .id_table = cx23885_pci_tbl,
1443 .probe = cx23885_initdev,
1444 .remove = __devexit_p(cx23885_finidev),
1450 static int cx23885_init(void)
1452 printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1453 (CX23885_VERSION_CODE >> 16) & 0xff,
1454 (CX23885_VERSION_CODE >> 8) & 0xff,
1455 CX23885_VERSION_CODE & 0xff);
1457 printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1458 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1460 return pci_register_driver(&cx23885_pci_driver);
1463 static void cx23885_fini(void)
1465 pci_unregister_driver(&cx23885_pci_driver);
1468 module_init(cx23885_init);
1469 module_exit(cx23885_fini);
1471 /* ----------------------------------------------------------- */
1476 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off