1 /************************************************************************
2 * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
17 #define s2BIT(loc) (0x8000000000000000ULL >> (loc))
18 #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19 #define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
33 #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
34 #define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL
35 #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
36 #define S2IO_BIT_RESET 1
37 #define S2IO_BIT_SET 2
38 #define CHECKBIT(value, nbit) (value & (1 << nbit))
40 /* Maximum time to flicker LED when asked to identify NIC using ethtool */
41 #define MAX_FLICKER_TIME 60000 /* 60 Secs */
43 /* Maximum outstanding splits to be configured into xena. */
45 XENA_ONE_SPLIT_TRANSACTION = 0,
46 XENA_TWO_SPLIT_TRANSACTION = 1,
47 XENA_THREE_SPLIT_TRANSACTION = 2,
48 XENA_FOUR_SPLIT_TRANSACTION = 3,
49 XENA_EIGHT_SPLIT_TRANSACTION = 4,
50 XENA_TWELVE_SPLIT_TRANSACTION = 5,
51 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
52 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
54 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
56 /* OS concerned variables and constants */
57 #define WATCH_DOG_TIMEOUT 15*HZ
59 #define ALIGN_SIZE 127
60 #define PCIX_COMMAND_REGISTER 0x62
63 * Debug related variables.
65 /* different debug levels. */
72 /* Global variable that defines the present debug level of the driver. */
73 static int debug_level = ERR_DBG;
75 /* DEBUG message print. */
76 #define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
78 #ifndef DMA_ERROR_CODE
79 #define DMA_ERROR_CODE (~(dma_addr_t)0x0)
82 /* Protocol assist features of the NIC */
83 #define L3_CKSUM_OK 0xFFFF
84 #define L4_CKSUM_OK 0xFFFF
85 #define S2IO_JUMBO_SIZE 9600
87 /* Driver statistics maintained by driver */
89 unsigned long long single_ecc_errs;
90 unsigned long long double_ecc_errs;
91 unsigned long long parity_err_cnt;
92 unsigned long long serious_err_cnt;
93 unsigned long long soft_reset_cnt;
94 unsigned long long fifo_full_cnt;
95 unsigned long long ring_full_cnt[8];
97 unsigned long long clubbed_frms_cnt;
98 unsigned long long sending_both;
99 unsigned long long outof_sequence_pkts;
100 unsigned long long flush_max_pkts;
101 unsigned long long sum_avg_pkts_aggregated;
102 unsigned long long num_aggregations;
103 /* Other statistics */
104 unsigned long long mem_alloc_fail_cnt;
105 unsigned long long pci_map_fail_cnt;
106 unsigned long long watchdog_timer_cnt;
107 unsigned long long mem_allocated;
108 unsigned long long mem_freed;
109 unsigned long long link_up_cnt;
110 unsigned long long link_down_cnt;
111 unsigned long long link_up_time;
112 unsigned long long link_down_time;
114 /* Transfer Code statistics */
115 unsigned long long tx_buf_abort_cnt;
116 unsigned long long tx_desc_abort_cnt;
117 unsigned long long tx_parity_err_cnt;
118 unsigned long long tx_link_loss_cnt;
119 unsigned long long tx_list_proc_err_cnt;
121 unsigned long long rx_parity_err_cnt;
122 unsigned long long rx_abort_cnt;
123 unsigned long long rx_parity_abort_cnt;
124 unsigned long long rx_rda_fail_cnt;
125 unsigned long long rx_unkn_prot_cnt;
126 unsigned long long rx_fcs_err_cnt;
127 unsigned long long rx_buf_size_err_cnt;
128 unsigned long long rx_rxd_corrupt_cnt;
129 unsigned long long rx_unkn_err_cnt;
131 /* Error/alarm statistics*/
132 unsigned long long tda_err_cnt;
133 unsigned long long pfc_err_cnt;
134 unsigned long long pcc_err_cnt;
135 unsigned long long tti_err_cnt;
136 unsigned long long lso_err_cnt;
137 unsigned long long tpa_err_cnt;
138 unsigned long long sm_err_cnt;
139 unsigned long long mac_tmac_err_cnt;
140 unsigned long long mac_rmac_err_cnt;
141 unsigned long long xgxs_txgxs_err_cnt;
142 unsigned long long xgxs_rxgxs_err_cnt;
143 unsigned long long rc_err_cnt;
144 unsigned long long prc_pcix_err_cnt;
145 unsigned long long rpa_err_cnt;
146 unsigned long long rda_err_cnt;
147 unsigned long long rti_err_cnt;
148 unsigned long long mc_err_cnt;
152 /* Xpak releated alarm and warnings */
154 u64 alarm_transceiver_temp_high;
155 u64 alarm_transceiver_temp_low;
156 u64 alarm_laser_bias_current_high;
157 u64 alarm_laser_bias_current_low;
158 u64 alarm_laser_output_power_high;
159 u64 alarm_laser_output_power_low;
160 u64 warn_transceiver_temp_high;
161 u64 warn_transceiver_temp_low;
162 u64 warn_laser_bias_current_high;
163 u64 warn_laser_bias_current_low;
164 u64 warn_laser_output_power_high;
165 u64 warn_laser_output_power_low;
167 u32 xpak_timer_count;
171 /* The statistics block of Xena */
173 /* Tx MAC statistics counters. */
174 __le32 tmac_data_octets;
176 __le64 tmac_drop_frms;
177 __le32 tmac_bcst_frms;
178 __le32 tmac_mcst_frms;
179 __le64 tmac_pause_ctrl_frms;
180 __le32 tmac_ucst_frms;
181 __le32 tmac_ttl_octets;
182 __le32 tmac_any_err_frms;
183 __le32 tmac_nucst_frms;
184 __le64 tmac_ttl_less_fb_octets;
185 __le64 tmac_vld_ip_octets;
194 /* Rx MAC Statistics counters. */
195 __le32 rmac_data_octets;
196 __le32 rmac_vld_frms;
197 __le64 rmac_fcs_err_frms;
198 __le64 rmac_drop_frms;
199 __le32 rmac_vld_bcst_frms;
200 __le32 rmac_vld_mcst_frms;
201 __le32 rmac_out_rng_len_err_frms;
202 __le32 rmac_in_rng_len_err_frms;
203 __le64 rmac_long_frms;
204 __le64 rmac_pause_ctrl_frms;
205 __le64 rmac_unsup_ctrl_frms;
206 __le32 rmac_accepted_ucst_frms;
207 __le32 rmac_ttl_octets;
208 __le32 rmac_discarded_frms;
209 __le32 rmac_accepted_nucst_frms;
211 __le32 rmac_drop_events;
212 __le64 rmac_ttl_less_fb_octets;
213 __le64 rmac_ttl_frms;
215 __le32 rmac_usized_frms;
217 __le32 rmac_frag_frms;
218 __le32 rmac_osized_frms;
220 __le32 rmac_jabber_frms;
221 __le64 rmac_ttl_64_frms;
222 __le64 rmac_ttl_65_127_frms;
224 __le64 rmac_ttl_128_255_frms;
225 __le64 rmac_ttl_256_511_frms;
227 __le64 rmac_ttl_512_1023_frms;
228 __le64 rmac_ttl_1024_1518_frms;
231 __le64 rmac_ip_octets;
233 __le32 rmac_hdr_err_ip;
237 __le32 rmac_err_drp_udp;
239 __le64 rmac_xgmii_err_sym;
257 __le32 rmac_pause_cnt;
258 __le64 rmac_xgmii_data_err_cnt;
259 __le64 rmac_xgmii_ctrl_err_cnt;
261 __le32 rmac_accepted_ip;
263 /* PCI/PCI-X Read transaction statistics. */
264 __le32 new_rd_req_cnt;
267 __le32 new_rd_req_rtry_cnt;
269 /* PCI/PCI-X Write/Read transaction statistics. */
271 __le32 wr_rtry_rd_ack_cnt;
272 __le32 new_wr_req_rtry_cnt;
273 __le32 new_wr_req_cnt;
277 /* PCI/PCI-X Write / DMA Transaction statistics. */
279 __le32 rd_rtry_wr_ack_cnt;
287 /* Tx MAC statistics overflow counters. */
288 __le32 tmac_data_octets_oflow;
289 __le32 tmac_frms_oflow;
290 __le32 tmac_bcst_frms_oflow;
291 __le32 tmac_mcst_frms_oflow;
292 __le32 tmac_ucst_frms_oflow;
293 __le32 tmac_ttl_octets_oflow;
294 __le32 tmac_any_err_frms_oflow;
295 __le32 tmac_nucst_frms_oflow;
296 __le64 tmac_vlan_frms;
297 __le32 tmac_drop_ip_oflow;
298 __le32 tmac_vld_ip_oflow;
299 __le32 tmac_rst_tcp_oflow;
300 __le32 tmac_icmp_oflow;
301 __le32 tpa_unknown_protocol;
302 __le32 tmac_udp_oflow;
304 __le32 tpa_parse_failure;
306 /* Rx MAC Statistics overflow counters. */
307 __le32 rmac_data_octets_oflow;
308 __le32 rmac_vld_frms_oflow;
309 __le32 rmac_vld_bcst_frms_oflow;
310 __le32 rmac_vld_mcst_frms_oflow;
311 __le32 rmac_accepted_ucst_frms_oflow;
312 __le32 rmac_ttl_octets_oflow;
313 __le32 rmac_discarded_frms_oflow;
314 __le32 rmac_accepted_nucst_frms_oflow;
315 __le32 rmac_usized_frms_oflow;
316 __le32 rmac_drop_events_oflow;
317 __le32 rmac_frag_frms_oflow;
318 __le32 rmac_osized_frms_oflow;
319 __le32 rmac_ip_oflow;
320 __le32 rmac_jabber_frms_oflow;
321 __le32 rmac_icmp_oflow;
322 __le32 rmac_drop_ip_oflow;
323 __le32 rmac_err_drp_udp_oflow;
324 __le32 rmac_udp_oflow;
326 __le32 rmac_pause_cnt_oflow;
327 __le64 rmac_ttl_1519_4095_frms;
328 __le64 rmac_ttl_4096_8191_frms;
329 __le64 rmac_ttl_8192_max_frms;
330 __le64 rmac_ttl_gt_max_frms;
331 __le64 rmac_osized_alt_frms;
332 __le64 rmac_jabber_alt_frms;
333 __le64 rmac_gt_max_alt_frms;
334 __le64 rmac_vlan_frms;
335 __le32 rmac_len_discard;
336 __le32 rmac_fcs_discard;
337 __le32 rmac_pf_discard;
338 __le32 rmac_da_discard;
339 __le32 rmac_red_discard;
340 __le32 rmac_rts_discard;
342 __le32 rmac_ingm_full_discard;
344 __le32 rmac_accepted_ip_oflow;
346 __le32 link_fault_cnt;
348 struct swStat sw_stat;
349 struct xpakStat xpak_stat;
352 /* Default value for 'vlan_strip_tag' configuration parameter */
353 #define NO_STRIP_IN_PROMISC 2
356 * Structures representing different init time configuration
357 * parameters of the NIC.
360 #define MAX_TX_FIFOS 8
361 #define MAX_RX_RINGS 8
363 #define FIFO_DEFAULT_NUM 1
365 #define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
366 #define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
367 #define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
368 #define MAX_TX_DESC (MAX_AVAILABLE_TXDS)
370 /* FIFO mappings for all possible number of fifos configured */
371 static int fifo_map[][MAX_TX_FIFOS] = {
372 {0, 0, 0, 0, 0, 0, 0, 0},
373 {0, 0, 0, 0, 1, 1, 1, 1},
374 {0, 0, 0, 1, 1, 1, 2, 2},
375 {0, 0, 1, 1, 2, 2, 3, 3},
376 {0, 0, 1, 1, 2, 2, 3, 4},
377 {0, 0, 1, 1, 2, 3, 4, 5},
378 {0, 0, 1, 2, 3, 4, 5, 6},
379 {0, 1, 2, 3, 4, 5, 6, 7},
382 /* Maintains Per FIFO related information. */
383 struct tx_fifo_config {
384 #define MAX_AVAILABLE_TXDS 8192
385 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
386 /* Priority definition */
387 #define TX_FIFO_PRI_0 0 /*Highest */
388 #define TX_FIFO_PRI_1 1
389 #define TX_FIFO_PRI_2 2
390 #define TX_FIFO_PRI_3 3
391 #define TX_FIFO_PRI_4 4
392 #define TX_FIFO_PRI_5 5
393 #define TX_FIFO_PRI_6 6
394 #define TX_FIFO_PRI_7 7 /*lowest */
395 u8 fifo_priority; /* specifies pointer level for FIFO */
396 /* user should not set twos fifos with same pri */
398 #define NO_SNOOP_TXD 0x01
399 #define NO_SNOOP_TXD_BUFFER 0x02
403 /* Maintains per Ring related information */
404 struct rx_ring_config {
405 u32 num_rxd; /*No of RxDs per Rx Ring */
406 #define RX_RING_PRI_0 0 /* highest */
407 #define RX_RING_PRI_1 1
408 #define RX_RING_PRI_2 2
409 #define RX_RING_PRI_3 3
410 #define RX_RING_PRI_4 4
411 #define RX_RING_PRI_5 5
412 #define RX_RING_PRI_6 6
413 #define RX_RING_PRI_7 7 /* lowest */
415 u8 ring_priority; /*Specifies service priority of ring */
416 /* OSM should not set any two rings with same priority */
417 u8 ring_org; /*Organization of ring */
418 #define RING_ORG_BUFF1 0x01
419 #define RX_RING_ORG_BUFF3 0x03
420 #define RX_RING_ORG_BUFF5 0x05
423 #define NO_SNOOP_RXD 0x01
424 #define NO_SNOOP_RXD_BUFFER 0x02
427 /* This structure provides contains values of the tunable parameters
430 struct config_param {
432 u32 tx_fifo_num; /*Number of Tx FIFOs */
434 u8 fifo_mapping[MAX_TX_FIFOS];
435 struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
436 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
443 /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
446 u32 rx_ring_num; /*Number of receive rings */
447 #define MAX_RX_BLOCKS_PER_RING 150
449 struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
451 #define HEADER_ETHERNET_II_802_3_SIZE 14
452 #define HEADER_802_2_SIZE 3
453 #define HEADER_SNAP_SIZE 5
454 #define HEADER_VLAN_SIZE 4
457 #define MAX_PYLD 1500
458 #define MAX_MTU (MAX_PYLD+18)
459 #define MAX_MTU_VLAN (MAX_PYLD+22)
460 #define MAX_PYLD_JUMBO 9600
461 #define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
462 #define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
464 int max_mc_addr; /* xena=64 herc=256 */
465 int max_mac_addr; /* xena=16 herc=64 */
466 int mc_start_offset; /* xena=16 herc=64 */
470 /* Structure representing MAC Addrs */
472 u8 mac_addr[ETH_ALEN];
475 /* Structure that represent every FIFO element in the BAR1
478 struct TxFIFO_element {
482 #define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
483 #define TX_FIFO_FIRST_LIST s2BIT(14)
484 #define TX_FIFO_LAST_LIST s2BIT(15)
485 #define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
486 #define TX_FIFO_SPECIAL_FUNC s2BIT(23)
487 #define TX_FIFO_DS_NO_SNOOP s2BIT(31)
488 #define TX_FIFO_BUFF_NO_SNOOP s2BIT(30)
491 /* Tx descriptor structure */
495 #define TXD_LIST_OWN_XENA s2BIT(7)
496 #define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
497 #define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
498 #define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
499 #define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23))
500 #define TXD_GATHER_CODE_FIRST s2BIT(22)
501 #define TXD_GATHER_CODE_LAST s2BIT(23)
502 #define TXD_TCP_LSO_EN s2BIT(30)
503 #define TXD_UDP_COF_EN s2BIT(31)
504 #define TXD_UFO_EN s2BIT(31) | s2BIT(30)
505 #define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
506 #define TXD_UFO_MSS(val) vBIT(val,34,14)
507 #define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
510 #define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7))
511 #define TXD_TX_CKO_IPV4_EN s2BIT(5)
512 #define TXD_TX_CKO_TCP_EN s2BIT(6)
513 #define TXD_TX_CKO_UDP_EN s2BIT(7)
514 #define TXD_VLAN_ENABLE s2BIT(15)
515 #define TXD_VLAN_TAG(val) vBIT(val,16,16)
516 #define TXD_INT_NUMBER(val) vBIT(val,34,6)
517 #define TXD_INT_TYPE_PER_LIST s2BIT(47)
518 #define TXD_INT_TYPE_UTILZ s2BIT(46)
519 #define TXD_SET_MARKER vBIT(0x6,0,4)
522 u64 Host_Control; /* reserved for host */
525 /* Structure to hold the phy and virt addr of every TxDL. */
526 struct list_info_hold {
527 dma_addr_t list_phy_addr;
528 void *list_virt_addr;
531 /* Rx descriptor structure for 1 buffer mode */
533 u64 Host_Control; /* reserved for host */
535 #define RXD_OWN_XENA s2BIT(7)
536 #define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
537 #define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
538 #define RXD_FRAME_PROTO_IPV4 s2BIT(27)
539 #define RXD_FRAME_PROTO_IPV6 s2BIT(28)
540 #define RXD_FRAME_IP_FRAG s2BIT(29)
541 #define RXD_FRAME_PROTO_TCP s2BIT(30)
542 #define RXD_FRAME_PROTO_UDP s2BIT(31)
543 #define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
544 #define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
545 #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
548 #define THE_RXD_MARK 0x3
549 #define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
550 #define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
552 #define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
553 #define SET_VLAN_TAG(val) vBIT(val,48,16)
554 #define SET_NUM_TAG(val) vBIT(val,16,32)
558 /* Rx descriptor structure for 1 buffer mode */
562 #define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
563 #define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
564 #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
565 (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
568 /* Rx descriptor structure for 3 or 2 buffer mode */
573 #define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
574 #define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
575 #define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
576 #define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
577 #define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
578 #define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
579 #define RXD_GET_BUFFER0_SIZE_3(Control_2) \
580 (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
581 #define RXD_GET_BUFFER1_SIZE_3(Control_2) \
582 (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
583 #define RXD_GET_BUFFER2_SIZE_3(Control_2) \
584 (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
594 /* Structure that represents the Rx descriptor block which contains
595 * 128 Rx descriptors.
598 #define MAX_RXDS_PER_BLOCK_1 127
599 struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
602 #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
603 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
605 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
606 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
607 * the upper 32 bits should
611 #define SIZE_OF_BLOCK 4096
613 #define RXD_MODE_1 0 /* One Buffer mode */
614 #define RXD_MODE_3B 1 /* Two Buffer mode */
616 /* Structure to hold virtual addresses of Buf0 and Buf1 in
625 /* Structure which stores all the MAC control parameters */
627 /* This structure stores the offset of the RxD in the ring
628 * from which the Rx Interrupt processor can start picking
629 * up the RxDs for processing.
631 struct rx_curr_get_info {
637 struct rx_curr_put_info {
643 /* This structure stores the offset of the TxDl in the FIFO
644 * from which the Tx Interrupt processor can start picking
645 * up the TxDLs for send complete interrupt processing.
647 struct tx_curr_get_info {
652 struct tx_curr_put_info {
662 /* Structure that holds the Phy and virt addresses of the Blocks */
663 struct rx_block_info {
664 void *block_virt_addr;
665 dma_addr_t block_dma_addr;
666 struct rxd_info *rxds;
669 /* Ring specific structure */
671 /* The ring number */
675 * Place holders for the virtual and physical addresses of
678 struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
683 * Put pointer info which indictes which RxD has to be replenished
686 struct rx_curr_put_info rx_curr_put_info;
689 * Get pointer info which indictes which is the last RxD that was
690 * processed by the driver.
692 struct rx_curr_get_info rx_curr_get_info;
694 /* Index to the absolute position of the put pointer of Rx ring */
697 /* Buffer Address store. */
699 struct s2io_nic *nic;
702 /* Fifo specific structure */
707 /* Maximum TxDs per TxDL */
710 /* Place holder of all the TX List's Phy and Virt addresses. */
711 struct list_info_hold *list_info;
714 * Current offset within the tx FIFO where driver would write
717 struct tx_curr_put_info tx_curr_put_info;
720 * Current offset within tx FIFO from where the driver would start freeing
723 struct tx_curr_get_info tx_curr_get_info;
724 #define FIFO_QUEUE_START 0
725 #define FIFO_QUEUE_STOP 1
728 /* copy of sp->dev pointer */
729 struct net_device *dev;
731 /* copy of multiq status */
737 /* Per fifo UFO in band structure */
740 struct s2io_nic *nic;
741 } ____cacheline_aligned;
743 /* Information related to the Tx and Rx FIFOs and Rings of Xena
744 * is maintained in this structure.
748 /* logical pointer of start of each Tx FIFO */
749 struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
751 /* Fifo specific structure */
752 struct fifo_info fifos[MAX_TX_FIFOS];
754 /* Save virtual address of TxD page with zero DMA addr(if any) */
755 void *zerodma_virt_addr;
758 /* Ring specific structure */
759 struct ring_info rings[MAX_RX_RINGS];
762 u16 mc_pause_threshold_q0q3;
763 u16 mc_pause_threshold_q4q7;
765 void *stats_mem; /* orignal pointer to allocated mem */
766 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
768 struct stat_block *stats_info; /* Logical address of the stat block */
771 /* structure representing the user defined MAC addresses */
777 /* Default Tunable parameters of the NIC. */
778 #define DEFAULT_FIFO_0_LEN 4096
779 #define DEFAULT_FIFO_1_7_LEN 512
780 #define SMALL_BLK_CNT 30
781 #define LARGE_BLK_CNT 100
784 * Structure to keep track of the MSI-X vectors and the corresponding
785 * argument registered against each vector
787 #define MAX_REQUESTED_MSI_X 17
788 struct s2io_msix_entry
795 #define MSIX_FIFO_TYPE 1
796 #define MSIX_RING_TYPE 2
799 #define MSIX_REGISTERED_SUCCESS 0xAA
802 struct msix_info_st {
807 /* Data structure to represent a LRO session */
809 struct sk_buff *parent;
810 struct sk_buff *last_frag;
826 /* These flags represent the devices temporary state */
827 enum s2io_device_state_t
829 __S2IO_STATE_LINK_TASK=0,
833 /* Structure representing one instance of the NIC */
837 * Count of packets to be processed in a given iteration, it will be indicated
838 * by the quota field of the device structure when NAPI is enabled.
841 struct net_device *dev;
842 struct napi_struct napi;
843 struct mac_info mac_control;
844 struct config_param config;
845 struct pci_dev *pdev;
848 #define MAX_MAC_SUPPORTED 16
849 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
851 struct mac_addr def_mac_addr[256];
853 struct net_device_stats stats;
855 int device_enabled_once;
858 struct tasklet_struct task;
859 volatile unsigned long tasklet_status;
861 /* Timer that handles I/O errors/exceptions */
862 struct timer_list alarm_timer;
864 /* Space to back up the PCI config space */
865 u32 config_space[256 / sizeof(u32)];
867 atomic_t rx_bufs_left[MAX_RX_RINGS];
874 #define MAX_ADDRS_SUPPORTED 64
877 struct usr_addr usr_addrs[256];
883 /* Id timer, used to blink NIC to physically identify NIC. */
884 struct timer_list id_timer;
886 /* Restart timer, used to restart NIC if the device is stuck and
887 * a schedule task that will set the correct Link state once the
888 * NIC's PHY has stabilized after a state change.
890 struct work_struct rst_timer_task;
891 struct work_struct set_link_task;
893 /* Flag that can be used to turn on or turn off the Rx checksum
898 /* after blink, the adapter must be restored with original
903 /* Last known link state. */
909 unsigned long long start_time;
910 struct vlan_group *vlgrp;
911 #define MSIX_FLG 0xA5
912 struct msix_entry *entries;
914 wait_queue_head_t msi_wait;
915 struct s2io_msix_entry *s2io_entries;
916 char desc[MAX_REQUESTED_MSI_X][25];
918 int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
920 struct msix_info_st msix_info[0x3f];
922 #define XFRAME_I_DEVICE 1
923 #define XFRAME_II_DEVICE 2
926 #define MAX_LRO_SESSIONS 32
927 struct lro lro0_n[MAX_LRO_SESSIONS];
928 unsigned long clubbed_frms_cnt;
929 unsigned long sending_both;
931 u16 lro_max_aggr_per_sess;
932 volatile unsigned long state;
934 u64 general_int_mask;
935 #define VPD_STRING_LEN 80
936 u8 product_name[VPD_STRING_LEN];
937 u8 serial_num[VPD_STRING_LEN];
940 #define RESET_ERROR 1;
943 /* OS related system calls */
945 static inline u64 readq(void __iomem *addr)
948 ret = readl(addr + 4);
957 static inline void writeq(u64 val, void __iomem *addr)
959 writel((u32) (val), addr);
960 writel((u32) (val >> 32), (addr + 4));
965 * Some registers have to be written in a particular order to
966 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
967 * is used to perform such ordered writes. Defines UF (Upper First)
968 * and LF (Lower First) will be used to specify the required write order.
972 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
977 writel((u32) (val), addr);
979 writel((u32) (val >> 32), (addr + 4));
980 ret = readl(addr + 4);
982 writel((u32) (val >> 32), (addr + 4));
983 ret = readl(addr + 4);
984 writel((u32) (val), addr);
989 /* Interrupt related values of Xena */
991 #define ENABLE_INTRS 1
992 #define DISABLE_INTRS 2
994 /* Highest level interrupt blocks */
995 #define TX_PIC_INTR (0x0001<<0)
996 #define TX_DMA_INTR (0x0001<<1)
997 #define TX_MAC_INTR (0x0001<<2)
998 #define TX_XGXS_INTR (0x0001<<3)
999 #define TX_TRAFFIC_INTR (0x0001<<4)
1000 #define RX_PIC_INTR (0x0001<<5)
1001 #define RX_DMA_INTR (0x0001<<6)
1002 #define RX_MAC_INTR (0x0001<<7)
1003 #define RX_XGXS_INTR (0x0001<<8)
1004 #define RX_TRAFFIC_INTR (0x0001<<9)
1005 #define MC_INTR (0x0001<<10)
1006 #define ENA_ALL_INTRS ( TX_PIC_INTR | \
1018 /* Interrupt masks for the general interrupt mask register */
1019 #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
1021 #define TXPIC_INT_M s2BIT(0)
1022 #define TXDMA_INT_M s2BIT(1)
1023 #define TXMAC_INT_M s2BIT(2)
1024 #define TXXGXS_INT_M s2BIT(3)
1025 #define TXTRAFFIC_INT_M s2BIT(8)
1026 #define PIC_RX_INT_M s2BIT(32)
1027 #define RXDMA_INT_M s2BIT(33)
1028 #define RXMAC_INT_M s2BIT(34)
1029 #define MC_INT_M s2BIT(35)
1030 #define RXXGXS_INT_M s2BIT(36)
1031 #define RXTRAFFIC_INT_M s2BIT(40)
1033 /* PIC level Interrupts TODO*/
1035 /* DMA level Inressupts */
1036 #define TXDMA_PFC_INT_M s2BIT(0)
1037 #define TXDMA_PCC_INT_M s2BIT(2)
1039 /* PFC block interrupts */
1040 #define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */
1042 /* PCC block interrupts. */
1043 #define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
1044 PCC_FB_ECC Error. */
1046 #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
1048 * Prototype declaration.
1050 static int __devinit s2io_init_nic(struct pci_dev *pdev,
1051 const struct pci_device_id *pre);
1052 static void __devexit s2io_rem_nic(struct pci_dev *pdev);
1053 static int init_shared_mem(struct s2io_nic *sp);
1054 static void free_shared_mem(struct s2io_nic *sp);
1055 static int init_nic(struct s2io_nic *nic);
1056 static void rx_intr_handler(struct ring_info *ring_data);
1057 static void tx_intr_handler(struct fifo_info *fifo_data);
1058 static void s2io_handle_errors(void * dev_id);
1060 static int s2io_starter(void);
1061 static void s2io_closer(void);
1062 static void s2io_tx_watchdog(struct net_device *dev);
1063 static void s2io_tasklet(unsigned long dev_addr);
1064 static void s2io_set_multicast(struct net_device *dev);
1065 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1066 static void s2io_link(struct s2io_nic * sp, int link);
1067 static void s2io_reset(struct s2io_nic * sp);
1068 static int s2io_poll(struct napi_struct *napi, int budget);
1069 static void s2io_init_pci(struct s2io_nic * sp);
1070 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr);
1071 static void s2io_alarm_handle(unsigned long data);
1073 s2io_msix_ring_handle(int irq, void *dev_id);
1075 s2io_msix_fifo_handle(int irq, void *dev_id);
1076 static irqreturn_t s2io_isr(int irq, void *dev_id);
1077 static int verify_xena_quiescence(struct s2io_nic *sp);
1078 static const struct ethtool_ops netdev_ethtool_ops;
1079 static void s2io_set_link(struct work_struct *work);
1080 static int s2io_set_swapper(struct s2io_nic * sp);
1081 static void s2io_card_down(struct s2io_nic *nic);
1082 static int s2io_card_up(struct s2io_nic *nic);
1083 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1085 static int s2io_add_isr(struct s2io_nic * sp);
1086 static void s2io_rem_isr(struct s2io_nic * sp);
1088 static void restore_xmsi_data(struct s2io_nic *nic);
1089 static void do_s2io_store_unicast_mc(struct s2io_nic *sp);
1090 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp);
1091 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset);
1092 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr);
1093 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset);
1094 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr);
1097 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
1098 struct RxD_t *rxdp, struct s2io_nic *sp);
1099 static void clear_lro_session(struct lro *lro);
1100 static void queue_rx_frame(struct sk_buff *skb);
1101 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1102 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1103 struct sk_buff *skb, u32 tcp_len);
1104 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
1106 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
1107 pci_channel_state_t state);
1108 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
1109 static void s2io_io_resume(struct pci_dev *pdev);
1111 #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1112 #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1113 #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1115 #define S2IO_PARM_INT(X, def_val) \
1116 static unsigned int X = def_val;\
1117 module_param(X , uint, 0);
1119 #endif /* _S2IO_H */