git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "core.h"
  21 #include "hw.h"
  22 #include "reg.h"
  23 #include "phy.h"
  24 #include "initvals.h"
  25
  26 static int btcoex_enable;
  27 module_param(btcoex_enable, bool, 0);
  28 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  29
  30 #define ATH9K_CLOCK_RATE_CCK            22
  31 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  32 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  33
  34 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
  35 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
  36                               enum ath9k_ht_macmode macmode);
  37 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
  38                               struct ar5416_eeprom_def *pEepData,
  39                               u32 reg, u32 value);
  40 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  41 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  42
  43 /********************/
  44 /* Helper Functions */
  45 /********************/
  46
  47 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
  48 {
  49         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  50         if (!ah->ah_curchan) /* should really check for CCK instead */
  51                 return clks / ATH9K_CLOCK_RATE_CCK;
  52         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  53                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  54         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  55 }
  56
  57 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
  58 {
  59         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69         if (!ah->ah_curchan) /* should really check for CCK instead */
  70                 return usecs *ATH9K_CLOCK_RATE_CCK;
  71         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  72                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  73         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  74 }
  75
  76 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
  77 {
  78         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  79         if (conf_is_ht40(conf))
  80                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  81         else
  82                 return ath9k_hw_mac_clks(ah, usecs);
  83 }
  84
  85 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
  86 {
  87         int i;
  88
  89         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
  90                 if ((REG_READ(ah, reg) & mask) == val)
  91                         return true;
  92
  93                 udelay(AH_TIME_QUANTUM);
  94         }
  95
  96         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
  97                 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
  98                 reg, REG_READ(ah, reg), mask, val);
  99
 100         return false;
 101 }
 102
 103 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 104 {
 105         u32 retval;
 106         int i;
 107
 108         for (i = 0, retval = 0; i < n; i++) {
 109                 retval = (retval << 1) | (val & 1);
 110                 val >>= 1;
 111         }
 112         return retval;
 113 }
 114
 115 bool ath9k_get_channel_edges(struct ath_hal *ah,
 116                              u16 flags, u16 *low,
 117                              u16 *high)
 118 {
 119         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
 120
 121         if (flags & CHANNEL_5GHZ) {
 122                 *low = pCap->low_5ghz_chan;
 123                 *high = pCap->high_5ghz_chan;
 124                 return true;
 125         }
 126         if ((flags & CHANNEL_2GHZ)) {
 127                 *low = pCap->low_2ghz_chan;
 128                 *high = pCap->high_2ghz_chan;
 129                 return true;
 130         }
 131         return false;
 132 }
 133
 134 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
 135                            struct ath_rate_table *rates,
 136                            u32 frameLen, u16 rateix,
 137                            bool shortPreamble)
 138 {
 139         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 140         u32 kbps;
 141
 142         kbps = rates->info[rateix].ratekbps;
 143
 144         if (kbps == 0)
 145                 return 0;
 146
 147         switch (rates->info[rateix].phy) {
 148         case WLAN_RC_PHY_CCK:
 149                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 150                 if (shortPreamble && rates->info[rateix].short_preamble)
 151                         phyTime >>= 1;
 152                 numBits = frameLen << 3;
 153                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 154                 break;
 155         case WLAN_RC_PHY_OFDM:
 156                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
 157                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 158                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 159                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 160                         txTime = OFDM_SIFS_TIME_QUARTER
 161                                 + OFDM_PREAMBLE_TIME_QUARTER
 162                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 163                 } else if (ah->ah_curchan &&
 164                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
 165                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 166                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 167                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 168                         txTime = OFDM_SIFS_TIME_HALF +
 169                                 OFDM_PREAMBLE_TIME_HALF
 170                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 171                 } else {
 172                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 173                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 174                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 175                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 176                                 + (numSymbols * OFDM_SYMBOL_TIME);
 177                 }
 178                 break;
 179         default:
 180                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 181                         "Unknown phy %u (rate ix %u)\n",
 182                         rates->info[rateix].phy, rateix);
 183                 txTime = 0;
 184                 break;
 185         }
 186
 187         return txTime;
 188 }
 189
 190 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
 191                                   struct ath9k_channel *chan,
 192                                   struct chan_centers *centers)
 193 {
 194         int8_t extoff;
 195         struct ath_hal_5416 *ahp = AH5416(ah);
 196
 197         if (!IS_CHAN_HT40(chan)) {
 198                 centers->ctl_center = centers->ext_center =
 199                         centers->synth_center = chan->channel;
 200                 return;
 201         }
 202
 203         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 204             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 205                 centers->synth_center =
 206                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 207                 extoff = 1;
 208         } else {
 209                 centers->synth_center =
 210                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 211                 extoff = -1;
 212         }
 213
 214         centers->ctl_center =
 215                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 216         centers->ext_center =
 217                 centers->synth_center + (extoff *
 218                          ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 219                           HT40_CHANNEL_CENTER_SHIFT : 15));
 220
 221 }
 222
 223 /******************/
 224 /* Chip Revisions */
 225 /******************/
 226
 227 static void ath9k_hw_read_revisions(struct ath_hal *ah)
 228 {
 229         u32 val;
 230
 231         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 232
 233         if (val == 0xFF) {
 234                 val = REG_READ(ah, AR_SREV);
 235                 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 236                 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
 237                 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 238         } else {
 239                 if (!AR_SREV_9100(ah))
 240                         ah->ah_macVersion = MS(val, AR_SREV_VERSION);
 241
 242                 ah->ah_macRev = val & AR_SREV_REVISION;
 243
 244                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
 245                         ah->ah_isPciExpress = true;
 246         }
 247 }
 248
 249 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
 250 {
 251         u32 val;
 252         int i;
 253
 254         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 255
 256         for (i = 0; i < 8; i++)
 257                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 258         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 259         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 260
 261         return ath9k_hw_reverse_bits(val, 8);
 262 }
 263
 264 /************************************/
 265 /* HW Attach, Detach, Init Routines */
 266 /************************************/
 267
 268 static void ath9k_hw_disablepcie(struct ath_hal *ah)
 269 {
 270         if (!AR_SREV_9100(ah))
 271                 return;
 272
 273         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 274         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 275         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 276         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 277         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 278         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 279         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 280         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 281         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 282
 283         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 284 }
 285
 286 static bool ath9k_hw_chip_test(struct ath_hal *ah)
 287 {
 288         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 289         u32 regHold[2];
 290         u32 patternData[4] = { 0x55555555,
 291                                0xaaaaaaaa,
 292                                0x66666666,
 293                                0x99999999 };
 294         int i, j;
 295
 296         for (i = 0; i < 2; i++) {
 297                 u32 addr = regAddr[i];
 298                 u32 wrData, rdData;
 299
 300                 regHold[i] = REG_READ(ah, addr);
 301                 for (j = 0; j < 0x100; j++) {
 302                         wrData = (j << 16) | j;
 303                         REG_WRITE(ah, addr, wrData);
 304                         rdData = REG_READ(ah, addr);
 305                         if (rdData != wrData) {
 306                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 307                                         "address test failed "
 308                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 309                                         addr, wrData, rdData);
 310                                 return false;
 311                         }
 312                 }
 313                 for (j = 0; j < 4; j++) {
 314                         wrData = patternData[j];
 315                         REG_WRITE(ah, addr, wrData);
 316                         rdData = REG_READ(ah, addr);
 317                         if (wrData != rdData) {
 318                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 319                                         "address test failed "
 320                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 321                                         addr, wrData, rdData);
 322                                 return false;
 323                         }
 324                 }
 325                 REG_WRITE(ah, regAddr[i], regHold[i]);
 326         }
 327         udelay(100);
 328         return true;
 329 }
 330
 331 static const char *ath9k_hw_devname(u16 devid)
 332 {
 333         switch (devid) {
 334         case AR5416_DEVID_PCI:
 335                 return "Atheros 5416";
 336         case AR5416_DEVID_PCIE:
 337                 return "Atheros 5418";
 338         case AR9160_DEVID_PCI:
 339                 return "Atheros 9160";
 340         case AR5416_AR9100_DEVID:
 341                 return "Atheros 9100";
 342         case AR9280_DEVID_PCI:
 343         case AR9280_DEVID_PCIE:
 344                 return "Atheros 9280";
 345         case AR9285_DEVID_PCIE:
 346                 return "Atheros 9285";
 347         }
 348
 349         return NULL;
 350 }
 351
 352 static void ath9k_hw_set_defaults(struct ath_hal *ah)
 353 {
 354         int i;
 355
 356         ah->ah_config.dma_beacon_response_time = 2;
 357         ah->ah_config.sw_beacon_response_time = 10;
 358         ah->ah_config.additional_swba_backoff = 0;
 359         ah->ah_config.ack_6mb = 0x0;
 360         ah->ah_config.cwm_ignore_extcca = 0;
 361         ah->ah_config.pcie_powersave_enable = 0;
 362         ah->ah_config.pcie_l1skp_enable = 0;
 363         ah->ah_config.pcie_clock_req = 0;
 364         ah->ah_config.pcie_power_reset = 0x100;
 365         ah->ah_config.pcie_restore = 0;
 366         ah->ah_config.pcie_waen = 0;
 367         ah->ah_config.analog_shiftreg = 1;
 368         ah->ah_config.ht_enable = 1;
 369         ah->ah_config.ofdm_trig_low = 200;
 370         ah->ah_config.ofdm_trig_high = 500;
 371         ah->ah_config.cck_trig_high = 200;
 372         ah->ah_config.cck_trig_low = 100;
 373         ah->ah_config.enable_ani = 1;
 374         ah->ah_config.noise_immunity_level = 4;
 375         ah->ah_config.ofdm_weaksignal_det = 1;
 376         ah->ah_config.cck_weaksignal_thr = 0;
 377         ah->ah_config.spur_immunity_level = 2;
 378         ah->ah_config.firstep_level = 0;
 379         ah->ah_config.rssi_thr_high = 40;
 380         ah->ah_config.rssi_thr_low = 7;
 381         ah->ah_config.diversity_control = 0;
 382         ah->ah_config.antenna_switch_swap = 0;
 383
 384         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 385                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
 386                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
 387         }
 388
 389         ah->ah_config.intr_mitigation = 1;
 390 }
 391
 392 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
 393                                               struct ath_softc *sc,
 394                                               void __iomem *mem,
 395                                               int *status)
 396 {
 397         static const u8 defbssidmask[ETH_ALEN] =
 398                 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 399         struct ath_hal_5416 *ahp;
 400         struct ath_hal *ah;
 401
 402         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
 403         if (ahp == NULL) {
 404                 DPRINTF(sc, ATH_DBG_FATAL,
 405                         "Cannot allocate memory for state block\n");
 406                 *status = -ENOMEM;
 407                 return NULL;
 408         }
 409
 410         ah = &ahp->ah;
 411         ah->ah_sc = sc;
 412         ah->ah_sh = mem;
 413         ah->ah_magic = AR5416_MAGIC;
 414         ah->ah_countryCode = CTRY_DEFAULT;
 415         ah->ah_devid = devid;
 416         ah->ah_subvendorid = 0;
 417
 418         ah->ah_flags = 0;
 419         if ((devid == AR5416_AR9100_DEVID))
 420                 ah->ah_macVersion = AR_SREV_VERSION_9100;
 421         if (!AR_SREV_9100(ah))
 422                 ah->ah_flags = AH_USE_EEPROM;
 423
 424         ah->ah_powerLimit = MAX_RATE_POWER;
 425         ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
 426         ahp->ah_atimWindow = 0;
 427         ahp->ah_diversityControl = ah->ah_config.diversity_control;
 428         ahp->ah_antennaSwitchSwap =
 429                 ah->ah_config.antenna_switch_swap;
 430         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 431         ahp->ah_beaconInterval = 100;
 432         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
 433         ahp->ah_slottime = (u32) -1;
 434         ahp->ah_acktimeout = (u32) -1;
 435         ahp->ah_ctstimeout = (u32) -1;
 436         ahp->ah_globaltxtimeout = (u32) -1;
 437         memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
 438
 439         ahp->ah_gBeaconRate = 0;
 440
 441         return ahp;
 442 }
 443
 444 static int ath9k_hw_rfattach(struct ath_hal *ah)
 445 {
 446         bool rfStatus = false;
 447         int ecode = 0;
 448
 449         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 450         if (!rfStatus) {
 451                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 452                         "RF setup failed, status %u\n", ecode);
 453                 return ecode;
 454         }
 455
 456         return 0;
 457 }
 458
 459 static int ath9k_hw_rf_claim(struct ath_hal *ah)
 460 {
 461         u32 val;
 462
 463         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 464
 465         val = ath9k_hw_get_radiorev(ah);
 466         switch (val & AR_RADIO_SREV_MAJOR) {
 467         case 0:
 468                 val = AR_RAD5133_SREV_MAJOR;
 469                 break;
 470         case AR_RAD5133_SREV_MAJOR:
 471         case AR_RAD5122_SREV_MAJOR:
 472         case AR_RAD2133_SREV_MAJOR:
 473         case AR_RAD2122_SREV_MAJOR:
 474                 break;
 475         default:
 476                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 477                         "5G Radio Chip Rev 0x%02X is not "
 478                         "supported by this driver\n",
 479                         ah->ah_analog5GhzRev);
 480                 return -EOPNOTSUPP;
 481         }
 482
 483         ah->ah_analog5GhzRev = val;
 484
 485         return 0;
 486 }
 487
 488 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
 489 {
 490         u32 sum;
 491         int i;
 492         u16 eeval;
 493         struct ath_hal_5416 *ahp = AH5416(ah);
 494
 495         sum = 0;
 496         for (i = 0; i < 3; i++) {
 497                 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
 498                 sum += eeval;
 499                 ahp->ah_macaddr[2 * i] = eeval >> 8;
 500                 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
 501         }
 502         if (sum == 0 || sum == 0xffff * 3) {
 503                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 504                         "mac address read failed: %pM\n",
 505                         ahp->ah_macaddr);
 506                 return -EADDRNOTAVAIL;
 507         }
 508
 509         return 0;
 510 }
 511
 512 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
 513 {
 514         u32 rxgain_type;
 515         struct ath_hal_5416 *ahp = AH5416(ah);
 516
 517         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 518                 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
 519
 520                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 521                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 522                         ar9280Modes_backoff_13db_rxgain_9280_2,
 523                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 524                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 525                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 526                         ar9280Modes_backoff_23db_rxgain_9280_2,
 527                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 528                 else
 529                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 530                         ar9280Modes_original_rxgain_9280_2,
 531                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 532         } else
 533                 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 534                         ar9280Modes_original_rxgain_9280_2,
 535                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 536 }
 537
 538 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
 539 {
 540         u32 txgain_type;
 541         struct ath_hal_5416 *ahp = AH5416(ah);
 542
 543         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 544                 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
 545
 546                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 547                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 548                         ar9280Modes_high_power_tx_gain_9280_2,
 549                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 550                 else
 551                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 552                         ar9280Modes_original_tx_gain_9280_2,
 553                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 554         } else
 555                 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 556                 ar9280Modes_original_tx_gain_9280_2,
 557                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 558 }
 559
 560 static int ath9k_hw_post_attach(struct ath_hal *ah)
 561 {
 562         int ecode;
 563
 564         if (!ath9k_hw_chip_test(ah)) {
 565                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 566                         "hardware self-test failed\n");
 567                 return -ENODEV;
 568         }
 569
 570         ecode = ath9k_hw_rf_claim(ah);
 571         if (ecode != 0)
 572                 return ecode;
 573
 574         ecode = ath9k_hw_eeprom_attach(ah);
 575         if (ecode != 0)
 576                 return ecode;
 577         ecode = ath9k_hw_rfattach(ah);
 578         if (ecode != 0)
 579                 return ecode;
 580
 581         if (!AR_SREV_9100(ah)) {
 582                 ath9k_hw_ani_setup(ah);
 583                 ath9k_hw_ani_attach(ah);
 584         }
 585
 586         return 0;
 587 }
 588
 589 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 590                                           void __iomem *mem, int *status)
 591 {
 592         struct ath_hal_5416 *ahp;
 593         struct ath_hal *ah;
 594         int ecode;
 595         u32 i, j;
 596
 597         ahp = ath9k_hw_newstate(devid, sc, mem, status);
 598         if (ahp == NULL)
 599                 return NULL;
 600
 601         ah = &ahp->ah;
 602
 603         ath9k_hw_set_defaults(ah);
 604
 605         if (ah->ah_config.intr_mitigation != 0)
 606                 ahp->ah_intrMitigation = true;
 607
 608         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 609                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
 610                 ecode = -EIO;
 611                 goto bad;
 612         }
 613
 614         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 615                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
 616                 ecode = -EIO;
 617                 goto bad;
 618         }
 619
 620         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
 621                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
 622                         ah->ah_config.serialize_regmode =
 623                                 SER_REG_MODE_ON;
 624                 } else {
 625                         ah->ah_config.serialize_regmode =
 626                                 SER_REG_MODE_OFF;
 627                 }
 628         }
 629
 630         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 631                 "serialize_regmode is %d\n",
 632                 ah->ah_config.serialize_regmode);
 633
 634         if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
 635             (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
 636             (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
 637             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
 638                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 639                         "Mac Chip Rev 0x%02x.%x is not supported by "
 640                         "this driver\n", ah->ah_macVersion, ah->ah_macRev);
 641                 ecode = -EOPNOTSUPP;
 642                 goto bad;
 643         }
 644
 645         if (AR_SREV_9100(ah)) {
 646                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 647                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
 648                 ah->ah_isPciExpress = false;
 649         }
 650         ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 651
 652         if (AR_SREV_9160_10_OR_LATER(ah)) {
 653                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 654                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
 655                         ahp->ah_adcGainCalData.calData =
 656                                 &adc_gain_cal_single_sample;
 657                         ahp->ah_adcDcCalData.calData =
 658                                 &adc_dc_cal_single_sample;
 659                         ahp->ah_adcDcCalInitData.calData =
 660                                 &adc_init_dc_cal;
 661                 } else {
 662                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 663                         ahp->ah_adcGainCalData.calData =
 664                                 &adc_gain_cal_multi_sample;
 665                         ahp->ah_adcDcCalData.calData =
 666                                 &adc_dc_cal_multi_sample;
 667                         ahp->ah_adcDcCalInitData.calData =
 668                                 &adc_init_dc_cal;
 669                 }
 670                 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 671         }
 672
 673         if (AR_SREV_9160(ah)) {
 674                 ah->ah_config.enable_ani = 1;
 675                 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
 676                                         ATH9K_ANI_FIRSTEP_LEVEL);
 677         } else {
 678                 ahp->ah_ani_function = ATH9K_ANI_ALL;
 679                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 680                         ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 681                 }
 682         }
 683
 684         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 685                 "This Mac Chip Rev 0x%02x.%x is \n",
 686                 ah->ah_macVersion, ah->ah_macRev);
 687
 688         if (AR_SREV_9285_12_OR_LATER(ah)) {
 689                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
 690                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 691                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
 692                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 693
 694                 if (ah->ah_config.pcie_clock_req) {
 695                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 696                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 697                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 698                 } else {
 699                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 700                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 701                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 702                                   2);
 703                 }
 704         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 705                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
 706                                ARRAY_SIZE(ar9285Modes_9285), 6);
 707                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
 708                                ARRAY_SIZE(ar9285Common_9285), 2);
 709
 710                 if (ah->ah_config.pcie_clock_req) {
 711                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 712                         ar9285PciePhy_clkreq_off_L1_9285,
 713                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 714                 } else {
 715                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 716                         ar9285PciePhy_clkreq_always_on_L1_9285,
 717                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 718                 }
 719         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 720                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
 721                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 722                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
 723                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 724
 725                 if (ah->ah_config.pcie_clock_req) {
 726                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 727                                ar9280PciePhy_clkreq_off_L1_9280,
 728                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 729                 } else {
 730                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 731                                ar9280PciePhy_clkreq_always_on_L1_9280,
 732                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 733                 }
 734                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
 735                                ar9280Modes_fast_clock_9280_2,
 736                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 737         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 738                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
 739                                ARRAY_SIZE(ar9280Modes_9280), 6);
 740                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
 741                                ARRAY_SIZE(ar9280Common_9280), 2);
 742         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 743                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
 744                                ARRAY_SIZE(ar5416Modes_9160), 6);
 745                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
 746                                ARRAY_SIZE(ar5416Common_9160), 2);
 747                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
 748                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 749                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
 750                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 751                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
 752                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 753                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
 754                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 755                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
 756                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 757                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
 758                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 759                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
 760                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 761                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
 762                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 763                 if (AR_SREV_9160_11(ah)) {
 764                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
 765                                        ar5416Addac_91601_1,
 766                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 767                 } else {
 768                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
 769                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 770                 }
 771         } else if (AR_SREV_9100_OR_LATER(ah)) {
 772                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
 773                                ARRAY_SIZE(ar5416Modes_9100), 6);
 774                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
 775                                ARRAY_SIZE(ar5416Common_9100), 2);
 776                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
 777                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 778                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
 779                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 780                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
 781                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 782                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
 783                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 784                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
 785                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 786                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
 787                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 788                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
 789                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 790                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
 791                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 792                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
 793                                ARRAY_SIZE(ar5416Addac_9100), 2);
 794         } else {
 795                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
 796                                ARRAY_SIZE(ar5416Modes), 6);
 797                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
 798                                ARRAY_SIZE(ar5416Common), 2);
 799                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
 800                                ARRAY_SIZE(ar5416Bank0), 2);
 801                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
 802                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 803                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
 804                                ARRAY_SIZE(ar5416Bank1), 2);
 805                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
 806                                ARRAY_SIZE(ar5416Bank2), 2);
 807                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
 808                                ARRAY_SIZE(ar5416Bank3), 3);
 809                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
 810                                ARRAY_SIZE(ar5416Bank6), 3);
 811                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
 812                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 813                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
 814                                ARRAY_SIZE(ar5416Bank7), 2);
 815                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
 816                                ARRAY_SIZE(ar5416Addac), 2);
 817         }
 818
 819         if (ah->ah_isPciExpress)
 820                 ath9k_hw_configpcipowersave(ah, 0);
 821         else
 822                 ath9k_hw_disablepcie(ah);
 823
 824         ecode = ath9k_hw_post_attach(ah);
 825         if (ecode != 0)
 826                 goto bad;
 827
 828         /* rxgain table */
 829         if (AR_SREV_9280_20(ah))
 830                 ath9k_hw_init_rxgain_ini(ah);
 831
 832         /* txgain table */
 833         if (AR_SREV_9280_20(ah))
 834                 ath9k_hw_init_txgain_ini(ah);
 835
 836         if (ah->ah_devid == AR9280_DEVID_PCI) {
 837                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
 838                         u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
 839
 840                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
 841                                 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
 842
 843                                 INI_RA(&ahp->ah_iniModes, i, j) =
 844                                         ath9k_hw_ini_fixup(ah,
 845                                                            &ahp->ah_eeprom.def,
 846                                                            reg, val);
 847                         }
 848                 }
 849         }
 850
 851         if (!ath9k_hw_fill_cap_info(ah)) {
 852                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 853                         "failed ath9k_hw_fill_cap_info\n");
 854                 ecode = -EINVAL;
 855                 goto bad;
 856         }
 857
 858         ecode = ath9k_hw_init_macaddr(ah);
 859         if (ecode != 0) {
 860                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 861                         "failed initializing mac address\n");
 862                 goto bad;
 863         }
 864
 865         if (AR_SREV_9285(ah))
 866                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
 867         else
 868                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
 869
 870         ath9k_init_nfcal_hist_buffer(ah);
 871
 872         return ah;
 873 bad:
 874         if (ahp)
 875                 ath9k_hw_detach((struct ath_hal *) ahp);
 876         if (status)
 877                 *status = ecode;
 878
 879         return NULL;
 880 }
 881
 882 static void ath9k_hw_init_bb(struct ath_hal *ah,
 883                              struct ath9k_channel *chan)
 884 {
 885         u32 synthDelay;
 886
 887         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 888         if (IS_CHAN_B(chan))
 889                 synthDelay = (4 * synthDelay) / 22;
 890         else
 891                 synthDelay /= 10;
 892
 893         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 894
 895         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 896 }
 897
 898 static void ath9k_hw_init_qos(struct ath_hal *ah)
 899 {
 900         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 901         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 902
 903         REG_WRITE(ah, AR_QOS_NO_ACK,
 904                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 905                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 906                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 907
 908         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 909         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 910         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 911         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 912         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 913 }
 914
 915 static void ath9k_hw_init_pll(struct ath_hal *ah,
 916                               struct ath9k_channel *chan)
 917 {
 918         u32 pll;
 919
 920         if (AR_SREV_9100(ah)) {
 921                 if (chan && IS_CHAN_5GHZ(chan))
 922                         pll = 0x1450;
 923                 else
 924                         pll = 0x1458;
 925         } else {
 926                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 927                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 928
 929                         if (chan && IS_CHAN_HALF_RATE(chan))
 930                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 931                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 932                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 933
 934                         if (chan && IS_CHAN_5GHZ(chan)) {
 935                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 936
 937
 938                                 if (AR_SREV_9280_20(ah)) {
 939                                         if (((chan->channel % 20) == 0)
 940                                             || ((chan->channel % 10) == 0))
 941                                                 pll = 0x2850;
 942                                         else
 943                                                 pll = 0x142c;
 944                                 }
 945                         } else {
 946                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 947                         }
 948
 949                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 950
 951                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 952
 953                         if (chan && IS_CHAN_HALF_RATE(chan))
 954                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 955                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 956                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 957
 958                         if (chan && IS_CHAN_5GHZ(chan))
 959                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
 960                         else
 961                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
 962                 } else {
 963                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
 964
 965                         if (chan && IS_CHAN_HALF_RATE(chan))
 966                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
 967                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 968                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
 969
 970                         if (chan && IS_CHAN_5GHZ(chan))
 971                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
 972                         else
 973                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
 974                 }
 975         }
 976         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 977
 978         udelay(RTC_PLL_SETTLE_DELAY);
 979
 980         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 981 }
 982
 983 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
 984 {
 985         struct ath_hal_5416 *ahp = AH5416(ah);
 986         int rx_chainmask, tx_chainmask;
 987
 988         rx_chainmask = ahp->ah_rxchainmask;
 989         tx_chainmask = ahp->ah_txchainmask;
 990
 991         switch (rx_chainmask) {
 992         case 0x5:
 993                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 994                             AR_PHY_SWAP_ALT_CHAIN);
 995         case 0x3:
 996                 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
 997                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
 998                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
 999                         break;
1000                 }
1001         case 0x1:
1002         case 0x2:
1003         case 0x7:
1004                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1005                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1006                 break;
1007         default:
1008                 break;
1009         }
1010
1011         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1012         if (tx_chainmask == 0x5) {
1013                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1014                             AR_PHY_SWAP_ALT_CHAIN);
1015         }
1016         if (AR_SREV_9100(ah))
1017                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1018                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1019 }
1020
1021 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1022                                           enum nl80211_iftype opmode)
1023 {
1024         struct ath_hal_5416 *ahp = AH5416(ah);
1025
1026         ahp->ah_maskReg = AR_IMR_TXERR |
1027                 AR_IMR_TXURN |
1028                 AR_IMR_RXERR |
1029                 AR_IMR_RXORN |
1030                 AR_IMR_BCNMISC;
1031
1032         if (ahp->ah_intrMitigation)
1033                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1034         else
1035                 ahp->ah_maskReg |= AR_IMR_RXOK;
1036
1037         ahp->ah_maskReg |= AR_IMR_TXOK;
1038
1039         if (opmode == NL80211_IFTYPE_AP)
1040                 ahp->ah_maskReg |= AR_IMR_MIB;
1041
1042         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1043         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1044
1045         if (!AR_SREV_9100(ah)) {
1046                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1047                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1048                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1049         }
1050 }
1051
1052 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1053 {
1054         struct ath_hal_5416 *ahp = AH5416(ah);
1055
1056         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1057                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1058                 ahp->ah_acktimeout = (u32) -1;
1059                 return false;
1060         } else {
1061                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1062                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1063                 ahp->ah_acktimeout = us;
1064                 return true;
1065         }
1066 }
1067
1068 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1069 {
1070         struct ath_hal_5416 *ahp = AH5416(ah);
1071
1072         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1073                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1074                 ahp->ah_ctstimeout = (u32) -1;
1075                 return false;
1076         } else {
1077                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1078                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1079                 ahp->ah_ctstimeout = us;
1080                 return true;
1081         }
1082 }
1083
1084 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1085 {
1086         struct ath_hal_5416 *ahp = AH5416(ah);
1087
1088         if (tu > 0xFFFF) {
1089                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1090                         "bad global tx timeout %u\n", tu);
1091                 ahp->ah_globaltxtimeout = (u32) -1;
1092                 return false;
1093         } else {
1094                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1095                 ahp->ah_globaltxtimeout = tu;
1096                 return true;
1097         }
1098 }
1099
1100 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1101 {
1102         struct ath_hal_5416 *ahp = AH5416(ah);
1103
1104         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1105                 ahp->ah_miscMode);
1106
1107         if (ahp->ah_miscMode != 0)
1108                 REG_WRITE(ah, AR_PCU_MISC,
1109                           REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1110         if (ahp->ah_slottime != (u32) -1)
1111                 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1112         if (ahp->ah_acktimeout != (u32) -1)
1113                 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1114         if (ahp->ah_ctstimeout != (u32) -1)
1115                 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1116         if (ahp->ah_globaltxtimeout != (u32) -1)
1117                 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1118 }
1119
1120 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1121 {
1122         return vendorid == ATHEROS_VENDOR_ID ?
1123                 ath9k_hw_devname(devid) : NULL;
1124 }
1125
1126 void ath9k_hw_detach(struct ath_hal *ah)
1127 {
1128         if (!AR_SREV_9100(ah))
1129                 ath9k_hw_ani_detach(ah);
1130
1131         ath9k_hw_rfdetach(ah);
1132         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1133         kfree(ah);
1134 }
1135
1136 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1137                                 void __iomem *mem, int *error)
1138 {
1139         struct ath_hal *ah = NULL;
1140
1141         switch (devid) {
1142         case AR5416_DEVID_PCI:
1143         case AR5416_DEVID_PCIE:
1144         case AR5416_AR9100_DEVID:
1145         case AR9160_DEVID_PCI:
1146         case AR9280_DEVID_PCI:
1147         case AR9280_DEVID_PCIE:
1148         case AR9285_DEVID_PCIE:
1149                 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1150                 break;
1151         default:
1152                 *error = -ENXIO;
1153                 break;
1154         }
1155
1156         return ah;
1157 }
1158
1159 /*******/
1160 /* INI */
1161 /*******/
1162
1163 static void ath9k_hw_override_ini(struct ath_hal *ah,
1164                                   struct ath9k_channel *chan)
1165 {
1166         /*
1167          * Set the RX_ABORT and RX_DIS and clear if off only after
1168          * RXE is set for MAC. This prevents frames with corrupted
1169          * descriptor status.
1170          */
1171         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1172
1173
1174         if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1175             AR_SREV_9280_10_OR_LATER(ah))
1176                 return;
1177
1178         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1179 }
1180
1181 static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1182                               struct ar5416_eeprom_def *pEepData,
1183                               u32 reg, u32 value)
1184 {
1185         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1186
1187         switch (ah->ah_devid) {
1188         case AR9280_DEVID_PCI:
1189                 if (reg == 0x7894) {
1190                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1191                                 "ini VAL: %x  EEPROM: %x\n", value,
1192                                 (pBase->version & 0xff));
1193
1194                         if ((pBase->version & 0xff) > 0x0a) {
1195                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1196                                         "PWDCLKIND: %d\n",
1197                                         pBase->pwdclkind);
1198                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1199                                 value |= AR_AN_TOP2_PWDCLKIND &
1200                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1201                         } else {
1202                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1203                                         "PWDCLKIND Earlier Rev\n");
1204                         }
1205
1206                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1207                                 "final ini VAL: %x\n", value);
1208                 }
1209                 break;
1210         }
1211
1212         return value;
1213 }
1214
1215 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1216                               struct ar5416_eeprom_def *pEepData,
1217                               u32 reg, u32 value)
1218 {
1219         struct ath_hal_5416 *ahp = AH5416(ah);
1220
1221         if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1222                 return value;
1223         else
1224                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1225 }
1226
1227 static int ath9k_hw_process_ini(struct ath_hal *ah,
1228                                 struct ath9k_channel *chan,
1229                                 enum ath9k_ht_macmode macmode)
1230 {
1231         int i, regWrites = 0;
1232         struct ath_hal_5416 *ahp = AH5416(ah);
1233         struct ieee80211_channel *channel = chan->chan;
1234         u32 modesIndex, freqIndex;
1235         int status;
1236
1237         switch (chan->chanmode) {
1238         case CHANNEL_A:
1239         case CHANNEL_A_HT20:
1240                 modesIndex = 1;
1241                 freqIndex = 1;
1242                 break;
1243         case CHANNEL_A_HT40PLUS:
1244         case CHANNEL_A_HT40MINUS:
1245                 modesIndex = 2;
1246                 freqIndex = 1;
1247                 break;
1248         case CHANNEL_G:
1249         case CHANNEL_G_HT20:
1250         case CHANNEL_B:
1251                 modesIndex = 4;
1252                 freqIndex = 2;
1253                 break;
1254         case CHANNEL_G_HT40PLUS:
1255         case CHANNEL_G_HT40MINUS:
1256                 modesIndex = 3;
1257                 freqIndex = 2;
1258                 break;
1259
1260         default:
1261                 return -EINVAL;
1262         }
1263
1264         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1265
1266         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1267
1268         ath9k_hw_set_addac(ah, chan);
1269
1270         if (AR_SREV_5416_V22_OR_LATER(ah)) {
1271                 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1272         } else {
1273                 struct ar5416IniArray temp;
1274                 u32 addacSize =
1275                         sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1276                         ahp->ah_iniAddac.ia_columns;
1277
1278                 memcpy(ahp->ah_addac5416_21,
1279                        ahp->ah_iniAddac.ia_array, addacSize);
1280
1281                 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1282
1283                 temp.ia_array = ahp->ah_addac5416_21;
1284                 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1285                 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1286                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1287         }
1288
1289         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1290
1291         for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1292                 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1293                 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1294
1295                 REG_WRITE(ah, reg, val);
1296
1297                 if (reg >= 0x7800 && reg < 0x78a0
1298                     && ah->ah_config.analog_shiftreg) {
1299                         udelay(100);
1300                 }
1301
1302                 DO_DELAY(regWrites);
1303         }
1304
1305         if (AR_SREV_9280(ah))
1306                 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1307
1308         if (AR_SREV_9280(ah))
1309                 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1310
1311         for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1312                 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1313                 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1314
1315                 REG_WRITE(ah, reg, val);
1316
1317                 if (reg >= 0x7800 && reg < 0x78a0
1318                     && ah->ah_config.analog_shiftreg) {
1319                         udelay(100);
1320                 }
1321
1322                 DO_DELAY(regWrites);
1323         }
1324
1325         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1326
1327         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1328                 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1329                                 regWrites);
1330         }
1331
1332         ath9k_hw_override_ini(ah, chan);
1333         ath9k_hw_set_regs(ah, chan, macmode);
1334         ath9k_hw_init_chain_masks(ah);
1335
1336         status = ath9k_hw_set_txpower(ah, chan,
1337                                       ath9k_regd_get_ctl(ah, chan),
1338                                       channel->max_antenna_gain * 2,
1339                                       channel->max_power * 2,
1340                                       min((u32) MAX_RATE_POWER,
1341                                           (u32) ah->ah_powerLimit));
1342         if (status != 0) {
1343                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1344                         "error init'ing transmit power\n");
1345                 return -EIO;
1346         }
1347
1348         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1349                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1350                         "ar5416SetRfRegs failed\n");
1351                 return -EIO;
1352         }
1353
1354         return 0;
1355 }
1356
1357 /****************************************/
1358 /* Reset and Channel Switching Routines */
1359 /****************************************/
1360
1361 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1362 {
1363         u32 rfMode = 0;
1364
1365         if (chan == NULL)
1366                 return;
1367
1368         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1369                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1370
1371         if (!AR_SREV_9280_10_OR_LATER(ah))
1372                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1373                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1374
1375         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1376                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1377
1378         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1379 }
1380
1381 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1382 {
1383         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1384 }
1385
1386 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1387 {
1388         u32 regval;
1389
1390         regval = REG_READ(ah, AR_AHB_MODE);
1391         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1392
1393         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1394         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1395
1396         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1397
1398         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1399         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1400
1401         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1402
1403         if (AR_SREV_9285(ah)) {
1404                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1405                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1406         } else {
1407                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1408                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1409         }
1410 }
1411
1412 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1413 {
1414         u32 val;
1415
1416         val = REG_READ(ah, AR_STA_ID1);
1417         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1418         switch (opmode) {
1419         case NL80211_IFTYPE_AP:
1420                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1421                           | AR_STA_ID1_KSRCH_MODE);
1422                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1423                 break;
1424         case NL80211_IFTYPE_ADHOC:
1425                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1426                           | AR_STA_ID1_KSRCH_MODE);
1427                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1428                 break;
1429         case NL80211_IFTYPE_STATION:
1430         case NL80211_IFTYPE_MONITOR:
1431                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1432                 break;
1433         }
1434 }
1435
1436 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1437                                                  u32 coef_scaled,
1438                                                  u32 *coef_mantissa,
1439                                                  u32 *coef_exponent)
1440 {
1441         u32 coef_exp, coef_man;
1442
1443         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1444                 if ((coef_scaled >> coef_exp) & 0x1)
1445                         break;
1446
1447         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1448
1449         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1450
1451         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1452         *coef_exponent = coef_exp - 16;
1453 }
1454
1455 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1456                                      struct ath9k_channel *chan)
1457 {
1458         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1459         u32 clockMhzScaled = 0x64000000;
1460         struct chan_centers centers;
1461
1462         if (IS_CHAN_HALF_RATE(chan))
1463                 clockMhzScaled = clockMhzScaled >> 1;
1464         else if (IS_CHAN_QUARTER_RATE(chan))
1465                 clockMhzScaled = clockMhzScaled >> 2;
1466
1467         ath9k_hw_get_channel_centers(ah, chan, &centers);
1468         coef_scaled = clockMhzScaled / centers.synth_center;
1469
1470         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1471                                       &ds_coef_exp);
1472
1473         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1474                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1475         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1476                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1477
1478         coef_scaled = (9 * coef_scaled) / 10;
1479
1480         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1481                                       &ds_coef_exp);
1482
1483         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1484                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1485         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1486                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1487 }
1488
1489 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1490 {
1491         u32 rst_flags;
1492         u32 tmpReg;
1493
1494         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1495                   AR_RTC_FORCE_WAKE_ON_INT);
1496
1497         if (AR_SREV_9100(ah)) {
1498                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1499                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1500         } else {
1501                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1502                 if (tmpReg &
1503                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1504                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1505                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1506                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1507                 } else {
1508                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1509                 }
1510
1511                 rst_flags = AR_RTC_RC_MAC_WARM;
1512                 if (type == ATH9K_RESET_COLD)
1513                         rst_flags |= AR_RTC_RC_MAC_COLD;
1514         }
1515
1516         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1517         udelay(50);
1518
1519         REG_WRITE(ah, AR_RTC_RC, 0);
1520         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
1521                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1522                         "RTC stuck in MAC reset\n");
1523                 return false;
1524         }
1525
1526         if (!AR_SREV_9100(ah))
1527                 REG_WRITE(ah, AR_RC, 0);
1528
1529         ath9k_hw_init_pll(ah, NULL);
1530
1531         if (AR_SREV_9100(ah))
1532                 udelay(50);
1533
1534         return true;
1535 }
1536
1537 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1538 {
1539         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1540                   AR_RTC_FORCE_WAKE_ON_INT);
1541
1542         REG_WRITE(ah, AR_RTC_RESET, 0);
1543         REG_WRITE(ah, AR_RTC_RESET, 1);
1544
1545         if (!ath9k_hw_wait(ah,
1546                            AR_RTC_STATUS,
1547                            AR_RTC_STATUS_M,
1548                            AR_RTC_STATUS_ON)) {
1549                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1550                 return false;
1551         }
1552
1553         ath9k_hw_read_revisions(ah);
1554
1555         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1556 }
1557
1558 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1559 {
1560         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1561                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1562
1563         switch (type) {
1564         case ATH9K_RESET_POWER_ON:
1565                 return ath9k_hw_set_reset_power_on(ah);
1566                 break;
1567         case ATH9K_RESET_WARM:
1568         case ATH9K_RESET_COLD:
1569                 return ath9k_hw_set_reset(ah, type);
1570                 break;
1571         default:
1572                 return false;
1573         }
1574 }
1575
1576 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1577                               enum ath9k_ht_macmode macmode)
1578 {
1579         u32 phymode;
1580         u32 enableDacFifo = 0;
1581         struct ath_hal_5416 *ahp = AH5416(ah);
1582
1583         if (AR_SREV_9285_10_OR_LATER(ah))
1584                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1585                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1586
1587         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1588                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1589
1590         if (IS_CHAN_HT40(chan)) {
1591                 phymode |= AR_PHY_FC_DYN2040_EN;
1592
1593                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1594                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1595                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1596
1597                 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1598                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1599         }
1600         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1601
1602         ath9k_hw_set11nmac2040(ah, macmode);
1603
1604         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1605         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1606 }
1607
1608 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1609                                 struct ath9k_channel *chan)
1610 {
1611         struct ath_hal_5416 *ahp = AH5416(ah);
1612
1613         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1614                 return false;
1615
1616         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1617                 return false;
1618
1619         ahp->ah_chipFullSleep = false;
1620
1621         ath9k_hw_init_pll(ah, chan);
1622
1623         ath9k_hw_set_rfmode(ah, chan);
1624
1625         return true;
1626 }
1627
1628 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1629                                     struct ath9k_channel *chan,
1630                                     enum ath9k_ht_macmode macmode)
1631 {
1632         struct ieee80211_channel *channel = chan->chan;
1633         u32 synthDelay, qnum;
1634
1635         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1636                 if (ath9k_hw_numtxpending(ah, qnum)) {
1637                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1638                                 "Transmit frames pending on queue %d\n", qnum);
1639                         return false;
1640                 }
1641         }
1642
1643         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1644         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1645                            AR_PHY_RFBUS_GRANT_EN)) {
1646                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1647                         "Could not kill baseband RX\n");
1648                 return false;
1649         }
1650
1651         ath9k_hw_set_regs(ah, chan, macmode);
1652
1653         if (AR_SREV_9280_10_OR_LATER(ah)) {
1654                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1655                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1656                                 "failed to set channel\n");
1657                         return false;
1658                 }
1659         } else {
1660                 if (!(ath9k_hw_set_channel(ah, chan))) {
1661                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1662                                 "failed to set channel\n");
1663                         return false;
1664                 }
1665         }
1666
1667         if (ath9k_hw_set_txpower(ah, chan,
1668                                  ath9k_regd_get_ctl(ah, chan),
1669                                  channel->max_antenna_gain * 2,
1670                                  channel->max_power * 2,
1671                                  min((u32) MAX_RATE_POWER,
1672                                      (u32) ah->ah_powerLimit)) != 0) {
1673                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1674                         "error init'ing transmit power\n");
1675                 return false;
1676         }
1677
1678         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1679         if (IS_CHAN_B(chan))
1680                 synthDelay = (4 * synthDelay) / 22;
1681         else
1682                 synthDelay /= 10;
1683
1684         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1685
1686         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1687
1688         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1689                 ath9k_hw_set_delta_slope(ah, chan);
1690
1691         if (AR_SREV_9280_10_OR_LATER(ah))
1692                 ath9k_hw_9280_spur_mitigate(ah, chan);
1693         else
1694                 ath9k_hw_spur_mitigate(ah, chan);
1695
1696         if (!chan->oneTimeCalsDone)
1697                 chan->oneTimeCalsDone = true;
1698
1699         return true;
1700 }
1701
1702 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1703 {
1704         int bb_spur = AR_NO_SPUR;
1705         int freq;
1706         int bin, cur_bin;
1707         int bb_spur_off, spur_subchannel_sd;
1708         int spur_freq_sd;
1709         int spur_delta_phase;
1710         int denominator;
1711         int upper, lower, cur_vit_mask;
1712         int tmp, newVal;
1713         int i;
1714         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1715                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1716         };
1717         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1718                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1719         };
1720         int inc[4] = { 0, 100, 0, 0 };
1721         struct chan_centers centers;
1722
1723         int8_t mask_m[123];
1724         int8_t mask_p[123];
1725         int8_t mask_amt;
1726         int tmp_mask;
1727         int cur_bb_spur;
1728         bool is2GHz = IS_CHAN_2GHZ(chan);
1729
1730         memset(&mask_m, 0, sizeof(int8_t) * 123);
1731         memset(&mask_p, 0, sizeof(int8_t) * 123);
1732
1733         ath9k_hw_get_channel_centers(ah, chan, &centers);
1734         freq = centers.synth_center;
1735
1736         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1737         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1738                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1739
1740                 if (is2GHz)
1741                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1742                 else
1743                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1744
1745                 if (AR_NO_SPUR == cur_bb_spur)
1746                         break;
1747                 cur_bb_spur = cur_bb_spur - freq;
1748
1749                 if (IS_CHAN_HT40(chan)) {
1750                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1751                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1752                                 bb_spur = cur_bb_spur;
1753                                 break;
1754                         }
1755                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1756                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1757                         bb_spur = cur_bb_spur;
1758                         break;
1759                 }
1760         }
1761
1762         if (AR_NO_SPUR == bb_spur) {
1763                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1764                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1765                 return;
1766         } else {
1767                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1768                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1769         }
1770
1771         bin = bb_spur * 320;
1772
1773         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1774
1775         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1776                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1777                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1778                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1779         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1780
1781         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1782                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1783                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1784                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1785                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1786         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1787
1788         if (IS_CHAN_HT40(chan)) {
1789                 if (bb_spur < 0) {
1790                         spur_subchannel_sd = 1;
1791                         bb_spur_off = bb_spur + 10;
1792                 } else {
1793                         spur_subchannel_sd = 0;
1794                         bb_spur_off = bb_spur - 10;
1795                 }
1796         } else {
1797                 spur_subchannel_sd = 0;
1798                 bb_spur_off = bb_spur;
1799         }
1800
1801         if (IS_CHAN_HT40(chan))
1802                 spur_delta_phase =
1803                         ((bb_spur * 262144) /
1804                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1805         else
1806                 spur_delta_phase =
1807                         ((bb_spur * 524288) /
1808                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1809
1810         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1811         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1812
1813         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1814                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1815                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1816         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1817
1818         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1819         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1820
1821         cur_bin = -6000;
1822         upper = bin + 100;
1823         lower = bin - 100;
1824
1825         for (i = 0; i < 4; i++) {
1826                 int pilot_mask = 0;
1827                 int chan_mask = 0;
1828                 int bp = 0;
1829                 for (bp = 0; bp < 30; bp++) {
1830                         if ((cur_bin > lower) && (cur_bin < upper)) {
1831                                 pilot_mask = pilot_mask | 0x1 << bp;
1832                                 chan_mask = chan_mask | 0x1 << bp;
1833                         }
1834                         cur_bin += 100;
1835                 }
1836                 cur_bin += inc[i];
1837                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1838                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1839         }
1840
1841         cur_vit_mask = 6100;
1842         upper = bin + 120;
1843         lower = bin - 120;
1844
1845         for (i = 0; i < 123; i++) {
1846                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1847
1848                         /* workaround for gcc bug #37014 */
1849                         volatile int tmp_v = abs(cur_vit_mask - bin);
1850
1851                         if (tmp_v < 75)
1852                                 mask_amt = 1;
1853                         else
1854                                 mask_amt = 0;
1855                         if (cur_vit_mask < 0)
1856                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1857                         else
1858                                 mask_p[cur_vit_mask / 100] = mask_amt;
1859                 }
1860                 cur_vit_mask -= 100;
1861         }
1862
1863         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1864                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1865                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1866                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1867                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1868                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1869                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1870                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1871         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1872         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1873
1874         tmp_mask = (mask_m[31] << 28)
1875                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1876                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1877                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1878                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1879                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1880                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1881                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1882         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1883         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1884
1885         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1886                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1887                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1888                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1889                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1890                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1891                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1892                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1893         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1894         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1895
1896         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1897                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1898                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1899                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1900                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1901                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1902                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1903                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1904         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1905         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1906
1907         tmp_mask = (mask_p[15] << 28)
1908                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1909                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1910                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1911                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1912                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1913                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1914                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1915         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1916         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1917
1918         tmp_mask = (mask_p[30] << 28)
1919                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1920                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1921                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1922                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1923                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1924                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1925                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1926         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1927         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1928
1929         tmp_mask = (mask_p[45] << 28)
1930                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1931                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1932                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1933                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1934                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1935                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1936                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1937         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1938         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1939
1940         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1941                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1942                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1943                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1944                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1945                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1946                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1947                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1948         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1949         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1950 }
1951
1952 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1953 {
1954         int bb_spur = AR_NO_SPUR;
1955         int bin, cur_bin;
1956         int spur_freq_sd;
1957         int spur_delta_phase;
1958         int denominator;
1959         int upper, lower, cur_vit_mask;
1960         int tmp, new;
1961         int i;
1962         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1963                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1964         };
1965         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1966                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1967         };
1968         int inc[4] = { 0, 100, 0, 0 };
1969
1970         int8_t mask_m[123];
1971         int8_t mask_p[123];
1972         int8_t mask_amt;
1973         int tmp_mask;
1974         int cur_bb_spur;
1975         bool is2GHz = IS_CHAN_2GHZ(chan);
1976
1977         memset(&mask_m, 0, sizeof(int8_t) * 123);
1978         memset(&mask_p, 0, sizeof(int8_t) * 123);
1979
1980         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1981                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1982                 if (AR_NO_SPUR == cur_bb_spur)
1983                         break;
1984                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1985                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1986                         bb_spur = cur_bb_spur;
1987                         break;
1988                 }
1989         }
1990
1991         if (AR_NO_SPUR == bb_spur)
1992                 return;
1993
1994         bin = bb_spur * 32;
1995
1996         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1997         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1998                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1999                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2000                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2001
2002         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2003
2004         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2005                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2006                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2007                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2008                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2009         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2010
2011         spur_delta_phase = ((bb_spur * 524288) / 100) &
2012                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2013
2014         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2015         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2016
2017         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2018                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2019                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2020         REG_WRITE(ah, AR_PHY_TIMING11, new);
2021
2022         cur_bin = -6000;
2023         upper = bin + 100;
2024         lower = bin - 100;
2025
2026         for (i = 0; i < 4; i++) {
2027                 int pilot_mask = 0;
2028                 int chan_mask = 0;
2029                 int bp = 0;
2030                 for (bp = 0; bp < 30; bp++) {
2031                         if ((cur_bin > lower) && (cur_bin < upper)) {
2032                                 pilot_mask = pilot_mask | 0x1 << bp;
2033                                 chan_mask = chan_mask | 0x1 << bp;
2034                         }
2035                         cur_bin += 100;
2036                 }
2037                 cur_bin += inc[i];
2038                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2039                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2040         }
2041
2042         cur_vit_mask = 6100;
2043         upper = bin + 120;
2044         lower = bin - 120;
2045
2046         for (i = 0; i < 123; i++) {
2047                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2048
2049                         /* workaround for gcc bug #37014 */
2050                         volatile int tmp_v = abs(cur_vit_mask - bin);
2051
2052                         if (tmp_v < 75)
2053                                 mask_amt = 1;
2054                         else
2055                                 mask_amt = 0;
2056                         if (cur_vit_mask < 0)
2057                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2058                         else
2059                                 mask_p[cur_vit_mask / 100] = mask_amt;
2060                 }
2061                 cur_vit_mask -= 100;
2062         }
2063
2064         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2065                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2066                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2067                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2068                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2069                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2070                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2071                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2072         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2073         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2074
2075         tmp_mask = (mask_m[31] << 28)
2076                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2077                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2078                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2079                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2080                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2081                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2082                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2083         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2084         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2085
2086         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2087                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2088                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2089                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2090                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2091                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2092                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2093                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2094         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2095         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2096
2097         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2098                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2099                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2100                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2101                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2102                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2103                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2104                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2105         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2106         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2107
2108         tmp_mask = (mask_p[15] << 28)
2109                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2110                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2111                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2112                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2113                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2114                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2115                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2116         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2117         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2118
2119         tmp_mask = (mask_p[30] << 28)
2120                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2121                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2122                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2123                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2124                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2125                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2126                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2127         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2128         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2129
2130         tmp_mask = (mask_p[45] << 28)
2131                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2132                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2133                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2134                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2135                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2136                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2137                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2138         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2139         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2140
2141         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2142                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2143                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2144                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2145                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2146                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2147                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2148                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2149         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2150         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2151 }
2152
2153 int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2154                     bool bChannelChange)
2155 {
2156         u32 saveLedState;
2157         struct ath_softc *sc = ah->ah_sc;
2158         struct ath_hal_5416 *ahp = AH5416(ah);
2159         struct ath9k_channel *curchan = ah->ah_curchan;
2160         u32 saveDefAntenna;
2161         u32 macStaId1;
2162         int i, rx_chainmask, r;
2163
2164         ahp->ah_extprotspacing = sc->sc_ht_extprotspacing;
2165         ahp->ah_txchainmask = sc->sc_tx_chainmask;
2166         ahp->ah_rxchainmask = sc->sc_rx_chainmask;
2167
2168         if (AR_SREV_9280(ah)) {
2169                 ahp->ah_txchainmask &= 0x3;
2170                 ahp->ah_rxchainmask &= 0x3;
2171         }
2172
2173         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2174                 return -EIO;
2175
2176         if (curchan)
2177                 ath9k_hw_getnf(ah, curchan);
2178
2179         if (bChannelChange &&
2180             (ahp->ah_chipFullSleep != true) &&
2181             (ah->ah_curchan != NULL) &&
2182             (chan->channel != ah->ah_curchan->channel) &&
2183             ((chan->channelFlags & CHANNEL_ALL) ==
2184              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2185             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2186                                    !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2187
2188                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2189                         ath9k_hw_loadnf(ah, ah->ah_curchan);
2190                         ath9k_hw_start_nfcal(ah);
2191                         return 0;
2192                 }
2193         }
2194
2195         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2196         if (saveDefAntenna == 0)
2197                 saveDefAntenna = 1;
2198
2199         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2200
2201         saveLedState = REG_READ(ah, AR_CFG_LED) &
2202                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2203                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2204
2205         ath9k_hw_mark_phy_inactive(ah);
2206
2207         if (!ath9k_hw_chip_reset(ah, chan)) {
2208                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2209                 return -EINVAL;
2210         }
2211
2212         if (AR_SREV_9280_10_OR_LATER(ah))
2213                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2214
2215         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2216         if (r)
2217                 return r;
2218
2219         /* Setup MFP options for CCMP */
2220         if (AR_SREV_9280_20_OR_LATER(ah)) {
2221                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2222                  * frames when constructing CCMP AAD. */
2223                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2224                               0xc7ff);
2225                 ah->sw_mgmt_crypto = false;
2226         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2227                 /* Disable hardware crypto for management frames */
2228                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2229                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2230                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2231                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2232                 ah->sw_mgmt_crypto = true;
2233         } else
2234                 ah->sw_mgmt_crypto = true;
2235
2236         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2237                 ath9k_hw_set_delta_slope(ah, chan);
2238
2239         if (AR_SREV_9280_10_OR_LATER(ah))
2240                 ath9k_hw_9280_spur_mitigate(ah, chan);
2241         else
2242                 ath9k_hw_spur_mitigate(ah, chan);
2243
2244         if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2245                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2246                         "error setting board options\n");
2247                 return -EIO;
2248         }
2249
2250         ath9k_hw_decrease_chain_power(ah, chan);
2251
2252         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2253         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2254                   | macStaId1
2255                   | AR_STA_ID1_RTS_USE_DEF
2256                   | (ah->ah_config.
2257                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2258                   | ahp->ah_staId1Defaults);
2259         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2260
2261         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2262         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2263
2264         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2265
2266         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2267         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2268                   ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2269
2270         REG_WRITE(ah, AR_ISR, ~0);
2271
2272         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2273
2274         if (AR_SREV_9280_10_OR_LATER(ah)) {
2275                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2276                         return -EIO;
2277         } else {
2278                 if (!(ath9k_hw_set_channel(ah, chan)))
2279                         return -EIO;
2280         }
2281
2282         for (i = 0; i < AR_NUM_DCU; i++)
2283                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2284
2285         ahp->ah_intrTxqs = 0;
2286         for (i = 0; i < ah->ah_caps.total_queues; i++)
2287                 ath9k_hw_resettxqueue(ah, i);
2288
2289         ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2290         ath9k_hw_init_qos(ah);
2291
2292 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2293         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2294                 ath9k_enable_rfkill(ah);
2295 #endif
2296         ath9k_hw_init_user_settings(ah);
2297
2298         REG_WRITE(ah, AR_STA_ID1,
2299                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2300
2301         ath9k_hw_set_dma(ah);
2302
2303         REG_WRITE(ah, AR_OBS, 8);
2304
2305         if (ahp->ah_intrMitigation) {
2306
2307                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2308                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2309         }
2310
2311         ath9k_hw_init_bb(ah, chan);
2312
2313         if (!ath9k_hw_init_cal(ah, chan))
2314                 return -EIO;;
2315
2316         rx_chainmask = ahp->ah_rxchainmask;
2317         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2318                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2319                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2320         }
2321
2322         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2323
2324         if (AR_SREV_9100(ah)) {
2325                 u32 mask;
2326                 mask = REG_READ(ah, AR_CFG);
2327                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2328                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2329                                 "CFG Byte Swap Set 0x%x\n", mask);
2330                 } else {
2331                         mask =
2332                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2333                         REG_WRITE(ah, AR_CFG, mask);
2334                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2335                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2336                 }
2337         } else {
2338 #ifdef __BIG_ENDIAN
2339                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2340 #endif
2341         }
2342
2343         return 0;
2344 }
2345
2346 /************************/
2347 /* Key Cache Management */
2348 /************************/
2349
2350 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2351 {
2352         u32 keyType;
2353
2354         if (entry >= ah->ah_caps.keycache_size) {
2355                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2356                         "entry %u out of range\n", entry);
2357                 return false;
2358         }
2359
2360         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2361
2362         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2363         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2364         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2365         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2366         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2367         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2368         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2369         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2370
2371         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2372                 u16 micentry = entry + 64;
2373
2374                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2375                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2376                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2377                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2378
2379         }
2380
2381         if (ah->ah_curchan == NULL)
2382                 return true;
2383
2384         return true;
2385 }
2386
2387 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2388 {
2389         u32 macHi, macLo;
2390
2391         if (entry >= ah->ah_caps.keycache_size) {
2392                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2393                         "entry %u out of range\n", entry);
2394                 return false;
2395         }
2396
2397         if (mac != NULL) {
2398                 macHi = (mac[5] << 8) | mac[4];
2399                 macLo = (mac[3] << 24) |
2400                         (mac[2] << 16) |
2401                         (mac[1] << 8) |
2402                         mac[0];
2403                 macLo >>= 1;
2404                 macLo |= (macHi & 1) << 31;
2405                 macHi >>= 1;
2406         } else {
2407                 macLo = macHi = 0;
2408         }
2409         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2410         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2411
2412         return true;
2413 }
2414
2415 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2416                                  const struct ath9k_keyval *k,
2417                                  const u8 *mac, int xorKey)
2418 {
2419         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2420         u32 key0, key1, key2, key3, key4;
2421         u32 keyType;
2422         u32 xorMask = xorKey ?
2423                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2424                  | ATH9K_KEY_XOR) : 0;
2425         struct ath_hal_5416 *ahp = AH5416(ah);
2426
2427         if (entry >= pCap->keycache_size) {
2428                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2429                         "entry %u out of range\n", entry);
2430                 return false;
2431         }
2432
2433         switch (k->kv_type) {
2434         case ATH9K_CIPHER_AES_OCB:
2435                 keyType = AR_KEYTABLE_TYPE_AES;
2436                 break;
2437         case ATH9K_CIPHER_AES_CCM:
2438                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2439                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2440                                 "AES-CCM not supported by mac rev 0x%x\n",
2441                                 ah->ah_macRev);
2442                         return false;
2443                 }
2444                 keyType = AR_KEYTABLE_TYPE_CCM;
2445                 break;
2446         case ATH9K_CIPHER_TKIP:
2447                 keyType = AR_KEYTABLE_TYPE_TKIP;
2448                 if (ATH9K_IS_MIC_ENABLED(ah)
2449                     && entry + 64 >= pCap->keycache_size) {
2450                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2451                                 "entry %u inappropriate for TKIP\n", entry);
2452                         return false;
2453                 }
2454                 break;
2455         case ATH9K_CIPHER_WEP:
2456                 if (k->kv_len < LEN_WEP40) {
2457                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2458                                 "WEP key length %u too small\n", k->kv_len);
2459                         return false;
2460                 }
2461                 if (k->kv_len <= LEN_WEP40)
2462                         keyType = AR_KEYTABLE_TYPE_40;
2463                 else if (k->kv_len <= LEN_WEP104)
2464                         keyType = AR_KEYTABLE_TYPE_104;
2465                 else
2466                         keyType = AR_KEYTABLE_TYPE_128;
2467                 break;
2468         case ATH9K_CIPHER_CLR:
2469                 keyType = AR_KEYTABLE_TYPE_CLR;
2470                 break;
2471         default:
2472                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2473                         "cipher %u not supported\n", k->kv_type);
2474                 return false;
2475         }
2476
2477         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2478         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2479         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2480         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2481         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2482         if (k->kv_len <= LEN_WEP104)
2483                 key4 &= 0xff;
2484
2485         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2486                 u16 micentry = entry + 64;
2487
2488                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2489                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2490                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2491                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2492                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2493                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2494                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2495
2496                 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2497                         u32 mic0, mic1, mic2, mic3, mic4;
2498
2499                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2500                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2501                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2502                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2503                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2504                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2505                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2506                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2507                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2508                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2509                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2510                                   AR_KEYTABLE_TYPE_CLR);
2511
2512                 } else {
2513                         u32 mic0, mic2;
2514
2515                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2516                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2517                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2518                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2519                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2520                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2521                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2522                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2523                                   AR_KEYTABLE_TYPE_CLR);
2524                 }
2525                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2526                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2527                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2528                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2529         } else {
2530                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2531                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2532                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2533                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2534                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2535                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2536
2537                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2538         }
2539
2540         if (ah->ah_curchan == NULL)
2541                 return true;
2542
2543         return true;
2544 }
2545
2546 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2547 {
2548         if (entry < ah->ah_caps.keycache_size) {
2549                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2550                 if (val & AR_KEYTABLE_VALID)
2551                         return true;
2552         }
2553         return false;
2554 }
2555
2556 /******************************/
2557 /* Power Management (Chipset) */
2558 /******************************/
2559
2560 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2561 {
2562         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2563         if (setChip) {
2564                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2565                             AR_RTC_FORCE_WAKE_EN);
2566                 if (!AR_SREV_9100(ah))
2567                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2568
2569                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2570                             AR_RTC_RESET_EN);
2571         }
2572 }
2573
2574 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2575 {
2576         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577         if (setChip) {
2578                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2579
2580                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2581                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2582                                   AR_RTC_FORCE_WAKE_ON_INT);
2583                 } else {
2584                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2585                                     AR_RTC_FORCE_WAKE_EN);
2586                 }
2587         }
2588 }
2589
2590 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2591                                      int setChip)
2592 {
2593         u32 val;
2594         int i;
2595
2596         if (setChip) {
2597                 if ((REG_READ(ah, AR_RTC_STATUS) &
2598                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2599                         if (ath9k_hw_set_reset_reg(ah,
2600                                            ATH9K_RESET_POWER_ON) != true) {
2601                                 return false;
2602                         }
2603                 }
2604                 if (AR_SREV_9100(ah))
2605                         REG_SET_BIT(ah, AR_RTC_RESET,
2606                                     AR_RTC_RESET_EN);
2607
2608                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2609                             AR_RTC_FORCE_WAKE_EN);
2610                 udelay(50);
2611
2612                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2613                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2614                         if (val == AR_RTC_STATUS_ON)
2615                                 break;
2616                         udelay(50);
2617                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2618                                     AR_RTC_FORCE_WAKE_EN);
2619                 }
2620                 if (i == 0) {
2621                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2622                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2623                         return false;
2624                 }
2625         }
2626
2627         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2628
2629         return true;
2630 }
2631
2632 bool ath9k_hw_setpower(struct ath_hal *ah,
2633                        enum ath9k_power_mode mode)
2634 {
2635         struct ath_hal_5416 *ahp = AH5416(ah);
2636         static const char *modes[] = {
2637                 "AWAKE",
2638                 "FULL-SLEEP",
2639                 "NETWORK SLEEP",
2640                 "UNDEFINED"
2641         };
2642         int status = true, setChip = true;
2643
2644         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2645                 modes[ah->ah_power_mode], modes[mode],
2646                 setChip ? "set chip " : "");
2647
2648         switch (mode) {
2649         case ATH9K_PM_AWAKE:
2650                 status = ath9k_hw_set_power_awake(ah, setChip);
2651                 break;
2652         case ATH9K_PM_FULL_SLEEP:
2653                 ath9k_set_power_sleep(ah, setChip);
2654                 ahp->ah_chipFullSleep = true;
2655                 break;
2656         case ATH9K_PM_NETWORK_SLEEP:
2657                 ath9k_set_power_network_sleep(ah, setChip);
2658                 break;
2659         default:
2660                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2661                         "Unknown power mode %u\n", mode);
2662                 return false;
2663         }
2664         ah->ah_power_mode = mode;
2665
2666         return status;
2667 }
2668
2669 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2670 {
2671         struct ath_hal_5416 *ahp = AH5416(ah);
2672         u8 i;
2673
2674         if (ah->ah_isPciExpress != true)
2675                 return;
2676
2677         if (ah->ah_config.pcie_powersave_enable == 2)
2678                 return;
2679
2680         if (restore)
2681                 return;
2682
2683         if (AR_SREV_9280_20_OR_LATER(ah)) {
2684                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2685                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2686                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2687                 }
2688                 udelay(1000);
2689         } else if (AR_SREV_9280(ah) &&
2690                    (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2691                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2692                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2693
2694                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2695                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2696                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2697
2698                 if (ah->ah_config.pcie_clock_req)
2699                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2700                 else
2701                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2702
2703                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2704                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2705                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2706
2707                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2708
2709                 udelay(1000);
2710         } else {
2711                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2712                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2713                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2714                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2715                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2716                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2717                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2718                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2719                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2720                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2721         }
2722
2723         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2724
2725         if (ah->ah_config.pcie_waen) {
2726                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2727         } else {
2728                 if (AR_SREV_9285(ah))
2729                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2730                 else if (AR_SREV_9280(ah))
2731                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2732                 else
2733                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2734         }
2735
2736 }
2737
2738 /**********************/
2739 /* Interrupt Handling */
2740 /**********************/
2741
2742 bool ath9k_hw_intrpend(struct ath_hal *ah)
2743 {
2744         u32 host_isr;
2745
2746         if (AR_SREV_9100(ah))
2747                 return true;
2748
2749         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2750         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2751                 return true;
2752
2753         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2754         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2755             && (host_isr != AR_INTR_SPURIOUS))
2756                 return true;
2757
2758         return false;
2759 }
2760
2761 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2762 {
2763         u32 isr = 0;
2764         u32 mask2 = 0;
2765         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2766         u32 sync_cause = 0;
2767         bool fatal_int = false;
2768         struct ath_hal_5416 *ahp = AH5416(ah);
2769
2770         if (!AR_SREV_9100(ah)) {
2771                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2772                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2773                             == AR_RTC_STATUS_ON) {
2774                                 isr = REG_READ(ah, AR_ISR);
2775                         }
2776                 }
2777
2778                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2779                         AR_INTR_SYNC_DEFAULT;
2780
2781                 *masked = 0;
2782
2783                 if (!isr && !sync_cause)
2784                         return false;
2785         } else {
2786                 *masked = 0;
2787                 isr = REG_READ(ah, AR_ISR);
2788         }
2789
2790         if (isr) {
2791                 if (isr & AR_ISR_BCNMISC) {
2792                         u32 isr2;
2793                         isr2 = REG_READ(ah, AR_ISR_S2);
2794                         if (isr2 & AR_ISR_S2_TIM)
2795                                 mask2 |= ATH9K_INT_TIM;
2796                         if (isr2 & AR_ISR_S2_DTIM)
2797                                 mask2 |= ATH9K_INT_DTIM;
2798                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2799                                 mask2 |= ATH9K_INT_DTIMSYNC;
2800                         if (isr2 & (AR_ISR_S2_CABEND))
2801                                 mask2 |= ATH9K_INT_CABEND;
2802                         if (isr2 & AR_ISR_S2_GTT)
2803                                 mask2 |= ATH9K_INT_GTT;
2804                         if (isr2 & AR_ISR_S2_CST)
2805                                 mask2 |= ATH9K_INT_CST;
2806                 }
2807
2808                 isr = REG_READ(ah, AR_ISR_RAC);
2809                 if (isr == 0xffffffff) {
2810                         *masked = 0;
2811                         return false;
2812                 }
2813
2814                 *masked = isr & ATH9K_INT_COMMON;
2815
2816                 if (ahp->ah_intrMitigation) {
2817                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2818                                 *masked |= ATH9K_INT_RX;
2819                 }
2820
2821                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2822                         *masked |= ATH9K_INT_RX;
2823                 if (isr &
2824                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2825                      AR_ISR_TXEOL)) {
2826                         u32 s0_s, s1_s;
2827
2828                         *masked |= ATH9K_INT_TX;
2829
2830                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2831                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2832                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2833
2834                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2835                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2836                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2837                 }
2838
2839                 if (isr & AR_ISR_RXORN) {
2840                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2841                                 "receive FIFO overrun interrupt\n");
2842                 }
2843
2844                 if (!AR_SREV_9100(ah)) {
2845                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2846                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2847                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2848                                         *masked |= ATH9K_INT_TIM_TIMER;
2849                         }
2850                 }
2851
2852                 *masked |= mask2;
2853         }
2854
2855         if (AR_SREV_9100(ah))
2856                 return true;
2857
2858         if (sync_cause) {
2859                 fatal_int =
2860                         (sync_cause &
2861                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2862                         ? true : false;
2863
2864                 if (fatal_int) {
2865                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2866                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2867                                         "received PCI FATAL interrupt\n");
2868                         }
2869                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2870                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2871                                         "received PCI PERR interrupt\n");
2872                         }
2873                 }
2874                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2875                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2876                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2877                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2878                         REG_WRITE(ah, AR_RC, 0);
2879                         *masked |= ATH9K_INT_FATAL;
2880                 }
2881                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2882                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2883                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2884                 }
2885
2886                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2887                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2888         }
2889
2890         return true;
2891 }
2892
2893 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2894 {
2895         return AH5416(ah)->ah_maskReg;
2896 }
2897
2898 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2899 {
2900         struct ath_hal_5416 *ahp = AH5416(ah);
2901         u32 omask = ahp->ah_maskReg;
2902         u32 mask, mask2;
2903         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2904
2905         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2906
2907         if (omask & ATH9K_INT_GLOBAL) {
2908                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2909                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2910                 (void) REG_READ(ah, AR_IER);
2911                 if (!AR_SREV_9100(ah)) {
2912                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2913                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2914
2915                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2916                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2917                 }
2918         }
2919
2920         mask = ints & ATH9K_INT_COMMON;
2921         mask2 = 0;
2922
2923         if (ints & ATH9K_INT_TX) {
2924                 if (ahp->ah_txOkInterruptMask)
2925                         mask |= AR_IMR_TXOK;
2926                 if (ahp->ah_txDescInterruptMask)
2927                         mask |= AR_IMR_TXDESC;
2928                 if (ahp->ah_txErrInterruptMask)
2929                         mask |= AR_IMR_TXERR;
2930                 if (ahp->ah_txEolInterruptMask)
2931                         mask |= AR_IMR_TXEOL;
2932         }
2933         if (ints & ATH9K_INT_RX) {
2934                 mask |= AR_IMR_RXERR;
2935                 if (ahp->ah_intrMitigation)
2936                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2937                 else
2938                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2939                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2940                         mask |= AR_IMR_GENTMR;
2941         }
2942
2943         if (ints & (ATH9K_INT_BMISC)) {
2944                 mask |= AR_IMR_BCNMISC;
2945                 if (ints & ATH9K_INT_TIM)
2946                         mask2 |= AR_IMR_S2_TIM;
2947                 if (ints & ATH9K_INT_DTIM)
2948                         mask2 |= AR_IMR_S2_DTIM;
2949                 if (ints & ATH9K_INT_DTIMSYNC)
2950                         mask2 |= AR_IMR_S2_DTIMSYNC;
2951                 if (ints & ATH9K_INT_CABEND)
2952                         mask2 |= (AR_IMR_S2_CABEND);
2953         }
2954
2955         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2956                 mask |= AR_IMR_BCNMISC;
2957                 if (ints & ATH9K_INT_GTT)
2958                         mask2 |= AR_IMR_S2_GTT;
2959                 if (ints & ATH9K_INT_CST)
2960                         mask2 |= AR_IMR_S2_CST;
2961         }
2962
2963         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2964         REG_WRITE(ah, AR_IMR, mask);
2965         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2966                                            AR_IMR_S2_DTIM |
2967                                            AR_IMR_S2_DTIMSYNC |
2968                                            AR_IMR_S2_CABEND |
2969                                            AR_IMR_S2_CABTO |
2970                                            AR_IMR_S2_TSFOOR |
2971                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
2972         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2973         ahp->ah_maskReg = ints;
2974
2975         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2976                 if (ints & ATH9K_INT_TIM_TIMER)
2977                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2978                 else
2979                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2980         }
2981
2982         if (ints & ATH9K_INT_GLOBAL) {
2983                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
2984                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2985                 if (!AR_SREV_9100(ah)) {
2986                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2987                                   AR_INTR_MAC_IRQ);
2988                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2989
2990
2991                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2992                                   AR_INTR_SYNC_DEFAULT);
2993                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2994                                   AR_INTR_SYNC_DEFAULT);
2995                 }
2996                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2997                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2998         }
2999
3000         return omask;
3001 }
3002
3003 /*******************/
3004 /* Beacon Handling */
3005 /*******************/
3006
3007 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3008 {
3009         struct ath_hal_5416 *ahp = AH5416(ah);
3010         int flags = 0;
3011
3012         ahp->ah_beaconInterval = beacon_period;
3013
3014         switch (ah->ah_opmode) {
3015         case NL80211_IFTYPE_STATION:
3016         case NL80211_IFTYPE_MONITOR:
3017                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3018                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3019                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3020                 flags |= AR_TBTT_TIMER_EN;
3021                 break;
3022         case NL80211_IFTYPE_ADHOC:
3023                 REG_SET_BIT(ah, AR_TXCFG,
3024                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3025                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3026                           TU_TO_USEC(next_beacon +
3027                                      (ahp->ah_atimWindow ? ahp->
3028                                       ah_atimWindow : 1)));
3029                 flags |= AR_NDP_TIMER_EN;
3030         case NL80211_IFTYPE_AP:
3031                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3032                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3033                           TU_TO_USEC(next_beacon -
3034                                      ah->ah_config.
3035                                      dma_beacon_response_time));
3036                 REG_WRITE(ah, AR_NEXT_SWBA,
3037                           TU_TO_USEC(next_beacon -
3038                                      ah->ah_config.
3039                                      sw_beacon_response_time));
3040                 flags |=
3041                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3042                 break;
3043         default:
3044                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3045                         "%s: unsupported opmode: %d\n",
3046                         __func__, ah->ah_opmode);
3047                 return;
3048                 break;
3049         }
3050
3051         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3052         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3053         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3054         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3055
3056         beacon_period &= ~ATH9K_BEACON_ENA;
3057         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3058                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3059                 ath9k_hw_reset_tsf(ah);
3060         }
3061
3062         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3063 }
3064
3065 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3066                                     const struct ath9k_beacon_state *bs)
3067 {
3068         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3069         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3070
3071         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3072
3073         REG_WRITE(ah, AR_BEACON_PERIOD,
3074                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3075         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3076                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3077
3078         REG_RMW_FIELD(ah, AR_RSSI_THR,
3079                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3080
3081         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3082
3083         if (bs->bs_sleepduration > beaconintval)
3084                 beaconintval = bs->bs_sleepduration;
3085
3086         dtimperiod = bs->bs_dtimperiod;
3087         if (bs->bs_sleepduration > dtimperiod)
3088                 dtimperiod = bs->bs_sleepduration;
3089
3090         if (beaconintval == dtimperiod)
3091                 nextTbtt = bs->bs_nextdtim;
3092         else
3093                 nextTbtt = bs->bs_nexttbtt;
3094
3095         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3096         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3097         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3098         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3099
3100         REG_WRITE(ah, AR_NEXT_DTIM,
3101                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3102         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3103
3104         REG_WRITE(ah, AR_SLEEP1,
3105                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3106                   | AR_SLEEP1_ASSUME_DTIM);
3107
3108         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3109                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3110         else
3111                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3112
3113         REG_WRITE(ah, AR_SLEEP2,
3114                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3115
3116         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3117         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3118
3119         REG_SET_BIT(ah, AR_TIMER_MODE,
3120                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3121                     AR_DTIM_TIMER_EN);
3122
3123 }
3124
3125 /*******************/
3126 /* HW Capabilities */
3127 /*******************/
3128
3129 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3130 {
3131         struct ath_hal_5416 *ahp = AH5416(ah);
3132         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3133         u16 capField = 0, eeval;
3134
3135         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3136
3137         ah->ah_currentRD = eeval;
3138
3139         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3140         ah->ah_currentRDExt = eeval;
3141
3142         capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3143
3144         if (ah->ah_opmode != NL80211_IFTYPE_AP &&
3145             ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3146                 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3147                         ah->ah_currentRD += 5;
3148                 else if (ah->ah_currentRD == 0x41)
3149                         ah->ah_currentRD = 0x43;
3150                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3151                         "regdomain mapped to 0x%x\n", ah->ah_currentRD);
3152         }
3153
3154         eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3155         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3156
3157         if (eeval & AR5416_OPFLAGS_11A) {
3158                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3159                 if (ah->ah_config.ht_enable) {
3160                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3161                                 set_bit(ATH9K_MODE_11NA_HT20,
3162                                         pCap->wireless_modes);
3163                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3164                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3165                                         pCap->wireless_modes);
3166                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3167                                         pCap->wireless_modes);
3168                         }
3169                 }
3170         }
3171
3172         if (eeval & AR5416_OPFLAGS_11G) {
3173                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3174                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3175                 if (ah->ah_config.ht_enable) {
3176                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3177                                 set_bit(ATH9K_MODE_11NG_HT20,
3178                                         pCap->wireless_modes);
3179                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3180                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3181                                         pCap->wireless_modes);
3182                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3183                                         pCap->wireless_modes);
3184                         }
3185                 }
3186         }
3187
3188         pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3189         if ((ah->ah_isPciExpress)
3190             || (eeval & AR5416_OPFLAGS_11A)) {
3191                 pCap->rx_chainmask =
3192                         ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3193         } else {
3194                 pCap->rx_chainmask =
3195                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3196         }
3197
3198         if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3199                 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3200
3201         pCap->low_2ghz_chan = 2312;
3202         pCap->high_2ghz_chan = 2732;
3203
3204         pCap->low_5ghz_chan = 4920;
3205         pCap->high_5ghz_chan = 6100;
3206
3207         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3208         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3209         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3210
3211         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3212         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3213         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3214
3215         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3216
3217         if (ah->ah_config.ht_enable)
3218                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3219         else
3220                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3221
3222         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3223         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3224         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3225         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3226
3227         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3228                 pCap->total_queues =
3229                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3230         else
3231                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3232
3233         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3234                 pCap->keycache_size =
3235                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3236         else
3237                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3238
3239         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3240         pCap->num_mr_retries = 4;
3241         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3242
3243         if (AR_SREV_9285_10_OR_LATER(ah))
3244                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3245         else if (AR_SREV_9280_10_OR_LATER(ah))
3246                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3247         else
3248                 pCap->num_gpio_pins = AR_NUM_GPIO;
3249
3250         if (AR_SREV_9280_10_OR_LATER(ah)) {
3251                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3252                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3253         } else {
3254                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3255                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3256         }
3257
3258         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3259                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3260                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3261         } else {
3262                 pCap->rts_aggr_limit = (8 * 1024);
3263         }
3264
3265         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3266
3267 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3268         ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3269         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3270                 ah->ah_rfkill_gpio =
3271                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3272                 ah->ah_rfkill_polarity =
3273                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3274
3275                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3276         }
3277 #endif
3278
3279         if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3280             (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3281             (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3282             (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3283             (ah->ah_macVersion == AR_SREV_VERSION_9280))
3284                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3285         else
3286                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3287
3288         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3289                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3290         else
3291                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3292
3293         if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3294                 pCap->reg_cap =
3295                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3296                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3297                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3298                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3299         } else {
3300                 pCap->reg_cap =
3301                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3302                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3303         }
3304
3305         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3306
3307         pCap->num_antcfg_5ghz =
3308                 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3309         pCap->num_antcfg_2ghz =
3310                 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3311
3312         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3313                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3314                 ah->ah_btactive_gpio = 6;
3315                 ah->ah_wlanactive_gpio = 5;
3316         }
3317
3318         return true;
3319 }
3320
3321 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3322                             u32 capability, u32 *result)
3323 {
3324         struct ath_hal_5416 *ahp = AH5416(ah);
3325         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3326
3327         switch (type) {
3328         case ATH9K_CAP_CIPHER:
3329                 switch (capability) {
3330                 case ATH9K_CIPHER_AES_CCM:
3331                 case ATH9K_CIPHER_AES_OCB:
3332                 case ATH9K_CIPHER_TKIP:
3333                 case ATH9K_CIPHER_WEP:
3334                 case ATH9K_CIPHER_MIC:
3335                 case ATH9K_CIPHER_CLR:
3336                         return true;
3337                 default:
3338                         return false;
3339                 }
3340         case ATH9K_CAP_TKIP_MIC:
3341                 switch (capability) {
3342                 case 0:
3343                         return true;
3344                 case 1:
3345                         return (ahp->ah_staId1Defaults &
3346                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3347                         false;
3348                 }
3349         case ATH9K_CAP_TKIP_SPLIT:
3350                 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3351                         false : true;
3352         case ATH9K_CAP_WME_TKIPMIC:
3353                 return 0;
3354         case ATH9K_CAP_PHYCOUNTERS:
3355                 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3356         case ATH9K_CAP_DIVERSITY:
3357                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3358                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3359                         true : false;
3360         case ATH9K_CAP_PHYDIAG:
3361                 return true;
3362         case ATH9K_CAP_MCAST_KEYSRCH:
3363                 switch (capability) {
3364                 case 0:
3365                         return true;
3366                 case 1:
3367                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3368                                 return false;
3369                         } else {
3370                                 return (ahp->ah_staId1Defaults &
3371                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3372                                         false;
3373                         }
3374                 }
3375                 return false;
3376         case ATH9K_CAP_TSF_ADJUST:
3377                 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3378                         true : false;
3379         case ATH9K_CAP_RFSILENT:
3380                 if (capability == 3)
3381                         return false;
3382         case ATH9K_CAP_ANT_CFG_2GHZ:
3383                 *result = pCap->num_antcfg_2ghz;
3384                 return true;
3385         case ATH9K_CAP_ANT_CFG_5GHZ:
3386                 *result = pCap->num_antcfg_5ghz;
3387                 return true;
3388         case ATH9K_CAP_TXPOW:
3389                 switch (capability) {
3390                 case 0:
3391                         return 0;
3392                 case 1:
3393                         *result = ah->ah_powerLimit;
3394                         return 0;
3395                 case 2:
3396                         *result = ah->ah_maxPowerLevel;
3397                         return 0;
3398                 case 3:
3399                         *result = ah->ah_tpScale;
3400                         return 0;
3401                 }
3402                 return false;
3403         default:
3404                 return false;
3405         }
3406 }
3407
3408 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3409                             u32 capability, u32 setting, int *status)
3410 {
3411         struct ath_hal_5416 *ahp = AH5416(ah);
3412         u32 v;
3413
3414         switch (type) {
3415         case ATH9K_CAP_TKIP_MIC:
3416                 if (setting)
3417                         ahp->ah_staId1Defaults |=
3418                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3419                 else
3420                         ahp->ah_staId1Defaults &=
3421                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3422                 return true;
3423         case ATH9K_CAP_DIVERSITY:
3424                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3425                 if (setting)
3426                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3427                 else
3428                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3429                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3430                 return true;
3431         case ATH9K_CAP_MCAST_KEYSRCH:
3432                 if (setting)
3433                         ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3434                 else
3435                         ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3436                 return true;
3437         case ATH9K_CAP_TSF_ADJUST:
3438                 if (setting)
3439                         ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3440                 else
3441                         ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3442                 return true;
3443         default:
3444                 return false;
3445         }
3446 }
3447
3448 /****************************/
3449 /* GPIO / RFKILL / Antennae */
3450 /****************************/
3451
3452 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3453                                          u32 gpio, u32 type)
3454 {
3455         int addr;
3456         u32 gpio_shift, tmp;
3457
3458         if (gpio > 11)
3459                 addr = AR_GPIO_OUTPUT_MUX3;
3460         else if (gpio > 5)
3461                 addr = AR_GPIO_OUTPUT_MUX2;
3462         else
3463                 addr = AR_GPIO_OUTPUT_MUX1;
3464
3465         gpio_shift = (gpio % 6) * 5;
3466
3467         if (AR_SREV_9280_20_OR_LATER(ah)
3468             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3469                 REG_RMW(ah, addr, (type << gpio_shift),
3470                         (0x1f << gpio_shift));
3471         } else {
3472                 tmp = REG_READ(ah, addr);
3473                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3474                 tmp &= ~(0x1f << gpio_shift);
3475                 tmp |= (type << gpio_shift);
3476                 REG_WRITE(ah, addr, tmp);
3477         }
3478 }
3479
3480 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3481 {
3482         u32 gpio_shift;
3483
3484         ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3485
3486         gpio_shift = gpio << 1;
3487
3488         REG_RMW(ah,
3489                 AR_GPIO_OE_OUT,
3490                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3491                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3492 }
3493
3494 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3495 {
3496 #define MS_REG_READ(x, y) \
3497         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3498
3499         if (gpio >= ah->ah_caps.num_gpio_pins)
3500                 return 0xffffffff;
3501
3502         if (AR_SREV_9285_10_OR_LATER(ah))
3503                 return MS_REG_READ(AR9285, gpio) != 0;
3504         else if (AR_SREV_9280_10_OR_LATER(ah))
3505                 return MS_REG_READ(AR928X, gpio) != 0;
3506         else
3507                 return MS_REG_READ(AR, gpio) != 0;
3508 }
3509
3510 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3511                          u32 ah_signal_type)
3512 {
3513         u32 gpio_shift;
3514
3515         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3516
3517         gpio_shift = 2 * gpio;
3518
3519         REG_RMW(ah,
3520                 AR_GPIO_OE_OUT,
3521                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3522                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3523 }
3524
3525 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3526 {
3527         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3528                 AR_GPIO_BIT(gpio));
3529 }
3530
3531 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3532 void ath9k_enable_rfkill(struct ath_hal *ah)
3533 {
3534         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3535                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3536
3537         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3538                     AR_GPIO_INPUT_MUX2_RFSILENT);
3539
3540         ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3541         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3542 }
3543 #endif
3544
3545 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3546 {
3547         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3548 }
3549
3550 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3551 {
3552         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3553 }
3554
3555 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3556                                enum ath9k_ant_setting settings,
3557                                struct ath9k_channel *chan,
3558                                u8 *tx_chainmask,
3559                                u8 *rx_chainmask,
3560                                u8 *antenna_cfgd)
3561 {
3562         struct ath_hal_5416 *ahp = AH5416(ah);
3563         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3564
3565         if (AR_SREV_9280(ah)) {
3566                 if (!tx_chainmask_cfg) {
3567
3568                         tx_chainmask_cfg = *tx_chainmask;
3569                         rx_chainmask_cfg = *rx_chainmask;
3570                 }
3571
3572                 switch (settings) {
3573                 case ATH9K_ANT_FIXED_A:
3574                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3575                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3576                         *antenna_cfgd = true;
3577                         break;
3578                 case ATH9K_ANT_FIXED_B:
3579                         if (ah->ah_caps.tx_chainmask >
3580                             ATH9K_ANTENNA1_CHAINMASK) {
3581                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3582                         }
3583                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3584                         *antenna_cfgd = true;
3585                         break;
3586                 case ATH9K_ANT_VARIABLE:
3587                         *tx_chainmask = tx_chainmask_cfg;
3588                         *rx_chainmask = rx_chainmask_cfg;
3589                         *antenna_cfgd = true;
3590                         break;
3591                 default:
3592                         break;
3593                 }
3594         } else {
3595                 ahp->ah_diversityControl = settings;
3596         }
3597
3598         return true;
3599 }
3600
3601 /*********************/
3602 /* General Operation */
3603 /*********************/
3604
3605 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3606 {
3607         u32 bits = REG_READ(ah, AR_RX_FILTER);
3608         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3609
3610         if (phybits & AR_PHY_ERR_RADAR)
3611                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3612         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3613                 bits |= ATH9K_RX_FILTER_PHYERR;
3614
3615         return bits;
3616 }
3617
3618 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3619 {
3620         u32 phybits;
3621
3622         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3623         phybits = 0;
3624         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3625                 phybits |= AR_PHY_ERR_RADAR;
3626         if (bits & ATH9K_RX_FILTER_PHYERR)
3627                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3628         REG_WRITE(ah, AR_PHY_ERR, phybits);
3629
3630         if (phybits)
3631                 REG_WRITE(ah, AR_RXCFG,
3632                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3633         else
3634                 REG_WRITE(ah, AR_RXCFG,
3635                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3636 }
3637
3638 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3639 {
3640         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3641 }
3642
3643 bool ath9k_hw_disable(struct ath_hal *ah)
3644 {
3645         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3646                 return false;
3647
3648         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3649 }
3650
3651 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3652 {
3653         struct ath9k_channel *chan = ah->ah_curchan;
3654         struct ieee80211_channel *channel = chan->chan;
3655
3656         ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3657
3658         if (ath9k_hw_set_txpower(ah, chan,
3659                                  ath9k_regd_get_ctl(ah, chan),
3660                                  channel->max_antenna_gain * 2,
3661                                  channel->max_power * 2,
3662                                  min((u32) MAX_RATE_POWER,
3663                                      (u32) ah->ah_powerLimit)) != 0)
3664                 return false;
3665
3666         return true;
3667 }
3668
3669 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3670 {
3671         struct ath_hal_5416 *ahp = AH5416(ah);
3672
3673         memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3674 }
3675
3676 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3677 {
3678         struct ath_hal_5416 *ahp = AH5416(ah);
3679
3680         memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3681
3682         return true;
3683 }
3684
3685 void ath9k_hw_setopmode(struct ath_hal *ah)
3686 {
3687         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3688 }
3689
3690 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3691 {
3692         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3693         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3694 }
3695
3696 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3697 {
3698         struct ath_hal_5416 *ahp = AH5416(ah);
3699
3700         memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3701 }
3702
3703 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3704 {
3705         struct ath_hal_5416 *ahp = AH5416(ah);
3706
3707         memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3708
3709         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3710         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3711
3712         return true;
3713 }
3714
3715 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3716 {
3717         struct ath_hal_5416 *ahp = AH5416(ah);
3718
3719         memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3720         ahp->ah_assocId = assocId;
3721
3722         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3723         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3724                   ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3725 }
3726
3727 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3728 {
3729         u64 tsf;
3730
3731         tsf = REG_READ(ah, AR_TSF_U32);
3732         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3733
3734         return tsf;
3735 }
3736
3737 void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64)
3738 {
3739         REG_WRITE(ah, AR_TSF_L32, 0x00000000);
3740         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3741         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3742 }
3743
3744 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3745 {
3746         int count;
3747
3748         count = 0;
3749         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3750                 count++;
3751                 if (count > 10) {
3752                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3753                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3754                         break;
3755                 }
3756                 udelay(10);
3757         }
3758         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3759 }
3760
3761 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3762 {
3763         struct ath_hal_5416 *ahp = AH5416(ah);
3764
3765         if (setting)
3766                 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3767         else
3768                 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3769
3770         return true;
3771 }
3772
3773 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3774 {
3775         struct ath_hal_5416 *ahp = AH5416(ah);
3776
3777         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3778                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3779                 ahp->ah_slottime = (u32) -1;
3780                 return false;
3781         } else {
3782                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3783                 ahp->ah_slottime = us;
3784                 return true;
3785         }
3786 }
3787
3788 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3789 {
3790         u32 macmode;
3791
3792         if (mode == ATH9K_HT_MACMODE_2040 &&
3793             !ah->ah_config.cwm_ignore_extcca)
3794                 macmode = AR_2040_JOINED_RX_CLEAR;
3795         else
3796                 macmode = 0;
3797
3798         REG_WRITE(ah, AR_2040_MODE, macmode);
3799 }
3800
3801 /***************************/
3802 /*  Bluetooth Coexistence  */
3803 /***************************/
3804
3805 void ath9k_hw_btcoex_enable(struct ath_hal *ah)
3806 {
3807         /* connect bt_active to baseband */
3808         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3809                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3810                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3811
3812         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3813                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3814
3815         /* Set input mux for bt_active to gpio pin */
3816         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3817                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3818                         ah->ah_btactive_gpio);
3819
3820         /* Configure the desired gpio port for input */
3821         ath9k_hw_cfg_gpio_input(ah, ah->ah_btactive_gpio);
3822
3823         /* Configure the desired GPIO port for TX_FRAME output */
3824         ath9k_hw_cfg_output(ah, ah->ah_wlanactive_gpio,
3825                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3826 }