2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Low-level vector interface routines
13 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes
14 * it to save wrong values... Be aware!
16 #include <linux/config.h>
19 #include <asm/vfpmacros.h>
20 #include <asm/hardware.h> /* should be moved into entry-macro.S */
21 #include <asm/arch/irqs.h> /* should be moved into entry-macro.S */
22 #include <asm/arch/entry-macro.S>
24 #include "entry-header.S"
27 * Interrupt handling. Preserves r7, r8, r9
30 1: get_irqnr_and_base r0, r6, r5, lr
33 @ routine called with r0 = irq number, r1 = struct pt_regs *
42 * this macro assumes that irqstat (r6) and base (r5) are
43 * preserved from get_irqnr_and_base above
45 test_for_ipi r0, r6, r5, lr
54 * Invalid mode handlers
56 .macro inv_entry, reason
57 sub sp, sp, #S_FRAME_SIZE
63 inv_entry BAD_PREFETCH
75 inv_entry BAD_UNDEFINSTR
78 @ XXX fall through to common_invalid
82 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
88 add r0, sp, #S_PC @ here for interlock avoidance
89 mov r7, #-1 @ "" "" "" ""
90 str r4, [sp] @ save preserved r0
91 stmia r0, {r5 - r7} @ lr_<exception>,
92 @ cpsr_<exception>, "old_r0"
102 sub sp, sp, #S_FRAME_SIZE
106 add r5, sp, #S_SP @ here for interlock avoidance
107 mov r4, #-1 @ "" "" "" ""
108 add r0, sp, #S_FRAME_SIZE @ "" "" "" ""
109 str r1, [sp] @ save the "real" r0 copied
110 @ from the exception stack
115 @ We are now ready to fill in the remaining blanks on the stack:
119 @ r2 - lr_<exception>, already fixed up for correct return/restart
120 @ r3 - spsr_<exception>
121 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
131 @ get ready to re-enable interrupts if appropriate
135 biceq r9, r9, #PSR_I_BIT
138 @ Call the processor-specific abort handler:
140 @ r2 - aborted context pc
141 @ r3 - aborted context cpsr
143 @ The abort handler must return the aborted address in r0, and
144 @ the fault status register in r1. r9 must be preserved.
155 @ set desired IRQ state, then call main handler
162 @ IRQs off again before pulling preserved data off the stack
167 @ restore SPSR and restart the instruction
171 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
177 #ifdef CONFIG_PREEMPT
179 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
180 add r7, r8, #1 @ increment it
181 str r7, [tsk, #TI_PREEMPT]
185 #ifdef CONFIG_PREEMPT
186 ldr r0, [tsk, #TI_FLAGS] @ get flags
187 tst r0, #_TIF_NEED_RESCHED
190 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value
191 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
193 strne r0, [r0, -r0] @ bug()
195 ldr r0, [sp, #S_PSR] @ irqs are already disabled
197 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
201 #ifdef CONFIG_PREEMPT
203 teq r8, #0 @ was preempt count = 0
204 ldreq r6, .LCirq_stat
206 ldr r0, [r6, #4] @ local_irq_count
207 ldr r1, [r6, #8] @ local_bh_count
210 mov r7, #0 @ preempt_schedule_irq
211 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0
212 1: bl preempt_schedule_irq @ irq en/disable is done inside
213 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
214 tst r0, #_TIF_NEED_RESCHED
215 beq preempt_return @ go again
224 @ call emulation code, which returns using r9 if it has emulated
225 @ the instruction, or the more conventional lr if we are to treat
226 @ this as a real undefined instruction
234 mov r0, sp @ struct pt_regs *regs
238 @ IRQs off again before pulling preserved data off the stack
243 @ restore SPSR and restart the instruction
245 ldr lr, [sp, #S_PSR] @ Get SVC cpsr
247 ldmia sp, {r0 - pc}^ @ Restore SVC registers
254 @ re-enable interrupts if appropriate
258 biceq r9, r9, #PSR_I_BIT
262 @ set args, then call main handler
264 @ r0 - address of faulting instruction
265 @ r1 - pointer to registers on stack
267 mov r0, r2 @ address (pc)
269 bl do_PrefetchAbort @ call abort handler
272 @ IRQs off again before pulling preserved data off the stack
277 @ restore SPSR and restart the instruction
281 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
292 #ifdef CONFIG_PREEMPT
301 sub sp, sp, #S_FRAME_SIZE
305 add r0, sp, #S_PC @ here for interlock avoidance
306 mov r4, #-1 @ "" "" "" ""
308 str r1, [sp] @ save the "real" r0 copied
309 @ from the exception stack
311 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
312 @ make sure our user space atomic helper is aborted
314 bichs r3, r3, #PSR_Z_BIT
318 @ We are now ready to fill in the remaining blanks on the stack:
320 @ r2 - lr_<exception>, already fixed up for correct return/restart
321 @ r3 - spsr_<exception>
322 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
324 @ Also, separately save sp_usr and lr_usr
330 @ Enable the alignment trap while in kernel mode
335 @ Clear FP to mark the first stack frame
345 @ Call the processor-specific abort handler:
347 @ r2 - aborted context pc
348 @ r3 - aborted context cpsr
350 @ The abort handler must return the aborted address in r0, and
351 @ the fault status register in r1.
362 @ IRQs on, then call the main handler
366 adr lr, ret_from_exception
374 #ifdef CONFIG_PREEMPT
375 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
376 add r7, r8, #1 @ increment it
377 str r7, [tsk, #TI_PREEMPT]
381 #ifdef CONFIG_PREEMPT
382 ldr r0, [tsk, #TI_PREEMPT]
383 str r8, [tsk, #TI_PREEMPT]
397 tst r3, #PSR_T_BIT @ Thumb mode?
398 bne fpundefinstr @ ignore FP
402 @ fall through to the emulation code, which returns using r9 if
403 @ it has emulated the instruction, or the more conventional lr
404 @ if we are to treat this as a real undefined instruction
409 adr r9, ret_from_exception
412 @ fallthrough to call_fpe
416 * The out of line fixup for the ldrt above.
418 .section .fixup, "ax"
421 .section __ex_table,"a"
426 * Check whether the instruction is a co-processor instruction.
427 * If yes, we need to call the relevant co-processor handler.
429 * Note that we don't do a full check here for the co-processor
430 * instructions; all instructions with bit 27 set are well
431 * defined. The only instructions that should fault are the
432 * co-processor instructions. However, we have to watch out
433 * for the ARM6/ARM7 SWI bug.
435 * Emulators may wish to make use of the following registers:
436 * r0 = instruction opcode.
438 * r10 = this threads thread_info structure.
441 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
442 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
443 and r8, r0, #0x0f000000 @ mask out op-code bits
444 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
447 get_thread_info r10 @ get current thread
448 and r8, r0, #0x00000f00 @ mask out CP number
450 add r6, r10, #TI_USED_CP
451 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
453 @ Test if we need to give access to iWMMXt coprocessors
454 ldr r5, [r10, #TI_FLAGS]
455 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
456 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
457 bcs iwmmxt_task_enable
460 add pc, pc, r8, lsr #6
464 b do_fpe @ CP#1 (FPE)
465 b do_fpe @ CP#2 (FPE)
474 b do_vfp @ CP#10 (VFP)
475 b do_vfp @ CP#11 (VFP)
477 mov pc, lr @ CP#10 (VFP)
478 mov pc, lr @ CP#11 (VFP)
482 mov pc, lr @ CP#14 (Debug)
483 mov pc, lr @ CP#15 (Control)
487 add r10, r10, #TI_FPSTATE @ r10 = workspace
488 ldr pc, [r4] @ Call FP module USR entry point
491 * The FP module is called with these registers set:
494 * r9 = normal "successful" return address
496 * lr = unrecognised FP instruction return address
506 adr lr, ret_from_exception
513 enable_irq @ Enable interrupts
514 mov r0, r2 @ address (pc)
516 bl do_PrefetchAbort @ call abort handler
519 * This is the return code to user mode for abort handlers
521 ENTRY(ret_from_exception)
527 * Register switch for ARMv3 and ARMv4 processors
528 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
529 * previous and next are guaranteed not to be the same.
532 add ip, r1, #TI_CPU_SAVE
533 ldr r3, [r2, #TI_TP_VALUE]
534 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
535 ldr r6, [r2, #TI_CPU_DOMAIN]!
536 #if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
540 #if defined(CONFIG_HAS_TLS_REG)
541 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
542 #elif !defined(CONFIG_TLS_REG_EMUL)
544 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
546 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
548 @ Always disable VFP so we can lazily save/restore the old
549 @ state. This occurs in the context of the previous thread.
551 bic r4, r4, #FPEXC_ENABLE
554 #if defined(CONFIG_IWMMXT)
555 bl iwmmxt_task_switch
556 #elif defined(CONFIG_CPU_XSCALE)
557 add r4, r2, #40 @ cpu_context_save->extra
561 ldmib r2, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
568 * These are segment of kernel provided user code reachable from user space
569 * at a fixed address in kernel memory. This is used to provide user space
570 * with some operations which require kernel help because of unimplemented
571 * native feature and/or instructions in many ARM CPUs. The idea is for
572 * this code to be executed directly in user mode for best efficiency but
573 * which is too intimate with the kernel counter part to be left to user
574 * libraries. In fact this code might even differ from one CPU to another
575 * depending on the available instruction set and restrictions like on
576 * SMP systems. In other words, the kernel reserves the right to change
577 * this code as needed without warning. Only the entry points and their
578 * results are guaranteed to be stable.
580 * Each segment is 32-byte aligned and will be moved to the top of the high
581 * vector page. New segments (if ever needed) must be added in front of
582 * existing ones. This mechanism should be used only for things that are
583 * really small and justified, and not be abused freely.
585 * User space is expected to implement those things inline when optimizing
586 * for a processor that has the necessary native support, but only if such
587 * resulting binaries are already to be incompatible with earlier ARM
588 * processors due to the use of unsupported instructions other than what
589 * is provided here. In other words don't make binaries unable to run on
590 * earlier processors just for the sake of not using these kernel helpers
591 * if your compiled code is not going to use the new instructions for other
596 .globl __kuser_helper_start
597 __kuser_helper_start:
600 * Reference prototype:
602 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
609 * lr = return address
613 * r0 = returned value (zero or non-zero)
614 * C flag = set if r0 == 0, clear if r0 != 0
620 * Definition and user space usage example:
622 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
623 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
625 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
626 * Return zero if *ptr was changed or non-zero if no exchange happened.
627 * The C flag is also set if *ptr was changed to allow for assembly
628 * optimization in the calling code.
630 * For example, a user space atomic_add implementation could look like this:
632 * #define atomic_add(ptr, val) \
633 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
634 * register unsigned int __result asm("r1"); \
636 * "1: @ atomic_add\n\t" \
637 * "ldr r0, [r2]\n\t" \
638 * "mov r3, #0xffff0fff\n\t" \
639 * "add lr, pc, #4\n\t" \
640 * "add r1, r0, %2\n\t" \
641 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
643 * : "=&r" (__result) \
644 * : "r" (__ptr), "rIL" (val) \
645 * : "r0","r3","ip","lr","cc","memory" ); \
649 __kuser_cmpxchg: @ 0xffff0fc0
651 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
654 * Poor you. No fast solution possible...
655 * The kernel itself must perform the operation.
656 * A special ghost syscall is used for that (see traps.c).
661 #elif __LINUX_ARM_ARCH__ < 6
664 * Theory of operation:
666 * We set the Z flag before loading oldval. If ever an exception
667 * occurs we can not be sure the loaded value will still be the same
668 * when the exception returns, therefore the user exception handler
669 * will clear the Z flag whenever the interrupted user code was
670 * actually from the kernel address space (see the usr_entry macro).
672 * The post-increment on the str is used to prevent a race with an
673 * exception happening just after the str instruction which would
674 * clear the Z flag although the exchange was done.
676 teq ip, ip @ set Z flag
677 ldr ip, [r2] @ load current val
678 add r3, r2, #1 @ prepare store ptr
679 teqeq ip, r0 @ compare with oldval if still allowed
680 streq r1, [r3, #-1]! @ store newval if still allowed
681 subs r0, r2, r3 @ if r2 == r3 the str occured
697 * Reference prototype:
699 * int __kernel_get_tls(void)
703 * lr = return address
711 * the Z flag might be lost
713 * Definition and user space usage example:
715 * typedef int (__kernel_get_tls_t)(void);
716 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
718 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
720 * This could be used as follows:
722 * #define __kernel_get_tls() \
723 * ({ register unsigned int __val asm("r0"); \
724 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
725 * : "=r" (__val) : : "lr","cc" ); \
729 __kuser_get_tls: @ 0xffff0fe0
731 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
733 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
738 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
744 .word 0 @ pad up to __kuser_helper_version
748 * Reference declaration:
750 * extern unsigned int __kernel_helper_version;
752 * Definition and user space usage example:
754 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
756 * User space may read this to determine the curent number of helpers
760 __kuser_helper_version: @ 0xffff0ffc
761 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
763 .globl __kuser_helper_end
770 * This code is copied to 0xffff0200 so we can use branches in the
771 * vectors, rather than ldr's. Note that this code must not
772 * exceed 0x300 bytes.
774 * Common stub entry macro:
775 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
777 * SP points to a minimal amount of processor-private memory, the address
778 * of which is copied into r0 for the mode specific abort handler.
780 .macro vector_stub, name, correction=0
785 sub lr, lr, #\correction
789 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
792 stmia sp, {r0, lr} @ save r0, lr
794 str lr, [sp, #8] @ save spsr
797 @ Prepare for SVC32 mode. IRQs remain disabled.
800 bic r0, r0, #MODE_MASK
801 orr r0, r0, #SVC_MODE
805 @ the branch table must immediately follow this code
809 ldr lr, [pc, lr, lsl #2]
810 movs pc, lr @ branch to handler in SVC mode
816 * Interrupt dispatcher
820 .long __irq_usr @ 0 (USR_26 / USR_32)
821 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
822 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
823 .long __irq_svc @ 3 (SVC_26 / SVC_32)
824 .long __irq_invalid @ 4
825 .long __irq_invalid @ 5
826 .long __irq_invalid @ 6
827 .long __irq_invalid @ 7
828 .long __irq_invalid @ 8
829 .long __irq_invalid @ 9
830 .long __irq_invalid @ a
831 .long __irq_invalid @ b
832 .long __irq_invalid @ c
833 .long __irq_invalid @ d
834 .long __irq_invalid @ e
835 .long __irq_invalid @ f
838 * Data abort dispatcher
839 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
843 .long __dabt_usr @ 0 (USR_26 / USR_32)
844 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
845 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
846 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
847 .long __dabt_invalid @ 4
848 .long __dabt_invalid @ 5
849 .long __dabt_invalid @ 6
850 .long __dabt_invalid @ 7
851 .long __dabt_invalid @ 8
852 .long __dabt_invalid @ 9
853 .long __dabt_invalid @ a
854 .long __dabt_invalid @ b
855 .long __dabt_invalid @ c
856 .long __dabt_invalid @ d
857 .long __dabt_invalid @ e
858 .long __dabt_invalid @ f
861 * Prefetch abort dispatcher
862 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
866 .long __pabt_usr @ 0 (USR_26 / USR_32)
867 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
868 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
869 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
870 .long __pabt_invalid @ 4
871 .long __pabt_invalid @ 5
872 .long __pabt_invalid @ 6
873 .long __pabt_invalid @ 7
874 .long __pabt_invalid @ 8
875 .long __pabt_invalid @ 9
876 .long __pabt_invalid @ a
877 .long __pabt_invalid @ b
878 .long __pabt_invalid @ c
879 .long __pabt_invalid @ d
880 .long __pabt_invalid @ e
881 .long __pabt_invalid @ f
884 * Undef instr entry dispatcher
885 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
889 .long __und_usr @ 0 (USR_26 / USR_32)
890 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
891 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
892 .long __und_svc @ 3 (SVC_26 / SVC_32)
893 .long __und_invalid @ 4
894 .long __und_invalid @ 5
895 .long __und_invalid @ 6
896 .long __und_invalid @ 7
897 .long __und_invalid @ 8
898 .long __und_invalid @ 9
899 .long __und_invalid @ a
900 .long __und_invalid @ b
901 .long __und_invalid @ c
902 .long __und_invalid @ d
903 .long __und_invalid @ e
904 .long __und_invalid @ f
908 /*=============================================================================
910 *-----------------------------------------------------------------------------
911 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
912 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
913 * Basically to switch modes, we *HAVE* to clobber one register... brain
914 * damage alert! I don't think that we can execute any code in here in any
915 * other mode than FIQ... Ok you can switch to another mode, but you can't
916 * get out of that mode without clobbering one register.
922 /*=============================================================================
923 * Address exception handler
924 *-----------------------------------------------------------------------------
925 * These aren't too critical.
926 * (they're not supposed to happen, and won't happen in 32-bit data mode).
933 * We group all the following data together to optimise
934 * for CPUs with separate I & D caches.
944 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
946 .globl __vectors_start
949 b vector_und + stubs_offset
950 ldr pc, .LCvswi + stubs_offset
951 b vector_pabt + stubs_offset
952 b vector_dabt + stubs_offset
953 b vector_addrexcptn + stubs_offset
954 b vector_irq + stubs_offset
955 b vector_fiq + stubs_offset
963 .globl cr_no_alignment
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