Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
[linux-2.6] / drivers / mtd / nand / s3c2410.c
1 /* linux/drivers/mtd/nand/s3c2410.c
2  *
3  * Copyright (c) 2004,2005 Simtec Electronics
4  *      http://www.simtec.co.uk/products/SWLINUX/
5  *      Ben Dooks <ben@simtec.co.uk>
6  *
7  * Samsung S3C2410/S3C240 NAND driver
8  *
9  * Changelog:
10  *      21-Sep-2004  BJD  Initial version
11  *      23-Sep-2004  BJD  Mulitple device support
12  *      28-Sep-2004  BJD  Fixed ECC placement for Hardware mode
13  *      12-Oct-2004  BJD  Fixed errors in use of platform data
14  *      18-Feb-2005  BJD  Fix sparse errors
15  *      14-Mar-2005  BJD  Applied tglx's code reduction patch
16  *      02-May-2005  BJD  Fixed s3c2440 support
17  *      02-May-2005  BJD  Reduced hwcontrol decode
18  *      20-Jun-2005  BJD  Updated s3c2440 support, fixed timing bug
19  *      08-Jul-2005  BJD  Fix OOPS when no platform data supplied
20  *      20-Oct-2005  BJD  Fix timing calculation bug
21  *      14-Jan-2006  BJD  Allow clock to be stopped when idle
22  *
23  * $Id: s3c2410.c,v 1.23 2006/04/01 18:06:29 bjd Exp $
24  *
25  * This program is free software; you can redistribute it and/or modify
26  * it under the terms of the GNU General Public License as published by
27  * the Free Software Foundation; either version 2 of the License, or
28  * (at your option) any later version.
29  *
30  * This program is distributed in the hope that it will be useful,
31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
33  * GNU General Public License for more details.
34  *
35  * You should have received a copy of the GNU General Public License
36  * along with this program; if not, write to the Free Software
37  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
38 */
39
40 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
41 #define DEBUG
42 #endif
43
44 #include <linux/module.h>
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/kernel.h>
48 #include <linux/string.h>
49 #include <linux/ioport.h>
50 #include <linux/platform_device.h>
51 #include <linux/delay.h>
52 #include <linux/err.h>
53 #include <linux/slab.h>
54 #include <linux/clk.h>
55
56 #include <linux/mtd/mtd.h>
57 #include <linux/mtd/nand.h>
58 #include <linux/mtd/nand_ecc.h>
59 #include <linux/mtd/partitions.h>
60
61 #include <asm/io.h>
62
63 #include <asm/arch/regs-nand.h>
64 #include <asm/arch/nand.h>
65
66 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
67 static int hardware_ecc = 1;
68 #else
69 static int hardware_ecc = 0;
70 #endif
71
72 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
73 static int clock_stop = 1;
74 #else
75 static const int clock_stop = 0;
76 #endif
77
78
79 /* new oob placement block for use with hardware ecc generation
80  */
81
82 static struct nand_ecclayout nand_hw_eccoob = {
83         .eccbytes = 3,
84         .eccpos = {0, 1, 2},
85         .oobfree = {{8, 8}}
86 };
87
88 /* controller and mtd information */
89
90 struct s3c2410_nand_info;
91
92 struct s3c2410_nand_mtd {
93         struct mtd_info                 mtd;
94         struct nand_chip                chip;
95         struct s3c2410_nand_set         *set;
96         struct s3c2410_nand_info        *info;
97         int                             scan_res;
98 };
99
100 enum s3c_cpu_type {
101         TYPE_S3C2410,
102         TYPE_S3C2412,
103         TYPE_S3C2440,
104 };
105
106 /* overview of the s3c2410 nand state */
107
108 struct s3c2410_nand_info {
109         /* mtd info */
110         struct nand_hw_control          controller;
111         struct s3c2410_nand_mtd         *mtds;
112         struct s3c2410_platform_nand    *platform;
113
114         /* device info */
115         struct device                   *device;
116         struct resource                 *area;
117         struct clk                      *clk;
118         void __iomem                    *regs;
119         void __iomem                    *sel_reg;
120         int                             sel_bit;
121         int                             mtd_count;
122
123         enum s3c_cpu_type               cpu_type;
124 };
125
126 /* conversion functions */
127
128 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
129 {
130         return container_of(mtd, struct s3c2410_nand_mtd, mtd);
131 }
132
133 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
134 {
135         return s3c2410_nand_mtd_toours(mtd)->info;
136 }
137
138 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
139 {
140         return platform_get_drvdata(dev);
141 }
142
143 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
144 {
145         return dev->dev.platform_data;
146 }
147
148 static inline int allow_clk_stop(struct s3c2410_nand_info *info)
149 {
150         return clock_stop;
151 }
152
153 /* timing calculations */
154
155 #define NS_IN_KHZ 1000000
156
157 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
158 {
159         int result;
160
161         result = (wanted * clk) / NS_IN_KHZ;
162         result++;
163
164         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
165
166         if (result > max) {
167                 printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
168                 return -1;
169         }
170
171         if (result < 1)
172                 result = 1;
173
174         return result;
175 }
176
177 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
178
179 /* controller setup */
180
181 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
182                                struct platform_device *pdev)
183 {
184         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
185         unsigned long clkrate = clk_get_rate(info->clk);
186         int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
187         int tacls, twrph0, twrph1;
188         unsigned long cfg = 0;
189
190         /* calculate the timing information for the controller */
191
192         clkrate /= 1000;        /* turn clock into kHz for ease of use */
193
194         if (plat != NULL) {
195                 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
196                 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
197                 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
198         } else {
199                 /* default timings */
200                 tacls = tacls_max;
201                 twrph0 = 8;
202                 twrph1 = 8;
203         }
204
205         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
206                 dev_err(info->device, "cannot get suitable timings\n");
207                 return -EINVAL;
208         }
209
210         dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
211                tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
212
213         switch (info->cpu_type) {
214         case TYPE_S3C2410:
215                 cfg = S3C2410_NFCONF_EN;
216                 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
217                 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
218                 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
219                 break;
220
221         case TYPE_S3C2440:
222         case TYPE_S3C2412:
223                 cfg = S3C2440_NFCONF_TACLS(tacls - 1);
224                 cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
225                 cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
226
227                 /* enable the controller and de-assert nFCE */
228
229                 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
230         }
231
232         dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
233
234         writel(cfg, info->regs + S3C2410_NFCONF);
235         return 0;
236 }
237
238 /* select chip */
239
240 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
241 {
242         struct s3c2410_nand_info *info;
243         struct s3c2410_nand_mtd *nmtd;
244         struct nand_chip *this = mtd->priv;
245         unsigned long cur;
246
247         nmtd = this->priv;
248         info = nmtd->info;
249
250         if (chip != -1 && allow_clk_stop(info))
251                 clk_enable(info->clk);
252
253         cur = readl(info->sel_reg);
254
255         if (chip == -1) {
256                 cur |= info->sel_bit;
257         } else {
258                 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
259                         dev_err(info->device, "invalid chip %d\n", chip);
260                         return;
261                 }
262
263                 if (info->platform != NULL) {
264                         if (info->platform->select_chip != NULL)
265                                 (info->platform->select_chip) (nmtd->set, chip);
266                 }
267
268                 cur &= ~info->sel_bit;
269         }
270
271         writel(cur, info->sel_reg);
272
273         if (chip == -1 && allow_clk_stop(info))
274                 clk_disable(info->clk);
275 }
276
277 /* s3c2410_nand_hwcontrol
278  *
279  * Issue command and address cycles to the chip
280 */
281
282 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
283                                    unsigned int ctrl)
284 {
285         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
286         
287         if (cmd == NAND_CMD_NONE)
288                 return;
289
290         if (ctrl & NAND_CLE)
291                 writeb(cmd, info->regs + S3C2410_NFCMD);
292         else
293                 writeb(cmd, info->regs + S3C2410_NFADDR);
294 }
295
296 /* command and control functions */
297
298 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
299                                    unsigned int ctrl)
300 {
301         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
302
303         if (cmd == NAND_CMD_NONE)
304                 return;
305
306         if (ctrl & NAND_CLE)
307                 writeb(cmd, info->regs + S3C2440_NFCMD);
308         else
309                 writeb(cmd, info->regs + S3C2440_NFADDR);
310 }
311
312 /* s3c2410_nand_devready()
313  *
314  * returns 0 if the nand is busy, 1 if it is ready
315 */
316
317 static int s3c2410_nand_devready(struct mtd_info *mtd)
318 {
319         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
320         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
321 }
322
323 static int s3c2440_nand_devready(struct mtd_info *mtd)
324 {
325         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
326         return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
327 }
328
329 static int s3c2412_nand_devready(struct mtd_info *mtd)
330 {
331         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
332         return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
333 }
334
335 /* ECC handling functions */
336
337 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
338                                      u_char *read_ecc, u_char *calc_ecc)
339 {
340         pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", mtd, dat, read_ecc, calc_ecc);
341
342         pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n",
343                  read_ecc[0], read_ecc[1], read_ecc[2], calc_ecc[0], calc_ecc[1], calc_ecc[2]);
344
345         if (read_ecc[0] == calc_ecc[0] && read_ecc[1] == calc_ecc[1] && read_ecc[2] == calc_ecc[2])
346                 return 0;
347
348         /* we curently have no method for correcting the error */
349
350         return -1;
351 }
352
353 /* ECC functions
354  *
355  * These allow the s3c2410 and s3c2440 to use the controller's ECC
356  * generator block to ECC the data as it passes through]
357 */
358
359 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
360 {
361         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
362         unsigned long ctrl;
363
364         ctrl = readl(info->regs + S3C2410_NFCONF);
365         ctrl |= S3C2410_NFCONF_INITECC;
366         writel(ctrl, info->regs + S3C2410_NFCONF);
367 }
368
369 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
370 {
371         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
372         unsigned long ctrl;
373
374         ctrl = readl(info->regs + S3C2440_NFCONT);
375         writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
376 }
377
378 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
379 {
380         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
381
382         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
383         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
384         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
385
386         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
387
388         return 0;
389 }
390
391 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
392 {
393         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
394         unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
395
396         ecc_code[0] = ecc;
397         ecc_code[1] = ecc >> 8;
398         ecc_code[2] = ecc >> 16;
399
400         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
401
402         return 0;
403 }
404
405 /* over-ride the standard functions for a little more speed. We can
406  * use read/write block to move the data buffers to/from the controller
407 */
408
409 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
410 {
411         struct nand_chip *this = mtd->priv;
412         readsb(this->IO_ADDR_R, buf, len);
413 }
414
415 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
416 {
417         struct nand_chip *this = mtd->priv;
418         writesb(this->IO_ADDR_W, buf, len);
419 }
420
421 /* device management functions */
422
423 static int s3c2410_nand_remove(struct platform_device *pdev)
424 {
425         struct s3c2410_nand_info *info = to_nand_info(pdev);
426
427         platform_set_drvdata(pdev, NULL);
428
429         if (info == NULL)
430                 return 0;
431
432         /* first thing we need to do is release all our mtds
433          * and their partitions, then go through freeing the
434          * resources used
435          */
436
437         if (info->mtds != NULL) {
438                 struct s3c2410_nand_mtd *ptr = info->mtds;
439                 int mtdno;
440
441                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
442                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
443                         nand_release(&ptr->mtd);
444                 }
445
446                 kfree(info->mtds);
447         }
448
449         /* free the common resources */
450
451         if (info->clk != NULL && !IS_ERR(info->clk)) {
452                 if (!allow_clk_stop(info))
453                         clk_disable(info->clk);
454                 clk_put(info->clk);
455         }
456
457         if (info->regs != NULL) {
458                 iounmap(info->regs);
459                 info->regs = NULL;
460         }
461
462         if (info->area != NULL) {
463                 release_resource(info->area);
464                 kfree(info->area);
465                 info->area = NULL;
466         }
467
468         kfree(info);
469
470         return 0;
471 }
472
473 #ifdef CONFIG_MTD_PARTITIONS
474 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
475                                       struct s3c2410_nand_mtd *mtd,
476                                       struct s3c2410_nand_set *set)
477 {
478         if (set == NULL)
479                 return add_mtd_device(&mtd->mtd);
480
481         if (set->nr_partitions > 0 && set->partitions != NULL) {
482                 return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
483         }
484
485         return add_mtd_device(&mtd->mtd);
486 }
487 #else
488 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
489                                       struct s3c2410_nand_mtd *mtd,
490                                       struct s3c2410_nand_set *set)
491 {
492         return add_mtd_device(&mtd->mtd);
493 }
494 #endif
495
496 /* s3c2410_nand_init_chip
497  *
498  * init a single instance of an chip
499 */
500
501 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
502                                    struct s3c2410_nand_mtd *nmtd,
503                                    struct s3c2410_nand_set *set)
504 {
505         struct nand_chip *chip = &nmtd->chip;
506         void __iomem *regs = info->regs;
507
508         chip->write_buf    = s3c2410_nand_write_buf;
509         chip->read_buf     = s3c2410_nand_read_buf;
510         chip->select_chip  = s3c2410_nand_select_chip;
511         chip->chip_delay   = 50;
512         chip->priv         = nmtd;
513         chip->options      = 0;
514         chip->controller   = &info->controller;
515
516         switch (info->cpu_type) {
517         case TYPE_S3C2410:
518                 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
519                 info->sel_reg   = regs + S3C2410_NFCONF;
520                 info->sel_bit   = S3C2410_NFCONF_nFCE;
521                 chip->cmd_ctrl  = s3c2410_nand_hwcontrol;
522                 chip->dev_ready = s3c2410_nand_devready;
523                 break;
524
525         case TYPE_S3C2440:
526                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
527                 info->sel_reg   = regs + S3C2440_NFCONT;
528                 info->sel_bit   = S3C2440_NFCONT_nFCE;
529                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
530                 chip->dev_ready = s3c2440_nand_devready;
531                 break;
532
533         case TYPE_S3C2412:
534                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
535                 info->sel_reg   = regs + S3C2440_NFCONT;
536                 info->sel_bit   = S3C2412_NFCONT_nFCE0;
537                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
538                 chip->dev_ready = s3c2412_nand_devready;
539
540                 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
541                         dev_info(info->device, "System booted from NAND\n");
542
543                 break;
544         }
545
546         chip->IO_ADDR_R = chip->IO_ADDR_W;
547
548         nmtd->info         = info;
549         nmtd->mtd.priv     = chip;
550         nmtd->mtd.owner    = THIS_MODULE;
551         nmtd->set          = set;
552
553         if (hardware_ecc) {
554                 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
555                 chip->ecc.correct   = s3c2410_nand_correct_data;
556                 chip->ecc.mode      = NAND_ECC_HW;
557                 chip->ecc.size      = 512;
558                 chip->ecc.bytes     = 3;
559                 chip->ecc.layout    = &nand_hw_eccoob;
560
561                 switch (info->cpu_type) {
562                 case TYPE_S3C2410:
563                         chip->ecc.hwctl     = s3c2410_nand_enable_hwecc;
564                         chip->ecc.calculate = s3c2410_nand_calculate_ecc;
565                         break;
566
567                 case TYPE_S3C2412:
568                 case TYPE_S3C2440:
569                         chip->ecc.hwctl     = s3c2440_nand_enable_hwecc;
570                         chip->ecc.calculate = s3c2440_nand_calculate_ecc;
571                         break;
572
573                 }
574         } else {
575                 chip->ecc.mode      = NAND_ECC_SOFT;
576         }
577 }
578
579 /* s3c2410_nand_probe
580  *
581  * called by device layer when it finds a device matching
582  * one our driver can handled. This code checks to see if
583  * it can allocate all necessary resources then calls the
584  * nand layer to look for devices
585 */
586
587 static int s3c24xx_nand_probe(struct platform_device *pdev,
588                               enum s3c_cpu_type cpu_type)
589 {
590         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
591         struct s3c2410_nand_info *info;
592         struct s3c2410_nand_mtd *nmtd;
593         struct s3c2410_nand_set *sets;
594         struct resource *res;
595         int err = 0;
596         int size;
597         int nr_sets;
598         int setno;
599
600         pr_debug("s3c2410_nand_probe(%p)\n", pdev);
601
602         info = kmalloc(sizeof(*info), GFP_KERNEL);
603         if (info == NULL) {
604                 dev_err(&pdev->dev, "no memory for flash info\n");
605                 err = -ENOMEM;
606                 goto exit_error;
607         }
608
609         memzero(info, sizeof(*info));
610         platform_set_drvdata(pdev, info);
611
612         spin_lock_init(&info->controller.lock);
613         init_waitqueue_head(&info->controller.wq);
614
615         /* get the clock source and enable it */
616
617         info->clk = clk_get(&pdev->dev, "nand");
618         if (IS_ERR(info->clk)) {
619                 dev_err(&pdev->dev, "failed to get clock");
620                 err = -ENOENT;
621                 goto exit_error;
622         }
623
624         clk_enable(info->clk);
625
626         /* allocate and map the resource */
627
628         /* currently we assume we have the one resource */
629         res  = pdev->resource;
630         size = res->end - res->start + 1;
631
632         info->area = request_mem_region(res->start, size, pdev->name);
633
634         if (info->area == NULL) {
635                 dev_err(&pdev->dev, "cannot reserve register region\n");
636                 err = -ENOENT;
637                 goto exit_error;
638         }
639
640         info->device     = &pdev->dev;
641         info->platform   = plat;
642         info->regs       = ioremap(res->start, size);
643         info->cpu_type   = cpu_type;
644
645         if (info->regs == NULL) {
646                 dev_err(&pdev->dev, "cannot reserve register region\n");
647                 err = -EIO;
648                 goto exit_error;
649         }
650
651         dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
652
653         /* initialise the hardware */
654
655         err = s3c2410_nand_inithw(info, pdev);
656         if (err != 0)
657                 goto exit_error;
658
659         sets = (plat != NULL) ? plat->sets : NULL;
660         nr_sets = (plat != NULL) ? plat->nr_sets : 1;
661
662         info->mtd_count = nr_sets;
663
664         /* allocate our information */
665
666         size = nr_sets * sizeof(*info->mtds);
667         info->mtds = kmalloc(size, GFP_KERNEL);
668         if (info->mtds == NULL) {
669                 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
670                 err = -ENOMEM;
671                 goto exit_error;
672         }
673
674         memzero(info->mtds, size);
675
676         /* initialise all possible chips */
677
678         nmtd = info->mtds;
679
680         for (setno = 0; setno < nr_sets; setno++, nmtd++) {
681                 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
682
683                 s3c2410_nand_init_chip(info, nmtd, sets);
684
685                 nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1);
686
687                 if (nmtd->scan_res == 0) {
688                         s3c2410_nand_add_partition(info, nmtd, sets);
689                 }
690
691                 if (sets != NULL)
692                         sets++;
693         }
694
695         if (allow_clk_stop(info)) {
696                 dev_info(&pdev->dev, "clock idle support enabled\n");
697                 clk_disable(info->clk);
698         }
699
700         pr_debug("initialised ok\n");
701         return 0;
702
703  exit_error:
704         s3c2410_nand_remove(pdev);
705
706         if (err == 0)
707                 err = -EINVAL;
708         return err;
709 }
710
711 /* PM Support */
712 #ifdef CONFIG_PM
713
714 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
715 {
716         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
717
718         if (info) {
719                 if (!allow_clk_stop(info))
720                         clk_disable(info->clk);
721         }
722
723         return 0;
724 }
725
726 static int s3c24xx_nand_resume(struct platform_device *dev)
727 {
728         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
729
730         if (info) {
731                 clk_enable(info->clk);
732                 s3c2410_nand_inithw(info, dev);
733
734                 if (allow_clk_stop(info))
735                         clk_disable(info->clk);
736         }
737
738         return 0;
739 }
740
741 #else
742 #define s3c24xx_nand_suspend NULL
743 #define s3c24xx_nand_resume NULL
744 #endif
745
746 /* driver device registration */
747
748 static int s3c2410_nand_probe(struct platform_device *dev)
749 {
750         return s3c24xx_nand_probe(dev, TYPE_S3C2410);
751 }
752
753 static int s3c2440_nand_probe(struct platform_device *dev)
754 {
755         return s3c24xx_nand_probe(dev, TYPE_S3C2440);
756 }
757
758 static int s3c2412_nand_probe(struct platform_device *dev)
759 {
760         return s3c24xx_nand_probe(dev, TYPE_S3C2412);
761 }
762
763 static struct platform_driver s3c2410_nand_driver = {
764         .probe          = s3c2410_nand_probe,
765         .remove         = s3c2410_nand_remove,
766         .suspend        = s3c24xx_nand_suspend,
767         .resume         = s3c24xx_nand_resume,
768         .driver         = {
769                 .name   = "s3c2410-nand",
770                 .owner  = THIS_MODULE,
771         },
772 };
773
774 static struct platform_driver s3c2440_nand_driver = {
775         .probe          = s3c2440_nand_probe,
776         .remove         = s3c2410_nand_remove,
777         .suspend        = s3c24xx_nand_suspend,
778         .resume         = s3c24xx_nand_resume,
779         .driver         = {
780                 .name   = "s3c2440-nand",
781                 .owner  = THIS_MODULE,
782         },
783 };
784
785 static struct platform_driver s3c2412_nand_driver = {
786         .probe          = s3c2412_nand_probe,
787         .remove         = s3c2410_nand_remove,
788         .suspend        = s3c24xx_nand_suspend,
789         .resume         = s3c24xx_nand_resume,
790         .driver         = {
791                 .name   = "s3c2412-nand",
792                 .owner  = THIS_MODULE,
793         },
794 };
795
796 static int __init s3c2410_nand_init(void)
797 {
798         printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
799
800         platform_driver_register(&s3c2412_nand_driver);
801         platform_driver_register(&s3c2440_nand_driver);
802         return platform_driver_register(&s3c2410_nand_driver);
803 }
804
805 static void __exit s3c2410_nand_exit(void)
806 {
807         platform_driver_unregister(&s3c2412_nand_driver);
808         platform_driver_unregister(&s3c2440_nand_driver);
809         platform_driver_unregister(&s3c2410_nand_driver);
810 }
811
812 module_init(s3c2410_nand_init);
813 module_exit(s3c2410_nand_exit);
814
815 MODULE_LICENSE("GPL");
816 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
817 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");