2 * Copyright (c) 2000-2009 LSI Corporation.
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
9 * mpi2_cnfg.h Version: 02.00.10
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
18 * Added Manufacturing Page 11.
19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
21 * 06-26-07 02.00.02 Adding generic structure for product-specific
22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
23 * Rework of BIOS Page 2 configuration page.
24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
26 * Added configuration pages IOC Page 8 and Driver
27 * Persistent Mapping Page 0.
28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
30 * RAID Physical Disk Pages 0 and 1, RAID Configuration
32 * Added new value for AccessStatus field of SAS Device
33 * Page 0 (_SATA_NEEDS_INITIALIZATION).
34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
38 * Modified IOC Page 7 to use masks and added field for
39 * SASBroadcastPrimitiveMasks.
40 * Added MPI2_CONFIG_PAGE_BIOS_4.
41 * Added MPI2_CONFIG_PAGE_LOG_0.
42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
43 * Added SAS Device IDs.
44 * Updated Integrated RAID configuration pages including
45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
50 * Added missing MaxNumRoutedSasAddresses field to
51 * MPI2_CONFIG_PAGE_EXPANDER_0.
52 * Added SAS Port Page 0.
53 * Modified structure layout for
54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
59 * Added two new values for the Physical Disk Coercion Size
60 * bits in the Flags field of Manufacturing Page 4.
61 * Added product-specific Manufacturing pages 16 to 31.
62 * Modified Flags bits for controlling write cache on SATA
63 * drives in IO Unit Page 1.
64 * Added new bit to AdditionalControlFlags of SAS IO Unit
65 * Page 1 to control Invalid Topology Correction.
66 * Added additional defines for RAID Volume Page 0
67 * VolumeStatusFlags field.
68 * Modified meaning of RAID Volume Page 0 VolumeSettings
69 * define for auto-configure of hot-swap drives.
70 * Added SupportedPhysDisks field to RAID Volume Page 1 and
71 * added related defines.
72 * Added PhysDiskAttributes field (and related defines) to
73 * RAID Physical Disk Page 0.
74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
75 * Added three new DiscoveryStatus bits for SAS IO Unit
76 * Page 0 and SAS Expander Page 0.
77 * Removed multiplexing information from SAS IO Unit pages.
78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
79 * Removed Zone Address Resolved bit from PhyInfo and from
80 * Expander Page 0 Flags field.
81 * Added two new AccessStatus values to SAS Device Page 0
82 * for indicating routing problems. Added 3 reserved words
84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
85 * Inserted missing reserved field into structure for IOC
87 * Added more pending task bits to RAID Volume Page 0
88 * VolumeStatusFlags defines.
89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
91 * and SAS Expander Page 0 to flag a downstream initiator
92 * when in simplified routing mode.
93 * Removed SATA Init Failure defines for DiscoveryStatus
94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
96 * Added PortGroups, DmaGroup, and ControlGroup fields to
98 * --------------------------------------------------------------------------
104 /*****************************************************************************
105 * Configuration Page Header and defines
106 *****************************************************************************/
108 /* Config Page Header */
109 typedef struct _MPI2_CONFIG_PAGE_HEADER
111 U8 PageVersion; /* 0x00 */
112 U8 PageLength; /* 0x01 */
113 U8 PageNumber; /* 0x02 */
114 U8 PageType; /* 0x03 */
115 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
116 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
118 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
120 MPI2_CONFIG_PAGE_HEADER Struct;
124 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
125 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
127 /* Extended Config Page Header */
128 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
130 U8 PageVersion; /* 0x00 */
131 U8 Reserved1; /* 0x01 */
132 U8 PageNumber; /* 0x02 */
133 U8 PageType; /* 0x03 */
134 U16 ExtPageLength; /* 0x04 */
135 U8 ExtPageType; /* 0x06 */
136 U8 Reserved2; /* 0x07 */
137 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
138 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
139 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
141 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
143 MPI2_CONFIG_PAGE_HEADER Struct;
144 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
148 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
149 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
152 /* PageType field values */
153 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
154 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
155 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
156 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
158 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
159 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
160 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
161 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
162 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
163 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
164 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
165 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
167 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
170 /* ExtPageType field values */
171 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
172 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
173 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
174 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
175 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
176 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
177 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
178 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
179 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
182 /*****************************************************************************
183 * PageAddress defines
184 *****************************************************************************/
186 /* RAID Volume PageAddress format */
187 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
188 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
189 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
191 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
194 /* RAID Physical Disk PageAddress format */
195 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
196 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
197 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
198 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
200 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
201 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
204 /* SAS Expander PageAddress format */
205 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
206 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
207 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
208 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
210 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
211 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
212 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
215 /* SAS Device PageAddress format */
216 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
217 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
218 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
220 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
223 /* SAS PHY PageAddress format */
224 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
225 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
226 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
228 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
229 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
232 /* SAS Port PageAddress format */
233 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
234 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
235 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
237 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
240 /* SAS Enclosure PageAddress format */
241 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
242 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
243 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
245 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
248 /* RAID Configuration PageAddress format */
249 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
250 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
251 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
252 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
254 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
257 /* Driver Persistent Mapping PageAddress format */
258 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
259 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
261 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
262 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
263 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
266 /****************************************************************************
267 * Configuration messages
268 ****************************************************************************/
270 /* Configuration Request Message */
271 typedef struct _MPI2_CONFIG_REQUEST
273 U8 Action; /* 0x00 */
274 U8 SGLFlags; /* 0x01 */
275 U8 ChainOffset; /* 0x02 */
276 U8 Function; /* 0x03 */
277 U16 ExtPageLength; /* 0x04 */
278 U8 ExtPageType; /* 0x06 */
279 U8 MsgFlags; /* 0x07 */
282 U16 Reserved1; /* 0x0A */
283 U32 Reserved2; /* 0x0C */
284 U32 Reserved3; /* 0x10 */
285 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
286 U32 PageAddress; /* 0x18 */
287 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
288 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
289 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
291 /* values for the Action field */
292 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
293 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
294 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
295 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
296 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
297 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
298 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
299 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
301 /* values for SGLFlags field are in the SGL section of mpi2.h */
304 /* Config Reply Message */
305 typedef struct _MPI2_CONFIG_REPLY
307 U8 Action; /* 0x00 */
308 U8 SGLFlags; /* 0x01 */
309 U8 MsgLength; /* 0x02 */
310 U8 Function; /* 0x03 */
311 U16 ExtPageLength; /* 0x04 */
312 U8 ExtPageType; /* 0x06 */
313 U8 MsgFlags; /* 0x07 */
316 U16 Reserved1; /* 0x0A */
317 U16 Reserved2; /* 0x0C */
318 U16 IOCStatus; /* 0x0E */
319 U32 IOCLogInfo; /* 0x10 */
320 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
321 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
322 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
326 /*****************************************************************************
328 * C o n f i g u r a t i o n P a g e s
330 *****************************************************************************/
332 /****************************************************************************
333 * Manufacturing Config pages
334 ****************************************************************************/
336 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
339 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
340 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
341 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
342 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
343 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
344 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
345 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
348 /* Manufacturing Page 0 */
350 typedef struct _MPI2_CONFIG_PAGE_MAN_0
352 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
353 U8 ChipName[16]; /* 0x04 */
354 U8 ChipRevision[8]; /* 0x14 */
355 U8 BoardName[16]; /* 0x1C */
356 U8 BoardAssembly[16]; /* 0x2C */
357 U8 BoardTracerNumber[16]; /* 0x3C */
358 } MPI2_CONFIG_PAGE_MAN_0,
359 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
360 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
362 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
365 /* Manufacturing Page 1 */
367 typedef struct _MPI2_CONFIG_PAGE_MAN_1
369 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
370 U8 VPD[256]; /* 0x04 */
371 } MPI2_CONFIG_PAGE_MAN_1,
372 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
373 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
375 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
378 typedef struct _MPI2_CHIP_REVISION_ID
380 U16 DeviceID; /* 0x00 */
381 U8 PCIRevisionID; /* 0x02 */
382 U8 Reserved; /* 0x03 */
383 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
384 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
387 /* Manufacturing Page 2 */
390 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
391 * one and check Header.PageLength at runtime.
393 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
394 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
397 typedef struct _MPI2_CONFIG_PAGE_MAN_2
399 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
400 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
401 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
402 } MPI2_CONFIG_PAGE_MAN_2,
403 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
404 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
406 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
409 /* Manufacturing Page 3 */
412 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
413 * one and check Header.PageLength at runtime.
415 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
416 #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
419 typedef struct _MPI2_CONFIG_PAGE_MAN_3
421 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
422 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
423 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
424 } MPI2_CONFIG_PAGE_MAN_3,
425 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
426 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
428 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
431 /* Manufacturing Page 4 */
433 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
435 U8 PowerSaveFlags; /* 0x00 */
436 U8 InternalOperationsSleepTime; /* 0x01 */
437 U8 InternalOperationsRunTime; /* 0x02 */
438 U8 HostIdleTime; /* 0x03 */
439 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
440 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
441 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
443 /* defines for the PowerSaveFlags field */
444 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
445 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
446 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
447 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
449 typedef struct _MPI2_CONFIG_PAGE_MAN_4
451 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
452 U32 Reserved1; /* 0x04 */
453 U32 Flags; /* 0x08 */
454 U8 InquirySize; /* 0x0C */
455 U8 Reserved2; /* 0x0D */
456 U16 Reserved3; /* 0x0E */
457 U8 InquiryData[56]; /* 0x10 */
458 U32 RAID0VolumeSettings; /* 0x48 */
459 U32 RAID1EVolumeSettings; /* 0x4C */
460 U32 RAID1VolumeSettings; /* 0x50 */
461 U32 RAID10VolumeSettings; /* 0x54 */
462 U32 Reserved4; /* 0x58 */
463 U32 Reserved5; /* 0x5C */
464 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
465 U8 MaxOCEDisks; /* 0x64 */
466 U8 ResyncRate; /* 0x65 */
467 U16 DataScrubDuration; /* 0x66 */
468 U8 MaxHotSpares; /* 0x68 */
469 U8 MaxPhysDisksPerVol; /* 0x69 */
470 U8 MaxPhysDisks; /* 0x6A */
471 U8 MaxVolumes; /* 0x6B */
472 } MPI2_CONFIG_PAGE_MAN_4,
473 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
474 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
476 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
478 /* Manufacturing Page 4 Flags field */
479 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
480 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
482 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
483 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
484 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
486 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
487 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
488 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
489 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
490 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
492 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
493 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
494 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
495 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
497 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
498 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
499 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
500 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
501 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
502 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
503 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
504 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
507 /* Manufacturing Page 5 */
510 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
511 * one and check Header.PageLength or NumPhys at runtime.
513 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
514 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
517 typedef struct _MPI2_MANUFACTURING5_ENTRY
520 U64 DeviceName; /* 0x08 */
521 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
522 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
524 typedef struct _MPI2_CONFIG_PAGE_MAN_5
526 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
527 U8 NumPhys; /* 0x04 */
528 U8 Reserved1; /* 0x05 */
529 U16 Reserved2; /* 0x06 */
530 U32 Reserved3; /* 0x08 */
531 U32 Reserved4; /* 0x0C */
532 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
533 } MPI2_CONFIG_PAGE_MAN_5,
534 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
535 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
537 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
540 /* Manufacturing Page 6 */
542 typedef struct _MPI2_CONFIG_PAGE_MAN_6
544 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
545 U32 ProductSpecificInfo;/* 0x04 */
546 } MPI2_CONFIG_PAGE_MAN_6,
547 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
548 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
550 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
553 /* Manufacturing Page 7 */
555 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
557 U32 Pinout; /* 0x00 */
558 U8 Connector[16]; /* 0x04 */
559 U8 Location; /* 0x14 */
560 U8 Reserved1; /* 0x15 */
562 U32 Reserved2; /* 0x18 */
563 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
564 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
566 /* defines for the Pinout field */
567 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
568 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
569 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
570 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
571 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
572 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
573 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
574 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
575 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
576 #define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
578 /* defines for the Location field */
579 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
580 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
581 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
582 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
583 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
584 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
585 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
588 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
589 * one and check NumPhys at runtime.
591 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
592 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
595 typedef struct _MPI2_CONFIG_PAGE_MAN_7
597 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
598 U32 Reserved1; /* 0x04 */
599 U32 Reserved2; /* 0x08 */
600 U32 Flags; /* 0x0C */
601 U8 EnclosureName[16]; /* 0x10 */
602 U8 NumPhys; /* 0x20 */
603 U8 Reserved3; /* 0x21 */
604 U16 Reserved4; /* 0x22 */
605 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
606 } MPI2_CONFIG_PAGE_MAN_7,
607 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
608 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
610 #define MPI2_MANUFACTURING7_PAGEVERSION (0x00)
612 /* defines for the Flags field */
613 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
617 * Generic structure to use for product-specific manufacturing pages
618 * (currently Manufacturing Page 8 through Manufacturing Page 31).
621 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
623 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
624 U32 ProductSpecificInfo;/* 0x04 */
625 } MPI2_CONFIG_PAGE_MAN_PS,
626 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
627 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
629 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
630 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
631 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
632 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
633 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
634 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
635 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
636 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
637 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
638 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
639 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
640 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
641 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
642 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
643 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
644 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
645 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
646 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
647 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
648 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
649 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
650 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
651 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
652 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
655 /****************************************************************************
656 * IO Unit Config Pages
657 ****************************************************************************/
661 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
663 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
664 U64 UniqueValue; /* 0x04 */
665 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
666 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
667 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
668 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
670 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
675 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
677 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
678 U32 Flags; /* 0x04 */
679 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
680 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
682 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
684 /* IO Unit Page 1 Flags defines */
685 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
686 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
687 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
688 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
689 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
690 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
691 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
692 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
693 #define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002)
694 #define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
700 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
701 * one and check Header.PageLength at runtime.
703 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
704 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
707 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
709 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
710 U8 GPIOCount; /* 0x04 */
711 U8 Reserved1; /* 0x05 */
712 U16 Reserved2; /* 0x06 */
713 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
714 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
715 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
717 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
719 /* defines for IO Unit Page 3 GPIOVal field */
720 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
721 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
722 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
723 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
726 /****************************************************************************
728 ****************************************************************************/
732 typedef struct _MPI2_CONFIG_PAGE_IOC_0
734 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
735 U32 Reserved1; /* 0x04 */
736 U32 Reserved2; /* 0x08 */
737 U16 VendorID; /* 0x0C */
738 U16 DeviceID; /* 0x0E */
739 U8 RevisionID; /* 0x10 */
740 U8 Reserved3; /* 0x11 */
741 U16 Reserved4; /* 0x12 */
742 U32 ClassCode; /* 0x14 */
743 U16 SubsystemVendorID; /* 0x18 */
744 U16 SubsystemID; /* 0x1A */
745 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
746 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
748 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
753 typedef struct _MPI2_CONFIG_PAGE_IOC_1
755 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
756 U32 Flags; /* 0x04 */
757 U32 CoalescingTimeout; /* 0x08 */
758 U8 CoalescingDepth; /* 0x0C */
759 U8 PCISlotNum; /* 0x0D */
760 U8 PCIBusNum; /* 0x0E */
761 U8 PCIDomainSegment; /* 0x0F */
762 U32 Reserved1; /* 0x10 */
763 U32 Reserved2; /* 0x14 */
764 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
765 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
767 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
769 /* defines for IOC Page 1 Flags field */
770 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
772 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
773 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
774 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
778 typedef struct _MPI2_CONFIG_PAGE_IOC_6
780 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
781 U32 CapabilitiesFlags; /* 0x04 */
782 U8 MaxDrivesRAID0; /* 0x08 */
783 U8 MaxDrivesRAID1; /* 0x09 */
784 U8 MaxDrivesRAID1E; /* 0x0A */
785 U8 MaxDrivesRAID10; /* 0x0B */
786 U8 MinDrivesRAID0; /* 0x0C */
787 U8 MinDrivesRAID1; /* 0x0D */
788 U8 MinDrivesRAID1E; /* 0x0E */
789 U8 MinDrivesRAID10; /* 0x0F */
790 U32 Reserved1; /* 0x10 */
791 U8 MaxGlobalHotSpares; /* 0x14 */
792 U8 MaxPhysDisks; /* 0x15 */
793 U8 MaxVolumes; /* 0x16 */
794 U8 MaxConfigs; /* 0x17 */
795 U8 MaxOCEDisks; /* 0x18 */
796 U8 Reserved2; /* 0x19 */
797 U16 Reserved3; /* 0x1A */
798 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
799 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
800 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
801 U32 Reserved4; /* 0x28 */
802 U32 Reserved5; /* 0x2C */
803 U16 DefaultMetadataSize; /* 0x30 */
804 U16 Reserved6; /* 0x32 */
805 U16 MaxBadBlockTableEntries; /* 0x34 */
806 U16 Reserved7; /* 0x36 */
807 U32 IRNvsramVersion; /* 0x38 */
808 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
809 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
811 #define MPI2_IOCPAGE6_PAGEVERSION (0x04)
813 /* defines for IOC Page 6 CapabilitiesFlags */
814 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
815 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
816 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
817 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
818 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
823 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
825 typedef struct _MPI2_CONFIG_PAGE_IOC_7
827 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
828 U32 Reserved1; /* 0x04 */
829 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
830 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
831 U16 Reserved2; /* 0x1A */
832 U32 Reserved3; /* 0x1C */
833 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
834 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
836 #define MPI2_IOCPAGE7_PAGEVERSION (0x01)
841 typedef struct _MPI2_CONFIG_PAGE_IOC_8
843 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
844 U8 NumDevsPerEnclosure; /* 0x04 */
845 U8 Reserved1; /* 0x05 */
846 U16 Reserved2; /* 0x06 */
847 U16 MaxPersistentEntries; /* 0x08 */
848 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
849 U16 Flags; /* 0x0C */
850 U16 Reserved3; /* 0x0E */
851 U16 IRVolumeMappingFlags; /* 0x10 */
852 U16 Reserved4; /* 0x12 */
853 U32 Reserved5; /* 0x14 */
854 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
855 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
857 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
859 /* defines for IOC Page 8 Flags field */
860 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
861 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
863 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
864 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
865 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
867 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
868 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
870 /* defines for IOC Page 8 IRVolumeMappingFlags */
871 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
872 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
873 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
876 /****************************************************************************
878 ****************************************************************************/
882 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
884 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
885 U32 BiosOptions; /* 0x04 */
886 U32 IOCSettings; /* 0x08 */
887 U32 Reserved1; /* 0x0C */
888 U32 DeviceSettings; /* 0x10 */
889 U16 NumberOfDevices; /* 0x14 */
890 U16 Reserved2; /* 0x16 */
891 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
892 U16 IOTimeoutSequential; /* 0x1A */
893 U16 IOTimeoutOther; /* 0x1C */
894 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
895 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
896 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
898 #define MPI2_BIOSPAGE1_PAGEVERSION (0x04)
900 /* values for BIOS Page 1 BiosOptions field */
901 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
903 /* values for BIOS Page 1 IOCSettings field */
904 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
905 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
906 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
908 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
909 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
910 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
911 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
913 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
914 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
915 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
916 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
917 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
919 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
921 /* values for BIOS Page 1 DeviceSettings field */
922 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
923 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
924 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
925 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
926 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
931 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
933 U32 Reserved1; /* 0x00 */
934 U32 Reserved2; /* 0x04 */
935 U32 Reserved3; /* 0x08 */
936 U32 Reserved4; /* 0x0C */
937 U32 Reserved5; /* 0x10 */
938 U32 Reserved6; /* 0x14 */
939 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
940 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
941 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
943 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
945 U64 SASAddress; /* 0x00 */
946 U8 LUN[8]; /* 0x08 */
947 U32 Reserved1; /* 0x10 */
948 U32 Reserved2; /* 0x14 */
949 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
950 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
952 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
954 U64 EnclosureLogicalID; /* 0x00 */
955 U32 Reserved1; /* 0x08 */
956 U32 Reserved2; /* 0x0C */
957 U16 SlotNumber; /* 0x10 */
958 U16 Reserved3; /* 0x12 */
959 U32 Reserved4; /* 0x14 */
960 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
961 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
962 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
964 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
966 U64 DeviceName; /* 0x00 */
967 U8 LUN[8]; /* 0x08 */
968 U32 Reserved1; /* 0x10 */
969 U32 Reserved2; /* 0x14 */
970 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
971 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
973 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
975 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
976 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
977 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
978 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
979 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
980 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
982 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
984 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
985 U32 Reserved1; /* 0x04 */
986 U32 Reserved2; /* 0x08 */
987 U32 Reserved3; /* 0x0C */
988 U32 Reserved4; /* 0x10 */
989 U32 Reserved5; /* 0x14 */
990 U32 Reserved6; /* 0x18 */
991 U8 ReqBootDeviceForm; /* 0x1C */
992 U8 Reserved7; /* 0x1D */
993 U16 Reserved8; /* 0x1E */
994 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
995 U8 ReqAltBootDeviceForm; /* 0x38 */
996 U8 Reserved9; /* 0x39 */
997 U16 Reserved10; /* 0x3A */
998 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
999 U8 CurrentBootDeviceForm; /* 0x58 */
1000 U8 Reserved11; /* 0x59 */
1001 U16 Reserved12; /* 0x5A */
1002 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1003 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1004 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1006 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1008 /* values for BIOS Page 2 BootDeviceForm fields */
1009 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1010 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1011 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1012 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1013 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1018 typedef struct _MPI2_ADAPTER_INFO
1020 U8 PciBusNumber; /* 0x00 */
1021 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1022 U16 AdapterFlags; /* 0x02 */
1023 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1024 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1026 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1027 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1029 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1031 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1032 U32 GlobalFlags; /* 0x04 */
1033 U32 BiosVersion; /* 0x08 */
1034 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1035 U32 Reserved1; /* 0x1C */
1036 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1037 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1039 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1041 /* values for BIOS Page 3 GlobalFlags */
1042 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1043 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1044 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1046 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1047 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1048 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1049 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1055 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1056 * one and check Header.PageLength or NumPhys at runtime.
1058 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1059 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1062 typedef struct _MPI2_BIOS4_ENTRY
1064 U64 ReassignmentWWID; /* 0x00 */
1065 U64 ReassignmentDeviceName; /* 0x08 */
1066 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1067 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1069 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1071 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1072 U8 NumPhys; /* 0x04 */
1073 U8 Reserved1; /* 0x05 */
1074 U16 Reserved2; /* 0x06 */
1075 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1076 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1077 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1079 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1082 /****************************************************************************
1083 * RAID Volume Config Pages
1084 ****************************************************************************/
1086 /* RAID Volume Page 0 */
1088 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1090 U8 RAIDSetNum; /* 0x00 */
1091 U8 PhysDiskMap; /* 0x01 */
1092 U8 PhysDiskNum; /* 0x02 */
1093 U8 Reserved; /* 0x03 */
1094 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1095 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1097 /* defines for the PhysDiskMap field */
1098 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1099 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1101 typedef struct _MPI2_RAIDVOL0_SETTINGS
1103 U16 Settings; /* 0x00 */
1104 U8 HotSparePool; /* 0x01 */
1105 U8 Reserved; /* 0x02 */
1106 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1107 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1109 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1110 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1111 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1112 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1113 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1114 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1115 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1116 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1117 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1119 /* RAID Volume Page 0 VolumeSettings defines */
1120 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1121 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1123 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1124 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1125 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1126 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1129 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1130 * one and check Header.PageLength at runtime.
1132 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1133 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1136 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1138 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1139 U16 DevHandle; /* 0x04 */
1140 U8 VolumeState; /* 0x06 */
1141 U8 VolumeType; /* 0x07 */
1142 U32 VolumeStatusFlags; /* 0x08 */
1143 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1144 U64 MaxLBA; /* 0x10 */
1145 U32 StripeSize; /* 0x18 */
1146 U16 BlockSize; /* 0x1C */
1147 U16 Reserved1; /* 0x1E */
1148 U8 SupportedPhysDisks; /* 0x20 */
1149 U8 ResyncRate; /* 0x21 */
1150 U16 DataScrubDuration; /* 0x22 */
1151 U8 NumPhysDisks; /* 0x24 */
1152 U8 Reserved2; /* 0x25 */
1153 U8 Reserved3; /* 0x26 */
1154 U8 InactiveStatus; /* 0x27 */
1155 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1156 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1157 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1159 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1161 /* values for RAID VolumeState */
1162 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1163 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1164 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1165 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1166 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1167 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1169 /* values for RAID VolumeType */
1170 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1171 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1172 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1173 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1174 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1176 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1177 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1178 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1179 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1180 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1181 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1182 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1183 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1184 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1185 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1186 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1187 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1188 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1189 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1190 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1191 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1192 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1193 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1194 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1196 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1197 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1198 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1199 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1200 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1202 /* values for RAID Volume Page 0 InactiveStatus field */
1203 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1204 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1205 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1206 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1207 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1208 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1209 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1212 /* RAID Volume Page 1 */
1214 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1216 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1217 U16 DevHandle; /* 0x04 */
1218 U16 Reserved0; /* 0x06 */
1219 U8 GUID[24]; /* 0x08 */
1220 U8 Name[16]; /* 0x20 */
1221 U64 WWID; /* 0x30 */
1222 U32 Reserved1; /* 0x38 */
1223 U32 Reserved2; /* 0x3C */
1224 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1225 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1227 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1230 /****************************************************************************
1231 * RAID Physical Disk Config Pages
1232 ****************************************************************************/
1234 /* RAID Physical Disk Page 0 */
1236 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1238 U16 Reserved1; /* 0x00 */
1239 U8 HotSparePool; /* 0x02 */
1240 U8 Reserved2; /* 0x03 */
1241 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1242 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1244 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1246 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1248 U8 VendorID[8]; /* 0x00 */
1249 U8 ProductID[16]; /* 0x08 */
1250 U8 ProductRevLevel[4]; /* 0x18 */
1251 U8 SerialNum[32]; /* 0x1C */
1252 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1253 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1254 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1256 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1258 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1259 U16 DevHandle; /* 0x04 */
1260 U8 Reserved1; /* 0x06 */
1261 U8 PhysDiskNum; /* 0x07 */
1262 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1263 U32 Reserved2; /* 0x0C */
1264 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1265 U32 Reserved3; /* 0x4C */
1266 U8 PhysDiskState; /* 0x50 */
1267 U8 OfflineReason; /* 0x51 */
1268 U8 IncompatibleReason; /* 0x52 */
1269 U8 PhysDiskAttributes; /* 0x53 */
1270 U32 PhysDiskStatusFlags; /* 0x54 */
1271 U64 DeviceMaxLBA; /* 0x58 */
1272 U64 HostMaxLBA; /* 0x60 */
1273 U64 CoercedMaxLBA; /* 0x68 */
1274 U16 BlockSize; /* 0x70 */
1275 U16 Reserved5; /* 0x72 */
1276 U32 Reserved6; /* 0x74 */
1277 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1278 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1279 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1281 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1283 /* PhysDiskState defines */
1284 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1285 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1286 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1287 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1288 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1289 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1290 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1291 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1293 /* OfflineReason defines */
1294 #define MPI2_PHYSDISK0_ONLINE (0x00)
1295 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1296 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1297 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1298 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1299 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1300 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1302 /* IncompatibleReason defines */
1303 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1304 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1305 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1306 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1307 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1308 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1309 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1311 /* PhysDiskAttributes defines */
1312 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1313 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1314 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1315 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1317 /* PhysDiskStatusFlags defines */
1318 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1319 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1320 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1321 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1322 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1323 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1324 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1325 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1328 /* RAID Physical Disk Page 1 */
1331 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1332 * one and check Header.PageLength or NumPhysDiskPaths at runtime.
1334 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1335 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1338 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1340 U16 DevHandle; /* 0x00 */
1341 U16 Reserved1; /* 0x02 */
1342 U64 WWID; /* 0x04 */
1343 U64 OwnerWWID; /* 0x0C */
1344 U8 OwnerIdentifier; /* 0x14 */
1345 U8 Reserved2; /* 0x15 */
1346 U16 Flags; /* 0x16 */
1347 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1348 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1350 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1351 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1352 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1353 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1355 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1357 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1358 U8 NumPhysDiskPaths; /* 0x04 */
1359 U8 PhysDiskNum; /* 0x05 */
1360 U16 Reserved1; /* 0x06 */
1361 U32 Reserved2; /* 0x08 */
1362 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1363 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1364 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1365 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1367 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1370 /****************************************************************************
1371 * values for fields used by several types of SAS Config Pages
1372 ****************************************************************************/
1374 /* values for NegotiatedLinkRates fields */
1375 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1376 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1377 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1378 /* link rates used for Negotiated Physical and Logical Link Rate */
1379 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1380 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1381 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1382 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1383 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1384 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1385 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1386 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1387 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1390 /* values for AttachedPhyInfo fields */
1391 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1392 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1393 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1395 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1396 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1397 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1398 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1399 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1400 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1401 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1402 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1403 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1404 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1407 /* values for PhyInfo fields */
1408 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1409 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1410 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1411 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1412 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1413 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1414 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1416 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1417 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1418 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1419 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1420 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1421 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1422 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1423 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1424 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1425 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1427 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1428 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1429 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1430 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1432 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1433 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1435 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1436 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1437 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1438 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1441 /* values for SAS ProgrammedLinkRate fields */
1442 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1443 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1444 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1445 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1446 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1447 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1448 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1449 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1450 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1451 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1454 /* values for SAS HwLinkRate fields */
1455 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1456 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1457 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1458 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1459 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1460 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1461 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1462 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1466 /****************************************************************************
1467 * SAS IO Unit Config Pages
1468 ****************************************************************************/
1470 /* SAS IO Unit Page 0 */
1472 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1475 U8 PortFlags; /* 0x01 */
1476 U8 PhyFlags; /* 0x02 */
1477 U8 NegotiatedLinkRate; /* 0x03 */
1478 U32 ControllerPhyDeviceInfo;/* 0x04 */
1479 U16 AttachedDevHandle; /* 0x08 */
1480 U16 ControllerDevHandle; /* 0x0A */
1481 U32 DiscoveryStatus; /* 0x0C */
1482 U32 Reserved; /* 0x10 */
1483 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1484 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1487 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1488 * one and check Header.ExtPageLength or NumPhys at runtime.
1490 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1491 #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1494 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1496 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1497 U32 Reserved1; /* 0x08 */
1498 U8 NumPhys; /* 0x0C */
1499 U8 Reserved2; /* 0x0D */
1500 U16 Reserved3; /* 0x0E */
1501 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1502 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1503 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1504 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1506 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1508 /* values for SAS IO Unit Page 0 PortFlags */
1509 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1510 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1512 /* values for SAS IO Unit Page 0 PhyFlags */
1513 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1514 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1516 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1518 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1520 /* values for SAS IO Unit Page 0 DiscoveryStatus */
1521 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1522 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1523 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1524 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1525 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1526 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1527 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1528 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1529 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1530 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1531 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1532 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1533 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1534 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1535 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1536 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1537 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1538 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1539 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1540 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1543 /* SAS IO Unit Page 1 */
1545 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1548 U8 PortFlags; /* 0x01 */
1549 U8 PhyFlags; /* 0x02 */
1550 U8 MaxMinLinkRate; /* 0x03 */
1551 U32 ControllerPhyDeviceInfo; /* 0x04 */
1552 U16 MaxTargetPortConnectTime; /* 0x08 */
1553 U16 Reserved1; /* 0x0A */
1554 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1555 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1558 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1559 * one and check Header.ExtPageLength or NumPhys at runtime.
1561 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1562 #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1565 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1567 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1568 U16 ControlFlags; /* 0x08 */
1569 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1570 U16 AdditionalControlFlags; /* 0x0C */
1571 U16 SASWideMaxQueueDepth; /* 0x0E */
1572 U8 NumPhys; /* 0x10 */
1573 U8 SATAMaxQDepth; /* 0x11 */
1574 U8 ReportDeviceMissingDelay; /* 0x12 */
1575 U8 IODeviceMissingDelay; /* 0x13 */
1576 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1577 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
1578 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1579 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1581 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1583 /* values for SAS IO Unit Page 1 ControlFlags */
1584 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1585 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1586 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1587 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1589 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1590 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1591 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1592 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1593 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1595 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1596 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1597 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1598 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1599 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1600 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1601 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1602 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
1604 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
1605 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1606 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1607 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1608 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1609 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1610 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1611 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1612 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1614 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1615 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1616 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1618 /* values for SAS IO Unit Page 1 PortFlags */
1619 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1621 /* values for SAS IO Unit Page 2 PhyFlags */
1622 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1623 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1625 /* values for SAS IO Unit Page 0 MaxMinLinkRate */
1626 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1627 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1628 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1629 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1630 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1631 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1632 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1633 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1635 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1638 /* SAS IO Unit Page 4 */
1640 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1642 U8 MaxTargetSpinup; /* 0x00 */
1643 U8 SpinupDelay; /* 0x01 */
1644 U16 Reserved1; /* 0x02 */
1645 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1646 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1649 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1650 * four and check Header.ExtPageLength or NumPhys at runtime.
1652 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1653 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
1656 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1658 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1659 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
1660 U32 Reserved1; /* 0x18 */
1661 U32 Reserved2; /* 0x1C */
1662 U32 Reserved3; /* 0x20 */
1663 U8 BootDeviceWaitTime; /* 0x24 */
1664 U8 Reserved4; /* 0x25 */
1665 U16 Reserved5; /* 0x26 */
1666 U8 NumPhys; /* 0x28 */
1667 U8 PEInitialSpinupDelay; /* 0x29 */
1668 U8 PEReplyDelay; /* 0x2A */
1669 U8 Flags; /* 0x2B */
1670 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
1671 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
1672 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
1673 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
1675 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
1677 /* defines for Flags field */
1678 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
1680 /* defines for PHY field */
1681 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
1684 /****************************************************************************
1685 * SAS Expander Config Pages
1686 ****************************************************************************/
1688 /* SAS Expander Page 0 */
1690 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
1692 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1693 U8 PhysicalPort; /* 0x08 */
1694 U8 ReportGenLength; /* 0x09 */
1695 U16 EnclosureHandle; /* 0x0A */
1696 U64 SASAddress; /* 0x0C */
1697 U32 DiscoveryStatus; /* 0x14 */
1698 U16 DevHandle; /* 0x18 */
1699 U16 ParentDevHandle; /* 0x1A */
1700 U16 ExpanderChangeCount; /* 0x1C */
1701 U16 ExpanderRouteIndexes; /* 0x1E */
1702 U8 NumPhys; /* 0x20 */
1703 U8 SASLevel; /* 0x21 */
1704 U16 Flags; /* 0x22 */
1705 U16 STPBusInactivityTimeLimit; /* 0x24 */
1706 U16 STPMaxConnectTimeLimit; /* 0x26 */
1707 U16 STP_SMP_NexusLossTime; /* 0x28 */
1708 U16 MaxNumRoutedSasAddresses; /* 0x2A */
1709 U64 ActiveZoneManagerSASAddress;/* 0x2C */
1710 U16 ZoneLockInactivityLimit; /* 0x34 */
1711 U16 Reserved1; /* 0x36 */
1712 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
1713 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
1715 #define MPI2_SASEXPANDER0_PAGEVERSION (0x05)
1717 /* values for SAS Expander Page 0 DiscoveryStatus field */
1718 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1719 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1720 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
1721 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1722 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1723 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1724 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1725 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
1726 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1727 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
1728 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
1729 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
1730 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
1731 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
1732 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
1733 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1734 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
1735 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
1736 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1737 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
1739 /* values for SAS Expander Page 0 Flags field */
1740 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
1741 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
1742 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
1743 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
1744 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
1745 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
1746 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
1747 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
1748 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
1749 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
1752 /* SAS Expander Page 1 */
1754 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
1756 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1757 U8 PhysicalPort; /* 0x08 */
1758 U8 Reserved1; /* 0x09 */
1759 U16 Reserved2; /* 0x0A */
1760 U8 NumPhys; /* 0x0C */
1762 U16 NumTableEntriesProgrammed; /* 0x0E */
1763 U8 ProgrammedLinkRate; /* 0x10 */
1764 U8 HwLinkRate; /* 0x11 */
1765 U16 AttachedDevHandle; /* 0x12 */
1766 U32 PhyInfo; /* 0x14 */
1767 U32 AttachedDeviceInfo; /* 0x18 */
1768 U16 ExpanderDevHandle; /* 0x1C */
1769 U8 ChangeCount; /* 0x1E */
1770 U8 NegotiatedLinkRate; /* 0x1F */
1771 U8 PhyIdentifier; /* 0x20 */
1772 U8 AttachedPhyIdentifier; /* 0x21 */
1773 U8 Reserved3; /* 0x22 */
1774 U8 DiscoveryInfo; /* 0x23 */
1775 U32 AttachedPhyInfo; /* 0x24 */
1776 U8 ZoneGroup; /* 0x28 */
1777 U8 SelfConfigStatus; /* 0x29 */
1778 U16 Reserved4; /* 0x2A */
1779 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
1780 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
1782 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
1784 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
1786 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
1788 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
1790 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
1792 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1794 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
1796 /* values for SAS Expander Page 1 DiscoveryInfo field */
1797 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
1798 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
1799 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
1802 /****************************************************************************
1803 * SAS Device Config Pages
1804 ****************************************************************************/
1806 /* SAS Device Page 0 */
1808 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
1810 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1811 U16 Slot; /* 0x08 */
1812 U16 EnclosureHandle; /* 0x0A */
1813 U64 SASAddress; /* 0x0C */
1814 U16 ParentDevHandle; /* 0x14 */
1815 U8 PhyNum; /* 0x16 */
1816 U8 AccessStatus; /* 0x17 */
1817 U16 DevHandle; /* 0x18 */
1818 U8 AttachedPhyIdentifier; /* 0x1A */
1819 U8 ZoneGroup; /* 0x1B */
1820 U32 DeviceInfo; /* 0x1C */
1821 U16 Flags; /* 0x20 */
1822 U8 PhysicalPort; /* 0x22 */
1823 U8 MaxPortConnections; /* 0x23 */
1824 U64 DeviceName; /* 0x24 */
1825 U8 PortGroups; /* 0x2C */
1826 U8 DmaGroup; /* 0x2D */
1827 U8 ControlGroup; /* 0x2E */
1828 U8 Reserved1; /* 0x2F */
1829 U32 Reserved2; /* 0x30 */
1830 U32 Reserved3; /* 0x34 */
1831 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
1832 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
1834 #define MPI2_SASDEVICE0_PAGEVERSION (0x08)
1836 /* values for SAS Device Page 0 AccessStatus field */
1837 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
1838 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
1839 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
1840 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
1841 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
1842 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
1843 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
1844 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
1845 /* specific values for SATA Init failures */
1846 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
1847 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
1848 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
1849 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
1850 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
1851 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
1852 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
1853 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
1854 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
1855 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
1856 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
1858 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
1860 /* values for SAS Device Page 0 Flags field */
1861 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
1862 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
1863 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
1864 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
1865 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
1866 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
1867 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
1868 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
1869 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
1872 /* SAS Device Page 1 */
1874 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
1876 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1877 U32 Reserved1; /* 0x08 */
1878 U64 SASAddress; /* 0x0C */
1879 U32 Reserved2; /* 0x14 */
1880 U16 DevHandle; /* 0x18 */
1881 U16 Reserved3; /* 0x1A */
1882 U8 InitialRegDeviceFIS[20];/* 0x1C */
1883 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
1884 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
1886 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
1889 /****************************************************************************
1890 * SAS PHY Config Pages
1891 ****************************************************************************/
1893 /* SAS PHY Page 0 */
1895 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
1897 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1898 U16 OwnerDevHandle; /* 0x08 */
1899 U16 Reserved1; /* 0x0A */
1900 U16 AttachedDevHandle; /* 0x0C */
1901 U8 AttachedPhyIdentifier; /* 0x0E */
1902 U8 Reserved2; /* 0x0F */
1903 U32 AttachedPhyInfo; /* 0x10 */
1904 U8 ProgrammedLinkRate; /* 0x14 */
1905 U8 HwLinkRate; /* 0x15 */
1906 U8 ChangeCount; /* 0x16 */
1907 U8 Flags; /* 0x17 */
1908 U32 PhyInfo; /* 0x18 */
1909 U8 NegotiatedLinkRate; /* 0x1C */
1910 U8 Reserved3; /* 0x1D */
1911 U16 Reserved4; /* 0x1E */
1912 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
1913 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
1915 #define MPI2_SASPHY0_PAGEVERSION (0x03)
1917 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
1919 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
1921 /* values for SAS PHY Page 0 Flags field */
1922 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
1924 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
1926 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1928 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
1931 /* SAS PHY Page 1 */
1933 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
1935 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1936 U32 Reserved1; /* 0x08 */
1937 U32 InvalidDwordCount; /* 0x0C */
1938 U32 RunningDisparityErrorCount; /* 0x10 */
1939 U32 LossDwordSynchCount; /* 0x14 */
1940 U32 PhyResetProblemCount; /* 0x18 */
1941 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
1942 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
1944 #define MPI2_SASPHY1_PAGEVERSION (0x01)
1947 /****************************************************************************
1948 * SAS Port Config Pages
1949 ****************************************************************************/
1951 /* SAS Port Page 0 */
1953 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
1955 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1956 U8 PortNumber; /* 0x08 */
1957 U8 PhysicalPort; /* 0x09 */
1958 U8 PortWidth; /* 0x0A */
1959 U8 PhysicalPortWidth; /* 0x0B */
1960 U8 ZoneGroup; /* 0x0C */
1961 U8 Reserved1; /* 0x0D */
1962 U16 Reserved2; /* 0x0E */
1963 U64 SASAddress; /* 0x10 */
1964 U32 DeviceInfo; /* 0x18 */
1965 U32 Reserved3; /* 0x1C */
1966 U32 Reserved4; /* 0x20 */
1967 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
1968 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
1970 #define MPI2_SASPORT0_PAGEVERSION (0x00)
1972 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
1975 /****************************************************************************
1976 * SAS Enclosure Config Pages
1977 ****************************************************************************/
1979 /* SAS Enclosure Page 0 */
1981 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
1983 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1984 U32 Reserved1; /* 0x08 */
1985 U64 EnclosureLogicalID; /* 0x0C */
1986 U16 Flags; /* 0x14 */
1987 U16 EnclosureHandle; /* 0x16 */
1988 U16 NumSlots; /* 0x18 */
1989 U16 StartSlot; /* 0x1A */
1990 U16 Reserved2; /* 0x1C */
1991 U16 SEPDevHandle; /* 0x1E */
1992 U32 Reserved3; /* 0x20 */
1993 U32 Reserved4; /* 0x24 */
1994 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
1995 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
1996 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
1998 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
2000 /* values for SAS Enclosure Page 0 Flags field */
2001 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2002 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2003 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2004 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2005 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2006 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2007 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2010 /****************************************************************************
2012 ****************************************************************************/
2017 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2018 * one and check Header.ExtPageLength or NumPhys at runtime.
2020 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2021 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2024 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2026 typedef struct _MPI2_LOG_0_ENTRY
2028 U64 TimeStamp; /* 0x00 */
2029 U32 Reserved1; /* 0x08 */
2030 U16 LogSequence; /* 0x0C */
2031 U16 LogEntryQualifier; /* 0x0E */
2032 U8 VP_ID; /* 0x10 */
2033 U8 VF_ID; /* 0x11 */
2034 U16 Reserved2; /* 0x12 */
2035 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2036 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2037 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2039 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2040 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2041 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2042 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2043 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2044 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2046 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2048 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2049 U32 Reserved1; /* 0x08 */
2050 U32 Reserved2; /* 0x0C */
2051 U16 NumLogEntries; /* 0x10 */
2052 U16 Reserved3; /* 0x12 */
2053 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2054 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2055 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2057 #define MPI2_LOG_0_PAGEVERSION (0x02)
2060 /****************************************************************************
2062 ****************************************************************************/
2067 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2068 * one and check Header.ExtPageLength or NumPhys at runtime.
2070 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2071 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2074 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2076 U16 ElementFlags; /* 0x00 */
2077 U16 VolDevHandle; /* 0x02 */
2078 U8 HotSparePool; /* 0x04 */
2079 U8 PhysDiskNum; /* 0x05 */
2080 U16 PhysDiskDevHandle; /* 0x06 */
2081 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2082 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2083 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2085 /* values for the ElementFlags field */
2086 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2087 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2088 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2089 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2090 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2093 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2095 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2096 U8 NumHotSpares; /* 0x08 */
2097 U8 NumPhysDisks; /* 0x09 */
2098 U8 NumVolumes; /* 0x0A */
2099 U8 ConfigNum; /* 0x0B */
2100 U32 Flags; /* 0x0C */
2101 U8 ConfigGUID[24]; /* 0x10 */
2102 U32 Reserved1; /* 0x28 */
2103 U8 NumElements; /* 0x2C */
2104 U8 Reserved2; /* 0x2D */
2105 U16 Reserved3; /* 0x2E */
2106 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2107 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2108 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2109 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2111 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2113 /* values for RAID Configuration Page 0 Flags field */
2114 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2117 /****************************************************************************
2118 * Driver Persistent Mapping Config Pages
2119 ****************************************************************************/
2121 /* Driver Persistent Mapping Page 0 */
2123 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2125 U64 PhysicalIdentifier; /* 0x00 */
2126 U16 MappingInformation; /* 0x08 */
2127 U16 DeviceIndex; /* 0x0A */
2128 U32 PhysicalBitsMapping; /* 0x0C */
2129 U32 Reserved1; /* 0x10 */
2130 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2131 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2132 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2134 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2136 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2137 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2138 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2139 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2140 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2142 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2144 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
2145 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2146 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2147 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
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