3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
20 #include <asm/errno.h>
26 static int pci_msi_enable = 1;
30 #ifndef arch_msi_check_device
31 int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
37 #ifndef arch_setup_msi_irqs
38 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
40 struct msi_desc *entry;
44 * If an architecture wants to support multiple MSI, it needs to
45 * override arch_setup_msi_irqs()
47 if (type == PCI_CAP_ID_MSI && nvec > 1)
50 list_for_each_entry(entry, &dev->msi_list, list) {
51 ret = arch_setup_msi_irq(dev, entry);
62 #ifndef arch_teardown_msi_irqs
63 void arch_teardown_msi_irqs(struct pci_dev *dev)
65 struct msi_desc *entry;
67 list_for_each_entry(entry, &dev->msi_list, list) {
71 nvec = 1 << entry->msi_attrib.multiple;
72 for (i = 0; i < nvec; i++)
73 arch_teardown_msi_irq(entry->irq + i);
78 static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
84 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
85 control &= ~PCI_MSI_FLAGS_ENABLE;
87 control |= PCI_MSI_FLAGS_ENABLE;
88 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
91 static void msix_set_enable(struct pci_dev *dev, int enable)
96 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
98 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
99 control &= ~PCI_MSIX_FLAGS_ENABLE;
101 control |= PCI_MSIX_FLAGS_ENABLE;
102 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
106 static inline __attribute_const__ u32 msi_mask(unsigned x)
108 /* Don't shift by >= width of type */
111 return (1 << (1 << x)) - 1;
114 static inline __attribute_const__ u32 msi_capable_mask(u16 control)
116 return msi_mask((control >> 1) & 7);
119 static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
121 return msi_mask((control >> 4) & 7);
125 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
126 * mask all MSI interrupts by clearing the MSI enable bit does not work
127 * reliably as devices without an INTx disable bit will then generate a
128 * level IRQ which will never be cleared.
130 static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
132 u32 mask_bits = desc->masked;
134 if (!desc->msi_attrib.maskbit)
139 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
144 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
146 desc->masked = __msi_mask_irq(desc, mask, flag);
150 * This internal function does not flush PCI writes to the device.
151 * All users must ensure that they read from the device before either
152 * assuming that the device state is up to date, or returning out of this
153 * file. This saves a few milliseconds when initialising devices with lots
154 * of MSI-X interrupts.
156 static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
158 u32 mask_bits = desc->masked;
159 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
160 PCI_MSIX_ENTRY_VECTOR_CTRL;
163 writel(mask_bits, desc->mask_base + offset);
168 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
170 desc->masked = __msix_mask_irq(desc, flag);
173 static void msi_set_mask_bit(unsigned irq, u32 flag)
175 struct msi_desc *desc = get_irq_msi(irq);
177 if (desc->msi_attrib.is_msix) {
178 msix_mask_irq(desc, flag);
179 readl(desc->mask_base); /* Flush write to device */
181 unsigned offset = irq - desc->dev->irq;
182 msi_mask_irq(desc, 1 << offset, flag << offset);
186 void mask_msi_irq(unsigned int irq)
188 msi_set_mask_bit(irq, 1);
191 void unmask_msi_irq(unsigned int irq)
193 msi_set_mask_bit(irq, 0);
196 void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
198 struct msi_desc *entry = get_irq_desc_msi(desc);
199 if (entry->msi_attrib.is_msix) {
200 void __iomem *base = entry->mask_base +
201 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
203 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
204 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
205 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
207 struct pci_dev *dev = entry->dev;
208 int pos = entry->msi_attrib.pos;
211 pci_read_config_dword(dev, msi_lower_address_reg(pos),
213 if (entry->msi_attrib.is_64) {
214 pci_read_config_dword(dev, msi_upper_address_reg(pos),
216 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
219 pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
225 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
227 struct irq_desc *desc = irq_to_desc(irq);
229 read_msi_msg_desc(desc, msg);
232 void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
234 struct msi_desc *entry = get_irq_desc_msi(desc);
235 if (entry->msi_attrib.is_msix) {
237 base = entry->mask_base +
238 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
240 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
241 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
242 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
244 struct pci_dev *dev = entry->dev;
245 int pos = entry->msi_attrib.pos;
248 pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
249 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
250 msgctl |= entry->msi_attrib.multiple << 4;
251 pci_write_config_word(dev, msi_control_reg(pos), msgctl);
253 pci_write_config_dword(dev, msi_lower_address_reg(pos),
255 if (entry->msi_attrib.is_64) {
256 pci_write_config_dword(dev, msi_upper_address_reg(pos),
258 pci_write_config_word(dev, msi_data_reg(pos, 1),
261 pci_write_config_word(dev, msi_data_reg(pos, 0),
268 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
270 struct irq_desc *desc = irq_to_desc(irq);
272 write_msi_msg_desc(desc, msg);
275 static int msi_free_irqs(struct pci_dev* dev);
277 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
279 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
283 INIT_LIST_HEAD(&desc->list);
289 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
291 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
292 pci_intx(dev, enable);
295 static void __pci_restore_msi_state(struct pci_dev *dev)
299 struct msi_desc *entry;
301 if (!dev->msi_enabled)
304 entry = get_irq_msi(dev->irq);
305 pos = entry->msi_attrib.pos;
307 pci_intx_for_msi(dev, 0);
308 msi_set_enable(dev, pos, 0);
309 write_msi_msg(dev->irq, &entry->msg);
311 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
312 msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
313 control &= ~PCI_MSI_FLAGS_QSIZE;
314 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
315 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
318 static void __pci_restore_msix_state(struct pci_dev *dev)
321 struct msi_desc *entry;
324 if (!dev->msix_enabled)
326 BUG_ON(list_empty(&dev->msi_list));
327 entry = list_entry(dev->msi_list.next, struct msi_desc, list);
328 pos = entry->msi_attrib.pos;
329 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
331 /* route the table */
332 pci_intx_for_msi(dev, 0);
333 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
334 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
336 list_for_each_entry(entry, &dev->msi_list, list) {
337 write_msi_msg(entry->irq, &entry->msg);
338 msix_mask_irq(entry, entry->masked);
341 control &= ~PCI_MSIX_FLAGS_MASKALL;
342 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
345 void pci_restore_msi_state(struct pci_dev *dev)
347 __pci_restore_msi_state(dev);
348 __pci_restore_msix_state(dev);
350 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
353 * msi_capability_init - configure device's MSI capability structure
354 * @dev: pointer to the pci_dev data structure of MSI device function
355 * @nvec: number of interrupts to allocate
357 * Setup the MSI capability structure of the device with the requested
358 * number of interrupts. A return value of zero indicates the successful
359 * setup of an entry with the new MSI irq. A negative return value indicates
360 * an error, and a positive return value indicates the number of interrupts
361 * which could have been allocated.
363 static int msi_capability_init(struct pci_dev *dev, int nvec)
365 struct msi_desc *entry;
370 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
371 msi_set_enable(dev, pos, 0); /* Disable MSI during set up */
373 pci_read_config_word(dev, msi_control_reg(pos), &control);
374 /* MSI Entry Initialization */
375 entry = alloc_msi_entry(dev);
379 entry->msi_attrib.is_msix = 0;
380 entry->msi_attrib.is_64 = is_64bit_address(control);
381 entry->msi_attrib.entry_nr = 0;
382 entry->msi_attrib.maskbit = is_mask_bit_support(control);
383 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
384 entry->msi_attrib.pos = pos;
386 entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64);
387 /* All MSIs are unmasked by default, Mask them all */
388 if (entry->msi_attrib.maskbit)
389 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
390 mask = msi_capable_mask(control);
391 msi_mask_irq(entry, mask, mask);
393 list_add_tail(&entry->list, &dev->msi_list);
395 /* Configure MSI capability structure */
396 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
398 msi_mask_irq(entry, mask, ~mask);
403 /* Set MSI enabled bits */
404 pci_intx_for_msi(dev, 0);
405 msi_set_enable(dev, pos, 1);
406 dev->msi_enabled = 1;
408 dev->irq = entry->irq;
413 * msix_capability_init - configure device's MSI-X capability
414 * @dev: pointer to the pci_dev data structure of MSI-X device function
415 * @entries: pointer to an array of struct msix_entry entries
416 * @nvec: number of @entries
418 * Setup the MSI-X capability structure of device function with a
419 * single MSI-X irq. A return of zero indicates the successful setup of
420 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
422 static int msix_capability_init(struct pci_dev *dev,
423 struct msix_entry *entries, int nvec)
425 struct msi_desc *entry;
426 int pos, i, j, nr_entries, ret;
427 unsigned long phys_addr;
433 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
434 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
436 /* Ensure MSI-X is disabled while it is set up */
437 control &= ~PCI_MSIX_FLAGS_ENABLE;
438 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
440 /* Request & Map MSI-X table region */
441 nr_entries = multi_msix_capable(control);
443 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
444 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
445 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
446 phys_addr = pci_resource_start (dev, bir) + table_offset;
447 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
451 for (i = 0; i < nvec; i++) {
452 entry = alloc_msi_entry(dev);
458 /* No enough memory. Don't try again */
462 j = entries[i].entry;
463 entry->msi_attrib.is_msix = 1;
464 entry->msi_attrib.is_64 = 1;
465 entry->msi_attrib.entry_nr = j;
466 entry->msi_attrib.default_irq = dev->irq;
467 entry->msi_attrib.pos = pos;
468 entry->mask_base = base;
470 list_add_tail(&entry->list, &dev->msi_list);
473 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
475 /* If we had some success report the number of irqs
476 * we succeeded in setting up. */
478 list_for_each_entry(entry, &dev->msi_list, list) {
479 if (entry->irq != 0) {
494 * Some devices require MSI-X to be enabled before we can touch the
495 * MSI-X registers. We need to mask all the vectors to prevent
496 * interrupts coming in before they're fully set up.
498 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
499 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
502 list_for_each_entry(entry, &dev->msi_list, list) {
503 entries[i].vector = entry->irq;
504 set_irq_msi(entry->irq, entry);
505 j = entries[i].entry;
506 entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE +
507 PCI_MSIX_ENTRY_VECTOR_CTRL);
508 msix_mask_irq(entry, 1);
512 /* Set MSI-X enabled bits and unmask the function */
513 pci_intx_for_msi(dev, 0);
514 dev->msix_enabled = 1;
516 control &= ~PCI_MSIX_FLAGS_MASKALL;
517 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
523 * pci_msi_check_device - check whether MSI may be enabled on a device
524 * @dev: pointer to the pci_dev data structure of MSI device function
525 * @nvec: how many MSIs have been requested ?
526 * @type: are we checking for MSI or MSI-X ?
528 * Look at global flags, the device itself, and its parent busses
529 * to determine if MSI/-X are supported for the device. If MSI/-X is
530 * supported return 0, else return an error code.
532 static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type)
537 /* MSI must be globally enabled and supported by the device */
538 if (!pci_msi_enable || !dev || dev->no_msi)
542 * You can't ask to have 0 or less MSIs configured.
544 * b) the list manipulation code assumes nvec >= 1.
549 /* Any bridge which does NOT route MSI transactions from it's
550 * secondary bus to it's primary bus must set NO_MSI flag on
551 * the secondary pci_bus.
552 * We expect only arch-specific PCI host bus controller driver
553 * or quirks for specific PCI bridges to be setting NO_MSI.
555 for (bus = dev->bus; bus; bus = bus->parent)
556 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
559 ret = arch_msi_check_device(dev, nvec, type);
563 if (!pci_find_capability(dev, type))
570 * pci_enable_msi_block - configure device's MSI capability structure
571 * @dev: device to configure
572 * @nvec: number of interrupts to configure
574 * Allocate IRQs for a device with the MSI capability.
575 * This function returns a negative errno if an error occurs. If it
576 * is unable to allocate the number of interrupts requested, it returns
577 * the number of interrupts it might be able to allocate. If it successfully
578 * allocates at least the number of interrupts requested, it returns 0 and
579 * updates the @dev's irq member to the lowest new interrupt number; the
580 * other interrupt numbers allocated to this device are consecutive.
582 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
584 int status, pos, maxvec;
587 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
590 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
591 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
595 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
599 WARN_ON(!!dev->msi_enabled);
601 /* Check whether driver already requested MSI-X irqs */
602 if (dev->msix_enabled) {
603 dev_info(&dev->dev, "can't enable MSI "
604 "(MSI-X already enabled)\n");
608 status = msi_capability_init(dev, nvec);
611 EXPORT_SYMBOL(pci_enable_msi_block);
613 void pci_msi_shutdown(struct pci_dev *dev)
615 struct msi_desc *desc;
620 if (!pci_msi_enable || !dev || !dev->msi_enabled)
623 BUG_ON(list_empty(&dev->msi_list));
624 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
625 pos = desc->msi_attrib.pos;
627 msi_set_enable(dev, pos, 0);
628 pci_intx_for_msi(dev, 1);
629 dev->msi_enabled = 0;
631 /* Return the device with MSI unmasked as initial states */
632 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl);
633 mask = msi_capable_mask(ctrl);
634 /* Keep cached state to be restored */
635 __msi_mask_irq(desc, mask, ~mask);
637 /* Restore dev->irq to its default pin-assertion irq */
638 dev->irq = desc->msi_attrib.default_irq;
641 void pci_disable_msi(struct pci_dev* dev)
643 struct msi_desc *entry;
645 if (!pci_msi_enable || !dev || !dev->msi_enabled)
648 pci_msi_shutdown(dev);
650 entry = list_entry(dev->msi_list.next, struct msi_desc, list);
651 if (entry->msi_attrib.is_msix)
656 EXPORT_SYMBOL(pci_disable_msi);
658 static int msi_free_irqs(struct pci_dev* dev)
660 struct msi_desc *entry, *tmp;
662 list_for_each_entry(entry, &dev->msi_list, list) {
666 nvec = 1 << entry->msi_attrib.multiple;
667 for (i = 0; i < nvec; i++)
668 BUG_ON(irq_has_action(entry->irq + i));
671 arch_teardown_msi_irqs(dev);
673 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
674 if (entry->msi_attrib.is_msix) {
675 if (list_is_last(&entry->list, &dev->msi_list))
676 iounmap(entry->mask_base);
678 list_del(&entry->list);
686 * pci_msix_table_size - return the number of device's MSI-X table entries
687 * @dev: pointer to the pci_dev data structure of MSI-X device function
689 int pci_msix_table_size(struct pci_dev *dev)
694 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
698 pci_read_config_word(dev, msi_control_reg(pos), &control);
699 return multi_msix_capable(control);
703 * pci_enable_msix - configure device's MSI-X capability structure
704 * @dev: pointer to the pci_dev data structure of MSI-X device function
705 * @entries: pointer to an array of MSI-X entries
706 * @nvec: number of MSI-X irqs requested for allocation by device driver
708 * Setup the MSI-X capability structure of device function with the number
709 * of requested irqs upon its software driver call to request for
710 * MSI-X mode enabled on its hardware device function. A return of zero
711 * indicates the successful configuration of MSI-X capability structure
712 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
713 * Or a return of > 0 indicates that driver request is exceeding the number
714 * of irqs or MSI-X vectors available. Driver should use the returned value to
715 * re-send its request.
717 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
719 int status, nr_entries;
725 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
729 nr_entries = pci_msix_table_size(dev);
730 if (nvec > nr_entries)
733 /* Check for any invalid entries */
734 for (i = 0; i < nvec; i++) {
735 if (entries[i].entry >= nr_entries)
736 return -EINVAL; /* invalid entry */
737 for (j = i + 1; j < nvec; j++) {
738 if (entries[i].entry == entries[j].entry)
739 return -EINVAL; /* duplicate entry */
742 WARN_ON(!!dev->msix_enabled);
744 /* Check whether driver already requested for MSI irq */
745 if (dev->msi_enabled) {
746 dev_info(&dev->dev, "can't enable MSI-X "
747 "(MSI IRQ already assigned)\n");
750 status = msix_capability_init(dev, entries, nvec);
753 EXPORT_SYMBOL(pci_enable_msix);
755 static void msix_free_all_irqs(struct pci_dev *dev)
760 void pci_msix_shutdown(struct pci_dev* dev)
762 struct msi_desc *entry;
764 if (!pci_msi_enable || !dev || !dev->msix_enabled)
767 /* Return the device with MSI-X masked as initial states */
768 list_for_each_entry(entry, &dev->msi_list, list) {
769 /* Keep cached states to be restored */
770 __msix_mask_irq(entry, 1);
773 msix_set_enable(dev, 0);
774 pci_intx_for_msi(dev, 1);
775 dev->msix_enabled = 0;
777 void pci_disable_msix(struct pci_dev* dev)
779 if (!pci_msi_enable || !dev || !dev->msix_enabled)
782 pci_msix_shutdown(dev);
784 msix_free_all_irqs(dev);
786 EXPORT_SYMBOL(pci_disable_msix);
789 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
790 * @dev: pointer to the pci_dev data structure of MSI(X) device function
792 * Being called during hotplug remove, from which the device function
793 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
794 * allocated for this device function, are reclaimed to unused state,
795 * which may be used later on.
797 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
799 if (!pci_msi_enable || !dev)
802 if (dev->msi_enabled)
805 if (dev->msix_enabled)
806 msix_free_all_irqs(dev);
809 void pci_no_msi(void)
815 * pci_msi_enabled - is MSI enabled?
817 * Returns true if MSI has not been disabled by the command-line option
820 int pci_msi_enabled(void)
822 return pci_msi_enable;
824 EXPORT_SYMBOL(pci_msi_enabled);
826 void pci_msi_init_pci_dev(struct pci_dev *dev)
828 INIT_LIST_HEAD(&dev->msi_list);