2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
18 /* Ugh. Need to stop exporting this to modules. */
19 LIST_HEAD(pci_root_buses);
20 EXPORT_SYMBOL(pci_root_buses);
23 static int find_anything(struct device *dev, void *data)
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
33 int no_pci_devices(void)
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
43 EXPORT_SYMBOL(no_pci_devices);
46 * PCI Bus Class Devices
48 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
50 struct device_attribute *attr,
54 const struct cpumask *cpumask;
56 cpumask = cpumask_of_pcibus(to_pci_bus(dev));
58 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) :
59 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
65 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
66 struct device_attribute *attr,
69 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
72 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
73 struct device_attribute *attr,
76 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
79 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
80 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
85 static void release_pcibus_dev(struct device *dev)
87 struct pci_bus *pci_bus = to_pci_bus(dev);
90 put_device(pci_bus->bridge);
94 static struct class pcibus_class = {
96 .dev_release = &release_pcibus_dev,
99 static int __init pcibus_class_init(void)
101 return class_register(&pcibus_class);
103 postcore_initcall(pcibus_class_init);
106 * Translate the low bits of the PCI base
107 * to the resource type
109 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
111 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
112 return IORESOURCE_IO;
114 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
115 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
117 return IORESOURCE_MEM;
120 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
122 u64 size = mask & maxbase; /* Find the significant bits */
126 /* Get the lowest of them to find the decode size, and
127 from that the extent. */
128 size = (size & ~(size-1)) - 1;
130 /* base == maxbase can be valid only if the BAR has
131 already been programmed with all 1s. */
132 if (base == maxbase && ((base | size) & mask) != mask)
138 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
140 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
141 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
145 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
147 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
148 return pci_bar_mem64;
149 return pci_bar_mem32;
153 * pci_read_base - read a PCI BAR
154 * @dev: the PCI device
155 * @type: type of the BAR
156 * @res: resource buffer to be filled in
157 * @pos: BAR position in the config space
159 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
161 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
162 struct resource *res, unsigned int pos)
166 mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
168 res->name = pci_name(dev);
170 pci_read_config_dword(dev, pos, &l);
171 pci_write_config_dword(dev, pos, mask);
172 pci_read_config_dword(dev, pos, &sz);
173 pci_write_config_dword(dev, pos, l);
176 * All bits set in sz means the device isn't working properly.
177 * If the BAR isn't implemented, all bits must be 0. If it's a
178 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
181 if (!sz || sz == 0xffffffff)
185 * I don't know how l can have all bits set. Copied from old code.
186 * Maybe it fixes a bug on some ancient platform.
191 if (type == pci_bar_unknown) {
192 type = decode_bar(res, l);
193 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
194 if (type == pci_bar_io) {
195 l &= PCI_BASE_ADDRESS_IO_MASK;
196 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
198 l &= PCI_BASE_ADDRESS_MEM_MASK;
199 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
202 res->flags |= (l & IORESOURCE_ROM_ENABLE);
203 l &= PCI_ROM_ADDRESS_MASK;
204 mask = (u32)PCI_ROM_ADDRESS_MASK;
207 if (type == pci_bar_mem64) {
210 u64 mask64 = mask | (u64)~0 << 32;
212 pci_read_config_dword(dev, pos + 4, &l);
213 pci_write_config_dword(dev, pos + 4, ~0);
214 pci_read_config_dword(dev, pos + 4, &sz);
215 pci_write_config_dword(dev, pos + 4, l);
217 l64 |= ((u64)l << 32);
218 sz64 |= ((u64)sz << 32);
220 sz64 = pci_size(l64, sz64, mask64);
225 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
226 dev_err(&dev->dev, "can't handle 64-bit BAR\n");
228 } else if ((sizeof(resource_size_t) < 8) && l) {
229 /* Address above 32-bit boundary; disable the BAR */
230 pci_write_config_dword(dev, pos, 0);
231 pci_write_config_dword(dev, pos + 4, 0);
236 res->end = l64 + sz64;
237 dev_printk(KERN_DEBUG, &dev->dev,
238 "reg %x 64bit mmio: %pR\n", pos, res);
241 res->flags |= IORESOURCE_MEM_64;
243 sz = pci_size(l, sz, mask);
251 dev_printk(KERN_DEBUG, &dev->dev, "reg %x %s: %pR\n", pos,
252 (res->flags & IORESOURCE_IO) ? "io port" : "32bit mmio",
257 return (type == pci_bar_mem64) ? 1 : 0;
263 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
265 unsigned int pos, reg;
267 for (pos = 0; pos < howmany; pos++) {
268 struct resource *res = &dev->resource[pos];
269 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
270 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
274 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
275 dev->rom_base_reg = rom;
276 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
277 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
278 IORESOURCE_SIZEALIGN;
279 __pci_read_base(dev, pci_bar_mem32, res, rom);
283 void __devinit pci_read_bridge_bases(struct pci_bus *child)
285 struct pci_dev *dev = child->self;
286 u8 io_base_lo, io_limit_lo;
287 u16 mem_base_lo, mem_limit_lo;
288 unsigned long base, limit;
289 struct resource *res;
292 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
295 if (dev->transparent) {
296 dev_info(&dev->dev, "transparent bridge\n");
297 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
298 child->resource[i] = child->parent->resource[i - 3];
301 res = child->resource[0];
302 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
303 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
304 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
305 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
307 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
308 u16 io_base_hi, io_limit_hi;
309 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
310 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
311 base |= (io_base_hi << 16);
312 limit |= (io_limit_hi << 16);
316 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
320 res->end = limit + 0xfff;
321 dev_printk(KERN_DEBUG, &dev->dev, "bridge io port: %pR\n", res);
324 res = child->resource[1];
325 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
326 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
327 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
328 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
330 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
332 res->end = limit + 0xfffff;
333 dev_printk(KERN_DEBUG, &dev->dev, "bridge 32bit mmio: %pR\n",
337 res = child->resource[2];
338 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
339 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
340 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
341 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
343 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
344 u32 mem_base_hi, mem_limit_hi;
345 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
346 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
349 * Some bridges set the base > limit by default, and some
350 * (broken) BIOSes do not initialize them. If we find
351 * this, just assume they are not being used.
353 if (mem_base_hi <= mem_limit_hi) {
354 #if BITS_PER_LONG == 64
355 base |= ((long) mem_base_hi) << 32;
356 limit |= ((long) mem_limit_hi) << 32;
358 if (mem_base_hi || mem_limit_hi) {
359 dev_err(&dev->dev, "can't handle 64-bit "
360 "address space for bridge\n");
367 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
368 IORESOURCE_MEM | IORESOURCE_PREFETCH;
369 if (res->flags & PCI_PREF_RANGE_TYPE_64)
370 res->flags |= IORESOURCE_MEM_64;
372 res->end = limit + 0xfffff;
373 dev_printk(KERN_DEBUG, &dev->dev, "bridge %sbit mmio pref: %pR\n",
374 (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64" : "32",
379 static struct pci_bus * pci_alloc_bus(void)
383 b = kzalloc(sizeof(*b), GFP_KERNEL);
385 INIT_LIST_HEAD(&b->node);
386 INIT_LIST_HEAD(&b->children);
387 INIT_LIST_HEAD(&b->devices);
388 INIT_LIST_HEAD(&b->slots);
393 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
394 struct pci_dev *bridge, int busnr)
396 struct pci_bus *child;
400 * Allocate a new bus, and inherit stuff from the parent..
402 child = pci_alloc_bus();
406 child->parent = parent;
407 child->ops = parent->ops;
408 child->sysdata = parent->sysdata;
409 child->bus_flags = parent->bus_flags;
411 /* initialize some portions of the bus device, but don't register it
412 * now as the parent is not properly set up yet. This device will get
413 * registered later in pci_bus_add_devices()
415 child->dev.class = &pcibus_class;
416 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
419 * Set up the primary, secondary and subordinate
422 child->number = child->secondary = busnr;
423 child->primary = parent->secondary;
424 child->subordinate = 0xff;
429 child->self = bridge;
430 child->bridge = get_device(&bridge->dev);
432 /* Set up default resource pointers and names.. */
433 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
434 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
435 child->resource[i]->name = child->name;
437 bridge->subordinate = child;
442 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
444 struct pci_bus *child;
446 child = pci_alloc_child_bus(parent, dev, busnr);
448 down_write(&pci_bus_sem);
449 list_add_tail(&child->node, &parent->children);
450 up_write(&pci_bus_sem);
455 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
457 struct pci_bus *parent = child->parent;
459 /* Attempts to fix that up are really dangerous unless
460 we're going to re-assign all bus numbers. */
461 if (!pcibios_assign_all_busses())
464 while (parent->parent && parent->subordinate < max) {
465 parent->subordinate = max;
466 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
467 parent = parent->parent;
472 * If it's a bridge, configure it and scan the bus behind it.
473 * For CardBus bridges, we don't scan behind as the devices will
474 * be handled by the bridge driver itself.
476 * We need to process bridges in two passes -- first we scan those
477 * already configured by the BIOS and after we are done with all of
478 * them, we proceed to assigning numbers to the remaining buses in
479 * order to avoid overlaps between old and new bus numbers.
481 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
483 struct pci_bus *child;
484 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
489 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
491 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
492 buses & 0xffffff, pass);
494 /* Check if setup is sensible at all */
496 ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) {
497 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
501 /* Disable MasterAbortMode during probing to avoid reporting
502 of bus errors (in some architectures) */
503 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
504 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
505 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
507 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) {
508 unsigned int cmax, busnr;
510 * Bus already configured by firmware, process it in the first
511 * pass and just note the configuration.
515 busnr = (buses >> 8) & 0xFF;
518 * If we already got to this bus through a different bridge,
519 * don't re-add it. This can happen with the i450NX chipset.
521 * However, we continue to descend down the hierarchy and
522 * scan remaining child buses.
524 child = pci_find_bus(pci_domain_nr(bus), busnr);
526 child = pci_add_new_bus(bus, dev, busnr);
529 child->primary = buses & 0xFF;
530 child->subordinate = (buses >> 16) & 0xFF;
531 child->bridge_ctl = bctl;
534 cmax = pci_scan_child_bus(child);
537 if (child->subordinate > max)
538 max = child->subordinate;
541 * We need to assign a number to this bus which we always
542 * do in the second pass.
545 if (pcibios_assign_all_busses() || broken)
546 /* Temporarily disable forwarding of the
547 configuration cycles on all bridges in
548 this bus segment to avoid possible
549 conflicts in the second pass between two
550 bridges programmed with overlapping
552 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
558 pci_write_config_word(dev, PCI_STATUS, 0xffff);
560 /* Prevent assigning a bus number that already exists.
561 * This can happen when a bridge is hot-plugged */
562 if (pci_find_bus(pci_domain_nr(bus), max+1))
564 child = pci_add_new_bus(bus, dev, ++max);
565 buses = (buses & 0xff000000)
566 | ((unsigned int)(child->primary) << 0)
567 | ((unsigned int)(child->secondary) << 8)
568 | ((unsigned int)(child->subordinate) << 16);
571 * yenta.c forces a secondary latency timer of 176.
572 * Copy that behaviour here.
575 buses &= ~0xff000000;
576 buses |= CARDBUS_LATENCY_TIMER << 24;
580 * We need to blast all three values with a single write.
582 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
585 child->bridge_ctl = bctl;
587 * Adjust subordinate busnr in parent buses.
588 * We do this before scanning for children because
589 * some devices may not be detected if the bios
592 pci_fixup_parent_subordinate_busnr(child, max);
593 /* Now we can scan all subordinate buses... */
594 max = pci_scan_child_bus(child);
596 * now fix it up again since we have found
597 * the real value of max.
599 pci_fixup_parent_subordinate_busnr(child, max);
602 * For CardBus bridges, we leave 4 bus numbers
603 * as cards with a PCI-to-PCI bridge can be
606 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
607 struct pci_bus *parent = bus;
608 if (pci_find_bus(pci_domain_nr(bus),
611 while (parent->parent) {
612 if ((!pcibios_assign_all_busses()) &&
613 (parent->subordinate > max) &&
614 (parent->subordinate <= max+i)) {
617 parent = parent->parent;
621 * Often, there are two cardbus bridges
622 * -- try to leave one valid bus number
630 pci_fixup_parent_subordinate_busnr(child, max);
633 * Set the subordinate bus number to its real value.
635 child->subordinate = max;
636 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
640 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
641 pci_domain_nr(bus), child->number);
643 /* Has only triggered on CardBus, fixup is in yenta_socket */
644 while (bus->parent) {
645 if ((child->subordinate > bus->subordinate) ||
646 (child->number > bus->subordinate) ||
647 (child->number < bus->number) ||
648 (child->subordinate < bus->number)) {
649 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
650 "hidden behind%s bridge #%02x (-#%02x)\n",
651 child->number, child->subordinate,
652 (bus->number > child->subordinate &&
653 bus->subordinate < child->number) ?
654 "wholly" : "partially",
655 bus->self->transparent ? " transparent" : "",
656 bus->number, bus->subordinate);
662 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
668 * Read interrupt line and base address registers.
669 * The architecture-dependent code can tweak these, of course.
671 static void pci_read_irq(struct pci_dev *dev)
675 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
678 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
682 static void set_pcie_port_type(struct pci_dev *pdev)
687 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
691 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
692 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
695 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
698 * pci_setup_device - fill in class and map information of a device
699 * @dev: the device structure to fill
701 * Initialize the device structure with information about the device's
702 * vendor,class,memory and IO-space addresses,IRQ lines etc.
703 * Called at initialisation of the PCI subsystem and by CardBus services.
704 * Returns 0 on success and negative if unknown type of device (not normal,
705 * bridge or CardBus).
707 int pci_setup_device(struct pci_dev *dev)
711 struct pci_slot *slot;
713 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
716 dev->sysdata = dev->bus->sysdata;
717 dev->dev.parent = dev->bus->bridge;
718 dev->dev.bus = &pci_bus_type;
719 dev->hdr_type = hdr_type & 0x7f;
720 dev->multifunction = !!(hdr_type & 0x80);
721 dev->error_state = pci_channel_io_normal;
722 set_pcie_port_type(dev);
724 list_for_each_entry(slot, &dev->bus->slots, list)
725 if (PCI_SLOT(dev->devfn) == slot->number)
728 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
729 set this higher, assuming the system even supports it. */
730 dev->dma_mask = 0xffffffff;
732 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
733 dev->bus->number, PCI_SLOT(dev->devfn),
734 PCI_FUNC(dev->devfn));
736 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
737 dev->revision = class & 0xff;
738 class >>= 8; /* upper 3 bytes */
742 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n",
743 dev->vendor, dev->device, class, dev->hdr_type);
745 /* need to have dev->class ready */
746 dev->cfg_size = pci_cfg_space_size(dev);
748 /* "Unknown power state" */
749 dev->current_state = PCI_UNKNOWN;
751 /* Early fixups, before probing the BARs */
752 pci_fixup_device(pci_fixup_early, dev);
753 /* device class may be changed after fixup */
754 class = dev->class >> 8;
756 switch (dev->hdr_type) { /* header type */
757 case PCI_HEADER_TYPE_NORMAL: /* standard header */
758 if (class == PCI_CLASS_BRIDGE_PCI)
761 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
762 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
763 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
766 * Do the ugly legacy mode stuff here rather than broken chip
767 * quirk code. Legacy mode ATA controllers have fixed
768 * addresses. These are not always echoed in BAR0-3, and
769 * BAR0-3 in a few cases contain junk!
771 if (class == PCI_CLASS_STORAGE_IDE) {
773 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
774 if ((progif & 1) == 0) {
775 dev->resource[0].start = 0x1F0;
776 dev->resource[0].end = 0x1F7;
777 dev->resource[0].flags = LEGACY_IO_RESOURCE;
778 dev->resource[1].start = 0x3F6;
779 dev->resource[1].end = 0x3F6;
780 dev->resource[1].flags = LEGACY_IO_RESOURCE;
782 if ((progif & 4) == 0) {
783 dev->resource[2].start = 0x170;
784 dev->resource[2].end = 0x177;
785 dev->resource[2].flags = LEGACY_IO_RESOURCE;
786 dev->resource[3].start = 0x376;
787 dev->resource[3].end = 0x376;
788 dev->resource[3].flags = LEGACY_IO_RESOURCE;
793 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
794 if (class != PCI_CLASS_BRIDGE_PCI)
796 /* The PCI-to-PCI bridge spec requires that subtractive
797 decoding (i.e. transparent) bridge must have programming
798 interface code of 0x01. */
800 dev->transparent = ((dev->class & 0xff) == 1);
801 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
804 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
805 if (class != PCI_CLASS_BRIDGE_CARDBUS)
808 pci_read_bases(dev, 1, 0);
809 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
810 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
813 default: /* unknown header */
814 dev_err(&dev->dev, "unknown header type %02x, "
815 "ignoring device\n", dev->hdr_type);
819 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
820 "type %02x)\n", class, dev->hdr_type);
821 dev->class = PCI_CLASS_NOT_DEFINED;
824 /* We found a fine healthy device, go go go... */
828 static void pci_release_capabilities(struct pci_dev *dev)
830 pci_vpd_release(dev);
831 pci_iov_release(dev);
835 * pci_release_dev - free a pci device structure when all users of it are finished.
836 * @dev: device that's been disconnected
838 * Will be called only by the device core when all users of this pci device are
841 static void pci_release_dev(struct device *dev)
843 struct pci_dev *pci_dev;
845 pci_dev = to_pci_dev(dev);
846 pci_release_capabilities(pci_dev);
851 * pci_cfg_space_size - get the configuration space size of the PCI device.
854 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
855 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
856 * access it. Maybe we don't have a way to generate extended config space
857 * accesses, or the device is behind a reverse Express bridge. So we try
858 * reading the dword at 0x100 which must either be 0 or a valid extended
861 int pci_cfg_space_size_ext(struct pci_dev *dev)
864 int pos = PCI_CFG_SPACE_SIZE;
866 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
868 if (status == 0xffffffff)
871 return PCI_CFG_SPACE_EXP_SIZE;
874 return PCI_CFG_SPACE_SIZE;
877 int pci_cfg_space_size(struct pci_dev *dev)
883 class = dev->class >> 8;
884 if (class == PCI_CLASS_BRIDGE_HOST)
885 return pci_cfg_space_size_ext(dev);
887 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
889 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
893 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
894 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
898 return pci_cfg_space_size_ext(dev);
901 return PCI_CFG_SPACE_SIZE;
904 static void pci_release_bus_bridge_dev(struct device *dev)
909 struct pci_dev *alloc_pci_dev(void)
913 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
917 INIT_LIST_HEAD(&dev->bus_list);
921 EXPORT_SYMBOL(alloc_pci_dev);
924 * Read the config data for a PCI device, sanity-check it
925 * and fill in the dev structure...
927 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
933 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
936 /* some broken boards return 0 or ~0 if a slot is empty: */
937 if (l == 0xffffffff || l == 0x00000000 ||
938 l == 0x0000ffff || l == 0xffff0000)
941 /* Configuration request Retry Status */
942 while (l == 0xffff0001) {
945 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
947 /* Card hasn't responded in 60 seconds? Must be stuck. */
948 if (delay > 60 * 1000) {
949 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
950 "responding\n", pci_domain_nr(bus),
951 bus->number, PCI_SLOT(devfn),
957 dev = alloc_pci_dev();
963 dev->vendor = l & 0xffff;
964 dev->device = (l >> 16) & 0xffff;
966 if (pci_setup_device(dev)) {
974 static void pci_init_capabilities(struct pci_dev *dev)
977 pci_msi_init_pci_dev(dev);
979 /* Buffers for saving PCIe and PCI-X capabilities */
980 pci_allocate_cap_save_buffers(dev);
982 /* Power Management */
984 platform_pci_wakeup_init(dev);
986 /* Vital Product Data */
987 pci_vpd_pci22_init(dev);
989 /* Alternative Routing-ID Forwarding */
992 /* Single Root I/O Virtualization */
996 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
998 device_initialize(&dev->dev);
999 dev->dev.release = pci_release_dev;
1002 dev->dev.dma_mask = &dev->dma_mask;
1003 dev->dev.dma_parms = &dev->dma_parms;
1004 dev->dev.coherent_dma_mask = 0xffffffffull;
1006 pci_set_dma_max_seg_size(dev, 65536);
1007 pci_set_dma_seg_boundary(dev, 0xffffffff);
1009 /* Fix up broken headers */
1010 pci_fixup_device(pci_fixup_header, dev);
1012 /* Initialize various capabilities */
1013 pci_init_capabilities(dev);
1016 * Add the device to our list of discovered devices
1017 * and the bus list for fixup functions, etc.
1019 down_write(&pci_bus_sem);
1020 list_add_tail(&dev->bus_list, &bus->devices);
1021 up_write(&pci_bus_sem);
1024 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1026 struct pci_dev *dev;
1028 dev = pci_get_slot(bus, devfn);
1034 dev = pci_scan_device(bus, devfn);
1038 pci_device_add(dev, bus);
1042 EXPORT_SYMBOL(pci_scan_single_device);
1045 * pci_scan_slot - scan a PCI slot on a bus for devices.
1046 * @bus: PCI bus to scan
1047 * @devfn: slot number to scan (must have zero function.)
1049 * Scan a PCI slot on the specified PCI bus for devices, adding
1050 * discovered devices to the @bus->devices list. New devices
1051 * will not have is_added set.
1053 * Returns the number of new devices found.
1055 int pci_scan_slot(struct pci_bus *bus, int devfn)
1058 struct pci_dev *dev;
1060 dev = pci_scan_single_device(bus, devfn);
1061 if (dev && !dev->is_added) /* new device? */
1064 if ((dev && dev->multifunction) ||
1065 (!dev && pcibios_scan_all_fns(bus, devfn))) {
1066 for (fn = 1; fn < 8; fn++) {
1067 dev = pci_scan_single_device(bus, devfn + fn);
1071 dev->multifunction = 1;
1076 /* only one slot has pcie device */
1077 if (bus->self && nr)
1078 pcie_aspm_init_link_state(bus->self);
1083 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1085 unsigned int devfn, pass, max = bus->secondary;
1086 struct pci_dev *dev;
1088 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1090 /* Go find them, Rover! */
1091 for (devfn = 0; devfn < 0x100; devfn += 8)
1092 pci_scan_slot(bus, devfn);
1094 /* Reserve buses for SR-IOV capability. */
1095 max += pci_iov_bus_range(bus);
1098 * After performing arch-dependent fixup of the bus, look behind
1099 * all PCI-to-PCI bridges on this bus.
1101 if (!bus->is_added) {
1102 pr_debug("PCI: Fixups for bus %04x:%02x\n",
1103 pci_domain_nr(bus), bus->number);
1104 pcibios_fixup_bus(bus);
1105 if (pci_is_root_bus(bus))
1109 for (pass=0; pass < 2; pass++)
1110 list_for_each_entry(dev, &bus->devices, bus_list) {
1111 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1112 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1113 max = pci_scan_bridge(bus, dev, max, pass);
1117 * We've scanned the bus and so we know all about what's on
1118 * the other side of any bridges that may be on this bus plus
1121 * Return how far we've got finding sub-buses.
1123 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1124 pci_domain_nr(bus), bus->number, max);
1128 struct pci_bus * pci_create_bus(struct device *parent,
1129 int bus, struct pci_ops *ops, void *sysdata)
1135 b = pci_alloc_bus();
1139 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1145 b->sysdata = sysdata;
1148 if (pci_find_bus(pci_domain_nr(b), bus)) {
1149 /* If we already got to this bus through a different bridge, ignore it */
1150 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1154 down_write(&pci_bus_sem);
1155 list_add_tail(&b->node, &pci_root_buses);
1156 up_write(&pci_bus_sem);
1158 dev->parent = parent;
1159 dev->release = pci_release_bus_bridge_dev;
1160 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1161 error = device_register(dev);
1164 b->bridge = get_device(dev);
1167 set_dev_node(b->bridge, pcibus_to_node(b));
1169 b->dev.class = &pcibus_class;
1170 b->dev.parent = b->bridge;
1171 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1172 error = device_register(&b->dev);
1174 goto class_dev_reg_err;
1175 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1177 goto dev_create_file_err;
1179 /* Create legacy_io and legacy_mem files for this bus */
1180 pci_create_legacy_files(b);
1182 b->number = b->secondary = bus;
1183 b->resource[0] = &ioport_resource;
1184 b->resource[1] = &iomem_resource;
1188 dev_create_file_err:
1189 device_unregister(&b->dev);
1191 device_unregister(dev);
1193 down_write(&pci_bus_sem);
1195 up_write(&pci_bus_sem);
1202 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1203 int bus, struct pci_ops *ops, void *sysdata)
1207 b = pci_create_bus(parent, bus, ops, sysdata);
1209 b->subordinate = pci_scan_child_bus(b);
1212 EXPORT_SYMBOL(pci_scan_bus_parented);
1214 #ifdef CONFIG_HOTPLUG
1216 * pci_rescan_bus - scan a PCI bus for devices.
1217 * @bus: PCI bus to scan
1219 * Scan a PCI bus and child buses for new devices, adds them,
1222 * Returns the max number of subordinate bus discovered.
1224 unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1227 struct pci_dev *dev;
1229 max = pci_scan_child_bus(bus);
1231 down_read(&pci_bus_sem);
1232 list_for_each_entry(dev, &bus->devices, bus_list)
1233 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1234 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1235 if (dev->subordinate)
1236 pci_bus_size_bridges(dev->subordinate);
1237 up_read(&pci_bus_sem);
1239 pci_bus_assign_resources(bus);
1240 pci_enable_bridges(bus);
1241 pci_bus_add_devices(bus);
1245 EXPORT_SYMBOL_GPL(pci_rescan_bus);
1247 EXPORT_SYMBOL(pci_add_new_bus);
1248 EXPORT_SYMBOL(pci_scan_slot);
1249 EXPORT_SYMBOL(pci_scan_bridge);
1250 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1253 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1255 const struct pci_dev *a = to_pci_dev(d_a);
1256 const struct pci_dev *b = to_pci_dev(d_b);
1258 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1259 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1261 if (a->bus->number < b->bus->number) return -1;
1262 else if (a->bus->number > b->bus->number) return 1;
1264 if (a->devfn < b->devfn) return -1;
1265 else if (a->devfn > b->devfn) return 1;
1270 void __init pci_sort_breadthfirst(void)
1272 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);