git.oblomov.eu Git - linux-2.6/blob - arch/avr32/mach-at32ap/at32ap700x.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/dw_dmac.h>
  11 #include <linux/fb.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/spi/spi.h>
  16 #include <linux/usb/atmel_usba_udc.h>
  17
  18 #include <asm/io.h>
  19 #include <asm/irq.h>
  20
  21 #include <asm/arch/at32ap700x.h>
  22 #include <asm/arch/board.h>
  23 #include <asm/arch/portmux.h>
  24
  25 #include <video/atmel_lcdc.h>
  26
  27 #include "clock.h"
  28 #include "hmatrix.h"
  29 #include "pio.h"
  30 #include "pm.h"
  31
  32
  33 #define PBMEM(base)                                     \
  34         {                                               \
  35                 .start          = base,                 \
  36                 .end            = base + 0x3ff,         \
  37                 .flags          = IORESOURCE_MEM,       \
  38         }
  39 #define IRQ(num)                                        \
  40         {                                               \
  41                 .start          = num,                  \
  42                 .end            = num,                  \
  43                 .flags          = IORESOURCE_IRQ,       \
  44         }
  45 #define NAMED_IRQ(num, _name)                           \
  46         {                                               \
  47                 .start          = num,                  \
  48                 .end            = num,                  \
  49                 .name           = _name,                \
  50                 .flags          = IORESOURCE_IRQ,       \
  51         }
  52
  53 /* REVISIT these assume *every* device supports DMA, but several
  54  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  55  */
  56 #define DEFINE_DEV(_name, _id)                                  \
  57 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  58 static struct platform_device _name##_id##_device = {           \
  59         .name           = #_name,                               \
  60         .id             = _id,                                  \
  61         .dev            = {                                     \
  62                 .dma_mask = &_name##_id##_dma_mask,             \
  63                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  64         },                                                      \
  65         .resource       = _name##_id##_resource,                \
  66         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  67 }
  68 #define DEFINE_DEV_DATA(_name, _id)                             \
  69 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  70 static struct platform_device _name##_id##_device = {           \
  71         .name           = #_name,                               \
  72         .id             = _id,                                  \
  73         .dev            = {                                     \
  74                 .dma_mask = &_name##_id##_dma_mask,             \
  75                 .platform_data  = &_name##_id##_data,           \
  76                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  77         },                                                      \
  78         .resource       = _name##_id##_resource,                \
  79         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  80 }
  81
  82 #define select_peripheral(pin, periph, flags)                   \
  83         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
  84
  85 #define DEV_CLK(_name, devname, bus, _index)                    \
  86 static struct clk devname##_##_name = {                         \
  87         .name           = #_name,                               \
  88         .dev            = &devname##_device.dev,                \
  89         .parent         = &bus##_clk,                           \
  90         .mode           = bus##_clk_mode,                       \
  91         .get_rate       = bus##_clk_get_rate,                   \
  92         .index          = _index,                               \
  93 }
  94
  95 static DEFINE_SPINLOCK(pm_lock);
  96
  97 unsigned long at32ap7000_osc_rates[3] = {
  98         [0] = 32768,
  99         /* FIXME: these are ATSTK1002-specific */
 100         [1] = 20000000,
 101         [2] = 12000000,
 102 };
 103
 104 static struct clk osc0;
 105 static struct clk osc1;
 106
 107 static unsigned long osc_get_rate(struct clk *clk)
 108 {
 109         return at32ap7000_osc_rates[clk->index];
 110 }
 111
 112 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 113 {
 114         unsigned long div, mul, rate;
 115
 116         div = PM_BFEXT(PLLDIV, control) + 1;
 117         mul = PM_BFEXT(PLLMUL, control) + 1;
 118
 119         rate = clk->parent->get_rate(clk->parent);
 120         rate = (rate + div / 2) / div;
 121         rate *= mul;
 122
 123         return rate;
 124 }
 125
 126 static long pll_set_rate(struct clk *clk, unsigned long rate,
 127                          u32 *pll_ctrl)
 128 {
 129         unsigned long mul;
 130         unsigned long mul_best_fit = 0;
 131         unsigned long div;
 132         unsigned long div_min;
 133         unsigned long div_max;
 134         unsigned long div_best_fit = 0;
 135         unsigned long base;
 136         unsigned long pll_in;
 137         unsigned long actual = 0;
 138         unsigned long rate_error;
 139         unsigned long rate_error_prev = ~0UL;
 140         u32 ctrl;
 141
 142         /* Rate must be between 80 MHz and 200 Mhz. */
 143         if (rate < 80000000UL || rate > 200000000UL)
 144                 return -EINVAL;
 145
 146         ctrl = PM_BF(PLLOPT, 4);
 147         base = clk->parent->get_rate(clk->parent);
 148
 149         /* PLL input frequency must be between 6 MHz and 32 MHz. */
 150         div_min = DIV_ROUND_UP(base, 32000000UL);
 151         div_max = base / 6000000UL;
 152
 153         if (div_max < div_min)
 154                 return -EINVAL;
 155
 156         for (div = div_min; div <= div_max; div++) {
 157                 pll_in = (base + div / 2) / div;
 158                 mul = (rate + pll_in / 2) / pll_in;
 159
 160                 if (mul == 0)
 161                         continue;
 162
 163                 actual = pll_in * mul;
 164                 rate_error = abs(actual - rate);
 165
 166                 if (rate_error < rate_error_prev) {
 167                         mul_best_fit = mul;
 168                         div_best_fit = div;
 169                         rate_error_prev = rate_error;
 170                 }
 171
 172                 if (rate_error == 0)
 173                         break;
 174         }
 175
 176         if (div_best_fit == 0)
 177                 return -EINVAL;
 178
 179         ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
 180         ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
 181         ctrl |= PM_BF(PLLCOUNT, 16);
 182
 183         if (clk->parent == &osc1)
 184                 ctrl |= PM_BIT(PLLOSC);
 185
 186         *pll_ctrl = ctrl;
 187
 188         return actual;
 189 }
 190
 191 static unsigned long pll0_get_rate(struct clk *clk)
 192 {
 193         u32 control;
 194
 195         control = pm_readl(PLL0);
 196
 197         return pll_get_rate(clk, control);
 198 }
 199
 200 static void pll1_mode(struct clk *clk, int enabled)
 201 {
 202         unsigned long timeout;
 203         u32 status;
 204         u32 ctrl;
 205
 206         ctrl = pm_readl(PLL1);
 207
 208         if (enabled) {
 209                 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
 210                         pr_debug("clk %s: failed to enable, rate not set\n",
 211                                         clk->name);
 212                         return;
 213                 }
 214
 215                 ctrl |= PM_BIT(PLLEN);
 216                 pm_writel(PLL1, ctrl);
 217
 218                 /* Wait for PLL lock. */
 219                 for (timeout = 10000; timeout; timeout--) {
 220                         status = pm_readl(ISR);
 221                         if (status & PM_BIT(LOCK1))
 222                                 break;
 223                         udelay(10);
 224                 }
 225
 226                 if (!(status & PM_BIT(LOCK1)))
 227                         printk(KERN_ERR "clk %s: timeout waiting for lock\n",
 228                                         clk->name);
 229         } else {
 230                 ctrl &= ~PM_BIT(PLLEN);
 231                 pm_writel(PLL1, ctrl);
 232         }
 233 }
 234
 235 static unsigned long pll1_get_rate(struct clk *clk)
 236 {
 237         u32 control;
 238
 239         control = pm_readl(PLL1);
 240
 241         return pll_get_rate(clk, control);
 242 }
 243
 244 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
 245 {
 246         u32 ctrl = 0;
 247         unsigned long actual_rate;
 248
 249         actual_rate = pll_set_rate(clk, rate, &ctrl);
 250
 251         if (apply) {
 252                 if (actual_rate != rate)
 253                         return -EINVAL;
 254                 if (clk->users > 0)
 255                         return -EBUSY;
 256                 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
 257                                 clk->name, rate, actual_rate);
 258                 pm_writel(PLL1, ctrl);
 259         }
 260
 261         return actual_rate;
 262 }
 263
 264 static int pll1_set_parent(struct clk *clk, struct clk *parent)
 265 {
 266         u32 ctrl;
 267
 268         if (clk->users > 0)
 269                 return -EBUSY;
 270
 271         ctrl = pm_readl(PLL1);
 272         WARN_ON(ctrl & PM_BIT(PLLEN));
 273
 274         if (parent == &osc0)
 275                 ctrl &= ~PM_BIT(PLLOSC);
 276         else if (parent == &osc1)
 277                 ctrl |= PM_BIT(PLLOSC);
 278         else
 279                 return -EINVAL;
 280
 281         pm_writel(PLL1, ctrl);
 282         clk->parent = parent;
 283
 284         return 0;
 285 }
 286
 287 /*
 288  * The AT32AP7000 has five primary clock sources: One 32kHz
 289  * oscillator, two crystal oscillators and two PLLs.
 290  */
 291 static struct clk osc32k = {
 292         .name           = "osc32k",
 293         .get_rate       = osc_get_rate,
 294         .users          = 1,
 295         .index          = 0,
 296 };
 297 static struct clk osc0 = {
 298         .name           = "osc0",
 299         .get_rate       = osc_get_rate,
 300         .users          = 1,
 301         .index          = 1,
 302 };
 303 static struct clk osc1 = {
 304         .name           = "osc1",
 305         .get_rate       = osc_get_rate,
 306         .index          = 2,
 307 };
 308 static struct clk pll0 = {
 309         .name           = "pll0",
 310         .get_rate       = pll0_get_rate,
 311         .parent         = &osc0,
 312 };
 313 static struct clk pll1 = {
 314         .name           = "pll1",
 315         .mode           = pll1_mode,
 316         .get_rate       = pll1_get_rate,
 317         .set_rate       = pll1_set_rate,
 318         .set_parent     = pll1_set_parent,
 319         .parent         = &osc0,
 320 };
 321
 322 /*
 323  * The main clock can be either osc0 or pll0.  The boot loader may
 324  * have chosen one for us, so we don't really know which one until we
 325  * have a look at the SM.
 326  */
 327 static struct clk *main_clock;
 328
 329 /*
 330  * Synchronous clocks are generated from the main clock. The clocks
 331  * must satisfy the constraint
 332  *   fCPU >= fHSB >= fPB
 333  * i.e. each clock must not be faster than its parent.
 334  */
 335 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 336 {
 337         return main_clock->get_rate(main_clock) >> shift;
 338 };
 339
 340 static void cpu_clk_mode(struct clk *clk, int enabled)
 341 {
 342         unsigned long flags;
 343         u32 mask;
 344
 345         spin_lock_irqsave(&pm_lock, flags);
 346         mask = pm_readl(CPU_MASK);
 347         if (enabled)
 348                 mask |= 1 << clk->index;
 349         else
 350                 mask &= ~(1 << clk->index);
 351         pm_writel(CPU_MASK, mask);
 352         spin_unlock_irqrestore(&pm_lock, flags);
 353 }
 354
 355 static unsigned long cpu_clk_get_rate(struct clk *clk)
 356 {
 357         unsigned long cksel, shift = 0;
 358
 359         cksel = pm_readl(CKSEL);
 360         if (cksel & PM_BIT(CPUDIV))
 361                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 362
 363         return bus_clk_get_rate(clk, shift);
 364 }
 365
 366 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 367 {
 368         u32 control;
 369         unsigned long parent_rate, child_div, actual_rate, div;
 370
 371         parent_rate = clk->parent->get_rate(clk->parent);
 372         control = pm_readl(CKSEL);
 373
 374         if (control & PM_BIT(HSBDIV))
 375                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 376         else
 377                 child_div = 1;
 378
 379         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 380                 actual_rate = parent_rate;
 381                 control &= ~PM_BIT(CPUDIV);
 382         } else {
 383                 unsigned int cpusel;
 384                 div = (parent_rate + rate / 2) / rate;
 385                 if (div > child_div)
 386                         div = child_div;
 387                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
 388                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 389                 actual_rate = parent_rate / (1 << (cpusel + 1));
 390         }
 391
 392         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 393                         clk->name, rate, actual_rate);
 394
 395         if (apply)
 396                 pm_writel(CKSEL, control);
 397
 398         return actual_rate;
 399 }
 400
 401 static void hsb_clk_mode(struct clk *clk, int enabled)
 402 {
 403         unsigned long flags;
 404         u32 mask;
 405
 406         spin_lock_irqsave(&pm_lock, flags);
 407         mask = pm_readl(HSB_MASK);
 408         if (enabled)
 409                 mask |= 1 << clk->index;
 410         else
 411                 mask &= ~(1 << clk->index);
 412         pm_writel(HSB_MASK, mask);
 413         spin_unlock_irqrestore(&pm_lock, flags);
 414 }
 415
 416 static unsigned long hsb_clk_get_rate(struct clk *clk)
 417 {
 418         unsigned long cksel, shift = 0;
 419
 420         cksel = pm_readl(CKSEL);
 421         if (cksel & PM_BIT(HSBDIV))
 422                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 423
 424         return bus_clk_get_rate(clk, shift);
 425 }
 426
 427 static void pba_clk_mode(struct clk *clk, int enabled)
 428 {
 429         unsigned long flags;
 430         u32 mask;
 431
 432         spin_lock_irqsave(&pm_lock, flags);
 433         mask = pm_readl(PBA_MASK);
 434         if (enabled)
 435                 mask |= 1 << clk->index;
 436         else
 437                 mask &= ~(1 << clk->index);
 438         pm_writel(PBA_MASK, mask);
 439         spin_unlock_irqrestore(&pm_lock, flags);
 440 }
 441
 442 static unsigned long pba_clk_get_rate(struct clk *clk)
 443 {
 444         unsigned long cksel, shift = 0;
 445
 446         cksel = pm_readl(CKSEL);
 447         if (cksel & PM_BIT(PBADIV))
 448                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 449
 450         return bus_clk_get_rate(clk, shift);
 451 }
 452
 453 static void pbb_clk_mode(struct clk *clk, int enabled)
 454 {
 455         unsigned long flags;
 456         u32 mask;
 457
 458         spin_lock_irqsave(&pm_lock, flags);
 459         mask = pm_readl(PBB_MASK);
 460         if (enabled)
 461                 mask |= 1 << clk->index;
 462         else
 463                 mask &= ~(1 << clk->index);
 464         pm_writel(PBB_MASK, mask);
 465         spin_unlock_irqrestore(&pm_lock, flags);
 466 }
 467
 468 static unsigned long pbb_clk_get_rate(struct clk *clk)
 469 {
 470         unsigned long cksel, shift = 0;
 471
 472         cksel = pm_readl(CKSEL);
 473         if (cksel & PM_BIT(PBBDIV))
 474                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 475
 476         return bus_clk_get_rate(clk, shift);
 477 }
 478
 479 static struct clk cpu_clk = {
 480         .name           = "cpu",
 481         .get_rate       = cpu_clk_get_rate,
 482         .set_rate       = cpu_clk_set_rate,
 483         .users          = 1,
 484 };
 485 static struct clk hsb_clk = {
 486         .name           = "hsb",
 487         .parent         = &cpu_clk,
 488         .get_rate       = hsb_clk_get_rate,
 489 };
 490 static struct clk pba_clk = {
 491         .name           = "pba",
 492         .parent         = &hsb_clk,
 493         .mode           = hsb_clk_mode,
 494         .get_rate       = pba_clk_get_rate,
 495         .index          = 1,
 496 };
 497 static struct clk pbb_clk = {
 498         .name           = "pbb",
 499         .parent         = &hsb_clk,
 500         .mode           = hsb_clk_mode,
 501         .get_rate       = pbb_clk_get_rate,
 502         .users          = 1,
 503         .index          = 2,
 504 };
 505
 506 /* --------------------------------------------------------------------
 507  *  Generic Clock operations
 508  * -------------------------------------------------------------------- */
 509
 510 static void genclk_mode(struct clk *clk, int enabled)
 511 {
 512         u32 control;
 513
 514         control = pm_readl(GCCTRL(clk->index));
 515         if (enabled)
 516                 control |= PM_BIT(CEN);
 517         else
 518                 control &= ~PM_BIT(CEN);
 519         pm_writel(GCCTRL(clk->index), control);
 520 }
 521
 522 static unsigned long genclk_get_rate(struct clk *clk)
 523 {
 524         u32 control;
 525         unsigned long div = 1;
 526
 527         control = pm_readl(GCCTRL(clk->index));
 528         if (control & PM_BIT(DIVEN))
 529                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 530
 531         return clk->parent->get_rate(clk->parent) / div;
 532 }
 533
 534 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 535 {
 536         u32 control;
 537         unsigned long parent_rate, actual_rate, div;
 538
 539         parent_rate = clk->parent->get_rate(clk->parent);
 540         control = pm_readl(GCCTRL(clk->index));
 541
 542         if (rate > 3 * parent_rate / 4) {
 543                 actual_rate = parent_rate;
 544                 control &= ~PM_BIT(DIVEN);
 545         } else {
 546                 div = (parent_rate + rate) / (2 * rate) - 1;
 547                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 548                 actual_rate = parent_rate / (2 * (div + 1));
 549         }
 550
 551         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 552                 clk->name, rate, actual_rate);
 553
 554         if (apply)
 555                 pm_writel(GCCTRL(clk->index), control);
 556
 557         return actual_rate;
 558 }
 559
 560 int genclk_set_parent(struct clk *clk, struct clk *parent)
 561 {
 562         u32 control;
 563
 564         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 565                 clk->name, parent->name, clk->parent->name);
 566
 567         control = pm_readl(GCCTRL(clk->index));
 568
 569         if (parent == &osc1 || parent == &pll1)
 570                 control |= PM_BIT(OSCSEL);
 571         else if (parent == &osc0 || parent == &pll0)
 572                 control &= ~PM_BIT(OSCSEL);
 573         else
 574                 return -EINVAL;
 575
 576         if (parent == &pll0 || parent == &pll1)
 577                 control |= PM_BIT(PLLSEL);
 578         else
 579                 control &= ~PM_BIT(PLLSEL);
 580
 581         pm_writel(GCCTRL(clk->index), control);
 582         clk->parent = parent;
 583
 584         return 0;
 585 }
 586
 587 static void __init genclk_init_parent(struct clk *clk)
 588 {
 589         u32 control;
 590         struct clk *parent;
 591
 592         BUG_ON(clk->index > 7);
 593
 594         control = pm_readl(GCCTRL(clk->index));
 595         if (control & PM_BIT(OSCSEL))
 596                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 597         else
 598                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 599
 600         clk->parent = parent;
 601 }
 602
 603 static struct dw_dma_platform_data dw_dmac0_data = {
 604         .nr_channels    = 3,
 605 };
 606
 607 static struct resource dw_dmac0_resource[] = {
 608         PBMEM(0xff200000),
 609         IRQ(2),
 610 };
 611 DEFINE_DEV_DATA(dw_dmac, 0);
 612 DEV_CLK(hclk, dw_dmac0, hsb, 10);
 613
 614 /* --------------------------------------------------------------------
 615  *  System peripherals
 616  * -------------------------------------------------------------------- */
 617 static struct resource at32_pm0_resource[] = {
 618         {
 619                 .start  = 0xfff00000,
 620                 .end    = 0xfff0007f,
 621                 .flags  = IORESOURCE_MEM,
 622         },
 623         IRQ(20),
 624 };
 625
 626 static struct resource at32ap700x_rtc0_resource[] = {
 627         {
 628                 .start  = 0xfff00080,
 629                 .end    = 0xfff000af,
 630                 .flags  = IORESOURCE_MEM,
 631         },
 632         IRQ(21),
 633 };
 634
 635 static struct resource at32_wdt0_resource[] = {
 636         {
 637                 .start  = 0xfff000b0,
 638                 .end    = 0xfff000cf,
 639                 .flags  = IORESOURCE_MEM,
 640         },
 641 };
 642
 643 static struct resource at32_eic0_resource[] = {
 644         {
 645                 .start  = 0xfff00100,
 646                 .end    = 0xfff0013f,
 647                 .flags  = IORESOURCE_MEM,
 648         },
 649         IRQ(19),
 650 };
 651
 652 DEFINE_DEV(at32_pm, 0);
 653 DEFINE_DEV(at32ap700x_rtc, 0);
 654 DEFINE_DEV(at32_wdt, 0);
 655 DEFINE_DEV(at32_eic, 0);
 656
 657 /*
 658  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 659  * is always running.
 660  */
 661 static struct clk at32_pm_pclk = {
 662         .name           = "pclk",
 663         .dev            = &at32_pm0_device.dev,
 664         .parent         = &pbb_clk,
 665         .mode           = pbb_clk_mode,
 666         .get_rate       = pbb_clk_get_rate,
 667         .users          = 1,
 668         .index          = 0,
 669 };
 670
 671 static struct resource intc0_resource[] = {
 672         PBMEM(0xfff00400),
 673 };
 674 struct platform_device at32_intc0_device = {
 675         .name           = "intc",
 676         .id             = 0,
 677         .resource       = intc0_resource,
 678         .num_resources  = ARRAY_SIZE(intc0_resource),
 679 };
 680 DEV_CLK(pclk, at32_intc0, pbb, 1);
 681
 682 static struct clk ebi_clk = {
 683         .name           = "ebi",
 684         .parent         = &hsb_clk,
 685         .mode           = hsb_clk_mode,
 686         .get_rate       = hsb_clk_get_rate,
 687         .users          = 1,
 688 };
 689 static struct clk hramc_clk = {
 690         .name           = "hramc",
 691         .parent         = &hsb_clk,
 692         .mode           = hsb_clk_mode,
 693         .get_rate       = hsb_clk_get_rate,
 694         .users          = 1,
 695         .index          = 3,
 696 };
 697
 698 static struct resource smc0_resource[] = {
 699         PBMEM(0xfff03400),
 700 };
 701 DEFINE_DEV(smc, 0);
 702 DEV_CLK(pclk, smc0, pbb, 13);
 703 DEV_CLK(mck, smc0, hsb, 0);
 704
 705 static struct platform_device pdc_device = {
 706         .name           = "pdc",
 707         .id             = 0,
 708 };
 709 DEV_CLK(hclk, pdc, hsb, 4);
 710 DEV_CLK(pclk, pdc, pba, 16);
 711
 712 static struct clk pico_clk = {
 713         .name           = "pico",
 714         .parent         = &cpu_clk,
 715         .mode           = cpu_clk_mode,
 716         .get_rate       = cpu_clk_get_rate,
 717         .users          = 1,
 718 };
 719
 720 /* --------------------------------------------------------------------
 721  * HMATRIX
 722  * -------------------------------------------------------------------- */
 723
 724 static struct clk hmatrix_clk = {
 725         .name           = "hmatrix_clk",
 726         .parent         = &pbb_clk,
 727         .mode           = pbb_clk_mode,
 728         .get_rate       = pbb_clk_get_rate,
 729         .index          = 2,
 730         .users          = 1,
 731 };
 732 #define HMATRIX_BASE    ((void __iomem *)0xfff00800)
 733
 734 #define hmatrix_readl(reg)                                      \
 735         __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
 736 #define hmatrix_writel(reg,value)                               \
 737         __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
 738
 739 /*
 740  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 741  * External Bus Interface (EBI). This can be used to enable special
 742  * features like CompactFlash support, NAND Flash support, etc. on
 743  * certain chipselects.
 744  */
 745 static inline void set_ebi_sfr_bits(u32 mask)
 746 {
 747         u32 sfr;
 748
 749         clk_enable(&hmatrix_clk);
 750         sfr = hmatrix_readl(SFR4);
 751         sfr |= mask;
 752         hmatrix_writel(SFR4, sfr);
 753         clk_disable(&hmatrix_clk);
 754 }
 755
 756 /* --------------------------------------------------------------------
 757  *  Timer/Counter (TC)
 758  * -------------------------------------------------------------------- */
 759
 760 static struct resource at32_tcb0_resource[] = {
 761         PBMEM(0xfff00c00),
 762         IRQ(22),
 763 };
 764 static struct platform_device at32_tcb0_device = {
 765         .name           = "atmel_tcb",
 766         .id             = 0,
 767         .resource       = at32_tcb0_resource,
 768         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
 769 };
 770 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
 771
 772 static struct resource at32_tcb1_resource[] = {
 773         PBMEM(0xfff01000),
 774         IRQ(23),
 775 };
 776 static struct platform_device at32_tcb1_device = {
 777         .name           = "atmel_tcb",
 778         .id             = 1,
 779         .resource       = at32_tcb1_resource,
 780         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
 781 };
 782 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
 783
 784 /* --------------------------------------------------------------------
 785  *  PIO
 786  * -------------------------------------------------------------------- */
 787
 788 static struct resource pio0_resource[] = {
 789         PBMEM(0xffe02800),
 790         IRQ(13),
 791 };
 792 DEFINE_DEV(pio, 0);
 793 DEV_CLK(mck, pio0, pba, 10);
 794
 795 static struct resource pio1_resource[] = {
 796         PBMEM(0xffe02c00),
 797         IRQ(14),
 798 };
 799 DEFINE_DEV(pio, 1);
 800 DEV_CLK(mck, pio1, pba, 11);
 801
 802 static struct resource pio2_resource[] = {
 803         PBMEM(0xffe03000),
 804         IRQ(15),
 805 };
 806 DEFINE_DEV(pio, 2);
 807 DEV_CLK(mck, pio2, pba, 12);
 808
 809 static struct resource pio3_resource[] = {
 810         PBMEM(0xffe03400),
 811         IRQ(16),
 812 };
 813 DEFINE_DEV(pio, 3);
 814 DEV_CLK(mck, pio3, pba, 13);
 815
 816 static struct resource pio4_resource[] = {
 817         PBMEM(0xffe03800),
 818         IRQ(17),
 819 };
 820 DEFINE_DEV(pio, 4);
 821 DEV_CLK(mck, pio4, pba, 14);
 822
 823 void __init at32_add_system_devices(void)
 824 {
 825         platform_device_register(&at32_pm0_device);
 826         platform_device_register(&at32_intc0_device);
 827         platform_device_register(&at32ap700x_rtc0_device);
 828         platform_device_register(&at32_wdt0_device);
 829         platform_device_register(&at32_eic0_device);
 830         platform_device_register(&smc0_device);
 831         platform_device_register(&pdc_device);
 832         platform_device_register(&dw_dmac0_device);
 833
 834         platform_device_register(&at32_tcb0_device);
 835         platform_device_register(&at32_tcb1_device);
 836
 837         platform_device_register(&pio0_device);
 838         platform_device_register(&pio1_device);
 839         platform_device_register(&pio2_device);
 840         platform_device_register(&pio3_device);
 841         platform_device_register(&pio4_device);
 842 }
 843
 844 /* --------------------------------------------------------------------
 845  *  USART
 846  * -------------------------------------------------------------------- */
 847
 848 static struct atmel_uart_data atmel_usart0_data = {
 849         .use_dma_tx     = 1,
 850         .use_dma_rx     = 1,
 851 };
 852 static struct resource atmel_usart0_resource[] = {
 853         PBMEM(0xffe00c00),
 854         IRQ(6),
 855 };
 856 DEFINE_DEV_DATA(atmel_usart, 0);
 857 DEV_CLK(usart, atmel_usart0, pba, 3);
 858
 859 static struct atmel_uart_data atmel_usart1_data = {
 860         .use_dma_tx     = 1,
 861         .use_dma_rx     = 1,
 862 };
 863 static struct resource atmel_usart1_resource[] = {
 864         PBMEM(0xffe01000),
 865         IRQ(7),
 866 };
 867 DEFINE_DEV_DATA(atmel_usart, 1);
 868 DEV_CLK(usart, atmel_usart1, pba, 4);
 869
 870 static struct atmel_uart_data atmel_usart2_data = {
 871         .use_dma_tx     = 1,
 872         .use_dma_rx     = 1,
 873 };
 874 static struct resource atmel_usart2_resource[] = {
 875         PBMEM(0xffe01400),
 876         IRQ(8),
 877 };
 878 DEFINE_DEV_DATA(atmel_usart, 2);
 879 DEV_CLK(usart, atmel_usart2, pba, 5);
 880
 881 static struct atmel_uart_data atmel_usart3_data = {
 882         .use_dma_tx     = 1,
 883         .use_dma_rx     = 1,
 884 };
 885 static struct resource atmel_usart3_resource[] = {
 886         PBMEM(0xffe01800),
 887         IRQ(9),
 888 };
 889 DEFINE_DEV_DATA(atmel_usart, 3);
 890 DEV_CLK(usart, atmel_usart3, pba, 6);
 891
 892 static inline void configure_usart0_pins(void)
 893 {
 894         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
 895         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
 896 }
 897
 898 static inline void configure_usart1_pins(void)
 899 {
 900         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
 901         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
 902 }
 903
 904 static inline void configure_usart2_pins(void)
 905 {
 906         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
 907         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
 908 }
 909
 910 static inline void configure_usart3_pins(void)
 911 {
 912         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
 913         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
 914 }
 915
 916 static struct platform_device *__initdata at32_usarts[4];
 917
 918 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 919 {
 920         struct platform_device *pdev;
 921
 922         switch (hw_id) {
 923         case 0:
 924                 pdev = &atmel_usart0_device;
 925                 configure_usart0_pins();
 926                 break;
 927         case 1:
 928                 pdev = &atmel_usart1_device;
 929                 configure_usart1_pins();
 930                 break;
 931         case 2:
 932                 pdev = &atmel_usart2_device;
 933                 configure_usart2_pins();
 934                 break;
 935         case 3:
 936                 pdev = &atmel_usart3_device;
 937                 configure_usart3_pins();
 938                 break;
 939         default:
 940                 return;
 941         }
 942
 943         if (PXSEG(pdev->resource[0].start) == P4SEG) {
 944                 /* Addresses in the P4 segment are permanently mapped 1:1 */
 945                 struct atmel_uart_data *data = pdev->dev.platform_data;
 946                 data->regs = (void __iomem *)pdev->resource[0].start;
 947         }
 948
 949         pdev->id = line;
 950         at32_usarts[line] = pdev;
 951 }
 952
 953 struct platform_device *__init at32_add_device_usart(unsigned int id)
 954 {
 955         platform_device_register(at32_usarts[id]);
 956         return at32_usarts[id];
 957 }
 958
 959 struct platform_device *atmel_default_console_device;
 960
 961 void __init at32_setup_serial_console(unsigned int usart_id)
 962 {
 963         atmel_default_console_device = at32_usarts[usart_id];
 964 }
 965
 966 /* --------------------------------------------------------------------
 967  *  Ethernet
 968  * -------------------------------------------------------------------- */
 969
 970 #ifdef CONFIG_CPU_AT32AP7000
 971 static struct eth_platform_data macb0_data;
 972 static struct resource macb0_resource[] = {
 973         PBMEM(0xfff01800),
 974         IRQ(25),
 975 };
 976 DEFINE_DEV_DATA(macb, 0);
 977 DEV_CLK(hclk, macb0, hsb, 8);
 978 DEV_CLK(pclk, macb0, pbb, 6);
 979
 980 static struct eth_platform_data macb1_data;
 981 static struct resource macb1_resource[] = {
 982         PBMEM(0xfff01c00),
 983         IRQ(26),
 984 };
 985 DEFINE_DEV_DATA(macb, 1);
 986 DEV_CLK(hclk, macb1, hsb, 9);
 987 DEV_CLK(pclk, macb1, pbb, 7);
 988
 989 struct platform_device *__init
 990 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
 991 {
 992         struct platform_device *pdev;
 993
 994         switch (id) {
 995         case 0:
 996                 pdev = &macb0_device;
 997
 998                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
 999                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
1000                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
1001                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
1002                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
1003                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
1004                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
1005                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
1006                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
1007                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
1008
1009                 if (!data->is_rmii) {
1010                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
1011                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
1012                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
1013                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
1014                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
1015                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
1016                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
1017                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
1018                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
1019                 }
1020                 break;
1021
1022         case 1:
1023                 pdev = &macb1_device;
1024
1025                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
1026                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
1027                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
1028                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
1029                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
1030                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
1031                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
1032                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
1033                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
1034                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
1035
1036                 if (!data->is_rmii) {
1037                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
1038                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
1039                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
1040                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
1041                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
1042                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
1043                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
1044                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
1045                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
1046                 }
1047                 break;
1048
1049         default:
1050                 return NULL;
1051         }
1052
1053         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1054         platform_device_register(pdev);
1055
1056         return pdev;
1057 }
1058 #endif
1059
1060 /* --------------------------------------------------------------------
1061  *  SPI
1062  * -------------------------------------------------------------------- */
1063 static struct resource atmel_spi0_resource[] = {
1064         PBMEM(0xffe00000),
1065         IRQ(3),
1066 };
1067 DEFINE_DEV(atmel_spi, 0);
1068 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1069
1070 static struct resource atmel_spi1_resource[] = {
1071         PBMEM(0xffe00400),
1072         IRQ(4),
1073 };
1074 DEFINE_DEV(atmel_spi, 1);
1075 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1076
1077 static void __init
1078 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1079                       unsigned int n, const u8 *pins)
1080 {
1081         unsigned int pin, mode;
1082
1083         for (; n; n--, b++) {
1084                 b->bus_num = bus_num;
1085                 if (b->chip_select >= 4)
1086                         continue;
1087                 pin = (unsigned)b->controller_data;
1088                 if (!pin) {
1089                         pin = pins[b->chip_select];
1090                         b->controller_data = (void *)pin;
1091                 }
1092                 mode = AT32_GPIOF_OUTPUT;
1093                 if (!(b->mode & SPI_CS_HIGH))
1094                         mode |= AT32_GPIOF_HIGH;
1095                 at32_select_gpio(pin, mode);
1096         }
1097 }
1098
1099 struct platform_device *__init
1100 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1101 {
1102         /*
1103          * Manage the chipselects as GPIOs, normally using the same pins
1104          * the SPI controller expects; but boards can use other pins.
1105          */
1106         static u8 __initdata spi0_pins[] =
1107                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1108                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1109         static u8 __initdata spi1_pins[] =
1110                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1111                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1112         struct platform_device *pdev;
1113
1114         switch (id) {
1115         case 0:
1116                 pdev = &atmel_spi0_device;
1117                 select_peripheral(PA(0),  PERIPH_A, 0); /* MISO  */
1118                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
1119                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
1120                 at32_spi_setup_slaves(0, b, n, spi0_pins);
1121                 break;
1122
1123         case 1:
1124                 pdev = &atmel_spi1_device;
1125                 select_peripheral(PB(0),  PERIPH_B, 0); /* MISO  */
1126                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
1127                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
1128                 at32_spi_setup_slaves(1, b, n, spi1_pins);
1129                 break;
1130
1131         default:
1132                 return NULL;
1133         }
1134
1135         spi_register_board_info(b, n);
1136         platform_device_register(pdev);
1137         return pdev;
1138 }
1139
1140 /* --------------------------------------------------------------------
1141  *  TWI
1142  * -------------------------------------------------------------------- */
1143 static struct resource atmel_twi0_resource[] __initdata = {
1144         PBMEM(0xffe00800),
1145         IRQ(5),
1146 };
1147 static struct clk atmel_twi0_pclk = {
1148         .name           = "twi_pclk",
1149         .parent         = &pba_clk,
1150         .mode           = pba_clk_mode,
1151         .get_rate       = pba_clk_get_rate,
1152         .index          = 2,
1153 };
1154
1155 struct platform_device *__init at32_add_device_twi(unsigned int id,
1156                                                     struct i2c_board_info *b,
1157                                                     unsigned int n)
1158 {
1159         struct platform_device *pdev;
1160
1161         if (id != 0)
1162                 return NULL;
1163
1164         pdev = platform_device_alloc("atmel_twi", id);
1165         if (!pdev)
1166                 return NULL;
1167
1168         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1169                                 ARRAY_SIZE(atmel_twi0_resource)))
1170                 goto err_add_resources;
1171
1172         select_peripheral(PA(6),  PERIPH_A, 0); /* SDA  */
1173         select_peripheral(PA(7),  PERIPH_A, 0); /* SDL  */
1174
1175         atmel_twi0_pclk.dev = &pdev->dev;
1176
1177         if (b)
1178                 i2c_register_board_info(id, b, n);
1179
1180         platform_device_add(pdev);
1181         return pdev;
1182
1183 err_add_resources:
1184         platform_device_put(pdev);
1185         return NULL;
1186 }
1187
1188 /* --------------------------------------------------------------------
1189  * MMC
1190  * -------------------------------------------------------------------- */
1191 static struct resource atmel_mci0_resource[] __initdata = {
1192         PBMEM(0xfff02400),
1193         IRQ(28),
1194 };
1195 static struct clk atmel_mci0_pclk = {
1196         .name           = "mci_clk",
1197         .parent         = &pbb_clk,
1198         .mode           = pbb_clk_mode,
1199         .get_rate       = pbb_clk_get_rate,
1200         .index          = 9,
1201 };
1202
1203 struct platform_device *__init at32_add_device_mci(unsigned int id)
1204 {
1205         struct platform_device *pdev;
1206
1207         if (id != 0)
1208                 return NULL;
1209
1210         pdev = platform_device_alloc("atmel_mci", id);
1211         if (!pdev)
1212                 return NULL;
1213
1214         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1215                                 ARRAY_SIZE(atmel_mci0_resource)))
1216                 goto err_add_resources;
1217
1218         select_peripheral(PA(10), PERIPH_A, 0); /* CLK   */
1219         select_peripheral(PA(11), PERIPH_A, 0); /* CMD   */
1220         select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1221         select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1222         select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1223         select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1224
1225         atmel_mci0_pclk.dev = &pdev->dev;
1226
1227         platform_device_add(pdev);
1228         return pdev;
1229
1230 err_add_resources:
1231         platform_device_put(pdev);
1232         return NULL;
1233 }
1234
1235 /* --------------------------------------------------------------------
1236  *  LCDC
1237  * -------------------------------------------------------------------- */
1238 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1239 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1240 static struct resource atmel_lcdfb0_resource[] = {
1241         {
1242                 .start          = 0xff000000,
1243                 .end            = 0xff000fff,
1244                 .flags          = IORESOURCE_MEM,
1245         },
1246         IRQ(1),
1247         {
1248                 /* Placeholder for pre-allocated fb memory */
1249                 .start          = 0x00000000,
1250                 .end            = 0x00000000,
1251                 .flags          = 0,
1252         },
1253 };
1254 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1255 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1256 static struct clk atmel_lcdfb0_pixclk = {
1257         .name           = "lcdc_clk",
1258         .dev            = &atmel_lcdfb0_device.dev,
1259         .mode           = genclk_mode,
1260         .get_rate       = genclk_get_rate,
1261         .set_rate       = genclk_set_rate,
1262         .set_parent     = genclk_set_parent,
1263         .index          = 7,
1264 };
1265
1266 struct platform_device *__init
1267 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1268                      unsigned long fbmem_start, unsigned long fbmem_len)
1269 {
1270         struct platform_device *pdev;
1271         struct atmel_lcdfb_info *info;
1272         struct fb_monspecs *monspecs;
1273         struct fb_videomode *modedb;
1274         unsigned int modedb_size;
1275
1276         /*
1277          * Do a deep copy of the fb data, monspecs and modedb. Make
1278          * sure all allocations are done before setting up the
1279          * portmux.
1280          */
1281         monspecs = kmemdup(data->default_monspecs,
1282                            sizeof(struct fb_monspecs), GFP_KERNEL);
1283         if (!monspecs)
1284                 return NULL;
1285
1286         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1287         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1288         if (!modedb)
1289                 goto err_dup_modedb;
1290         monspecs->modedb = modedb;
1291
1292         switch (id) {
1293         case 0:
1294                 pdev = &atmel_lcdfb0_device;
1295                 select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
1296                 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1297                 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1298                 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1299                 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
1300                 select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
1301                 select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1302                 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
1303                 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
1304                 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
1305                 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
1306                 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
1307                 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1308                 select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1309                 select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1310                 select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
1311                 select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
1312                 select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
1313                 select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
1314                 select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
1315                 select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1316                 select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1317                 select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1318                 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1319                 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1320                 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1321                 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1322                 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1323                 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1324                 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1325                 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1326
1327                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1328                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1329                 break;
1330
1331         default:
1332                 goto err_invalid_id;
1333         }
1334
1335         if (fbmem_len) {
1336                 pdev->resource[2].start = fbmem_start;
1337                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1338                 pdev->resource[2].flags = IORESOURCE_MEM;
1339         }
1340
1341         info = pdev->dev.platform_data;
1342         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1343         info->default_monspecs = monspecs;
1344
1345         platform_device_register(pdev);
1346         return pdev;
1347
1348 err_invalid_id:
1349         kfree(modedb);
1350 err_dup_modedb:
1351         kfree(monspecs);
1352         return NULL;
1353 }
1354 #endif
1355
1356 /* --------------------------------------------------------------------
1357  *  PWM
1358  * -------------------------------------------------------------------- */
1359 static struct resource atmel_pwm0_resource[] __initdata = {
1360         PBMEM(0xfff01400),
1361         IRQ(24),
1362 };
1363 static struct clk atmel_pwm0_mck = {
1364         .name           = "mck",
1365         .parent         = &pbb_clk,
1366         .mode           = pbb_clk_mode,
1367         .get_rate       = pbb_clk_get_rate,
1368         .index          = 5,
1369 };
1370
1371 struct platform_device *__init at32_add_device_pwm(u32 mask)
1372 {
1373         struct platform_device *pdev;
1374
1375         if (!mask)
1376                 return NULL;
1377
1378         pdev = platform_device_alloc("atmel_pwm", 0);
1379         if (!pdev)
1380                 return NULL;
1381
1382         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1383                                 ARRAY_SIZE(atmel_pwm0_resource)))
1384                 goto out_free_pdev;
1385
1386         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1387                 goto out_free_pdev;
1388
1389         if (mask & (1 << 0))
1390                 select_peripheral(PA(28), PERIPH_A, 0);
1391         if (mask & (1 << 1))
1392                 select_peripheral(PA(29), PERIPH_A, 0);
1393         if (mask & (1 << 2))
1394                 select_peripheral(PA(21), PERIPH_B, 0);
1395         if (mask & (1 << 3))
1396                 select_peripheral(PA(22), PERIPH_B, 0);
1397
1398         atmel_pwm0_mck.dev = &pdev->dev;
1399
1400         platform_device_add(pdev);
1401
1402         return pdev;
1403
1404 out_free_pdev:
1405         platform_device_put(pdev);
1406         return NULL;
1407 }
1408
1409 /* --------------------------------------------------------------------
1410  *  SSC
1411  * -------------------------------------------------------------------- */
1412 static struct resource ssc0_resource[] = {
1413         PBMEM(0xffe01c00),
1414         IRQ(10),
1415 };
1416 DEFINE_DEV(ssc, 0);
1417 DEV_CLK(pclk, ssc0, pba, 7);
1418
1419 static struct resource ssc1_resource[] = {
1420         PBMEM(0xffe02000),
1421         IRQ(11),
1422 };
1423 DEFINE_DEV(ssc, 1);
1424 DEV_CLK(pclk, ssc1, pba, 8);
1425
1426 static struct resource ssc2_resource[] = {
1427         PBMEM(0xffe02400),
1428         IRQ(12),
1429 };
1430 DEFINE_DEV(ssc, 2);
1431 DEV_CLK(pclk, ssc2, pba, 9);
1432
1433 struct platform_device *__init
1434 at32_add_device_ssc(unsigned int id, unsigned int flags)
1435 {
1436         struct platform_device *pdev;
1437
1438         switch (id) {
1439         case 0:
1440                 pdev = &ssc0_device;
1441                 if (flags & ATMEL_SSC_RF)
1442                         select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1443                 if (flags & ATMEL_SSC_RK)
1444                         select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1445                 if (flags & ATMEL_SSC_TK)
1446                         select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1447                 if (flags & ATMEL_SSC_TF)
1448                         select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1449                 if (flags & ATMEL_SSC_TD)
1450                         select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1451                 if (flags & ATMEL_SSC_RD)
1452                         select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1453                 break;
1454         case 1:
1455                 pdev = &ssc1_device;
1456                 if (flags & ATMEL_SSC_RF)
1457                         select_peripheral(PA(0), PERIPH_B, 0);  /* RF */
1458                 if (flags & ATMEL_SSC_RK)
1459                         select_peripheral(PA(1), PERIPH_B, 0);  /* RK */
1460                 if (flags & ATMEL_SSC_TK)
1461                         select_peripheral(PA(2), PERIPH_B, 0);  /* TK */
1462                 if (flags & ATMEL_SSC_TF)
1463                         select_peripheral(PA(3), PERIPH_B, 0);  /* TF */
1464                 if (flags & ATMEL_SSC_TD)
1465                         select_peripheral(PA(4), PERIPH_B, 0);  /* TD */
1466                 if (flags & ATMEL_SSC_RD)
1467                         select_peripheral(PA(5), PERIPH_B, 0);  /* RD */
1468                 break;
1469         case 2:
1470                 pdev = &ssc2_device;
1471                 if (flags & ATMEL_SSC_TD)
1472                         select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1473                 if (flags & ATMEL_SSC_RD)
1474                         select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1475                 if (flags & ATMEL_SSC_TK)
1476                         select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1477                 if (flags & ATMEL_SSC_TF)
1478                         select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1479                 if (flags & ATMEL_SSC_RF)
1480                         select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1481                 if (flags & ATMEL_SSC_RK)
1482                         select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1483                 break;
1484         default:
1485                 return NULL;
1486         }
1487
1488         platform_device_register(pdev);
1489         return pdev;
1490 }
1491
1492 /* --------------------------------------------------------------------
1493  *  USB Device Controller
1494  * -------------------------------------------------------------------- */
1495 static struct resource usba0_resource[] __initdata = {
1496         {
1497                 .start          = 0xff300000,
1498                 .end            = 0xff3fffff,
1499                 .flags          = IORESOURCE_MEM,
1500         }, {
1501                 .start          = 0xfff03000,
1502                 .end            = 0xfff033ff,
1503                 .flags          = IORESOURCE_MEM,
1504         },
1505         IRQ(31),
1506 };
1507 static struct clk usba0_pclk = {
1508         .name           = "pclk",
1509         .parent         = &pbb_clk,
1510         .mode           = pbb_clk_mode,
1511         .get_rate       = pbb_clk_get_rate,
1512         .index          = 12,
1513 };
1514 static struct clk usba0_hclk = {
1515         .name           = "hclk",
1516         .parent         = &hsb_clk,
1517         .mode           = hsb_clk_mode,
1518         .get_rate       = hsb_clk_get_rate,
1519         .index          = 6,
1520 };
1521
1522 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1523         [idx] = {                                               \
1524                 .name           = nam,                          \
1525                 .index          = idx,                          \
1526                 .fifo_size      = maxpkt,                       \
1527                 .nr_banks       = maxbk,                        \
1528                 .can_dma        = dma,                          \
1529                 .can_isoc       = isoc,                         \
1530         }
1531
1532 static struct usba_ep_data at32_usba_ep[] __initdata = {
1533         EP("ep0",     0,   64, 1, 0, 0),
1534         EP("ep1",     1,  512, 2, 1, 1),
1535         EP("ep2",     2,  512, 2, 1, 1),
1536         EP("ep3-int", 3,   64, 3, 1, 0),
1537         EP("ep4-int", 4,   64, 3, 1, 0),
1538         EP("ep5",     5, 1024, 3, 1, 1),
1539         EP("ep6",     6, 1024, 3, 1, 1),
1540 };
1541
1542 #undef EP
1543
1544 struct platform_device *__init
1545 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1546 {
1547         /*
1548          * pdata doesn't have room for any endpoints, so we need to
1549          * append room for the ones we need right after it.
1550          */
1551         struct {
1552                 struct usba_platform_data pdata;
1553                 struct usba_ep_data ep[7];
1554         } usba_data;
1555         struct platform_device *pdev;
1556
1557         if (id != 0)
1558                 return NULL;
1559
1560         pdev = platform_device_alloc("atmel_usba_udc", 0);
1561         if (!pdev)
1562                 return NULL;
1563
1564         if (platform_device_add_resources(pdev, usba0_resource,
1565                                           ARRAY_SIZE(usba0_resource)))
1566                 goto out_free_pdev;
1567
1568         if (data)
1569                 usba_data.pdata.vbus_pin = data->vbus_pin;
1570         else
1571                 usba_data.pdata.vbus_pin = -EINVAL;
1572
1573         data = &usba_data.pdata;
1574         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1575         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1576
1577         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1578                 goto out_free_pdev;
1579
1580         if (data->vbus_pin >= 0)
1581                 at32_select_gpio(data->vbus_pin, 0);
1582
1583         usba0_pclk.dev = &pdev->dev;
1584         usba0_hclk.dev = &pdev->dev;
1585
1586         platform_device_add(pdev);
1587
1588         return pdev;
1589
1590 out_free_pdev:
1591         platform_device_put(pdev);
1592         return NULL;
1593 }
1594
1595 /* --------------------------------------------------------------------
1596  * IDE / CompactFlash
1597  * -------------------------------------------------------------------- */
1598 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1599 static struct resource at32_smc_cs4_resource[] __initdata = {
1600         {
1601                 .start  = 0x04000000,
1602                 .end    = 0x07ffffff,
1603                 .flags  = IORESOURCE_MEM,
1604         },
1605         IRQ(~0UL), /* Magic IRQ will be overridden */
1606 };
1607 static struct resource at32_smc_cs5_resource[] __initdata = {
1608         {
1609                 .start  = 0x20000000,
1610                 .end    = 0x23ffffff,
1611                 .flags  = IORESOURCE_MEM,
1612         },
1613         IRQ(~0UL), /* Magic IRQ will be overridden */
1614 };
1615
1616 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1617                 unsigned int cs, unsigned int extint)
1618 {
1619         static unsigned int extint_pin_map[4] __initdata = {
1620                 GPIO_PIN_PB(25),
1621                 GPIO_PIN_PB(26),
1622                 GPIO_PIN_PB(27),
1623                 GPIO_PIN_PB(28),
1624         };
1625         static bool common_pins_initialized __initdata = false;
1626         unsigned int extint_pin;
1627         int ret;
1628
1629         if (extint >= ARRAY_SIZE(extint_pin_map))
1630                 return -EINVAL;
1631         extint_pin = extint_pin_map[extint];
1632
1633         switch (cs) {
1634         case 4:
1635                 ret = platform_device_add_resources(pdev,
1636                                 at32_smc_cs4_resource,
1637                                 ARRAY_SIZE(at32_smc_cs4_resource));
1638                 if (ret)
1639                         return ret;
1640
1641                 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4   -> OE_N  */
1642                 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1643                 break;
1644         case 5:
1645                 ret = platform_device_add_resources(pdev,
1646                                 at32_smc_cs5_resource,
1647                                 ARRAY_SIZE(at32_smc_cs5_resource));
1648                 if (ret)
1649                         return ret;
1650
1651                 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5   -> OE_N  */
1652                 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1653                 break;
1654         default:
1655                 return -EINVAL;
1656         }
1657
1658         if (!common_pins_initialized) {
1659                 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1  -> CS0_N */
1660                 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2  -> CS1_N */
1661                 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW  -> DIR   */
1662                 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT  <- IORDY */
1663                 common_pins_initialized = true;
1664         }
1665
1666         at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1667
1668         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1669         pdev->resource[1].end = pdev->resource[1].start;
1670
1671         return 0;
1672 }
1673
1674 struct platform_device *__init
1675 at32_add_device_ide(unsigned int id, unsigned int extint,
1676                     struct ide_platform_data *data)
1677 {
1678         struct platform_device *pdev;
1679
1680         pdev = platform_device_alloc("at32_ide", id);
1681         if (!pdev)
1682                 goto fail;
1683
1684         if (platform_device_add_data(pdev, data,
1685                                 sizeof(struct ide_platform_data)))
1686                 goto fail;
1687
1688         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1689                 goto fail;
1690
1691         platform_device_add(pdev);
1692         return pdev;
1693
1694 fail:
1695         platform_device_put(pdev);
1696         return NULL;
1697 }
1698
1699 struct platform_device *__init
1700 at32_add_device_cf(unsigned int id, unsigned int extint,
1701                     struct cf_platform_data *data)
1702 {
1703         struct platform_device *pdev;
1704
1705         pdev = platform_device_alloc("at32_cf", id);
1706         if (!pdev)
1707                 goto fail;
1708
1709         if (platform_device_add_data(pdev, data,
1710                                 sizeof(struct cf_platform_data)))
1711                 goto fail;
1712
1713         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1714                 goto fail;
1715
1716         if (data->detect_pin != GPIO_PIN_NONE)
1717                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1718         if (data->reset_pin != GPIO_PIN_NONE)
1719                 at32_select_gpio(data->reset_pin, 0);
1720         if (data->vcc_pin != GPIO_PIN_NONE)
1721                 at32_select_gpio(data->vcc_pin, 0);
1722         /* READY is used as extint, so we can't select it as gpio */
1723
1724         platform_device_add(pdev);
1725         return pdev;
1726
1727 fail:
1728         platform_device_put(pdev);
1729         return NULL;
1730 }
1731 #endif
1732
1733 /* --------------------------------------------------------------------
1734  * AC97C
1735  * -------------------------------------------------------------------- */
1736 static struct resource atmel_ac97c0_resource[] __initdata = {
1737         PBMEM(0xfff02800),
1738         IRQ(29),
1739 };
1740 static struct clk atmel_ac97c0_pclk = {
1741         .name           = "pclk",
1742         .parent         = &pbb_clk,
1743         .mode           = pbb_clk_mode,
1744         .get_rate       = pbb_clk_get_rate,
1745         .index          = 10,
1746 };
1747
1748 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1749 {
1750         struct platform_device *pdev;
1751
1752         if (id != 0)
1753                 return NULL;
1754
1755         pdev = platform_device_alloc("atmel_ac97c", id);
1756         if (!pdev)
1757                 return NULL;
1758
1759         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1760                                 ARRAY_SIZE(atmel_ac97c0_resource)))
1761                 goto err_add_resources;
1762
1763         select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1764         select_peripheral(PB(21), PERIPH_B, 0); /* SDO  */
1765         select_peripheral(PB(22), PERIPH_B, 0); /* SDI  */
1766         select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1767
1768         atmel_ac97c0_pclk.dev = &pdev->dev;
1769
1770         platform_device_add(pdev);
1771         return pdev;
1772
1773 err_add_resources:
1774         platform_device_put(pdev);
1775         return NULL;
1776 }
1777
1778 /* --------------------------------------------------------------------
1779  * ABDAC
1780  * -------------------------------------------------------------------- */
1781 static struct resource abdac0_resource[] __initdata = {
1782         PBMEM(0xfff02000),
1783         IRQ(27),
1784 };
1785 static struct clk abdac0_pclk = {
1786         .name           = "pclk",
1787         .parent         = &pbb_clk,
1788         .mode           = pbb_clk_mode,
1789         .get_rate       = pbb_clk_get_rate,
1790         .index          = 8,
1791 };
1792 static struct clk abdac0_sample_clk = {
1793         .name           = "sample_clk",
1794         .mode           = genclk_mode,
1795         .get_rate       = genclk_get_rate,
1796         .set_rate       = genclk_set_rate,
1797         .set_parent     = genclk_set_parent,
1798         .index          = 6,
1799 };
1800
1801 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1802 {
1803         struct platform_device *pdev;
1804
1805         if (id != 0)
1806                 return NULL;
1807
1808         pdev = platform_device_alloc("abdac", id);
1809         if (!pdev)
1810                 return NULL;
1811
1812         if (platform_device_add_resources(pdev, abdac0_resource,
1813                                 ARRAY_SIZE(abdac0_resource)))
1814                 goto err_add_resources;
1815
1816         select_peripheral(PB(20), PERIPH_A, 0); /* DATA1        */
1817         select_peripheral(PB(21), PERIPH_A, 0); /* DATA0        */
1818         select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1       */
1819         select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0       */
1820
1821         abdac0_pclk.dev = &pdev->dev;
1822         abdac0_sample_clk.dev = &pdev->dev;
1823
1824         platform_device_add(pdev);
1825         return pdev;
1826
1827 err_add_resources:
1828         platform_device_put(pdev);
1829         return NULL;
1830 }
1831
1832 /* --------------------------------------------------------------------
1833  *  GCLK
1834  * -------------------------------------------------------------------- */
1835 static struct clk gclk0 = {
1836         .name           = "gclk0",
1837         .mode           = genclk_mode,
1838         .get_rate       = genclk_get_rate,
1839         .set_rate       = genclk_set_rate,
1840         .set_parent     = genclk_set_parent,
1841         .index          = 0,
1842 };
1843 static struct clk gclk1 = {
1844         .name           = "gclk1",
1845         .mode           = genclk_mode,
1846         .get_rate       = genclk_get_rate,
1847         .set_rate       = genclk_set_rate,
1848         .set_parent     = genclk_set_parent,
1849         .index          = 1,
1850 };
1851 static struct clk gclk2 = {
1852         .name           = "gclk2",
1853         .mode           = genclk_mode,
1854         .get_rate       = genclk_get_rate,
1855         .set_rate       = genclk_set_rate,
1856         .set_parent     = genclk_set_parent,
1857         .index          = 2,
1858 };
1859 static struct clk gclk3 = {
1860         .name           = "gclk3",
1861         .mode           = genclk_mode,
1862         .get_rate       = genclk_get_rate,
1863         .set_rate       = genclk_set_rate,
1864         .set_parent     = genclk_set_parent,
1865         .index          = 3,
1866 };
1867 static struct clk gclk4 = {
1868         .name           = "gclk4",
1869         .mode           = genclk_mode,
1870         .get_rate       = genclk_get_rate,
1871         .set_rate       = genclk_set_rate,
1872         .set_parent     = genclk_set_parent,
1873         .index          = 4,
1874 };
1875
1876 struct clk *at32_clock_list[] = {
1877         &osc32k,
1878         &osc0,
1879         &osc1,
1880         &pll0,
1881         &pll1,
1882         &cpu_clk,
1883         &hsb_clk,
1884         &pba_clk,
1885         &pbb_clk,
1886         &at32_pm_pclk,
1887         &at32_intc0_pclk,
1888         &hmatrix_clk,
1889         &ebi_clk,
1890         &hramc_clk,
1891         &smc0_pclk,
1892         &smc0_mck,
1893         &pdc_hclk,
1894         &pdc_pclk,
1895         &dw_dmac0_hclk,
1896         &pico_clk,
1897         &pio0_mck,
1898         &pio1_mck,
1899         &pio2_mck,
1900         &pio3_mck,
1901         &pio4_mck,
1902         &at32_tcb0_t0_clk,
1903         &at32_tcb1_t0_clk,
1904         &atmel_usart0_usart,
1905         &atmel_usart1_usart,
1906         &atmel_usart2_usart,
1907         &atmel_usart3_usart,
1908         &atmel_pwm0_mck,
1909 #if defined(CONFIG_CPU_AT32AP7000)
1910         &macb0_hclk,
1911         &macb0_pclk,
1912         &macb1_hclk,
1913         &macb1_pclk,
1914 #endif
1915         &atmel_spi0_spi_clk,
1916         &atmel_spi1_spi_clk,
1917         &atmel_twi0_pclk,
1918         &atmel_mci0_pclk,
1919 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1920         &atmel_lcdfb0_hck1,
1921         &atmel_lcdfb0_pixclk,
1922 #endif
1923         &ssc0_pclk,
1924         &ssc1_pclk,
1925         &ssc2_pclk,
1926         &usba0_hclk,
1927         &usba0_pclk,
1928         &atmel_ac97c0_pclk,
1929         &abdac0_pclk,
1930         &abdac0_sample_clk,
1931         &gclk0,
1932         &gclk1,
1933         &gclk2,
1934         &gclk3,
1935         &gclk4,
1936 };
1937 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1938
1939 void __init at32_portmux_init(void)
1940 {
1941         at32_init_pio(&pio0_device);
1942         at32_init_pio(&pio1_device);
1943         at32_init_pio(&pio2_device);
1944         at32_init_pio(&pio3_device);
1945         at32_init_pio(&pio4_device);
1946 }
1947
1948 void __init at32_clock_init(void)
1949 {
1950         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1951         int i;
1952
1953         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
1954                 main_clock = &pll0;
1955                 cpu_clk.parent = &pll0;
1956         } else {
1957                 main_clock = &osc0;
1958                 cpu_clk.parent = &osc0;
1959         }
1960
1961         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
1962                 pll0.parent = &osc1;
1963         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
1964                 pll1.parent = &osc1;
1965
1966         genclk_init_parent(&gclk0);
1967         genclk_init_parent(&gclk1);
1968         genclk_init_parent(&gclk2);
1969         genclk_init_parent(&gclk3);
1970         genclk_init_parent(&gclk4);
1971 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1972         genclk_init_parent(&atmel_lcdfb0_pixclk);
1973 #endif
1974         genclk_init_parent(&abdac0_sample_clk);
1975
1976         /*
1977          * Turn on all clocks that have at least one user already, and
1978          * turn off everything else. We only do this for module
1979          * clocks, and even though it isn't particularly pretty to
1980          * check the address of the mode function, it should do the
1981          * trick...
1982          */
1983         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1984                 struct clk *clk = at32_clock_list[i];
1985
1986                 if (clk->users == 0)
1987                         continue;
1988
1989                 if (clk->mode == &cpu_clk_mode)
1990                         cpu_mask |= 1 << clk->index;
1991                 else if (clk->mode == &hsb_clk_mode)
1992                         hsb_mask |= 1 << clk->index;
1993                 else if (clk->mode == &pba_clk_mode)
1994                         pba_mask |= 1 << clk->index;
1995                 else if (clk->mode == &pbb_clk_mode)
1996                         pbb_mask |= 1 << clk->index;
1997         }
1998
1999         pm_writel(CPU_MASK, cpu_mask);
2000         pm_writel(HSB_MASK, hsb_mask);
2001         pm_writel(PBA_MASK, pba_mask);
2002         pm_writel(PBB_MASK, pbb_mask);
2003 }