git.oblomov.eu Git - linux-2.6/blob - drivers/net/igb/e1000_82575.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* e1000_82575
  29  * e1000_82576
  30  */
  31
  32 #include <linux/types.h>
  33 #include <linux/slab.h>
  34
  35 #include "e1000_mac.h"
  36 #include "e1000_82575.h"
  37
  38 static s32  igb_get_invariants_82575(struct e1000_hw *);
  39 static s32  igb_acquire_phy_82575(struct e1000_hw *);
  40 static void igb_release_phy_82575(struct e1000_hw *);
  41 static s32  igb_acquire_nvm_82575(struct e1000_hw *);
  42 static void igb_release_nvm_82575(struct e1000_hw *);
  43 static s32  igb_check_for_link_82575(struct e1000_hw *);
  44 static s32  igb_get_cfg_done_82575(struct e1000_hw *);
  45 static s32  igb_init_hw_82575(struct e1000_hw *);
  46 static s32  igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
  47 static s32  igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
  48 static void igb_rar_set_82575(struct e1000_hw *, u8 *, u32);
  49 static s32  igb_reset_hw_82575(struct e1000_hw *);
  50 static s32  igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
  51 static s32  igb_setup_copper_link_82575(struct e1000_hw *);
  52 static s32  igb_setup_fiber_serdes_link_82575(struct e1000_hw *);
  53 static s32  igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
  54 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
  55 static s32  igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
  56 static s32  igb_configure_pcs_link_82575(struct e1000_hw *);
  57 static s32  igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
  58                                                  u16 *);
  59 static s32  igb_get_phy_id_82575(struct e1000_hw *);
  60 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
  61 static bool igb_sgmii_active_82575(struct e1000_hw *);
  62 static s32  igb_reset_init_script_82575(struct e1000_hw *);
  63 static s32  igb_read_mac_addr_82575(struct e1000_hw *);
  64
  65
  66 struct e1000_dev_spec_82575 {
  67         bool sgmii_active;
  68 };
  69
  70 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
  71 {
  72         struct e1000_phy_info *phy = &hw->phy;
  73         struct e1000_nvm_info *nvm = &hw->nvm;
  74         struct e1000_mac_info *mac = &hw->mac;
  75         struct e1000_dev_spec_82575 *dev_spec;
  76         u32 eecd;
  77         s32 ret_val;
  78         u16 size;
  79         u32 ctrl_ext = 0;
  80
  81         switch (hw->device_id) {
  82         case E1000_DEV_ID_82575EB_COPPER:
  83         case E1000_DEV_ID_82575EB_FIBER_SERDES:
  84         case E1000_DEV_ID_82575GB_QUAD_COPPER:
  85                 mac->type = e1000_82575;
  86                 break;
  87         default:
  88                 return -E1000_ERR_MAC_INIT;
  89                 break;
  90         }
  91
  92         /* MAC initialization */
  93         hw->dev_spec_size = sizeof(struct e1000_dev_spec_82575);
  94
  95         /* Device-specific structure allocation */
  96         hw->dev_spec = kzalloc(hw->dev_spec_size, GFP_KERNEL);
  97
  98         if (!hw->dev_spec)
  99                 return -ENOMEM;
 100
 101         dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
 102
 103         /* Set media type */
 104         /*
 105          * The 82575 uses bits 22:23 for link mode. The mode can be changed
 106          * based on the EEPROM. We cannot rely upon device ID. There
 107          * is no distinguishable difference between fiber and internal
 108          * SerDes mode on the 82575. There can be an external PHY attached
 109          * on the SGMII interface. For this, we'll set sgmii_active to true.
 110          */
 111         phy->media_type = e1000_media_type_copper;
 112         dev_spec->sgmii_active = false;
 113
 114         ctrl_ext = rd32(E1000_CTRL_EXT);
 115         if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) ==
 116             E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) {
 117                 hw->phy.media_type = e1000_media_type_internal_serdes;
 118                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 119         } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) {
 120                 dev_spec->sgmii_active = true;
 121                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 122         } else {
 123                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 124         }
 125         wr32(E1000_CTRL_EXT, ctrl_ext);
 126
 127         /* Set mta register count */
 128         mac->mta_reg_count = 128;
 129         /* Set rar entry count */
 130         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 131         /* Set if part includes ASF firmware */
 132         mac->asf_firmware_present = true;
 133         /* Set if manageability features are enabled. */
 134         mac->arc_subsystem_valid =
 135                 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
 136                         ? true : false;
 137
 138         /* physical interface link setup */
 139         mac->ops.setup_physical_interface =
 140                 (hw->phy.media_type == e1000_media_type_copper)
 141                         ? igb_setup_copper_link_82575
 142                         : igb_setup_fiber_serdes_link_82575;
 143
 144         /* NVM initialization */
 145         eecd = rd32(E1000_EECD);
 146
 147         nvm->opcode_bits        = 8;
 148         nvm->delay_usec         = 1;
 149         switch (nvm->override) {
 150         case e1000_nvm_override_spi_large:
 151                 nvm->page_size    = 32;
 152                 nvm->address_bits = 16;
 153                 break;
 154         case e1000_nvm_override_spi_small:
 155                 nvm->page_size    = 8;
 156                 nvm->address_bits = 8;
 157                 break;
 158         default:
 159                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 160                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 161                 break;
 162         }
 163
 164         nvm->type = e1000_nvm_eeprom_spi;
 165
 166         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 167                      E1000_EECD_SIZE_EX_SHIFT);
 168
 169         /*
 170          * Added to a constant, "size" becomes the left-shift value
 171          * for setting word_size.
 172          */
 173         size += NVM_WORD_SIZE_BASE_SHIFT;
 174         nvm->word_size = 1 << size;
 175
 176         /* setup PHY parameters */
 177         if (phy->media_type != e1000_media_type_copper) {
 178                 phy->type = e1000_phy_none;
 179                 return 0;
 180         }
 181
 182         phy->autoneg_mask        = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 183         phy->reset_delay_us      = 100;
 184
 185         /* PHY function pointers */
 186         if (igb_sgmii_active_82575(hw)) {
 187                 phy->ops.reset_phy          = igb_phy_hw_reset_sgmii_82575;
 188                 phy->ops.read_phy_reg       = igb_read_phy_reg_sgmii_82575;
 189                 phy->ops.write_phy_reg      = igb_write_phy_reg_sgmii_82575;
 190         } else {
 191                 phy->ops.reset_phy          = igb_phy_hw_reset;
 192                 phy->ops.read_phy_reg       = igb_read_phy_reg_igp;
 193                 phy->ops.write_phy_reg      = igb_write_phy_reg_igp;
 194         }
 195
 196         /* Set phy->phy_addr and phy->id. */
 197         ret_val = igb_get_phy_id_82575(hw);
 198         if (ret_val)
 199                 return ret_val;
 200
 201         /* Verify phy id and set remaining function pointers */
 202         switch (phy->id) {
 203         case M88E1111_I_PHY_ID:
 204                 phy->type                   = e1000_phy_m88;
 205                 phy->ops.get_phy_info       = igb_get_phy_info_m88;
 206                 phy->ops.get_cable_length   = igb_get_cable_length_m88;
 207                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 208                 break;
 209         case IGP03E1000_E_PHY_ID:
 210                 phy->type                   = e1000_phy_igp_3;
 211                 phy->ops.get_phy_info       = igb_get_phy_info_igp;
 212                 phy->ops.get_cable_length   = igb_get_cable_length_igp_2;
 213                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
 214                 phy->ops.set_d0_lplu_state  = igb_set_d0_lplu_state_82575;
 215                 phy->ops.set_d3_lplu_state  = igb_set_d3_lplu_state;
 216                 break;
 217         default:
 218                 return -E1000_ERR_PHY;
 219         }
 220
 221         return 0;
 222 }
 223
 224 /**
 225  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 226  *  @hw: pointer to the HW structure
 227  *
 228  *  Acquire access rights to the correct PHY.  This is a
 229  *  function pointer entry point called by the api module.
 230  **/
 231 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
 232 {
 233         u16 mask;
 234
 235         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 236
 237         return igb_acquire_swfw_sync_82575(hw, mask);
 238 }
 239
 240 /**
 241  *  e1000_release_phy_82575 - Release rights to access PHY
 242  *  @hw: pointer to the HW structure
 243  *
 244  *  A wrapper to release access rights to the correct PHY.  This is a
 245  *  function pointer entry point called by the api module.
 246  **/
 247 static void igb_release_phy_82575(struct e1000_hw *hw)
 248 {
 249         u16 mask;
 250
 251         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 252         igb_release_swfw_sync_82575(hw, mask);
 253 }
 254
 255 /**
 256  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 257  *  @hw: pointer to the HW structure
 258  *  @offset: register offset to be read
 259  *  @data: pointer to the read data
 260  *
 261  *  Reads the PHY register at offset using the serial gigabit media independent
 262  *  interface and stores the retrieved information in data.
 263  **/
 264 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 265                                           u16 *data)
 266 {
 267         struct e1000_phy_info *phy = &hw->phy;
 268         u32 i, i2ccmd = 0;
 269
 270         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 271                 hw_dbg(hw, "PHY Address %u is out of range\n", offset);
 272                 return -E1000_ERR_PARAM;
 273         }
 274
 275         /*
 276          * Set up Op-code, Phy Address, and register address in the I2CCMD
 277          * register.  The MAC will take care of interfacing with the
 278          * PHY to retrieve the desired data.
 279          */
 280         i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
 281                   (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
 282                   (E1000_I2CCMD_OPCODE_READ));
 283
 284         wr32(E1000_I2CCMD, i2ccmd);
 285
 286         /* Poll the ready bit to see if the I2C read completed */
 287         for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
 288                 udelay(50);
 289                 i2ccmd = rd32(E1000_I2CCMD);
 290                 if (i2ccmd & E1000_I2CCMD_READY)
 291                         break;
 292         }
 293         if (!(i2ccmd & E1000_I2CCMD_READY)) {
 294                 hw_dbg(hw, "I2CCMD Read did not complete\n");
 295                 return -E1000_ERR_PHY;
 296         }
 297         if (i2ccmd & E1000_I2CCMD_ERROR) {
 298                 hw_dbg(hw, "I2CCMD Error bit set\n");
 299                 return -E1000_ERR_PHY;
 300         }
 301
 302         /* Need to byte-swap the 16-bit value. */
 303         *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
 304
 305         return 0;
 306 }
 307
 308 /**
 309  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 310  *  @hw: pointer to the HW structure
 311  *  @offset: register offset to write to
 312  *  @data: data to write at register offset
 313  *
 314  *  Writes the data to PHY register at the offset using the serial gigabit
 315  *  media independent interface.
 316  **/
 317 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 318                                            u16 data)
 319 {
 320         struct e1000_phy_info *phy = &hw->phy;
 321         u32 i, i2ccmd = 0;
 322         u16 phy_data_swapped;
 323
 324         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 325                 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
 326                 return -E1000_ERR_PARAM;
 327         }
 328
 329         /* Swap the data bytes for the I2C interface */
 330         phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
 331
 332         /*
 333          * Set up Op-code, Phy Address, and register address in the I2CCMD
 334          * register.  The MAC will take care of interfacing with the
 335          * PHY to retrieve the desired data.
 336          */
 337         i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
 338                   (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
 339                   E1000_I2CCMD_OPCODE_WRITE |
 340                   phy_data_swapped);
 341
 342         wr32(E1000_I2CCMD, i2ccmd);
 343
 344         /* Poll the ready bit to see if the I2C read completed */
 345         for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
 346                 udelay(50);
 347                 i2ccmd = rd32(E1000_I2CCMD);
 348                 if (i2ccmd & E1000_I2CCMD_READY)
 349                         break;
 350         }
 351         if (!(i2ccmd & E1000_I2CCMD_READY)) {
 352                 hw_dbg(hw, "I2CCMD Write did not complete\n");
 353                 return -E1000_ERR_PHY;
 354         }
 355         if (i2ccmd & E1000_I2CCMD_ERROR) {
 356                 hw_dbg(hw, "I2CCMD Error bit set\n");
 357                 return -E1000_ERR_PHY;
 358         }
 359
 360         return 0;
 361 }
 362
 363 /**
 364  *  e1000_get_phy_id_82575 - Retreive PHY addr and id
 365  *  @hw: pointer to the HW structure
 366  *
 367  *  Retreives the PHY address and ID for both PHY's which do and do not use
 368  *  sgmi interface.
 369  **/
 370 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
 371 {
 372         struct e1000_phy_info *phy = &hw->phy;
 373         s32  ret_val = 0;
 374         u16 phy_id;
 375
 376         /*
 377          * For SGMII PHYs, we try the list of possible addresses until
 378          * we find one that works.  For non-SGMII PHYs
 379          * (e.g. integrated copper PHYs), an address of 1 should
 380          * work.  The result of this function should mean phy->phy_addr
 381          * and phy->id are set correctly.
 382          */
 383         if (!(igb_sgmii_active_82575(hw))) {
 384                 phy->addr = 1;
 385                 ret_val = igb_get_phy_id(hw);
 386                 goto out;
 387         }
 388
 389         /*
 390          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 391          * Therefore, we need to test 1-7
 392          */
 393         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 394                 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 395                 if (ret_val == 0) {
 396                         hw_dbg(hw, "Vendor ID 0x%08X read at address %u\n",
 397                                   phy_id,
 398                                   phy->addr);
 399                         /*
 400                          * At the time of this writing, The M88 part is
 401                          * the only supported SGMII PHY product.
 402                          */
 403                         if (phy_id == M88_VENDOR)
 404                                 break;
 405                 } else {
 406                         hw_dbg(hw, "PHY address %u was unreadable\n",
 407                                   phy->addr);
 408                 }
 409         }
 410
 411         /* A valid PHY type couldn't be found. */
 412         if (phy->addr == 8) {
 413                 phy->addr = 0;
 414                 ret_val = -E1000_ERR_PHY;
 415                 goto out;
 416         }
 417
 418         ret_val = igb_get_phy_id(hw);
 419
 420 out:
 421         return ret_val;
 422 }
 423
 424 /**
 425  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 426  *  @hw: pointer to the HW structure
 427  *
 428  *  Resets the PHY using the serial gigabit media independent interface.
 429  **/
 430 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 431 {
 432         s32 ret_val;
 433
 434         /*
 435          * This isn't a true "hard" reset, but is the only reset
 436          * available to us at this time.
 437          */
 438
 439         hw_dbg(hw, "Soft resetting SGMII attached PHY...\n");
 440
 441         /*
 442          * SFP documentation requires the following to configure the SPF module
 443          * to work on SGMII.  No further documentation is given.
 444          */
 445         ret_val = hw->phy.ops.write_phy_reg(hw, 0x1B, 0x8084);
 446         if (ret_val)
 447                 goto out;
 448
 449         ret_val = igb_phy_sw_reset(hw);
 450
 451 out:
 452         return ret_val;
 453 }
 454
 455 /**
 456  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 457  *  @hw: pointer to the HW structure
 458  *  @active: true to enable LPLU, false to disable
 459  *
 460  *  Sets the LPLU D0 state according to the active flag.  When
 461  *  activating LPLU this function also disables smart speed
 462  *  and vice versa.  LPLU will not be activated unless the
 463  *  device autonegotiation advertisement meets standards of
 464  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 465  *  This is a function pointer entry point only called by
 466  *  PHY setup routines.
 467  **/
 468 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 469 {
 470         struct e1000_phy_info *phy = &hw->phy;
 471         s32 ret_val;
 472         u16 data;
 473
 474         ret_val = hw->phy.ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 475                                            &data);
 476         if (ret_val)
 477                 goto out;
 478
 479         if (active) {
 480                 data |= IGP02E1000_PM_D0_LPLU;
 481                 ret_val = hw->phy.ops.write_phy_reg(hw,
 482                                               IGP02E1000_PHY_POWER_MGMT,
 483                                               data);
 484                 if (ret_val)
 485                         goto out;
 486
 487                 /* When LPLU is enabled, we should disable SmartSpeed */
 488                 ret_val = hw->phy.ops.read_phy_reg(hw,
 489                                              IGP01E1000_PHY_PORT_CONFIG,
 490                                              &data);
 491                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 492                 ret_val = hw->phy.ops.write_phy_reg(hw,
 493                                               IGP01E1000_PHY_PORT_CONFIG,
 494                                               data);
 495                 if (ret_val)
 496                         goto out;
 497         } else {
 498                 data &= ~IGP02E1000_PM_D0_LPLU;
 499                 ret_val = hw->phy.ops.write_phy_reg(hw,
 500                                               IGP02E1000_PHY_POWER_MGMT,
 501                                               data);
 502                 /*
 503                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 504                  * during Dx states where the power conservation is most
 505                  * important.  During driver activity we should enable
 506                  * SmartSpeed, so performance is maintained.
 507                  */
 508                 if (phy->smart_speed == e1000_smart_speed_on) {
 509                         ret_val = hw->phy.ops.read_phy_reg(hw,
 510                                                      IGP01E1000_PHY_PORT_CONFIG,
 511                                                      &data);
 512                         if (ret_val)
 513                                 goto out;
 514
 515                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 516                         ret_val = hw->phy.ops.write_phy_reg(hw,
 517                                                      IGP01E1000_PHY_PORT_CONFIG,
 518                                                      data);
 519                         if (ret_val)
 520                                 goto out;
 521                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 522                         ret_val = hw->phy.ops.read_phy_reg(hw,
 523                                                      IGP01E1000_PHY_PORT_CONFIG,
 524                                                      &data);
 525                         if (ret_val)
 526                                 goto out;
 527
 528                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 529                         ret_val = hw->phy.ops.write_phy_reg(hw,
 530                                                      IGP01E1000_PHY_PORT_CONFIG,
 531                                                      data);
 532                         if (ret_val)
 533                                 goto out;
 534                 }
 535         }
 536
 537 out:
 538         return ret_val;
 539 }
 540
 541 /**
 542  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 543  *  @hw: pointer to the HW structure
 544  *
 545  *  Acquire the necessary semaphores for exclussive access to the EEPROM.
 546  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 547  *  Return successful if access grant bit set, else clear the request for
 548  *  EEPROM access and return -E1000_ERR_NVM (-1).
 549  **/
 550 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
 551 {
 552         s32 ret_val;
 553
 554         ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 555         if (ret_val)
 556                 goto out;
 557
 558         ret_val = igb_acquire_nvm(hw);
 559
 560         if (ret_val)
 561                 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 562
 563 out:
 564         return ret_val;
 565 }
 566
 567 /**
 568  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
 569  *  @hw: pointer to the HW structure
 570  *
 571  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
 572  *  then release the semaphores acquired.
 573  **/
 574 static void igb_release_nvm_82575(struct e1000_hw *hw)
 575 {
 576         igb_release_nvm(hw);
 577         igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 578 }
 579
 580 /**
 581  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
 582  *  @hw: pointer to the HW structure
 583  *  @mask: specifies which semaphore to acquire
 584  *
 585  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 586  *  will also specify which port we're acquiring the lock for.
 587  **/
 588 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
 589 {
 590         u32 swfw_sync;
 591         u32 swmask = mask;
 592         u32 fwmask = mask << 16;
 593         s32 ret_val = 0;
 594         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
 595
 596         while (i < timeout) {
 597                 if (igb_get_hw_semaphore(hw)) {
 598                         ret_val = -E1000_ERR_SWFW_SYNC;
 599                         goto out;
 600                 }
 601
 602                 swfw_sync = rd32(E1000_SW_FW_SYNC);
 603                 if (!(swfw_sync & (fwmask | swmask)))
 604                         break;
 605
 606                 /*
 607                  * Firmware currently using resource (fwmask)
 608                  * or other software thread using resource (swmask)
 609                  */
 610                 igb_put_hw_semaphore(hw);
 611                 mdelay(5);
 612                 i++;
 613         }
 614
 615         if (i == timeout) {
 616                 hw_dbg(hw, "Can't access resource, SW_FW_SYNC timeout.\n");
 617                 ret_val = -E1000_ERR_SWFW_SYNC;
 618                 goto out;
 619         }
 620
 621         swfw_sync |= swmask;
 622         wr32(E1000_SW_FW_SYNC, swfw_sync);
 623
 624         igb_put_hw_semaphore(hw);
 625
 626 out:
 627         return ret_val;
 628 }
 629
 630 /**
 631  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
 632  *  @hw: pointer to the HW structure
 633  *  @mask: specifies which semaphore to acquire
 634  *
 635  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 636  *  will also specify which port we're releasing the lock for.
 637  **/
 638 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
 639 {
 640         u32 swfw_sync;
 641
 642         while (igb_get_hw_semaphore(hw) != 0);
 643         /* Empty */
 644
 645         swfw_sync = rd32(E1000_SW_FW_SYNC);
 646         swfw_sync &= ~mask;
 647         wr32(E1000_SW_FW_SYNC, swfw_sync);
 648
 649         igb_put_hw_semaphore(hw);
 650 }
 651
 652 /**
 653  *  e1000_get_cfg_done_82575 - Read config done bit
 654  *  @hw: pointer to the HW structure
 655  *
 656  *  Read the management control register for the config done bit for
 657  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
 658  *  to read the config done bit, so an error is *ONLY* logged and returns
 659  *  0.  If we were to return with error, EEPROM-less silicon
 660  *  would not be able to be reset or change link.
 661  **/
 662 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
 663 {
 664         s32 timeout = PHY_CFG_TIMEOUT;
 665         s32 ret_val = 0;
 666         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 667
 668         if (hw->bus.func == 1)
 669                 mask = E1000_NVM_CFG_DONE_PORT_1;
 670
 671         while (timeout) {
 672                 if (rd32(E1000_EEMNGCTL) & mask)
 673                         break;
 674                 msleep(1);
 675                 timeout--;
 676         }
 677         if (!timeout)
 678                 hw_dbg(hw, "MNG configuration cycle has not completed.\n");
 679
 680         /* If EEPROM is not marked present, init the PHY manually */
 681         if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
 682             (hw->phy.type == e1000_phy_igp_3))
 683                 igb_phy_init_script_igp3(hw);
 684
 685         return ret_val;
 686 }
 687
 688 /**
 689  *  e1000_check_for_link_82575 - Check for link
 690  *  @hw: pointer to the HW structure
 691  *
 692  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
 693  *  use the generic interface for determining link.
 694  **/
 695 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
 696 {
 697         s32 ret_val;
 698         u16 speed, duplex;
 699
 700         /* SGMII link check is done through the PCS register. */
 701         if ((hw->phy.media_type != e1000_media_type_copper) ||
 702             (igb_sgmii_active_82575(hw)))
 703                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
 704                                                                &duplex);
 705         else
 706                 ret_val = igb_check_for_copper_link(hw);
 707
 708         return ret_val;
 709 }
 710
 711 /**
 712  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
 713  *  @hw: pointer to the HW structure
 714  *  @speed: stores the current speed
 715  *  @duplex: stores the current duplex
 716  *
 717  *  Using the physical coding sub-layer (PCS), retreive the current speed and
 718  *  duplex, then store the values in the pointers provided.
 719  **/
 720 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
 721                                                 u16 *duplex)
 722 {
 723         struct e1000_mac_info *mac = &hw->mac;
 724         u32 pcs;
 725
 726         /* Set up defaults for the return values of this function */
 727         mac->serdes_has_link = false;
 728         *speed = 0;
 729         *duplex = 0;
 730
 731         /*
 732          * Read the PCS Status register for link state. For non-copper mode,
 733          * the status register is not accurate. The PCS status register is
 734          * used instead.
 735          */
 736         pcs = rd32(E1000_PCS_LSTAT);
 737
 738         /*
 739          * The link up bit determines when link is up on autoneg. The sync ok
 740          * gets set once both sides sync up and agree upon link. Stable link
 741          * can be determined by checking for both link up and link sync ok
 742          */
 743         if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
 744                 mac->serdes_has_link = true;
 745
 746                 /* Detect and store PCS speed */
 747                 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
 748                         *speed = SPEED_1000;
 749                 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
 750                         *speed = SPEED_100;
 751                 } else {
 752                         *speed = SPEED_10;
 753                 }
 754
 755                 /* Detect and store PCS duplex */
 756                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
 757                         *duplex = FULL_DUPLEX;
 758                 } else {
 759                         *duplex = HALF_DUPLEX;
 760                 }
 761         }
 762
 763         return 0;
 764 }
 765
 766 /**
 767  *  e1000_rar_set_82575 - Set receive address register
 768  *  @hw: pointer to the HW structure
 769  *  @addr: pointer to the receive address
 770  *  @index: receive address array register
 771  *
 772  *  Sets the receive address array register at index to the address passed
 773  *  in by addr.
 774  **/
 775 static void igb_rar_set_82575(struct e1000_hw *hw, u8 *addr, u32 index)
 776 {
 777         if (index < E1000_RAR_ENTRIES_82575)
 778                 igb_rar_set(hw, addr, index);
 779
 780         return;
 781 }
 782
 783 /**
 784  *  e1000_reset_hw_82575 - Reset hardware
 785  *  @hw: pointer to the HW structure
 786  *
 787  *  This resets the hardware into a known state.  This is a
 788  *  function pointer entry point called by the api module.
 789  **/
 790 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
 791 {
 792         u32 ctrl, icr;
 793         s32 ret_val;
 794
 795         /*
 796          * Prevent the PCI-E bus from sticking if there is no TLP connection
 797          * on the last TLP read/write transaction when MAC is reset.
 798          */
 799         ret_val = igb_disable_pcie_master(hw);
 800         if (ret_val)
 801                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 802
 803         hw_dbg(hw, "Masking off all interrupts\n");
 804         wr32(E1000_IMC, 0xffffffff);
 805
 806         wr32(E1000_RCTL, 0);
 807         wr32(E1000_TCTL, E1000_TCTL_PSP);
 808         wrfl();
 809
 810         msleep(10);
 811
 812         ctrl = rd32(E1000_CTRL);
 813
 814         hw_dbg(hw, "Issuing a global reset to MAC\n");
 815         wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
 816
 817         ret_val = igb_get_auto_rd_done(hw);
 818         if (ret_val) {
 819                 /*
 820                  * When auto config read does not complete, do not
 821                  * return with an error. This can happen in situations
 822                  * where there is no eeprom and prevents getting link.
 823                  */
 824                 hw_dbg(hw, "Auto Read Done did not complete\n");
 825         }
 826
 827         /* If EEPROM is not present, run manual init scripts */
 828         if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
 829                 igb_reset_init_script_82575(hw);
 830
 831         /* Clear any pending interrupt events. */
 832         wr32(E1000_IMC, 0xffffffff);
 833         icr = rd32(E1000_ICR);
 834
 835         igb_check_alt_mac_addr(hw);
 836
 837         return ret_val;
 838 }
 839
 840 /**
 841  *  e1000_init_hw_82575 - Initialize hardware
 842  *  @hw: pointer to the HW structure
 843  *
 844  *  This inits the hardware readying it for operation.
 845  **/
 846 static s32 igb_init_hw_82575(struct e1000_hw *hw)
 847 {
 848         struct e1000_mac_info *mac = &hw->mac;
 849         s32 ret_val;
 850         u16 i, rar_count = mac->rar_entry_count;
 851
 852         /* Initialize identification LED */
 853         ret_val = igb_id_led_init(hw);
 854         if (ret_val) {
 855                 hw_dbg(hw, "Error initializing identification LED\n");
 856                 /* This is not fatal and we should not stop init due to this */
 857         }
 858
 859         /* Disabling VLAN filtering */
 860         hw_dbg(hw, "Initializing the IEEE VLAN\n");
 861         igb_clear_vfta(hw);
 862
 863         /* Setup the receive address */
 864         igb_init_rx_addrs(hw, rar_count);
 865         /* Zero out the Multicast HASH table */
 866         hw_dbg(hw, "Zeroing the MTA\n");
 867         for (i = 0; i < mac->mta_reg_count; i++)
 868                 array_wr32(E1000_MTA, i, 0);
 869
 870         /* Setup link and flow control */
 871         ret_val = igb_setup_link(hw);
 872
 873         /*
 874          * Clear all of the statistics registers (clear on read).  It is
 875          * important that we do this after we have tried to establish link
 876          * because the symbol error count will increment wildly if there
 877          * is no link.
 878          */
 879         igb_clear_hw_cntrs_82575(hw);
 880
 881         return ret_val;
 882 }
 883
 884 /**
 885  *  e1000_setup_copper_link_82575 - Configure copper link settings
 886  *  @hw: pointer to the HW structure
 887  *
 888  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
 889  *  for link, once link is established calls to configure collision distance
 890  *  and flow control are called.
 891  **/
 892 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
 893 {
 894         u32 ctrl, led_ctrl;
 895         s32  ret_val;
 896         bool link;
 897
 898         ctrl = rd32(E1000_CTRL);
 899         ctrl |= E1000_CTRL_SLU;
 900         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 901         wr32(E1000_CTRL, ctrl);
 902
 903         switch (hw->phy.type) {
 904         case e1000_phy_m88:
 905                 ret_val = igb_copper_link_setup_m88(hw);
 906                 break;
 907         case e1000_phy_igp_3:
 908                 ret_val = igb_copper_link_setup_igp(hw);
 909                 /* Setup activity LED */
 910                 led_ctrl = rd32(E1000_LEDCTL);
 911                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
 912                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 913                 wr32(E1000_LEDCTL, led_ctrl);
 914                 break;
 915         default:
 916                 ret_val = -E1000_ERR_PHY;
 917                 break;
 918         }
 919
 920         if (ret_val)
 921                 goto out;
 922
 923         if (hw->mac.autoneg) {
 924                 /*
 925                  * Setup autoneg and flow control advertisement
 926                  * and perform autonegotiation.
 927                  */
 928                 ret_val = igb_copper_link_autoneg(hw);
 929                 if (ret_val)
 930                         goto out;
 931         } else {
 932                 /*
 933                  * PHY will be set to 10H, 10F, 100H or 100F
 934                  * depending on user settings.
 935                  */
 936                 hw_dbg(hw, "Forcing Speed and Duplex\n");
 937                 ret_val = igb_phy_force_speed_duplex(hw);
 938                 if (ret_val) {
 939                         hw_dbg(hw, "Error Forcing Speed and Duplex\n");
 940                         goto out;
 941                 }
 942         }
 943
 944         ret_val = igb_configure_pcs_link_82575(hw);
 945         if (ret_val)
 946                 goto out;
 947
 948         /*
 949          * Check link status. Wait up to 100 microseconds for link to become
 950          * valid.
 951          */
 952         ret_val = igb_phy_has_link(hw,
 953                                              COPPER_LINK_UP_LIMIT,
 954                                              10,
 955                                              &link);
 956         if (ret_val)
 957                 goto out;
 958
 959         if (link) {
 960                 hw_dbg(hw, "Valid link established!!!\n");
 961                 /* Config the MAC and PHY after link is up */
 962                 igb_config_collision_dist(hw);
 963                 ret_val = igb_config_fc_after_link_up(hw);
 964         } else {
 965                 hw_dbg(hw, "Unable to establish link!!!\n");
 966         }
 967
 968 out:
 969         return ret_val;
 970 }
 971
 972 /**
 973  *  e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
 974  *  @hw: pointer to the HW structure
 975  *
 976  *  Configures speed and duplex for fiber and serdes links.
 977  **/
 978 static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
 979 {
 980         u32 reg;
 981
 982         /*
 983          * On the 82575, SerDes loopback mode persists until it is
 984          * explicitly turned off or a power cycle is performed.  A read to
 985          * the register does not indicate its status.  Therefore, we ensure
 986          * loopback mode is disabled during initialization.
 987          */
 988         wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
 989
 990         /* Force link up, set 1gb, set both sw defined pins */
 991         reg = rd32(E1000_CTRL);
 992         reg |= E1000_CTRL_SLU |
 993                E1000_CTRL_SPD_1000 |
 994                E1000_CTRL_FRCSPD |
 995                E1000_CTRL_SWDPIN0 |
 996                E1000_CTRL_SWDPIN1;
 997         wr32(E1000_CTRL, reg);
 998
 999         /* Set switch control to serdes energy detect */
1000         reg = rd32(E1000_CONNSW);
1001         reg |= E1000_CONNSW_ENRGSRC;
1002         wr32(E1000_CONNSW, reg);
1003
1004         /*
1005          * New SerDes mode allows for forcing speed or autonegotiating speed
1006          * at 1gb. Autoneg should be default set by most drivers. This is the
1007          * mode that will be compatible with older link partners and switches.
1008          * However, both are supported by the hardware and some drivers/tools.
1009          */
1010         reg = rd32(E1000_PCS_LCTL);
1011
1012         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1013                 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1014
1015         if (hw->mac.autoneg) {
1016                 /* Set PCS register for autoneg */
1017                 reg |= E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1018                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1019                        E1000_PCS_LCTL_AN_ENABLE |     /* Enable Autoneg */
1020                        E1000_PCS_LCTL_AN_RESTART;     /* Restart autoneg */
1021                 hw_dbg(hw, "Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1022         } else {
1023                 /* Set PCS register for forced speed */
1024                 reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1025                        E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1026                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1027                        E1000_PCS_LCTL_FSD |           /* Force Speed */
1028                        E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1029                 hw_dbg(hw, "Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1030         }
1031         wr32(E1000_PCS_LCTL, reg);
1032
1033         return 0;
1034 }
1035
1036 /**
1037  *  e1000_configure_pcs_link_82575 - Configure PCS link
1038  *  @hw: pointer to the HW structure
1039  *
1040  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1041  *  only used on copper connections where the serialized gigabit media
1042  *  independent interface (sgmii) is being used.  Configures the link
1043  *  for auto-negotiation or forces speed/duplex.
1044  **/
1045 static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw)
1046 {
1047         struct e1000_mac_info *mac = &hw->mac;
1048         u32 reg = 0;
1049
1050         if (hw->phy.media_type != e1000_media_type_copper ||
1051             !(igb_sgmii_active_82575(hw)))
1052                 goto out;
1053
1054         /* For SGMII, we need to issue a PCS autoneg restart */
1055         reg = rd32(E1000_PCS_LCTL);
1056
1057         /* AN time out should be disabled for SGMII mode */
1058         reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1059
1060         if (mac->autoneg) {
1061                 /* Make sure forced speed and force link are not set */
1062                 reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1063
1064                 /*
1065                  * The PHY should be setup prior to calling this function.
1066                  * All we need to do is restart autoneg and enable autoneg.
1067                  */
1068                 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
1069         } else {
1070                 /* Set PCS regiseter for forced speed */
1071
1072                 /* Turn off bits for full duplex, speed, and autoneg */
1073                 reg &= ~(E1000_PCS_LCTL_FSV_1000 |
1074                          E1000_PCS_LCTL_FSV_100 |
1075                          E1000_PCS_LCTL_FDV_FULL |
1076                          E1000_PCS_LCTL_AN_ENABLE);
1077
1078                 /* Check for duplex first */
1079                 if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
1080                         reg |= E1000_PCS_LCTL_FDV_FULL;
1081
1082                 /* Now set speed */
1083                 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED)
1084                         reg |= E1000_PCS_LCTL_FSV_100;
1085
1086                 /* Force speed and force link */
1087                 reg |= E1000_PCS_LCTL_FSD |
1088                        E1000_PCS_LCTL_FORCE_LINK |
1089                        E1000_PCS_LCTL_FLV_LINK_UP;
1090
1091                 hw_dbg(hw,
1092                        "Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1093                        reg);
1094         }
1095         wr32(E1000_PCS_LCTL, reg);
1096
1097 out:
1098         return 0;
1099 }
1100
1101 /**
1102  *  e1000_sgmii_active_82575 - Return sgmii state
1103  *  @hw: pointer to the HW structure
1104  *
1105  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1106  *  which can be enabled for use in the embedded applications.  Simply
1107  *  return the current state of the sgmii interface.
1108  **/
1109 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1110 {
1111         struct e1000_dev_spec_82575 *dev_spec;
1112         bool ret_val;
1113
1114         if (hw->mac.type != e1000_82575) {
1115                 ret_val = false;
1116                 goto out;
1117         }
1118
1119         dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
1120
1121         ret_val = dev_spec->sgmii_active;
1122
1123 out:
1124         return ret_val;
1125 }
1126
1127 /**
1128  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1129  *  @hw: pointer to the HW structure
1130  *
1131  *  Inits recommended HW defaults after a reset when there is no EEPROM
1132  *  detected. This is only for the 82575.
1133  **/
1134 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1135 {
1136         if (hw->mac.type == e1000_82575) {
1137                 hw_dbg(hw, "Running reset init script for 82575\n");
1138                 /* SerDes configuration via SERDESCTRL */
1139                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1140                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1141                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1142                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1143
1144                 /* CCM configuration via CCMCTL register */
1145                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1146                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1147
1148                 /* PCIe lanes configuration */
1149                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1150                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1151                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1152                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1153
1154                 /* PCIe PLL Configuration */
1155                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1156                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1157                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1158         }
1159
1160         return 0;
1161 }
1162
1163 /**
1164  *  e1000_read_mac_addr_82575 - Read device MAC address
1165  *  @hw: pointer to the HW structure
1166  **/
1167 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1168 {
1169         s32 ret_val = 0;
1170
1171         if (igb_check_alt_mac_addr(hw))
1172                 ret_val = igb_read_mac_addr(hw);
1173
1174         return ret_val;
1175 }
1176
1177 /**
1178  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1179  *  @hw: pointer to the HW structure
1180  *
1181  *  Clears the hardware counters by reading the counter registers.
1182  **/
1183 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1184 {
1185         u32 temp;
1186
1187         igb_clear_hw_cntrs_base(hw);
1188
1189         temp = rd32(E1000_PRC64);
1190         temp = rd32(E1000_PRC127);
1191         temp = rd32(E1000_PRC255);
1192         temp = rd32(E1000_PRC511);
1193         temp = rd32(E1000_PRC1023);
1194         temp = rd32(E1000_PRC1522);
1195         temp = rd32(E1000_PTC64);
1196         temp = rd32(E1000_PTC127);
1197         temp = rd32(E1000_PTC255);
1198         temp = rd32(E1000_PTC511);
1199         temp = rd32(E1000_PTC1023);
1200         temp = rd32(E1000_PTC1522);
1201
1202         temp = rd32(E1000_ALGNERRC);
1203         temp = rd32(E1000_RXERRC);
1204         temp = rd32(E1000_TNCRS);
1205         temp = rd32(E1000_CEXTERR);
1206         temp = rd32(E1000_TSCTC);
1207         temp = rd32(E1000_TSCTFC);
1208
1209         temp = rd32(E1000_MGTPRC);
1210         temp = rd32(E1000_MGTPDC);
1211         temp = rd32(E1000_MGTPTC);
1212
1213         temp = rd32(E1000_IAC);
1214         temp = rd32(E1000_ICRXOC);
1215
1216         temp = rd32(E1000_ICRXPTC);
1217         temp = rd32(E1000_ICRXATC);
1218         temp = rd32(E1000_ICTXPTC);
1219         temp = rd32(E1000_ICTXATC);
1220         temp = rd32(E1000_ICTXQEC);
1221         temp = rd32(E1000_ICTXQMTC);
1222         temp = rd32(E1000_ICRXDMTC);
1223
1224         temp = rd32(E1000_CBTMPC);
1225         temp = rd32(E1000_HTDPMC);
1226         temp = rd32(E1000_CBRMPC);
1227         temp = rd32(E1000_RPTHC);
1228         temp = rd32(E1000_HGPTC);
1229         temp = rd32(E1000_HTCBDPC);
1230         temp = rd32(E1000_HGORCL);
1231         temp = rd32(E1000_HGORCH);
1232         temp = rd32(E1000_HGOTCL);
1233         temp = rd32(E1000_HGOTCH);
1234         temp = rd32(E1000_LENERRS);
1235
1236         /* This register should not be read in copper configurations */
1237         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1238                 temp = rd32(E1000_SCVPC);
1239 }
1240
1241 static struct e1000_mac_operations e1000_mac_ops_82575 = {
1242         .reset_hw             = igb_reset_hw_82575,
1243         .init_hw              = igb_init_hw_82575,
1244         .check_for_link       = igb_check_for_link_82575,
1245         .rar_set              = igb_rar_set_82575,
1246         .read_mac_addr        = igb_read_mac_addr_82575,
1247         .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1248 };
1249
1250 static struct e1000_phy_operations e1000_phy_ops_82575 = {
1251         .acquire_phy          = igb_acquire_phy_82575,
1252         .get_cfg_done         = igb_get_cfg_done_82575,
1253         .release_phy          = igb_release_phy_82575,
1254 };
1255
1256 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
1257         .acquire_nvm          = igb_acquire_nvm_82575,
1258         .read_nvm             = igb_read_nvm_eerd,
1259         .release_nvm          = igb_release_nvm_82575,
1260         .write_nvm            = igb_write_nvm_spi,
1261 };
1262
1263 const struct e1000_info e1000_82575_info = {
1264         .get_invariants = igb_get_invariants_82575,
1265         .mac_ops = &e1000_mac_ops_82575,
1266         .phy_ops = &e1000_phy_ops_82575,
1267         .nvm_ops = &e1000_nvm_ops_82575,
1268 };
1269