2 * arch/ppc/platforms/4xx/sycamore.h
4 * Macros, definitions, and data structures specific to the IBM PowerPC
5 * 405GPr "Sycamore" evaluation board.
7 * Author: Armin Kuster <akuster@mvista.com>
9 * 2000 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
16 #ifndef __ASM_SYCAMORE_H__
17 #define __ASM_SYCAMORE_H__
19 #include <platforms/4xx/ibm405gpr.h>
23 * Data structure defining board information maintained by the boot
24 * ROM on IBM's "Sycamore" evaluation board. An effort has been made to
25 * keep the field names consistent with the 8xx 'bd_t' board info
29 typedef struct board_info {
30 unsigned char bi_s_version[4]; /* Version of this structure */
31 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
32 unsigned int bi_memsize; /* DRAM installed, in bytes */
33 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
34 unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
35 unsigned int bi_intfreq; /* Processor speed, in Hz */
36 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
37 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
40 /* Some 4xx parts use a different timebase frequency from the internal clock.
42 #define bi_tbfreq bi_intfreq
45 /* Memory map for the IBM "Sycamore" 405GP evaluation board.
46 * Generic 4xx plus RTC.
49 extern void *sycamore_rtc_base;
50 #define SYCAMORE_RTC_PADDR ((uint)0xf0000000)
51 #define SYCAMORE_RTC_VADDR SYCAMORE_RTC_PADDR
52 #define SYCAMORE_RTC_SIZE ((uint)8*1024)
54 #ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
55 #define BASE_BAUD 201600
57 #define BASE_BAUD 691200
60 #define SYCAMORE_PS2_BASE 0xF0100000
61 #define SYCAMORE_FPGA_BASE 0xF0300000
63 #define PPC4xx_MACHINE_NAME "IBM Sycamore"
65 #endif /* !__ASSEMBLY__ */
66 #endif /* __ASM_SYCAMORE_H__ */
67 #endif /* __KERNEL__ */