git.oblomov.eu Git - linux-2.6/blob - drivers/ssb/driver_chipcommon.c

   1 /*
   2  * Sonics Silicon Backplane
   3  * Broadcom ChipCommon core driver
   4  *
   5  * Copyright 2005, Broadcom Corporation
   6  * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include <linux/ssb/ssb.h>
  12 #include <linux/ssb/ssb_regs.h>
  13 #include <linux/pci.h>
  14
  15 #include "ssb_private.h"
  16
  17
  18 /* Clock sources */
  19 enum ssb_clksrc {
  20         /* PCI clock */
  21         SSB_CHIPCO_CLKSRC_PCI,
  22         /* Crystal slow clock oscillator */
  23         SSB_CHIPCO_CLKSRC_XTALOS,
  24         /* Low power oscillator */
  25         SSB_CHIPCO_CLKSRC_LOPWROS,
  26 };
  27
  28
  29 static inline u32 chipco_read32(struct ssb_chipcommon *cc,
  30                                 u16 offset)
  31 {
  32         return ssb_read32(cc->dev, offset);
  33 }
  34
  35 static inline void chipco_write32(struct ssb_chipcommon *cc,
  36                                   u16 offset,
  37                                   u32 value)
  38 {
  39         ssb_write32(cc->dev, offset, value);
  40 }
  41
  42 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
  43                                         u32 mask, u32 value)
  44 {
  45         value &= mask;
  46         value |= chipco_read32(cc, offset) & ~mask;
  47         chipco_write32(cc, offset, value);
  48
  49         return value;
  50 }
  51
  52 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
  53                               enum ssb_clkmode mode)
  54 {
  55         struct ssb_device *ccdev = cc->dev;
  56         struct ssb_bus *bus;
  57         u32 tmp;
  58
  59         if (!ccdev)
  60                 return;
  61         bus = ccdev->bus;
  62         /* chipcommon cores prior to rev6 don't support dynamic clock control */
  63         if (ccdev->id.revision < 6)
  64                 return;
  65         /* chipcommon cores rev10 are a whole new ball game */
  66         if (ccdev->id.revision >= 10)
  67                 return;
  68         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
  69                 return;
  70
  71         switch (mode) {
  72         case SSB_CLKMODE_SLOW:
  73                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
  74                 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
  75                 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
  76                 break;
  77         case SSB_CLKMODE_FAST:
  78                 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
  79                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
  80                 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
  81                 tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
  82                 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
  83                 break;
  84         case SSB_CLKMODE_DYNAMIC:
  85                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
  86                 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
  87                 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
  88                 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
  89                 if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
  90                         tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
  91                 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
  92
  93                 /* for dynamic control, we have to release our xtal_pu "force on" */
  94                 if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
  95                         ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
  96                 break;
  97         default:
  98                 SSB_WARN_ON(1);
  99         }
 100 }
 101
 102 /* Get the Slow Clock Source */
 103 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
 104 {
 105         struct ssb_bus *bus = cc->dev->bus;
 106         u32 uninitialized_var(tmp);
 107
 108         if (cc->dev->id.revision < 6) {
 109                 if (bus->bustype == SSB_BUSTYPE_SSB ||
 110                     bus->bustype == SSB_BUSTYPE_PCMCIA)
 111                         return SSB_CHIPCO_CLKSRC_XTALOS;
 112                 if (bus->bustype == SSB_BUSTYPE_PCI) {
 113                         pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
 114                         if (tmp & 0x10)
 115                                 return SSB_CHIPCO_CLKSRC_PCI;
 116                         return SSB_CHIPCO_CLKSRC_XTALOS;
 117                 }
 118         }
 119         if (cc->dev->id.revision < 10) {
 120                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
 121                 tmp &= 0x7;
 122                 if (tmp == 0)
 123                         return SSB_CHIPCO_CLKSRC_LOPWROS;
 124                 if (tmp == 1)
 125                         return SSB_CHIPCO_CLKSRC_XTALOS;
 126                 if (tmp == 2)
 127                         return SSB_CHIPCO_CLKSRC_PCI;
 128         }
 129
 130         return SSB_CHIPCO_CLKSRC_XTALOS;
 131 }
 132
 133 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
 134 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
 135 {
 136         int uninitialized_var(limit);
 137         enum ssb_clksrc clocksrc;
 138         int divisor = 1;
 139         u32 tmp;
 140
 141         clocksrc = chipco_pctl_get_slowclksrc(cc);
 142         if (cc->dev->id.revision < 6) {
 143                 switch (clocksrc) {
 144                 case SSB_CHIPCO_CLKSRC_PCI:
 145                         divisor = 64;
 146                         break;
 147                 case SSB_CHIPCO_CLKSRC_XTALOS:
 148                         divisor = 32;
 149                         break;
 150                 default:
 151                         SSB_WARN_ON(1);
 152                 }
 153         } else if (cc->dev->id.revision < 10) {
 154                 switch (clocksrc) {
 155                 case SSB_CHIPCO_CLKSRC_LOPWROS:
 156                         break;
 157                 case SSB_CHIPCO_CLKSRC_XTALOS:
 158                 case SSB_CHIPCO_CLKSRC_PCI:
 159                         tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
 160                         divisor = (tmp >> 16) + 1;
 161                         divisor *= 4;
 162                         break;
 163                 }
 164         } else {
 165                 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
 166                 divisor = (tmp >> 16) + 1;
 167                 divisor *= 4;
 168         }
 169
 170         switch (clocksrc) {
 171         case SSB_CHIPCO_CLKSRC_LOPWROS:
 172                 if (get_max)
 173                         limit = 43000;
 174                 else
 175                         limit = 25000;
 176                 break;
 177         case SSB_CHIPCO_CLKSRC_XTALOS:
 178                 if (get_max)
 179                         limit = 20200000;
 180                 else
 181                         limit = 19800000;
 182                 break;
 183         case SSB_CHIPCO_CLKSRC_PCI:
 184                 if (get_max)
 185                         limit = 34000000;
 186                 else
 187                         limit = 25000000;
 188                 break;
 189         }
 190         limit /= divisor;
 191
 192         return limit;
 193 }
 194
 195 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
 196 {
 197         struct ssb_bus *bus = cc->dev->bus;
 198
 199         if (bus->chip_id == 0x4321) {
 200                 if (bus->chip_rev == 0)
 201                         chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
 202                 else if (bus->chip_rev == 1)
 203                         chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
 204         }
 205
 206         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
 207                 return;
 208
 209         if (cc->dev->id.revision >= 10) {
 210                 /* Set Idle Power clock rate to 1Mhz */
 211                 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
 212                                (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
 213                                 0x0000FFFF) | 0x00040000);
 214         } else {
 215                 int maxfreq;
 216
 217                 maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
 218                 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
 219                                (maxfreq * 150 + 999999) / 1000000);
 220                 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
 221                                (maxfreq * 15 + 999999) / 1000000);
 222         }
 223 }
 224
 225 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
 226 {
 227         struct ssb_bus *bus = cc->dev->bus;
 228         int minfreq;
 229         unsigned int tmp;
 230         u32 pll_on_delay;
 231
 232         if (bus->bustype != SSB_BUSTYPE_PCI)
 233                 return;
 234         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
 235                 return;
 236
 237         minfreq = chipco_pctl_clockfreqlimit(cc, 0);
 238         pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
 239         tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
 240         SSB_WARN_ON(tmp & ~0xFFFF);
 241
 242         cc->fast_pwrup_delay = tmp;
 243 }
 244
 245 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
 246 {
 247         if (!cc->dev)
 248                 return; /* We don't have a ChipCommon */
 249         chipco_powercontrol_init(cc);
 250         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 251         calc_fast_powerup_delay(cc);
 252 }
 253
 254 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
 255 {
 256         if (!cc->dev)
 257                 return;
 258         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
 259 }
 260
 261 void ssb_chipco_resume(struct ssb_chipcommon *cc)
 262 {
 263         if (!cc->dev)
 264                 return;
 265         chipco_powercontrol_init(cc);
 266         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 267 }
 268
 269 /* Get the processor clock */
 270 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
 271                              u32 *plltype, u32 *n, u32 *m)
 272 {
 273         *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
 274         *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
 275         switch (*plltype) {
 276         case SSB_PLLTYPE_2:
 277         case SSB_PLLTYPE_4:
 278         case SSB_PLLTYPE_6:
 279         case SSB_PLLTYPE_7:
 280                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
 281                 break;
 282         case SSB_PLLTYPE_3:
 283                 /* 5350 uses m2 to control mips */
 284                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
 285                 break;
 286         default:
 287                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
 288                 break;
 289         }
 290 }
 291
 292 /* Get the bus clock */
 293 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
 294                                  u32 *plltype, u32 *n, u32 *m)
 295 {
 296         *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
 297         *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
 298         switch (*plltype) {
 299         case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
 300                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
 301                 break;
 302         case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
 303                 if (cc->dev->bus->chip_id != 0x5365) {
 304                         *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
 305                         break;
 306                 }
 307                 /* Fallthough */
 308         default:
 309                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
 310         }
 311 }
 312
 313 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
 314                             unsigned long ns)
 315 {
 316         struct ssb_device *dev = cc->dev;
 317         struct ssb_bus *bus = dev->bus;
 318         u32 tmp;
 319
 320         /* set register for external IO to control LED. */
 321         chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
 322         tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;            /* Waitcount-3 = 10ns */
 323         tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT;   /* Waitcount-1 = 40ns */
 324         tmp |= DIV_ROUND_UP(240, ns);                           /* Waitcount-0 = 240ns */
 325         chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp);       /* 0x01020a0c for a 100Mhz clock */
 326
 327         /* Set timing for the flash */
 328         tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT;   /* Waitcount-3 = 10nS */
 329         tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT;  /* Waitcount-1 = 10nS */
 330         tmp |= DIV_ROUND_UP(120, ns);                           /* Waitcount-0 = 120nS */
 331         if ((bus->chip_id == 0x5365) ||
 332             (dev->id.revision < 9))
 333                 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
 334         if ((bus->chip_id == 0x5365) ||
 335             (dev->id.revision < 9) ||
 336             ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
 337                 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
 338
 339         if (bus->chip_id == 0x5350) {
 340                 /* Enable EXTIF */
 341                 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;      /* Waitcount-3 = 10ns */
 342                 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT;  /* Waitcount-2 = 20ns */
 343                 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
 344                 tmp |= DIV_ROUND_UP(120, ns);                     /* Waitcount-0 = 120ns */
 345                 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
 346         }
 347 }
 348
 349 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
 350 void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 351 {
 352         /* instant NMI */
 353         chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 354 }
 355
 356 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 357 {
 358         chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
 359 }
 360
 361 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
 362 {
 363         return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
 364 }
 365
 366 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
 367 {
 368         return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
 369 }
 370
 371 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
 372 {
 373         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
 374 }
 375
 376 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
 377 {
 378         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
 379 }
 380
 381 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
 382 {
 383         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
 384 }
 385
 386 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 387 {
 388         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
 389 }
 390
 391 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
 392 {
 393         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
 394 }
 395
 396 #ifdef CONFIG_SSB_SERIAL
 397 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
 398                            struct ssb_serial_port *ports)
 399 {
 400         struct ssb_bus *bus = cc->dev->bus;
 401         int nr_ports = 0;
 402         u32 plltype;
 403         unsigned int irq;
 404         u32 baud_base, div;
 405         u32 i, n;
 406         unsigned int ccrev = cc->dev->id.revision;
 407
 408         plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
 409         irq = ssb_mips_irq(cc->dev);
 410
 411         if (plltype == SSB_PLLTYPE_1) {
 412                 /* PLL clock */
 413                 baud_base = ssb_calc_clock_rate(plltype,
 414                                                 chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
 415                                                 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
 416                 div = 1;
 417         } else {
 418                 if (ccrev == 20) {
 419                         /* BCM5354 uses constant 25MHz clock */
 420                         baud_base = 25000000;
 421                         div = 48;
 422                         /* Set the override bit so we don't divide it */
 423                         chipco_write32(cc, SSB_CHIPCO_CORECTL,
 424                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
 425                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
 426                 } else if ((ccrev >= 11) && (ccrev != 15)) {
 427                         /* Fixed ALP clock */
 428                         baud_base = 20000000;
 429                         if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 430                                 /* FIXME: baud_base is different for devices with a PMU */
 431                                 SSB_WARN_ON(1);
 432                         }
 433                         div = 1;
 434                         if (ccrev >= 21) {
 435                                 /* Turn off UART clock before switching clocksource. */
 436                                 chipco_write32(cc, SSB_CHIPCO_CORECTL,
 437                                                chipco_read32(cc, SSB_CHIPCO_CORECTL)
 438                                                & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
 439                         }
 440                         /* Set the override bit so we don't divide it */
 441                         chipco_write32(cc, SSB_CHIPCO_CORECTL,
 442                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
 443                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
 444                         if (ccrev >= 21) {
 445                                 /* Re-enable the UART clock. */
 446                                 chipco_write32(cc, SSB_CHIPCO_CORECTL,
 447                                                chipco_read32(cc, SSB_CHIPCO_CORECTL)
 448                                                | SSB_CHIPCO_CORECTL_UARTCLKEN);
 449                         }
 450                 } else if (ccrev >= 3) {
 451                         /* Internal backplane clock */
 452                         baud_base = ssb_clockspeed(bus);
 453                         div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
 454                               & SSB_CHIPCO_CLKDIV_UART;
 455                 } else {
 456                         /* Fixed internal backplane clock */
 457                         baud_base = 88000000;
 458                         div = 48;
 459                 }
 460
 461                 /* Clock source depends on strapping if UartClkOverride is unset */
 462                 if ((ccrev > 0) &&
 463                     !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
 464                         if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
 465                             SSB_CHIPCO_CAP_UARTCLK_INT) {
 466                                 /* Internal divided backplane clock */
 467                                 baud_base /= div;
 468                         } else {
 469                                 /* Assume external clock of 1.8432 MHz */
 470                                 baud_base = 1843200;
 471                         }
 472                 }
 473         }
 474
 475         /* Determine the registers of the UARTs */
 476         n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
 477         for (i = 0; i < n; i++) {
 478                 void __iomem *cc_mmio;
 479                 void __iomem *uart_regs;
 480
 481                 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
 482                 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
 483                 /* Offset changed at after rev 0 */
 484                 if (ccrev == 0)
 485                         uart_regs += (i * 8);
 486                 else
 487                         uart_regs += (i * 256);
 488
 489                 nr_ports++;
 490                 ports[i].regs = uart_regs;
 491                 ports[i].irq = irq;
 492                 ports[i].baud_base = baud_base;
 493                 ports[i].reg_shift = 0;
 494         }
 495
 496         return nr_ports;
 497 }
 498 #endif /* CONFIG_SSB_SERIAL */