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   1 /*
   2     comedi/drivers/gsc_hpdi.c
   3     This is a driver for the General Standards Corporation High
   4     Speed Parallel Digital Interface rs485 boards.
   5
   6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7     Copyright (C) 2003 Coherent Imaging Systems
   8
   9     COMEDI - Linux Control and Measurement Device Interface
  10     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  11
  12     This program is free software; you can redistribute it and/or modify
  13     it under the terms of the GNU General Public License as published by
  14     the Free Software Foundation; either version 2 of the License, or
  15     (at your option) any later version.
  16
  17     This program is distributed in the hope that it will be useful,
  18     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20     GNU General Public License for more details.
  21
  22     You should have received a copy of the GNU General Public License
  23     along with this program; if not, write to the Free Software
  24     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25
  26 ************************************************************************/
  27
  28 /*
  29
  30 Driver: gsc_hpdi
  31 Description: General Standards Corporation High
  32     Speed Parallel Digital Interface rs485 boards
  33 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  34 Status: only receive mode works, transmit not supported
  35 Updated: 2003-02-20
  36 Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
  37   PMC-HPDI32
  38
  39 Configuration options:
  40    [0] - PCI bus of device (optional)
  41    [1] - PCI slot of device (optional)
  42
  43 There are some additional hpdi models available from GSC for which
  44 support could be added to this driver.
  45
  46 */
  47
  48 #include "../comedidev.h"
  49 #include <linux/delay.h>
  50
  51 #include "comedi_pci.h"
  52 #include "plx9080.h"
  53 #include "comedi_fc.h"
  54
  55 static int hpdi_attach(struct comedi_device * dev, struct comedi_devconfig * it);
  56 static int hpdi_detach(struct comedi_device * dev);
  57 void abort_dma(struct comedi_device * dev, unsigned int channel);
  58 static int hpdi_cmd(struct comedi_device * dev, struct comedi_subdevice * s);
  59 static int hpdi_cmd_test(struct comedi_device * dev, struct comedi_subdevice * s,
  60         struct comedi_cmd * cmd);
  61 static int hpdi_cancel(struct comedi_device * dev, struct comedi_subdevice * s);
  62 static irqreturn_t handle_interrupt(int irq, void *d PT_REGS_ARG);
  63 static int dio_config_block_size(struct comedi_device * dev, unsigned int * data);
  64
  65 #undef HPDI_DEBUG               // disable debugging messages
  66 //#define HPDI_DEBUG    // enable debugging code
  67
  68 #ifdef HPDI_DEBUG
  69 #define DEBUG_PRINT(format, args...)  rt_printk(format , ## args )
  70 #else
  71 #define DEBUG_PRINT(format, args...)
  72 #endif
  73
  74 #define TIMER_BASE 50           // 20MHz master clock
  75 #define DMA_BUFFER_SIZE 0x10000
  76 #define NUM_DMA_BUFFERS 4
  77 #define NUM_DMA_DESCRIPTORS 256
  78
  79 // indices of base address regions
  80 enum base_address_regions {
  81         PLX9080_BADDRINDEX = 0,
  82         HPDI_BADDRINDEX = 2,
  83 };
  84
  85 enum hpdi_registers {
  86         FIRMWARE_REV_REG = 0x0,
  87         BOARD_CONTROL_REG = 0x4,
  88         BOARD_STATUS_REG = 0x8,
  89         TX_PROG_ALMOST_REG = 0xc,
  90         RX_PROG_ALMOST_REG = 0x10,
  91         FEATURES_REG = 0x14,
  92         FIFO_REG = 0x18,
  93         TX_STATUS_COUNT_REG = 0x1c,
  94         TX_LINE_VALID_COUNT_REG = 0x20,
  95         TX_LINE_INVALID_COUNT_REG = 0x24,
  96         RX_STATUS_COUNT_REG = 0x28,
  97         RX_LINE_COUNT_REG = 0x2c,
  98         INTERRUPT_CONTROL_REG = 0x30,
  99         INTERRUPT_STATUS_REG = 0x34,
 100         TX_CLOCK_DIVIDER_REG = 0x38,
 101         TX_FIFO_SIZE_REG = 0x40,
 102         RX_FIFO_SIZE_REG = 0x44,
 103         TX_FIFO_WORDS_REG = 0x48,
 104         RX_FIFO_WORDS_REG = 0x4c,
 105         INTERRUPT_EDGE_LEVEL_REG = 0x50,
 106         INTERRUPT_POLARITY_REG = 0x54,
 107 };
 108
 109 int command_channel_valid(unsigned int channel)
 110 {
 111         if (channel == 0 || channel > 6) {
 112                 rt_printk("gsc_hpdi: bug! invalid cable command channel\n");
 113                 return 0;
 114         }
 115         return 1;
 116 }
 117
 118 // bit definitions
 119
 120 enum firmware_revision_bits {
 121         FEATURES_REG_PRESENT_BIT = 0x8000,
 122 };
 123 int firmware_revision(uint32_t fwr_bits)
 124 {
 125         return fwr_bits & 0xff;
 126 }
 127
 128 int pcb_revision(uint32_t fwr_bits)
 129 {
 130         return (fwr_bits >> 8) & 0xff;
 131 }
 132
 133 int hpdi_subid(uint32_t fwr_bits)
 134 {
 135         return (fwr_bits >> 16) & 0xff;
 136 }
 137
 138 enum board_control_bits {
 139         BOARD_RESET_BIT = 0x1,  /* wait 10usec before accessing fifos */
 140         TX_FIFO_RESET_BIT = 0x2,
 141         RX_FIFO_RESET_BIT = 0x4,
 142         TX_ENABLE_BIT = 0x10,
 143         RX_ENABLE_BIT = 0x20,
 144         DEMAND_DMA_DIRECTION_TX_BIT = 0x40,     /* for channel 0, channel 1 can only transmit (when present) */
 145         LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
 146         START_TX_BIT = 0x10,
 147         CABLE_THROTTLE_ENABLE_BIT = 0x20,
 148         TEST_MODE_ENABLE_BIT = 0x80000000,
 149 };
 150 uint32_t command_discrete_output_bits(unsigned int channel, int output,
 151         int output_value)
 152 {
 153         uint32_t bits = 0;
 154
 155         if (command_channel_valid(channel) == 0)
 156                 return 0;
 157         if (output) {
 158                 bits |= 0x1 << (16 + channel);
 159                 if (output_value)
 160                         bits |= 0x1 << (24 + channel);
 161         } else
 162                 bits |= 0x1 << (24 + channel);
 163
 164         return bits;
 165 }
 166
 167 enum board_status_bits {
 168         COMMAND_LINE_STATUS_MASK = 0x7f,
 169         TX_IN_PROGRESS_BIT = 0x80,
 170         TX_NOT_EMPTY_BIT = 0x100,
 171         TX_NOT_ALMOST_EMPTY_BIT = 0x200,
 172         TX_NOT_ALMOST_FULL_BIT = 0x400,
 173         TX_NOT_FULL_BIT = 0x800,
 174         RX_NOT_EMPTY_BIT = 0x1000,
 175         RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
 176         RX_NOT_ALMOST_FULL_BIT = 0x4000,
 177         RX_NOT_FULL_BIT = 0x8000,
 178         BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
 179         BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
 180         TX_OVERRUN_BIT = 0x200000,
 181         RX_UNDERRUN_BIT = 0x400000,
 182         RX_OVERRUN_BIT = 0x800000,
 183 };
 184
 185 uint32_t almost_full_bits(unsigned int num_words)
 186 {
 187 // XXX need to add or subtract one?
 188         return (num_words << 16) & 0xff0000;
 189 }
 190
 191 uint32_t almost_empty_bits(unsigned int num_words)
 192 {
 193         return num_words & 0xffff;
 194 }
 195 unsigned int almost_full_num_words(uint32_t bits)
 196 {
 197 // XXX need to add or subtract one?
 198         return (bits >> 16) & 0xffff;
 199 }
 200 unsigned int almost_empty_num_words(uint32_t bits)
 201 {
 202         return bits & 0xffff;
 203 }
 204
 205 enum features_bits {
 206         FIFO_SIZE_PRESENT_BIT = 0x1,
 207         FIFO_WORDS_PRESENT_BIT = 0x2,
 208         LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
 209         GPIO_SUPPORTED_BIT = 0x8,
 210         PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
 211         OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
 212 };
 213
 214 enum interrupt_sources {
 215         FRAME_VALID_START_INTR = 0,
 216         FRAME_VALID_END_INTR = 1,
 217         TX_FIFO_EMPTY_INTR = 8,
 218         TX_FIFO_ALMOST_EMPTY_INTR = 9,
 219         TX_FIFO_ALMOST_FULL_INTR = 10,
 220         TX_FIFO_FULL_INTR = 11,
 221         RX_EMPTY_INTR = 12,
 222         RX_ALMOST_EMPTY_INTR = 13,
 223         RX_ALMOST_FULL_INTR = 14,
 224         RX_FULL_INTR = 15,
 225 };
 226 int command_intr_source(unsigned int channel)
 227 {
 228         if (command_channel_valid(channel) == 0)
 229                 channel = 1;
 230         return channel + 1;
 231 }
 232
 233 uint32_t intr_bit(int interrupt_source)
 234 {
 235         return 0x1 << interrupt_source;
 236 }
 237
 238 uint32_t tx_clock_divisor_bits(unsigned int divisor)
 239 {
 240         return divisor & 0xff;
 241 }
 242
 243 unsigned int fifo_size(uint32_t fifo_size_bits)
 244 {
 245         return fifo_size_bits & 0xfffff;
 246 }
 247
 248 unsigned int fifo_words(uint32_t fifo_words_bits)
 249 {
 250         return fifo_words_bits & 0xfffff;
 251 }
 252
 253 uint32_t intr_edge_bit(int interrupt_source)
 254 {
 255         return 0x1 << interrupt_source;
 256 }
 257
 258 uint32_t intr_active_high_bit(int interrupt_source)
 259 {
 260         return 0x1 << interrupt_source;
 261 }
 262
 263 struct hpdi_board {
 264
 265         char *name;
 266         int device_id;          // pci device id
 267         int subdevice_id;       // pci subdevice id
 268 };
 269
 270
 271 static const struct hpdi_board hpdi_boards[] = {
 272         {
 273               name:     "pci-hpdi32",
 274               device_id:PCI_DEVICE_ID_PLX_9080,
 275               subdevice_id:0x2400,
 276                 },
 277 #if 0
 278         {
 279               name:     "pxi-hpdi32",
 280               device_id:0x9656,
 281               subdevice_id:0x2705,
 282                 },
 283 #endif
 284 };
 285
 286 static inline unsigned int num_boards(void)
 287 {
 288         return sizeof(hpdi_boards) / sizeof(struct hpdi_board);
 289 }
 290
 291 static DEFINE_PCI_DEVICE_TABLE(hpdi_pci_table) = {
 292         {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX, 0x2400,
 293                 0, 0, 0},
 294         {0}
 295 };
 296
 297 MODULE_DEVICE_TABLE(pci, hpdi_pci_table);
 298
 299 static inline struct hpdi_board *board(const struct comedi_device * dev)
 300 {
 301         return (struct hpdi_board *) dev->board_ptr;
 302 }
 303
 304 typedef struct {
 305         struct pci_dev *hw_dev; // pointer to board's pci_dev struct
 306         // base addresses (physical)
 307         resource_size_t plx9080_phys_iobase;
 308         resource_size_t hpdi_phys_iobase;
 309         // base addresses (ioremapped)
 310         void *plx9080_iobase;
 311         void *hpdi_iobase;
 312         uint32_t *dio_buffer[NUM_DMA_BUFFERS];  // dma buffers
 313         dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];       // physical addresses of dma buffers
 314         struct plx_dma_desc *dma_desc;  // array of dma descriptors read by plx9080, allocated to get proper alignment
 315         dma_addr_t dma_desc_phys_addr;  // physical address of dma descriptor array
 316         unsigned int num_dma_descriptors;
 317         uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS]; // pointer to start of buffers indexed by descriptor
 318         volatile unsigned int dma_desc_index;   // index of the dma descriptor that is currently being used
 319         unsigned int tx_fifo_size;
 320         unsigned int rx_fifo_size;
 321         volatile unsigned long dio_count;
 322         volatile uint32_t bits[24];     // software copies of values written to hpdi registers
 323         volatile unsigned int block_size;       // number of bytes at which to generate COMEDI_CB_BLOCK events
 324         unsigned dio_config_output:1;
 325 } hpdi_private;
 326
 327 static inline hpdi_private *priv(struct comedi_device * dev)
 328 {
 329         return dev->private;
 330 }
 331
 332 static struct comedi_driver driver_hpdi = {
 333       driver_name:"gsc_hpdi",
 334       module:THIS_MODULE,
 335       attach:hpdi_attach,
 336       detach:hpdi_detach,
 337 };
 338
 339 COMEDI_PCI_INITCLEANUP(driver_hpdi, hpdi_pci_table);
 340
 341 static int dio_config_insn(struct comedi_device * dev, struct comedi_subdevice * s,
 342         struct comedi_insn * insn, unsigned int * data)
 343 {
 344         switch (data[0]) {
 345         case INSN_CONFIG_DIO_OUTPUT:
 346                 priv(dev)->dio_config_output = 1;
 347                 return insn->n;
 348                 break;
 349         case INSN_CONFIG_DIO_INPUT:
 350                 priv(dev)->dio_config_output = 0;
 351                 return insn->n;
 352                 break;
 353         case INSN_CONFIG_DIO_QUERY:
 354                 data[1] =
 355                         priv(dev)->
 356                         dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT;
 357                 return insn->n;
 358                 break;
 359         case INSN_CONFIG_BLOCK_SIZE:
 360                 return dio_config_block_size(dev, data);
 361                 break;
 362         default:
 363                 break;
 364         }
 365
 366         return -EINVAL;
 367 }
 368
 369 static void disable_plx_interrupts(struct comedi_device * dev)
 370 {
 371         writel(0, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
 372 }
 373
 374 // initialize plx9080 chip
 375 static void init_plx9080(struct comedi_device * dev)
 376 {
 377         uint32_t bits;
 378         void *plx_iobase = priv(dev)->plx9080_iobase;
 379
 380         // plx9080 dump
 381         DEBUG_PRINT(" plx interrupt status 0x%x\n",
 382                 readl(plx_iobase + PLX_INTRCS_REG));
 383         DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
 384         DEBUG_PRINT(" plx control reg 0x%x\n",
 385                 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG));
 386
 387         DEBUG_PRINT(" plx revision 0x%x\n",
 388                 readl(plx_iobase + PLX_REVISION_REG));
 389         DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
 390                 readl(plx_iobase + PLX_DMA0_MODE_REG));
 391         DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
 392                 readl(plx_iobase + PLX_DMA1_MODE_REG));
 393         DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
 394                 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
 395         DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
 396                 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
 397         DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
 398                 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
 399         DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
 400                 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
 401         DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
 402                 readb(plx_iobase + PLX_DMA0_CS_REG));
 403         DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
 404                 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
 405         DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
 406 #ifdef __BIG_ENDIAN
 407         bits = BIGEND_DMA0 | BIGEND_DMA1;
 408 #else
 409         bits = 0;
 410 #endif
 411         writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
 412
 413         disable_plx_interrupts(dev);
 414
 415         abort_dma(dev, 0);
 416         abort_dma(dev, 1);
 417
 418         // configure dma0 mode
 419         bits = 0;
 420         // enable ready input
 421         bits |= PLX_DMA_EN_READYIN_BIT;
 422         // enable dma chaining
 423         bits |= PLX_EN_CHAIN_BIT;
 424         // enable interrupt on dma done (probably don't need this, since chain never finishes)
 425         bits |= PLX_EN_DMA_DONE_INTR_BIT;
 426         // don't increment local address during transfers (we are transferring from a fixed fifo register)
 427         bits |= PLX_LOCAL_ADDR_CONST_BIT;
 428         // route dma interrupt to pci bus
 429         bits |= PLX_DMA_INTR_PCI_BIT;
 430         // enable demand mode
 431         bits |= PLX_DEMAND_MODE_BIT;
 432         // enable local burst mode
 433         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
 434         bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
 435         writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
 436 }
 437
 438 /* Allocate and initialize the subdevice structures.
 439  */
 440 static int setup_subdevices(struct comedi_device * dev)
 441 {
 442         struct comedi_subdevice *s;
 443
 444         if (alloc_subdevices(dev, 1) < 0)
 445                 return -ENOMEM;
 446
 447         s = dev->subdevices + 0;
 448         /* analog input subdevice */
 449         dev->read_subdev = s;
 450 /*      dev->write_subdev = s; */
 451         s->type = COMEDI_SUBD_DIO;
 452         s->subdev_flags =
 453                 SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ;
 454         s->n_chan = 32;
 455         s->len_chanlist = 32;
 456         s->maxdata = 1;
 457         s->range_table = &range_digital;
 458         s->insn_config = dio_config_insn;
 459         s->do_cmd = hpdi_cmd;
 460         s->do_cmdtest = hpdi_cmd_test;
 461         s->cancel = hpdi_cancel;
 462
 463         return 0;
 464 }
 465
 466 static int init_hpdi(struct comedi_device * dev)
 467 {
 468         uint32_t plx_intcsr_bits;
 469
 470         writel(BOARD_RESET_BIT, priv(dev)->hpdi_iobase + BOARD_CONTROL_REG);
 471         comedi_udelay(10);
 472
 473         writel(almost_empty_bits(32) | almost_full_bits(32),
 474                 priv(dev)->hpdi_iobase + RX_PROG_ALMOST_REG);
 475         writel(almost_empty_bits(32) | almost_full_bits(32),
 476                 priv(dev)->hpdi_iobase + TX_PROG_ALMOST_REG);
 477
 478         priv(dev)->tx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
 479                         TX_FIFO_SIZE_REG));
 480         priv(dev)->rx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
 481                         RX_FIFO_SIZE_REG));
 482
 483         writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
 484
 485         // enable interrupts
 486         plx_intcsr_bits =
 487                 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
 488                 ICS_DMA0_E;
 489         writel(plx_intcsr_bits, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
 490
 491         return 0;
 492 }
 493
 494 // setup dma descriptors so a link completes every 'transfer_size' bytes
 495 static int setup_dma_descriptors(struct comedi_device * dev,
 496         unsigned int transfer_size)
 497 {
 498         unsigned int buffer_index, buffer_offset;
 499         uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
 500                 PLX_XFER_LOCAL_TO_PCI;
 501         unsigned int i;
 502
 503         if (transfer_size > DMA_BUFFER_SIZE)
 504                 transfer_size = DMA_BUFFER_SIZE;
 505         transfer_size -= transfer_size % sizeof(uint32_t);
 506         if (transfer_size == 0)
 507                 return -1;
 508
 509         DEBUG_PRINT(" transfer_size %i\n", transfer_size);
 510         DEBUG_PRINT(" descriptors at 0x%lx\n",
 511                 (unsigned long)priv(dev)->dma_desc_phys_addr);
 512
 513         buffer_offset = 0;
 514         buffer_index = 0;
 515         for (i = 0; i < NUM_DMA_DESCRIPTORS &&
 516                 buffer_index < NUM_DMA_BUFFERS; i++) {
 517                 priv(dev)->dma_desc[i].pci_start_addr =
 518                         cpu_to_le32(priv(dev)->
 519                         dio_buffer_phys_addr[buffer_index] + buffer_offset);
 520                 priv(dev)->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
 521                 priv(dev)->dma_desc[i].transfer_size =
 522                         cpu_to_le32(transfer_size);
 523                 priv(dev)->dma_desc[i].next =
 524                         cpu_to_le32((priv(dev)->dma_desc_phys_addr + (i +
 525                                         1) *
 526                                 sizeof(priv(dev)->dma_desc[0])) | next_bits);
 527
 528                 priv(dev)->desc_dio_buffer[i] =
 529                         priv(dev)->dio_buffer[buffer_index] +
 530                         (buffer_offset / sizeof(uint32_t));
 531
 532                 buffer_offset += transfer_size;
 533                 if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) {
 534                         buffer_offset = 0;
 535                         buffer_index++;
 536                 }
 537
 538                 DEBUG_PRINT(" desc %i\n", i);
 539                 DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n",
 540                         priv(dev)->desc_dio_buffer[i],
 541                         (unsigned long)priv(dev)->dma_desc[i].pci_start_addr);
 542                 DEBUG_PRINT(" next 0x%lx\n",
 543                         (unsigned long)priv(dev)->dma_desc[i].next);
 544         }
 545         priv(dev)->num_dma_descriptors = i;
 546         // fix last descriptor to point back to first
 547         priv(dev)->dma_desc[i - 1].next =
 548                 cpu_to_le32(priv(dev)->dma_desc_phys_addr | next_bits);
 549         DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1,
 550                 (unsigned long)priv(dev)->dma_desc[i - 1].next);
 551
 552         priv(dev)->block_size = transfer_size;
 553
 554         return transfer_size;
 555 }
 556
 557 static int hpdi_attach(struct comedi_device * dev, struct comedi_devconfig * it)
 558 {
 559         struct pci_dev *pcidev;
 560         int i;
 561         int retval;
 562
 563         printk("comedi%d: gsc_hpdi\n", dev->minor);
 564
 565         if (alloc_private(dev, sizeof(hpdi_private)) < 0)
 566                 return -ENOMEM;
 567
 568         pcidev = NULL;
 569         for (i = 0; i < num_boards() && dev->board_ptr == NULL; i++) {
 570                 do {
 571                         pcidev = pci_get_subsys(PCI_VENDOR_ID_PLX,
 572                                 hpdi_boards[i].device_id, PCI_VENDOR_ID_PLX,
 573                                 hpdi_boards[i].subdevice_id, pcidev);
 574                         // was a particular bus/slot requested?
 575                         if (it->options[0] || it->options[1]) {
 576                                 // are we on the wrong bus/slot?
 577                                 if (pcidev->bus->number != it->options[0] ||
 578                                         PCI_SLOT(pcidev->devfn) !=
 579                                         it->options[1])
 580                                         continue;
 581                         }
 582                         if (pcidev) {
 583                                 priv(dev)->hw_dev = pcidev;
 584                                 dev->board_ptr = hpdi_boards + i;
 585                                 break;
 586                         }
 587                 } while (pcidev != NULL);
 588         }
 589         if (dev->board_ptr == NULL) {
 590                 printk("gsc_hpdi: no hpdi card found\n");
 591                 return -EIO;
 592         }
 593
 594         printk("gsc_hpdi: found %s on bus %i, slot %i\n", board(dev)->name,
 595                 pcidev->bus->number, PCI_SLOT(pcidev->devfn));
 596
 597         if (comedi_pci_enable(pcidev, driver_hpdi.driver_name)) {
 598                 printk(KERN_WARNING
 599                         " failed enable PCI device and request regions\n");
 600                 return -EIO;
 601         }
 602         pci_set_master(pcidev);
 603
 604         //Initialize dev->board_name
 605         dev->board_name = board(dev)->name;
 606
 607         priv(dev)->plx9080_phys_iobase =
 608                 pci_resource_start(pcidev, PLX9080_BADDRINDEX);
 609         priv(dev)->hpdi_phys_iobase =
 610                 pci_resource_start(pcidev, HPDI_BADDRINDEX);
 611
 612         // remap, won't work with 2.0 kernels but who cares
 613         priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
 614                 pci_resource_len(pcidev, PLX9080_BADDRINDEX));
 615         priv(dev)->hpdi_iobase = ioremap(priv(dev)->hpdi_phys_iobase,
 616                 pci_resource_len(pcidev, HPDI_BADDRINDEX));
 617         if (!priv(dev)->plx9080_iobase || !priv(dev)->hpdi_iobase) {
 618                 printk(" failed to remap io memory\n");
 619                 return -ENOMEM;
 620         }
 621
 622         DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
 623         DEBUG_PRINT(" hpdi remapped to 0x%p\n", priv(dev)->hpdi_iobase);
 624
 625         init_plx9080(dev);
 626
 627         // get irq
 628         if (comedi_request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
 629                         driver_hpdi.driver_name, dev)) {
 630                 printk(" unable to allocate irq %u\n", pcidev->irq);
 631                 return -EINVAL;
 632         }
 633         dev->irq = pcidev->irq;
 634
 635         printk(" irq %u\n", dev->irq);
 636
 637         // alocate pci dma buffers
 638         for (i = 0; i < NUM_DMA_BUFFERS; i++) {
 639                 priv(dev)->dio_buffer[i] =
 640                         pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE,
 641                         &priv(dev)->dio_buffer_phys_addr[i]);
 642                 DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n",
 643                         priv(dev)->dio_buffer[i],
 644                         (unsigned long)priv(dev)->dio_buffer_phys_addr[i]);
 645         }
 646         // allocate dma descriptors
 647         priv(dev)->dma_desc = pci_alloc_consistent(priv(dev)->hw_dev,
 648                 sizeof(struct plx_dma_desc) * NUM_DMA_DESCRIPTORS,
 649                 &priv(dev)->dma_desc_phys_addr);
 650         if (priv(dev)->dma_desc_phys_addr & 0xf) {
 651                 printk(" dma descriptors not quad-word aligned (bug)\n");
 652                 return -EIO;
 653         }
 654
 655         retval = setup_dma_descriptors(dev, 0x1000);
 656         if (retval < 0)
 657                 return retval;
 658
 659         retval = setup_subdevices(dev);
 660         if (retval < 0)
 661                 return retval;
 662
 663         return init_hpdi(dev);
 664 }
 665
 666 static int hpdi_detach(struct comedi_device * dev)
 667 {
 668         unsigned int i;
 669
 670         printk("comedi%d: gsc_hpdi: remove\n", dev->minor);
 671
 672         if (dev->irq)
 673                 comedi_free_irq(dev->irq, dev);
 674         if (priv(dev)) {
 675                 if (priv(dev)->hw_dev) {
 676                         if (priv(dev)->plx9080_iobase) {
 677                                 disable_plx_interrupts(dev);
 678                                 iounmap((void *)priv(dev)->plx9080_iobase);
 679                         }
 680                         if (priv(dev)->hpdi_iobase)
 681                                 iounmap((void *)priv(dev)->hpdi_iobase);
 682                         // free pci dma buffers
 683                         for (i = 0; i < NUM_DMA_BUFFERS; i++) {
 684                                 if (priv(dev)->dio_buffer[i])
 685                                         pci_free_consistent(priv(dev)->hw_dev,
 686                                                 DMA_BUFFER_SIZE,
 687                                                 priv(dev)->dio_buffer[i],
 688                                                 priv(dev)->
 689                                                 dio_buffer_phys_addr[i]);
 690                         }
 691                         // free dma descriptors
 692                         if (priv(dev)->dma_desc)
 693                                 pci_free_consistent(priv(dev)->hw_dev,
 694                                         sizeof(struct plx_dma_desc) *
 695                                         NUM_DMA_DESCRIPTORS,
 696                                         priv(dev)->dma_desc,
 697                                         priv(dev)->dma_desc_phys_addr);
 698                         if (priv(dev)->hpdi_phys_iobase) {
 699                                 comedi_pci_disable(priv(dev)->hw_dev);
 700                         }
 701                         pci_dev_put(priv(dev)->hw_dev);
 702                 }
 703         }
 704         return 0;
 705 }
 706
 707 static int dio_config_block_size(struct comedi_device * dev, unsigned int * data)
 708 {
 709         unsigned int requested_block_size;
 710         int retval;
 711
 712         requested_block_size = data[1];
 713
 714         retval = setup_dma_descriptors(dev, requested_block_size);
 715         if (retval < 0)
 716                 return retval;
 717
 718         data[1] = retval;
 719
 720         return 2;
 721 }
 722
 723 static int di_cmd_test(struct comedi_device * dev, struct comedi_subdevice * s,
 724         struct comedi_cmd * cmd)
 725 {
 726         int err = 0;
 727         int tmp;
 728         int i;
 729
 730         /* step 1: make sure trigger sources are trivially valid */
 731
 732         tmp = cmd->start_src;
 733         cmd->start_src &= TRIG_NOW;
 734         if (!cmd->start_src || tmp != cmd->start_src)
 735                 err++;
 736
 737         tmp = cmd->scan_begin_src;
 738         cmd->scan_begin_src &= TRIG_EXT;
 739         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
 740                 err++;
 741
 742         tmp = cmd->convert_src;
 743         cmd->convert_src &= TRIG_NOW;
 744         if (!cmd->convert_src || tmp != cmd->convert_src)
 745                 err++;
 746
 747         tmp = cmd->scan_end_src;
 748         cmd->scan_end_src &= TRIG_COUNT;
 749         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
 750                 err++;
 751
 752         tmp = cmd->stop_src;
 753         cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
 754         if (!cmd->stop_src || tmp != cmd->stop_src)
 755                 err++;
 756
 757         if (err)
 758                 return 1;
 759
 760         /* step 2: make sure trigger sources are unique and mutually compatible */
 761
 762         // uniqueness check
 763         if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
 764                 err++;
 765
 766         if (err)
 767                 return 2;
 768
 769         /* step 3: make sure arguments are trivially compatible */
 770
 771         if (!cmd->chanlist_len) {
 772                 cmd->chanlist_len = 32;
 773                 err++;
 774         }
 775         if (cmd->scan_end_arg != cmd->chanlist_len) {
 776                 cmd->scan_end_arg = cmd->chanlist_len;
 777                 err++;
 778         }
 779
 780         switch (cmd->stop_src) {
 781         case TRIG_COUNT:
 782                 if (!cmd->stop_arg) {
 783                         cmd->stop_arg = 1;
 784                         err++;
 785                 }
 786                 break;
 787         case TRIG_NONE:
 788                 if (cmd->stop_arg != 0) {
 789                         cmd->stop_arg = 0;
 790                         err++;
 791                 }
 792                 break;
 793         default:
 794                 break;
 795         }
 796
 797         if (err)
 798                 return 3;
 799
 800         /* step 4: fix up any arguments */
 801
 802         if (err)
 803                 return 4;
 804
 805         if (cmd->chanlist) {
 806                 for (i = 1; i < cmd->chanlist_len; i++) {
 807                         if (CR_CHAN(cmd->chanlist[i]) != i) {
 808                                 // XXX could support 8 channels or 16 channels
 809                                 comedi_error(dev,
 810                                         "chanlist must be channels 0 to 31 in order");
 811                                 err++;
 812                                 break;
 813                         }
 814                 }
 815         }
 816
 817         if (err)
 818                 return 5;
 819
 820         return 0;
 821 }
 822
 823 static int hpdi_cmd_test(struct comedi_device * dev, struct comedi_subdevice * s,
 824         struct comedi_cmd * cmd)
 825 {
 826         if (priv(dev)->dio_config_output) {
 827                 return -EINVAL;
 828         } else
 829                 return di_cmd_test(dev, s, cmd);
 830 }
 831
 832 static inline void hpdi_writel(struct comedi_device * dev, uint32_t bits,
 833         unsigned int offset)
 834 {
 835         writel(bits | priv(dev)->bits[offset / sizeof(uint32_t)],
 836                 priv(dev)->hpdi_iobase + offset);
 837 }
 838
 839 static int di_cmd(struct comedi_device * dev, struct comedi_subdevice * s)
 840 {
 841         uint32_t bits;
 842         unsigned long flags;
 843         struct comedi_async *async = s->async;
 844         struct comedi_cmd *cmd = &async->cmd;
 845
 846         hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
 847
 848         DEBUG_PRINT("hpdi: in di_cmd\n");
 849
 850         abort_dma(dev, 0);
 851
 852         priv(dev)->dma_desc_index = 0;
 853
 854         /* These register are supposedly unused during chained dma,
 855          * but I have found that left over values from last operation
 856          * occasionally cause problems with transfer of first dma
 857          * block.  Initializing them to zero seems to fix the problem. */
 858         writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
 859         writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
 860         writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
 861         // give location of first dma descriptor
 862         bits = priv(dev)->
 863                 dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
 864                 PLX_XFER_LOCAL_TO_PCI;
 865         writel(bits, priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
 866
 867         // spinlock for plx dma control/status reg
 868         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 869         // enable dma transfer
 870         writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
 871                 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
 872         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 873
 874         if (cmd->stop_src == TRIG_COUNT)
 875                 priv(dev)->dio_count = cmd->stop_arg;
 876         else
 877                 priv(dev)->dio_count = 1;
 878
 879         // clear over/under run status flags
 880         writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
 881                 priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
 882         // enable interrupts
 883         writel(intr_bit(RX_FULL_INTR),
 884                 priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
 885
 886         DEBUG_PRINT("hpdi: starting rx\n");
 887         hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
 888
 889         return 0;
 890 }
 891
 892 static int hpdi_cmd(struct comedi_device * dev, struct comedi_subdevice * s)
 893 {
 894         if (priv(dev)->dio_config_output) {
 895                 return -EINVAL;
 896         } else
 897                 return di_cmd(dev, s);
 898 }
 899
 900 static void drain_dma_buffers(struct comedi_device * dev, unsigned int channel)
 901 {
 902         struct comedi_async *async = dev->read_subdev->async;
 903         uint32_t next_transfer_addr;
 904         int j;
 905         int num_samples = 0;
 906         void *pci_addr_reg;
 907
 908         if (channel)
 909                 pci_addr_reg =
 910                         priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
 911         else
 912                 pci_addr_reg =
 913                         priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
 914
 915         // loop until we have read all the full buffers
 916         j = 0;
 917         for (next_transfer_addr = readl(pci_addr_reg);
 918                 (next_transfer_addr <
 919                         le32_to_cpu(priv(dev)->dma_desc[priv(dev)->
 920                                         dma_desc_index].pci_start_addr)
 921                         || next_transfer_addr >=
 922                         le32_to_cpu(priv(dev)->dma_desc[priv(dev)->
 923                                         dma_desc_index].pci_start_addr) +
 924                         priv(dev)->block_size)
 925                 && j < priv(dev)->num_dma_descriptors; j++) {
 926                 // transfer data from dma buffer to comedi buffer
 927                 num_samples = priv(dev)->block_size / sizeof(uint32_t);
 928                 if (async->cmd.stop_src == TRIG_COUNT) {
 929                         if (num_samples > priv(dev)->dio_count)
 930                                 num_samples = priv(dev)->dio_count;
 931                         priv(dev)->dio_count -= num_samples;
 932                 }
 933                 cfc_write_array_to_buffer(dev->read_subdev,
 934                         priv(dev)->desc_dio_buffer[priv(dev)->dma_desc_index],
 935                         num_samples * sizeof(uint32_t));
 936                 priv(dev)->dma_desc_index++;
 937                 priv(dev)->dma_desc_index %= priv(dev)->num_dma_descriptors;
 938
 939                 DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long)
 940                         priv(dev)->dma_desc[priv(dev)->dma_desc_index].next);
 941                 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
 942         }
 943         // XXX check for buffer overrun somehow
 944 }
 945
 946 static irqreturn_t handle_interrupt(int irq, void *d PT_REGS_ARG)
 947 {
 948         struct comedi_device *dev = d;
 949         struct comedi_subdevice *s = dev->read_subdev;
 950         struct comedi_async *async = s->async;
 951         uint32_t hpdi_intr_status, hpdi_board_status;
 952         uint32_t plx_status;
 953         uint32_t plx_bits;
 954         uint8_t dma0_status, dma1_status;
 955         unsigned long flags;
 956
 957         if (!dev->attached) {
 958                 return IRQ_NONE;
 959         }
 960
 961         plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
 962         if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0) {
 963                 return IRQ_NONE;
 964         }
 965
 966         hpdi_intr_status = readl(priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
 967         hpdi_board_status = readl(priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
 968
 969         async->events = 0;
 970
 971         if (hpdi_intr_status) {
 972                 DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status);
 973                 writel(hpdi_intr_status,
 974                         priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
 975         }
 976         // spin lock makes sure noone else changes plx dma control reg
 977         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 978         dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
 979         if (plx_status & ICS_DMA0_A) {  // dma chan 0 interrupt
 980                 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
 981                         priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
 982
 983                 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
 984                 if (dma0_status & PLX_DMA_EN_BIT) {
 985                         drain_dma_buffers(dev, 0);
 986                 }
 987                 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
 988         }
 989         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 990
 991         // spin lock makes sure noone else changes plx dma control reg
 992         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 993         dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
 994         if (plx_status & ICS_DMA1_A)    // XXX
 995         {                       // dma chan 1 interrupt
 996                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
 997                         priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
 998                 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
 999
1000                 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
1001         }
1002         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1003
1004         // clear possible plx9080 interrupt sources
1005         if (plx_status & ICS_LDIA) {    // clear local doorbell interrupt
1006                 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
1007                 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
1008                 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
1009         }
1010
1011         if (hpdi_board_status & RX_OVERRUN_BIT) {
1012                 comedi_error(dev, "rx fifo overrun");
1013                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1014                 DEBUG_PRINT("dma0_status 0x%x\n",
1015                         (int)readb(priv(dev)->plx9080_iobase +
1016                                 PLX_DMA0_CS_REG));
1017         }
1018
1019         if (hpdi_board_status & RX_UNDERRUN_BIT) {
1020                 comedi_error(dev, "rx fifo underrun");
1021                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1022         }
1023
1024         if (priv(dev)->dio_count == 0)
1025                 async->events |= COMEDI_CB_EOA;
1026
1027         DEBUG_PRINT("board status 0x%x, ", hpdi_board_status);
1028         DEBUG_PRINT("plx status 0x%x\n", plx_status);
1029         if (async->events)
1030                 DEBUG_PRINT(" events 0x%x\n", async->events);
1031
1032         cfc_handle_events(dev, s);
1033
1034         return IRQ_HANDLED;
1035 }
1036
1037 void abort_dma(struct comedi_device * dev, unsigned int channel)
1038 {
1039         unsigned long flags;
1040
1041         // spinlock for plx dma control/status reg
1042         comedi_spin_lock_irqsave(&dev->spinlock, flags);
1043
1044         plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
1045
1046         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1047 }
1048
1049 static int hpdi_cancel(struct comedi_device * dev, struct comedi_subdevice * s)
1050 {
1051         hpdi_writel(dev, 0, BOARD_CONTROL_REG);
1052
1053         writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
1054
1055         abort_dma(dev, 0);
1056
1057         return 0;
1058 }