git.oblomov.eu Git - linux-2.6/blob - drivers/i2c/busses/i2c-s3c2410.c

   1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
   2  *
   3  * Copyright (C) 2004,2005 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 I2C Controller
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25
  26 #include <linux/i2c.h>
  27 #include <linux/i2c-id.h>
  28 #include <linux/init.h>
  29 #include <linux/time.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/delay.h>
  32 #include <linux/errno.h>
  33 #include <linux/err.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/clk.h>
  36 #include <linux/cpufreq.h>
  37
  38 #include <mach/hardware.h>
  39 #include <asm/irq.h>
  40 #include <asm/io.h>
  41
  42 #include <mach/regs-gpio.h>
  43 #include <asm/plat-s3c/regs-iic.h>
  44 #include <asm/plat-s3c/iic.h>
  45
  46 /* i2c controller state */
  47
  48 enum s3c24xx_i2c_state {
  49         STATE_IDLE,
  50         STATE_START,
  51         STATE_READ,
  52         STATE_WRITE,
  53         STATE_STOP
  54 };
  55
  56 struct s3c24xx_i2c {
  57         spinlock_t              lock;
  58         wait_queue_head_t       wait;
  59
  60         struct i2c_msg          *msg;
  61         unsigned int            msg_num;
  62         unsigned int            msg_idx;
  63         unsigned int            msg_ptr;
  64
  65         unsigned int            tx_setup;
  66
  67         enum s3c24xx_i2c_state  state;
  68         unsigned long           clkrate;
  69
  70         void __iomem            *regs;
  71         struct clk              *clk;
  72         struct device           *dev;
  73         struct resource         *irq;
  74         struct resource         *ioarea;
  75         struct i2c_adapter      adap;
  76
  77 #ifdef CONFIG_CPU_FREQ
  78         struct notifier_block   freq_transition;
  79 #endif
  80 };
  81
  82 /* default platform data to use if not supplied in the platform_device
  83 */
  84
  85 static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
  86         .flags          = 0,
  87         .slave_addr     = 0x10,
  88         .bus_freq       = 100*1000,
  89         .max_freq       = 400*1000,
  90         .sda_delay      = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
  91 };
  92
  93 /* s3c24xx_i2c_is2440()
  94  *
  95  * return true is this is an s3c2440
  96 */
  97
  98 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
  99 {
 100         struct platform_device *pdev = to_platform_device(i2c->dev);
 101
 102         return !strcmp(pdev->name, "s3c2440-i2c");
 103 }
 104
 105
 106 /* s3c24xx_i2c_get_platformdata
 107  *
 108  * get the platform data associated with the given device, or return
 109  * the default if there is none
 110 */
 111
 112 static inline struct s3c2410_platform_i2c *
 113 s3c24xx_i2c_get_platformdata(struct device *dev)
 114 {
 115         if (dev->platform_data != NULL)
 116                 return (struct s3c2410_platform_i2c *)dev->platform_data;
 117
 118         return &s3c24xx_i2c_default_platform;
 119 }
 120
 121 /* s3c24xx_i2c_master_complete
 122  *
 123  * complete the message and wake up the caller, using the given return code,
 124  * or zero to mean ok.
 125 */
 126
 127 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 128 {
 129         dev_dbg(i2c->dev, "master_complete %d\n", ret);
 130
 131         i2c->msg_ptr = 0;
 132         i2c->msg = NULL;
 133         i2c->msg_idx++;
 134         i2c->msg_num = 0;
 135         if (ret)
 136                 i2c->msg_idx = ret;
 137
 138         wake_up(&i2c->wait);
 139 }
 140
 141 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 142 {
 143         unsigned long tmp;
 144
 145         tmp = readl(i2c->regs + S3C2410_IICCON);
 146         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 147 }
 148
 149 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 150 {
 151         unsigned long tmp;
 152
 153         tmp = readl(i2c->regs + S3C2410_IICCON);
 154         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 155 }
 156
 157 /* irq enable/disable functions */
 158
 159 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 160 {
 161         unsigned long tmp;
 162
 163         tmp = readl(i2c->regs + S3C2410_IICCON);
 164         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 165 }
 166
 167 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 168 {
 169         unsigned long tmp;
 170
 171         tmp = readl(i2c->regs + S3C2410_IICCON);
 172         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 173 }
 174
 175
 176 /* s3c24xx_i2c_message_start
 177  *
 178  * put the start of a message onto the bus
 179 */
 180
 181 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 182                                       struct i2c_msg *msg)
 183 {
 184         unsigned int addr = (msg->addr & 0x7f) << 1;
 185         unsigned long stat;
 186         unsigned long iiccon;
 187
 188         stat = 0;
 189         stat |=  S3C2410_IICSTAT_TXRXEN;
 190
 191         if (msg->flags & I2C_M_RD) {
 192                 stat |= S3C2410_IICSTAT_MASTER_RX;
 193                 addr |= 1;
 194         } else
 195                 stat |= S3C2410_IICSTAT_MASTER_TX;
 196
 197         if (msg->flags & I2C_M_REV_DIR_ADDR)
 198                 addr ^= 1;
 199
 200         /* todo - check for wether ack wanted or not */
 201         s3c24xx_i2c_enable_ack(i2c);
 202
 203         iiccon = readl(i2c->regs + S3C2410_IICCON);
 204         writel(stat, i2c->regs + S3C2410_IICSTAT);
 205
 206         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
 207         writeb(addr, i2c->regs + S3C2410_IICDS);
 208
 209         /* delay here to ensure the data byte has gotten onto the bus
 210          * before the transaction is started */
 211
 212         ndelay(i2c->tx_setup);
 213
 214         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
 215         writel(iiccon, i2c->regs + S3C2410_IICCON);
 216
 217         stat |= S3C2410_IICSTAT_START;
 218         writel(stat, i2c->regs + S3C2410_IICSTAT);
 219 }
 220
 221 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 222 {
 223         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 224
 225         dev_dbg(i2c->dev, "STOP\n");
 226
 227         /* stop the transfer */
 228         iicstat &= ~S3C2410_IICSTAT_START;
 229         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 230
 231         i2c->state = STATE_STOP;
 232
 233         s3c24xx_i2c_master_complete(i2c, ret);
 234         s3c24xx_i2c_disable_irq(i2c);
 235 }
 236
 237 /* helper functions to determine the current state in the set of
 238  * messages we are sending */
 239
 240 /* is_lastmsg()
 241  *
 242  * returns TRUE if the current message is the last in the set
 243 */
 244
 245 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 246 {
 247         return i2c->msg_idx >= (i2c->msg_num - 1);
 248 }
 249
 250 /* is_msglast
 251  *
 252  * returns TRUE if we this is the last byte in the current message
 253 */
 254
 255 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 256 {
 257         return i2c->msg_ptr == i2c->msg->len-1;
 258 }
 259
 260 /* is_msgend
 261  *
 262  * returns TRUE if we reached the end of the current message
 263 */
 264
 265 static inline int is_msgend(struct s3c24xx_i2c *i2c)
 266 {
 267         return i2c->msg_ptr >= i2c->msg->len;
 268 }
 269
 270 /* i2s_s3c_irq_nextbyte
 271  *
 272  * process an interrupt and work out what to do
 273  */
 274
 275 static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 276 {
 277         unsigned long tmp;
 278         unsigned char byte;
 279         int ret = 0;
 280
 281         switch (i2c->state) {
 282
 283         case STATE_IDLE:
 284                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
 285                 goto out;
 286                 break;
 287
 288         case STATE_STOP:
 289                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
 290                 s3c24xx_i2c_disable_irq(i2c);
 291                 goto out_ack;
 292
 293         case STATE_START:
 294                 /* last thing we did was send a start condition on the
 295                  * bus, or started a new i2c message
 296                  */
 297
 298                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
 299                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 300                         /* ack was not received... */
 301
 302                         dev_dbg(i2c->dev, "ack was not received\n");
 303                         s3c24xx_i2c_stop(i2c, -ENXIO);
 304                         goto out_ack;
 305                 }
 306
 307                 if (i2c->msg->flags & I2C_M_RD)
 308                         i2c->state = STATE_READ;
 309                 else
 310                         i2c->state = STATE_WRITE;
 311
 312                 /* terminate the transfer if there is nothing to do
 313                  * as this is used by the i2c probe to find devices. */
 314
 315                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
 316                         s3c24xx_i2c_stop(i2c, 0);
 317                         goto out_ack;
 318                 }
 319
 320                 if (i2c->state == STATE_READ)
 321                         goto prepare_read;
 322
 323                 /* fall through to the write state, as we will need to
 324                  * send a byte as well */
 325
 326         case STATE_WRITE:
 327                 /* we are writing data to the device... check for the
 328                  * end of the message, and if so, work out what to do
 329                  */
 330
 331                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 332                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
 333                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
 334
 335                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
 336                                 goto out_ack;
 337                         }
 338                 }
 339
 340  retry_write:
 341
 342                 if (!is_msgend(i2c)) {
 343                         byte = i2c->msg->buf[i2c->msg_ptr++];
 344                         writeb(byte, i2c->regs + S3C2410_IICDS);
 345
 346                         /* delay after writing the byte to allow the
 347                          * data setup time on the bus, as writing the
 348                          * data to the register causes the first bit
 349                          * to appear on SDA, and SCL will change as
 350                          * soon as the interrupt is acknowledged */
 351
 352                         ndelay(i2c->tx_setup);
 353
 354                 } else if (!is_lastmsg(i2c)) {
 355                         /* we need to go to the next i2c message */
 356
 357                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
 358
 359                         i2c->msg_ptr = 0;
 360                         i2c->msg_idx++;
 361                         i2c->msg++;
 362
 363                         /* check to see if we need to do another message */
 364                         if (i2c->msg->flags & I2C_M_NOSTART) {
 365
 366                                 if (i2c->msg->flags & I2C_M_RD) {
 367                                         /* cannot do this, the controller
 368                                          * forces us to send a new START
 369                                          * when we change direction */
 370
 371                                         s3c24xx_i2c_stop(i2c, -EINVAL);
 372                                 }
 373
 374                                 goto retry_write;
 375                         } else {
 376                                 /* send the new start */
 377                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
 378                                 i2c->state = STATE_START;
 379                         }
 380
 381                 } else {
 382                         /* send stop */
 383
 384                         s3c24xx_i2c_stop(i2c, 0);
 385                 }
 386                 break;
 387
 388         case STATE_READ:
 389                 /* we have a byte of data in the data register, do
 390                  * something with it, and then work out wether we are
 391                  * going to do any more read/write
 392                  */
 393
 394                 byte = readb(i2c->regs + S3C2410_IICDS);
 395                 i2c->msg->buf[i2c->msg_ptr++] = byte;
 396
 397  prepare_read:
 398                 if (is_msglast(i2c)) {
 399                         /* last byte of buffer */
 400
 401                         if (is_lastmsg(i2c))
 402                                 s3c24xx_i2c_disable_ack(i2c);
 403
 404                 } else if (is_msgend(i2c)) {
 405                         /* ok, we've read the entire buffer, see if there
 406                          * is anything else we need to do */
 407
 408                         if (is_lastmsg(i2c)) {
 409                                 /* last message, send stop and complete */
 410                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
 411
 412                                 s3c24xx_i2c_stop(i2c, 0);
 413                         } else {
 414                                 /* go to the next transfer */
 415                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
 416
 417                                 i2c->msg_ptr = 0;
 418                                 i2c->msg_idx++;
 419                                 i2c->msg++;
 420                         }
 421                 }
 422
 423                 break;
 424         }
 425
 426         /* acknowlegde the IRQ and get back on with the work */
 427
 428  out_ack:
 429         tmp = readl(i2c->regs + S3C2410_IICCON);
 430         tmp &= ~S3C2410_IICCON_IRQPEND;
 431         writel(tmp, i2c->regs + S3C2410_IICCON);
 432  out:
 433         return ret;
 434 }
 435
 436 /* s3c24xx_i2c_irq
 437  *
 438  * top level IRQ servicing routine
 439 */
 440
 441 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
 442 {
 443         struct s3c24xx_i2c *i2c = dev_id;
 444         unsigned long status;
 445         unsigned long tmp;
 446
 447         status = readl(i2c->regs + S3C2410_IICSTAT);
 448
 449         if (status & S3C2410_IICSTAT_ARBITR) {
 450                 /* deal with arbitration loss */
 451                 dev_err(i2c->dev, "deal with arbitration loss\n");
 452         }
 453
 454         if (i2c->state == STATE_IDLE) {
 455                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 456
 457                 tmp = readl(i2c->regs + S3C2410_IICCON);
 458                 tmp &= ~S3C2410_IICCON_IRQPEND;
 459                 writel(tmp, i2c->regs +  S3C2410_IICCON);
 460                 goto out;
 461         }
 462
 463         /* pretty much this leaves us with the fact that we've
 464          * transmitted or received whatever byte we last sent */
 465
 466         i2s_s3c_irq_nextbyte(i2c, status);
 467
 468  out:
 469         return IRQ_HANDLED;
 470 }
 471
 472
 473 /* s3c24xx_i2c_set_master
 474  *
 475  * get the i2c bus for a master transaction
 476 */
 477
 478 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 479 {
 480         unsigned long iicstat;
 481         int timeout = 400;
 482
 483         while (timeout-- > 0) {
 484                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 485
 486                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
 487                         return 0;
 488
 489                 msleep(1);
 490         }
 491
 492         dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n",
 493                 __raw_readl(S3C2410_GPEDAT));
 494
 495         return -ETIMEDOUT;
 496 }
 497
 498 /* s3c24xx_i2c_doxfer
 499  *
 500  * this starts an i2c transfer
 501 */
 502
 503 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 504                               struct i2c_msg *msgs, int num)
 505 {
 506         unsigned long timeout;
 507         int ret;
 508
 509         if (!(readl(i2c->regs + S3C2410_IICCON) & S3C2410_IICCON_IRQEN))
 510                 return -EIO;
 511
 512         ret = s3c24xx_i2c_set_master(i2c);
 513         if (ret != 0) {
 514                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
 515                 ret = -EAGAIN;
 516                 goto out;
 517         }
 518
 519         spin_lock_irq(&i2c->lock);
 520
 521         i2c->msg     = msgs;
 522         i2c->msg_num = num;
 523         i2c->msg_ptr = 0;
 524         i2c->msg_idx = 0;
 525         i2c->state   = STATE_START;
 526
 527         s3c24xx_i2c_enable_irq(i2c);
 528         s3c24xx_i2c_message_start(i2c, msgs);
 529         spin_unlock_irq(&i2c->lock);
 530
 531         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 532
 533         ret = i2c->msg_idx;
 534
 535         /* having these next two as dev_err() makes life very
 536          * noisy when doing an i2cdetect */
 537
 538         if (timeout == 0)
 539                 dev_dbg(i2c->dev, "timeout\n");
 540         else if (ret != num)
 541                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 542
 543         /* ensure the stop has been through the bus */
 544
 545         msleep(1);
 546
 547  out:
 548         return ret;
 549 }
 550
 551 /* s3c24xx_i2c_xfer
 552  *
 553  * first port of call from the i2c bus code when an message needs
 554  * transferring across the i2c bus.
 555 */
 556
 557 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
 558                         struct i2c_msg *msgs, int num)
 559 {
 560         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
 561         int retry;
 562         int ret;
 563
 564         for (retry = 0; retry < adap->retries; retry++) {
 565
 566                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 567
 568                 if (ret != -EAGAIN)
 569                         return ret;
 570
 571                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
 572
 573                 udelay(100);
 574         }
 575
 576         return -EREMOTEIO;
 577 }
 578
 579 /* declare our i2c functionality */
 580 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
 581 {
 582         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 583 }
 584
 585 /* i2c bus registration info */
 586
 587 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
 588         .master_xfer            = s3c24xx_i2c_xfer,
 589         .functionality          = s3c24xx_i2c_func,
 590 };
 591
 592 static struct s3c24xx_i2c s3c24xx_i2c = {
 593         .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock),
 594         .wait           = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
 595         .tx_setup       = 50,
 596         .adap           = {
 597                 .name                   = "s3c2410-i2c",
 598                 .owner                  = THIS_MODULE,
 599                 .algo                   = &s3c24xx_i2c_algorithm,
 600                 .retries                = 2,
 601                 .class                  = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 602         },
 603 };
 604
 605 /* s3c24xx_i2c_calcdivisor
 606  *
 607  * return the divisor settings for a given frequency
 608 */
 609
 610 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
 611                                    unsigned int *div1, unsigned int *divs)
 612 {
 613         unsigned int calc_divs = clkin / wanted;
 614         unsigned int calc_div1;
 615
 616         if (calc_divs > (16*16))
 617                 calc_div1 = 512;
 618         else
 619                 calc_div1 = 16;
 620
 621         calc_divs += calc_div1-1;
 622         calc_divs /= calc_div1;
 623
 624         if (calc_divs == 0)
 625                 calc_divs = 1;
 626         if (calc_divs > 17)
 627                 calc_divs = 17;
 628
 629         *divs = calc_divs;
 630         *div1 = calc_div1;
 631
 632         return clkin / (calc_divs * calc_div1);
 633 }
 634
 635 /* freq_acceptable
 636  *
 637  * test wether a frequency is within the acceptable range of error
 638 */
 639
 640 static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
 641 {
 642         int diff = freq - wanted;
 643
 644         return diff >= -2 && diff <= 2;
 645 }
 646
 647 /* s3c24xx_i2c_clockrate
 648  *
 649  * work out a divisor for the user requested frequency setting,
 650  * either by the requested frequency, or scanning the acceptable
 651  * range of frequencies until something is found
 652 */
 653
 654 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 655 {
 656         struct s3c2410_platform_i2c *pdata;
 657         unsigned long clkin = clk_get_rate(i2c->clk);
 658         unsigned int divs, div1;
 659         u32 iiccon;
 660         int freq;
 661         int start, end;
 662
 663         i2c->clkrate = clkin;
 664
 665         pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
 666         clkin /= 1000;          /* clkin now in KHz */
 667
 668         dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
 669                  pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
 670
 671         if (pdata->bus_freq != 0) {
 672                 freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000,
 673                                                &div1, &divs);
 674                 if (freq_acceptable(freq, pdata->bus_freq/1000))
 675                         goto found;
 676         }
 677
 678         /* ok, we may have to search for something suitable... */
 679
 680         start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq;
 681         end = pdata->min_freq;
 682
 683         start /= 1000;
 684         end /= 1000;
 685
 686         /* search loop... */
 687
 688         for (; start > end; start--) {
 689                 freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs);
 690                 if (freq_acceptable(freq, start))
 691                         goto found;
 692         }
 693
 694         /* cannot find frequency spec */
 695
 696         return -EINVAL;
 697
 698  found:
 699         *got = freq;
 700
 701         iiccon = readl(i2c->regs + S3C2410_IICCON);
 702         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
 703         iiccon |= (divs-1);
 704
 705         if (div1 == 512)
 706                 iiccon |= S3C2410_IICCON_TXDIV_512;
 707
 708         writel(iiccon, i2c->regs + S3C2410_IICCON);
 709
 710         return 0;
 711 }
 712
 713 #ifdef CONFIG_CPU_FREQ
 714
 715 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
 716
 717 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
 718                                           unsigned long val, void *data)
 719 {
 720         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
 721         unsigned long flags;
 722         unsigned int got;
 723         int delta_f;
 724         int ret;
 725
 726         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
 727
 728         /* if we're post-change and the input clock has slowed down
 729          * or at pre-change and the clock is about to speed up, then
 730          * adjust our clock rate. <0 is slow, >0 speedup.
 731          */
 732
 733         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
 734             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
 735                 spin_lock_irqsave(&i2c->lock, flags);
 736                 ret = s3c24xx_i2c_clockrate(i2c, &got);
 737                 spin_unlock_irqrestore(&i2c->lock, flags);
 738
 739                 if (ret < 0)
 740                         dev_err(i2c->dev, "cannot find frequency\n");
 741                 else
 742                         dev_info(i2c->dev, "setting freq %d\n", got);
 743         }
 744
 745         return 0;
 746 }
 747
 748 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 749 {
 750         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
 751
 752         return cpufreq_register_notifier(&i2c->freq_transition,
 753                                          CPUFREQ_TRANSITION_NOTIFIER);
 754 }
 755
 756 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 757 {
 758         cpufreq_unregister_notifier(&i2c->freq_transition,
 759                                     CPUFREQ_TRANSITION_NOTIFIER);
 760 }
 761
 762 #else
 763 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 764 {
 765         return 0;
 766 }
 767
 768 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 769 {
 770 }
 771 #endif
 772
 773 /* s3c24xx_i2c_init
 774  *
 775  * initialise the controller, set the IO lines and frequency
 776 */
 777
 778 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
 779 {
 780         unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
 781         struct s3c2410_platform_i2c *pdata;
 782         unsigned int freq;
 783
 784         /* get the plafrom data */
 785
 786         pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
 787
 788         /* inititalise the gpio */
 789
 790         s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
 791         s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
 792
 793         /* write slave address */
 794
 795         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
 796
 797         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
 798
 799         writel(iicon, i2c->regs + S3C2410_IICCON);
 800
 801         /* we need to work out the divisors for the clock... */
 802
 803         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
 804                 writel(0, i2c->regs + S3C2410_IICCON);
 805                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
 806                 return -EINVAL;
 807         }
 808
 809         /* todo - check that the i2c lines aren't being dragged anywhere */
 810
 811         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
 812         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
 813
 814         /* check for s3c2440 i2c controller  */
 815
 816         if (s3c24xx_i2c_is2440(i2c)) {
 817                 dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay);
 818
 819                 writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC);
 820         }
 821
 822         return 0;
 823 }
 824
 825 /* s3c24xx_i2c_probe
 826  *
 827  * called by the bus driver when a suitable device is found
 828 */
 829
 830 static int s3c24xx_i2c_probe(struct platform_device *pdev)
 831 {
 832         struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
 833         struct s3c2410_platform_i2c *pdata;
 834         struct resource *res;
 835         int ret;
 836
 837         pdata = s3c24xx_i2c_get_platformdata(&pdev->dev);
 838
 839         /* find the clock and enable it */
 840
 841         i2c->dev = &pdev->dev;
 842         i2c->clk = clk_get(&pdev->dev, "i2c");
 843         if (IS_ERR(i2c->clk)) {
 844                 dev_err(&pdev->dev, "cannot get clock\n");
 845                 ret = -ENOENT;
 846                 goto err_noclk;
 847         }
 848
 849         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
 850
 851         clk_enable(i2c->clk);
 852
 853         /* map the registers */
 854
 855         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 856         if (res == NULL) {
 857                 dev_err(&pdev->dev, "cannot find IO resource\n");
 858                 ret = -ENOENT;
 859                 goto err_clk;
 860         }
 861
 862         i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
 863                                          pdev->name);
 864
 865         if (i2c->ioarea == NULL) {
 866                 dev_err(&pdev->dev, "cannot request IO\n");
 867                 ret = -ENXIO;
 868                 goto err_clk;
 869         }
 870
 871         i2c->regs = ioremap(res->start, (res->end-res->start)+1);
 872
 873         if (i2c->regs == NULL) {
 874                 dev_err(&pdev->dev, "cannot map IO\n");
 875                 ret = -ENXIO;
 876                 goto err_ioarea;
 877         }
 878
 879         dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
 880                 i2c->regs, i2c->ioarea, res);
 881
 882         /* setup info block for the i2c core */
 883
 884         i2c->adap.algo_data = i2c;
 885         i2c->adap.dev.parent = &pdev->dev;
 886
 887         /* initialise the i2c controller */
 888
 889         ret = s3c24xx_i2c_init(i2c);
 890         if (ret != 0)
 891                 goto err_iomap;
 892
 893         /* find the IRQ for this unit (note, this relies on the init call to
 894          * ensure no current IRQs pending
 895          */
 896
 897         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 898         if (res == NULL) {
 899                 dev_err(&pdev->dev, "cannot find IRQ\n");
 900                 ret = -ENOENT;
 901                 goto err_iomap;
 902         }
 903
 904         ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED,
 905                           pdev->name, i2c);
 906
 907         if (ret != 0) {
 908                 dev_err(&pdev->dev, "cannot claim IRQ\n");
 909                 goto err_iomap;
 910         }
 911
 912         i2c->irq = res;
 913
 914         dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res,
 915                 (unsigned long)res->start);
 916
 917         ret = s3c24xx_i2c_register_cpufreq(i2c);
 918         if (ret < 0) {
 919                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
 920                 goto err_irq;
 921         }
 922
 923         /* Note, previous versions of the driver used i2c_add_adapter()
 924          * to add the bus at any number. We now pass the bus number via
 925          * the platform data, so if unset it will now default to always
 926          * being bus 0.
 927          */
 928
 929         i2c->adap.nr = pdata->bus_num;
 930
 931         ret = i2c_add_numbered_adapter(&i2c->adap);
 932         if (ret < 0) {
 933                 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
 934                 goto err_cpufreq;
 935         }
 936
 937         platform_set_drvdata(pdev, i2c);
 938
 939         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id);
 940         return 0;
 941
 942  err_cpufreq:
 943         s3c24xx_i2c_deregister_cpufreq(i2c);
 944
 945  err_irq:
 946         free_irq(i2c->irq->start, i2c);
 947
 948  err_iomap:
 949         iounmap(i2c->regs);
 950
 951  err_ioarea:
 952         release_resource(i2c->ioarea);
 953         kfree(i2c->ioarea);
 954
 955  err_clk:
 956         clk_disable(i2c->clk);
 957         clk_put(i2c->clk);
 958
 959  err_noclk:
 960         return ret;
 961 }
 962
 963 /* s3c24xx_i2c_remove
 964  *
 965  * called when device is removed from the bus
 966 */
 967
 968 static int s3c24xx_i2c_remove(struct platform_device *pdev)
 969 {
 970         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
 971
 972         s3c24xx_i2c_deregister_cpufreq(i2c);
 973
 974         i2c_del_adapter(&i2c->adap);
 975         free_irq(i2c->irq->start, i2c);
 976
 977         clk_disable(i2c->clk);
 978         clk_put(i2c->clk);
 979
 980         iounmap(i2c->regs);
 981
 982         release_resource(i2c->ioarea);
 983         kfree(i2c->ioarea);
 984
 985         return 0;
 986 }
 987
 988 #ifdef CONFIG_PM
 989 static int s3c24xx_i2c_resume(struct platform_device *dev)
 990 {
 991         struct s3c24xx_i2c *i2c = platform_get_drvdata(dev);
 992
 993         if (i2c != NULL)
 994                 s3c24xx_i2c_init(i2c);
 995
 996         return 0;
 997 }
 998
 999 #else
1000 #define s3c24xx_i2c_resume NULL
1001 #endif
1002
1003 /* device driver for platform bus bits */
1004
1005 static struct platform_driver s3c2410_i2c_driver = {
1006         .probe          = s3c24xx_i2c_probe,
1007         .remove         = s3c24xx_i2c_remove,
1008         .resume         = s3c24xx_i2c_resume,
1009         .driver         = {
1010                 .owner  = THIS_MODULE,
1011                 .name   = "s3c2410-i2c",
1012         },
1013 };
1014
1015 static struct platform_driver s3c2440_i2c_driver = {
1016         .probe          = s3c24xx_i2c_probe,
1017         .remove         = s3c24xx_i2c_remove,
1018         .resume         = s3c24xx_i2c_resume,
1019         .driver         = {
1020                 .owner  = THIS_MODULE,
1021                 .name   = "s3c2440-i2c",
1022         },
1023 };
1024
1025 static int __init i2c_adap_s3c_init(void)
1026 {
1027         int ret;
1028
1029         ret = platform_driver_register(&s3c2410_i2c_driver);
1030         if (ret == 0) {
1031                 ret = platform_driver_register(&s3c2440_i2c_driver);
1032                 if (ret)
1033                         platform_driver_unregister(&s3c2410_i2c_driver);
1034         }
1035
1036         return ret;
1037 }
1038
1039 static void __exit i2c_adap_s3c_exit(void)
1040 {
1041         platform_driver_unregister(&s3c2410_i2c_driver);
1042         platform_driver_unregister(&s3c2440_i2c_driver);
1043 }
1044
1045 module_init(i2c_adap_s3c_init);
1046 module_exit(i2c_adap_s3c_exit);
1047
1048 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1049 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1050 MODULE_LICENSE("GPL");
1051 MODULE_ALIAS("platform:s3c2410-i2c");
1052 MODULE_ALIAS("platform:s3c2440-i2c");