Merge branches 'sh/pci-express-integration', 'sh/rsk-updates', 'sh/platform-updates...
[linux-2.6] / drivers / net / ixgbe / ixgbe_ethtool.c
1 /*******************************************************************************
2
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for ixgbe */
29
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/vmalloc.h>
36 #include <linux/uaccess.h>
37
38 #include "ixgbe.h"
39
40
41 #define IXGBE_ALL_RAR_ENTRIES 16
42
43 struct ixgbe_stats {
44         char stat_string[ETH_GSTRING_LEN];
45         int sizeof_stat;
46         int stat_offset;
47 };
48
49 #define IXGBE_STAT(m) sizeof(((struct ixgbe_adapter *)0)->m), \
50                              offsetof(struct ixgbe_adapter, m)
51 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
52         {"rx_packets", IXGBE_STAT(net_stats.rx_packets)},
53         {"tx_packets", IXGBE_STAT(net_stats.tx_packets)},
54         {"rx_bytes", IXGBE_STAT(net_stats.rx_bytes)},
55         {"tx_bytes", IXGBE_STAT(net_stats.tx_bytes)},
56         {"lsc_int", IXGBE_STAT(lsc_int)},
57         {"tx_busy", IXGBE_STAT(tx_busy)},
58         {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
59         {"rx_errors", IXGBE_STAT(net_stats.rx_errors)},
60         {"tx_errors", IXGBE_STAT(net_stats.tx_errors)},
61         {"rx_dropped", IXGBE_STAT(net_stats.rx_dropped)},
62         {"tx_dropped", IXGBE_STAT(net_stats.tx_dropped)},
63         {"multicast", IXGBE_STAT(net_stats.multicast)},
64         {"broadcast", IXGBE_STAT(stats.bprc)},
65         {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
66         {"collisions", IXGBE_STAT(net_stats.collisions)},
67         {"rx_over_errors", IXGBE_STAT(net_stats.rx_over_errors)},
68         {"rx_crc_errors", IXGBE_STAT(net_stats.rx_crc_errors)},
69         {"rx_frame_errors", IXGBE_STAT(net_stats.rx_frame_errors)},
70         {"hw_rsc_count", IXGBE_STAT(rsc_count)},
71         {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
72         {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
73         {"rx_fifo_errors", IXGBE_STAT(net_stats.rx_fifo_errors)},
74         {"rx_missed_errors", IXGBE_STAT(net_stats.rx_missed_errors)},
75         {"tx_aborted_errors", IXGBE_STAT(net_stats.tx_aborted_errors)},
76         {"tx_carrier_errors", IXGBE_STAT(net_stats.tx_carrier_errors)},
77         {"tx_fifo_errors", IXGBE_STAT(net_stats.tx_fifo_errors)},
78         {"tx_heartbeat_errors", IXGBE_STAT(net_stats.tx_heartbeat_errors)},
79         {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
80         {"tx_restart_queue", IXGBE_STAT(restart_queue)},
81         {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
82         {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
83         {"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)},
84         {"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)},
85         {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
86         {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
87         {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
88         {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
89         {"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)},
90         {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
91         {"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)},
92         {"rx_header_split", IXGBE_STAT(rx_hdr_split)},
93         {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
94         {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
95         {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
96 #ifdef IXGBE_FCOE
97         {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
98         {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
99         {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
100         {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
101         {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
102         {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
103 #endif /* IXGBE_FCOE */
104 };
105
106 #define IXGBE_QUEUE_STATS_LEN \
107         ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
108         ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
109         (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
110 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
111 #define IXGBE_PB_STATS_LEN ( \
112                  (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
113                  IXGBE_FLAG_DCB_ENABLED) ? \
114                  (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
115                   sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
116                   sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
117                   sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
118                   / sizeof(u64) : 0)
119 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
120                          IXGBE_PB_STATS_LEN + \
121                          IXGBE_QUEUE_STATS_LEN)
122
123 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
124         "Register test  (offline)", "Eeprom test    (offline)",
125         "Interrupt test (offline)", "Loopback test  (offline)",
126         "Link test   (on/offline)"
127 };
128 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
129
130 static int ixgbe_get_settings(struct net_device *netdev,
131                               struct ethtool_cmd *ecmd)
132 {
133         struct ixgbe_adapter *adapter = netdev_priv(netdev);
134         struct ixgbe_hw *hw = &adapter->hw;
135         u32 link_speed = 0;
136         bool link_up;
137
138         ecmd->supported = SUPPORTED_10000baseT_Full;
139         ecmd->autoneg = AUTONEG_ENABLE;
140         ecmd->transceiver = XCVR_EXTERNAL;
141         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
142             (hw->mac.type == ixgbe_mac_82599EB)) {
143                 ecmd->supported |= (SUPPORTED_1000baseT_Full |
144                                     SUPPORTED_Autoneg);
145
146                 ecmd->advertising = ADVERTISED_Autoneg;
147                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
148                         ecmd->advertising |= ADVERTISED_10000baseT_Full;
149                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
150                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
151                 /*
152                  * It's possible that phy.autoneg_advertised may not be
153                  * set yet.  If so display what the default would be -
154                  * both 1G and 10G supported.
155                  */
156                 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
157                                            ADVERTISED_10000baseT_Full)))
158                         ecmd->advertising |= (ADVERTISED_10000baseT_Full |
159                                               ADVERTISED_1000baseT_Full);
160
161                 if (hw->phy.media_type == ixgbe_media_type_copper) {
162                         ecmd->supported |= SUPPORTED_TP;
163                         ecmd->advertising |= ADVERTISED_TP;
164                         ecmd->port = PORT_TP;
165                 } else {
166                         ecmd->supported |= SUPPORTED_FIBRE;
167                         ecmd->advertising |= ADVERTISED_FIBRE;
168                         ecmd->port = PORT_FIBRE;
169                 }
170         } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
171                 /* Set as FIBRE until SERDES defined in kernel */
172                 switch (hw->device_id) {
173                 case IXGBE_DEV_ID_82598:
174                         ecmd->supported |= (SUPPORTED_1000baseT_Full |
175                                 SUPPORTED_FIBRE);
176                         ecmd->advertising = (ADVERTISED_10000baseT_Full |
177                                 ADVERTISED_1000baseT_Full |
178                                 ADVERTISED_FIBRE);
179                         ecmd->port = PORT_FIBRE;
180                         break;
181                 case IXGBE_DEV_ID_82598_BX:
182                         ecmd->supported = (SUPPORTED_1000baseT_Full |
183                                            SUPPORTED_FIBRE);
184                         ecmd->advertising = (ADVERTISED_1000baseT_Full |
185                                              ADVERTISED_FIBRE);
186                         ecmd->port = PORT_FIBRE;
187                         ecmd->autoneg = AUTONEG_DISABLE;
188                         break;
189                 }
190         } else {
191                 ecmd->supported |= SUPPORTED_FIBRE;
192                 ecmd->advertising = (ADVERTISED_10000baseT_Full |
193                                      ADVERTISED_FIBRE);
194                 ecmd->port = PORT_FIBRE;
195                 ecmd->autoneg = AUTONEG_DISABLE;
196         }
197
198         hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
199         if (link_up) {
200                 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
201                                SPEED_10000 : SPEED_1000;
202                 ecmd->duplex = DUPLEX_FULL;
203         } else {
204                 ecmd->speed = -1;
205                 ecmd->duplex = -1;
206         }
207
208         return 0;
209 }
210
211 static int ixgbe_set_settings(struct net_device *netdev,
212                               struct ethtool_cmd *ecmd)
213 {
214         struct ixgbe_adapter *adapter = netdev_priv(netdev);
215         struct ixgbe_hw *hw = &adapter->hw;
216         u32 advertised, old;
217         s32 err = 0;
218
219         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
220             (hw->mac.type == ixgbe_mac_82599EB)) {
221                 /* 10000/copper and 1000/copper must autoneg
222                  * this function does not support any duplex forcing, but can
223                  * limit the advertising of the adapter to only 10000 or 1000 */
224                 if (ecmd->autoneg == AUTONEG_DISABLE)
225                         return -EINVAL;
226
227                 old = hw->phy.autoneg_advertised;
228                 advertised = 0;
229                 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
230                         advertised |= IXGBE_LINK_SPEED_10GB_FULL;
231
232                 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
233                         advertised |= IXGBE_LINK_SPEED_1GB_FULL;
234
235                 if (old == advertised)
236                         return err;
237                 /* this sets the link speed and restarts auto-neg */
238                 hw->mac.autotry_restart = true;
239                 err = hw->mac.ops.setup_link_speed(hw, advertised, true, true);
240                 if (err) {
241                         DPRINTK(PROBE, INFO,
242                                 "setup link failed with code %d\n", err);
243                         hw->mac.ops.setup_link_speed(hw, old, true, true);
244                 }
245         } else {
246                 /* in this case we currently only support 10Gb/FULL */
247                 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
248                     (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
249                         return -EINVAL;
250         }
251
252         return err;
253 }
254
255 static void ixgbe_get_pauseparam(struct net_device *netdev,
256                                  struct ethtool_pauseparam *pause)
257 {
258         struct ixgbe_adapter *adapter = netdev_priv(netdev);
259         struct ixgbe_hw *hw = &adapter->hw;
260
261         /*
262          * Flow Control Autoneg isn't on if
263          *  - we didn't ask for it OR
264          *  - it failed, we know this by tx & rx being off
265          */
266         if (hw->fc.disable_fc_autoneg ||
267             (hw->fc.current_mode == ixgbe_fc_none))
268                 pause->autoneg = 0;
269         else
270                 pause->autoneg = 1;
271
272 #ifdef CONFIG_DCB
273         if (hw->fc.current_mode == ixgbe_fc_pfc) {
274                 pause->rx_pause = 0;
275                 pause->tx_pause = 0;
276         }
277
278 #endif
279         if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
280                 pause->rx_pause = 1;
281         } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
282                 pause->tx_pause = 1;
283         } else if (hw->fc.current_mode == ixgbe_fc_full) {
284                 pause->rx_pause = 1;
285                 pause->tx_pause = 1;
286         }
287 }
288
289 static int ixgbe_set_pauseparam(struct net_device *netdev,
290                                 struct ethtool_pauseparam *pause)
291 {
292         struct ixgbe_adapter *adapter = netdev_priv(netdev);
293         struct ixgbe_hw *hw = &adapter->hw;
294         struct ixgbe_fc_info fc;
295
296 #ifdef CONFIG_DCB
297         if (adapter->dcb_cfg.pfc_mode_enable ||
298                 ((hw->mac.type == ixgbe_mac_82598EB) &&
299                 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
300                 return -EINVAL;
301
302 #endif
303
304         fc = hw->fc;
305
306         if (pause->autoneg != AUTONEG_ENABLE)
307                 fc.disable_fc_autoneg = true;
308         else
309                 fc.disable_fc_autoneg = false;
310
311         if (pause->rx_pause && pause->tx_pause)
312                 fc.requested_mode = ixgbe_fc_full;
313         else if (pause->rx_pause && !pause->tx_pause)
314                 fc.requested_mode = ixgbe_fc_rx_pause;
315         else if (!pause->rx_pause && pause->tx_pause)
316                 fc.requested_mode = ixgbe_fc_tx_pause;
317         else if (!pause->rx_pause && !pause->tx_pause)
318                 fc.requested_mode = ixgbe_fc_none;
319         else
320                 return -EINVAL;
321
322 #ifdef CONFIG_DCB
323         adapter->last_lfc_mode = fc.requested_mode;
324 #endif
325
326         /* if the thing changed then we'll update and use new autoneg */
327         if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
328                 hw->fc = fc;
329                 if (netif_running(netdev))
330                         ixgbe_reinit_locked(adapter);
331                 else
332                         ixgbe_reset(adapter);
333         }
334
335         return 0;
336 }
337
338 static u32 ixgbe_get_rx_csum(struct net_device *netdev)
339 {
340         struct ixgbe_adapter *adapter = netdev_priv(netdev);
341         return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
342 }
343
344 static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
345 {
346         struct ixgbe_adapter *adapter = netdev_priv(netdev);
347         if (data)
348                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
349         else
350                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
351
352         if (netif_running(netdev))
353                 ixgbe_reinit_locked(adapter);
354         else
355                 ixgbe_reset(adapter);
356
357         return 0;
358 }
359
360 static u32 ixgbe_get_tx_csum(struct net_device *netdev)
361 {
362         return (netdev->features & NETIF_F_IP_CSUM) != 0;
363 }
364
365 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
366 {
367         struct ixgbe_adapter *adapter = netdev_priv(netdev);
368
369         if (data) {
370                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
371                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
372                         netdev->features |= NETIF_F_SCTP_CSUM;
373         } else {
374                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
375                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
376                         netdev->features &= ~NETIF_F_SCTP_CSUM;
377         }
378
379         return 0;
380 }
381
382 static int ixgbe_set_tso(struct net_device *netdev, u32 data)
383 {
384         if (data) {
385                 netdev->features |= NETIF_F_TSO;
386                 netdev->features |= NETIF_F_TSO6;
387         } else {
388                 netif_tx_stop_all_queues(netdev);
389                 netdev->features &= ~NETIF_F_TSO;
390                 netdev->features &= ~NETIF_F_TSO6;
391                 netif_tx_start_all_queues(netdev);
392         }
393         return 0;
394 }
395
396 static u32 ixgbe_get_msglevel(struct net_device *netdev)
397 {
398         struct ixgbe_adapter *adapter = netdev_priv(netdev);
399         return adapter->msg_enable;
400 }
401
402 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
403 {
404         struct ixgbe_adapter *adapter = netdev_priv(netdev);
405         adapter->msg_enable = data;
406 }
407
408 static int ixgbe_get_regs_len(struct net_device *netdev)
409 {
410 #define IXGBE_REGS_LEN  1128
411         return IXGBE_REGS_LEN * sizeof(u32);
412 }
413
414 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
415
416 static void ixgbe_get_regs(struct net_device *netdev,
417                            struct ethtool_regs *regs, void *p)
418 {
419         struct ixgbe_adapter *adapter = netdev_priv(netdev);
420         struct ixgbe_hw *hw = &adapter->hw;
421         u32 *regs_buff = p;
422         u8 i;
423
424         memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
425
426         regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
427
428         /* General Registers */
429         regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
430         regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
431         regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
432         regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
433         regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
434         regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
435         regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
436         regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
437
438         /* NVM Register */
439         regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
440         regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
441         regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
442         regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
443         regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
444         regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
445         regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
446         regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
447         regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
448         regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
449
450         /* Interrupt */
451         /* don't read EICR because it can clear interrupt causes, instead
452          * read EICS which is a shadow but doesn't clear EICR */
453         regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
454         regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
455         regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
456         regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
457         regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
458         regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
459         regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
460         regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
461         regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
462         regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
463         regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
464         regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
465
466         /* Flow Control */
467         regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
468         regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
469         regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
470         regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
471         regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
472         for (i = 0; i < 8; i++)
473                 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
474         for (i = 0; i < 8; i++)
475                 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
476         regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
477         regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
478
479         /* Receive DMA */
480         for (i = 0; i < 64; i++)
481                 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
482         for (i = 0; i < 64; i++)
483                 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
484         for (i = 0; i < 64; i++)
485                 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
486         for (i = 0; i < 64; i++)
487                 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
488         for (i = 0; i < 64; i++)
489                 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
490         for (i = 0; i < 64; i++)
491                 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
492         for (i = 0; i < 16; i++)
493                 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
494         for (i = 0; i < 16; i++)
495                 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
496         regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
497         for (i = 0; i < 8; i++)
498                 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
499         regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
500         regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
501
502         /* Receive */
503         regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
504         regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
505         for (i = 0; i < 16; i++)
506                 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
507         for (i = 0; i < 16; i++)
508                 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
509         regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
510         regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
511         regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
512         regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
513         regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
514         regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
515         for (i = 0; i < 8; i++)
516                 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
517         for (i = 0; i < 8; i++)
518                 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
519         regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
520
521         /* Transmit */
522         for (i = 0; i < 32; i++)
523                 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
524         for (i = 0; i < 32; i++)
525                 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
526         for (i = 0; i < 32; i++)
527                 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
528         for (i = 0; i < 32; i++)
529                 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
530         for (i = 0; i < 32; i++)
531                 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
532         for (i = 0; i < 32; i++)
533                 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
534         for (i = 0; i < 32; i++)
535                 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
536         for (i = 0; i < 32; i++)
537                 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
538         regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
539         for (i = 0; i < 16; i++)
540                 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
541         regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
542         for (i = 0; i < 8; i++)
543                 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
544         regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
545
546         /* Wake Up */
547         regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
548         regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
549         regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
550         regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
551         regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
552         regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
553         regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
554         regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
555         regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
556
557         regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
558         regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
559         regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
560         regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
561         for (i = 0; i < 8; i++)
562                 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
563         for (i = 0; i < 8; i++)
564                 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
565         for (i = 0; i < 8; i++)
566                 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
567         for (i = 0; i < 8; i++)
568                 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
569         for (i = 0; i < 8; i++)
570                 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
571         for (i = 0; i < 8; i++)
572                 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
573
574         /* Statistics */
575         regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
576         regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
577         regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
578         regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
579         for (i = 0; i < 8; i++)
580                 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
581         regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
582         regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
583         regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
584         regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
585         regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
586         regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
587         regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
588         for (i = 0; i < 8; i++)
589                 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
590         for (i = 0; i < 8; i++)
591                 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
592         for (i = 0; i < 8; i++)
593                 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
594         for (i = 0; i < 8; i++)
595                 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
596         regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
597         regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
598         regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
599         regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
600         regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
601         regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
602         regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
603         regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
604         regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
605         regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
606         regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
607         regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
608         for (i = 0; i < 8; i++)
609                 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
610         regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
611         regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
612         regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
613         regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
614         regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
615         regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
616         regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
617         regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
618         regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
619         regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
620         regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
621         regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
622         regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
623         regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
624         regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
625         regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
626         regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
627         regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
628         regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
629         for (i = 0; i < 16; i++)
630                 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
631         for (i = 0; i < 16; i++)
632                 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
633         for (i = 0; i < 16; i++)
634                 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
635         for (i = 0; i < 16; i++)
636                 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
637
638         /* MAC */
639         regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
640         regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
641         regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
642         regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
643         regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
644         regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
645         regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
646         regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
647         regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
648         regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
649         regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
650         regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
651         regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
652         regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
653         regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
654         regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
655         regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
656         regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
657         regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
658         regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
659         regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
660         regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
661         regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
662         regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
663         regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
664         regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
665         regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
666         regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
667         regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
668         regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
669         regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
670         regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
671         regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
672
673         /* Diagnostic */
674         regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
675         for (i = 0; i < 8; i++)
676                 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
677         regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
678         for (i = 0; i < 4; i++)
679                 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
680         regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
681         regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
682         for (i = 0; i < 8; i++)
683                 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
684         regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
685         for (i = 0; i < 4; i++)
686                 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
687         regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
688         regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
689         regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
690         regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
691         regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
692         regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
693         regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
694         regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
695         regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
696         regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
697         regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
698         for (i = 0; i < 8; i++)
699                 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
700         regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
701         regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
702         regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
703         regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
704         regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
705         regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
706         regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
707         regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
708         regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
709 }
710
711 static int ixgbe_get_eeprom_len(struct net_device *netdev)
712 {
713         struct ixgbe_adapter *adapter = netdev_priv(netdev);
714         return adapter->hw.eeprom.word_size * 2;
715 }
716
717 static int ixgbe_get_eeprom(struct net_device *netdev,
718                             struct ethtool_eeprom *eeprom, u8 *bytes)
719 {
720         struct ixgbe_adapter *adapter = netdev_priv(netdev);
721         struct ixgbe_hw *hw = &adapter->hw;
722         u16 *eeprom_buff;
723         int first_word, last_word, eeprom_len;
724         int ret_val = 0;
725         u16 i;
726
727         if (eeprom->len == 0)
728                 return -EINVAL;
729
730         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
731
732         first_word = eeprom->offset >> 1;
733         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
734         eeprom_len = last_word - first_word + 1;
735
736         eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
737         if (!eeprom_buff)
738                 return -ENOMEM;
739
740         for (i = 0; i < eeprom_len; i++) {
741                 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
742                     &eeprom_buff[i])))
743                         break;
744         }
745
746         /* Device's eeprom is always little-endian, word addressable */
747         for (i = 0; i < eeprom_len; i++)
748                 le16_to_cpus(&eeprom_buff[i]);
749
750         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
751         kfree(eeprom_buff);
752
753         return ret_val;
754 }
755
756 static void ixgbe_get_drvinfo(struct net_device *netdev,
757                               struct ethtool_drvinfo *drvinfo)
758 {
759         struct ixgbe_adapter *adapter = netdev_priv(netdev);
760         char firmware_version[32];
761
762         strncpy(drvinfo->driver, ixgbe_driver_name, 32);
763         strncpy(drvinfo->version, ixgbe_driver_version, 32);
764
765         sprintf(firmware_version, "%d.%d-%d",
766                 (adapter->eeprom_version & 0xF000) >> 12,
767                 (adapter->eeprom_version & 0x0FF0) >> 4,
768                 adapter->eeprom_version & 0x000F);
769
770         strncpy(drvinfo->fw_version, firmware_version, 32);
771         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
772         drvinfo->n_stats = IXGBE_STATS_LEN;
773         drvinfo->testinfo_len = IXGBE_TEST_LEN;
774         drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
775 }
776
777 static void ixgbe_get_ringparam(struct net_device *netdev,
778                                 struct ethtool_ringparam *ring)
779 {
780         struct ixgbe_adapter *adapter = netdev_priv(netdev);
781         struct ixgbe_ring *tx_ring = adapter->tx_ring;
782         struct ixgbe_ring *rx_ring = adapter->rx_ring;
783
784         ring->rx_max_pending = IXGBE_MAX_RXD;
785         ring->tx_max_pending = IXGBE_MAX_TXD;
786         ring->rx_mini_max_pending = 0;
787         ring->rx_jumbo_max_pending = 0;
788         ring->rx_pending = rx_ring->count;
789         ring->tx_pending = tx_ring->count;
790         ring->rx_mini_pending = 0;
791         ring->rx_jumbo_pending = 0;
792 }
793
794 static int ixgbe_set_ringparam(struct net_device *netdev,
795                                struct ethtool_ringparam *ring)
796 {
797         struct ixgbe_adapter *adapter = netdev_priv(netdev);
798         struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
799         int i, err;
800         u32 new_rx_count, new_tx_count;
801         bool need_update = false;
802
803         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
804                 return -EINVAL;
805
806         new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
807         new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
808         new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
809
810         new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
811         new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
812         new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
813
814         if ((new_tx_count == adapter->tx_ring->count) &&
815             (new_rx_count == adapter->rx_ring->count)) {
816                 /* nothing to do */
817                 return 0;
818         }
819
820         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
821                 msleep(1);
822
823         temp_tx_ring = kcalloc(adapter->num_tx_queues,
824                                sizeof(struct ixgbe_ring), GFP_KERNEL);
825         if (!temp_tx_ring) {
826                 err = -ENOMEM;
827                 goto err_setup;
828         }
829
830         if (new_tx_count != adapter->tx_ring_count) {
831                 memcpy(temp_tx_ring, adapter->tx_ring,
832                        adapter->num_tx_queues * sizeof(struct ixgbe_ring));
833                 for (i = 0; i < adapter->num_tx_queues; i++) {
834                         temp_tx_ring[i].count = new_tx_count;
835                         err = ixgbe_setup_tx_resources(adapter,
836                                                        &temp_tx_ring[i]);
837                         if (err) {
838                                 while (i) {
839                                         i--;
840                                         ixgbe_free_tx_resources(adapter,
841                                                                 &temp_tx_ring[i]);
842                                 }
843                                 goto err_setup;
844                         }
845                 }
846                 need_update = true;
847         }
848
849         temp_rx_ring = kcalloc(adapter->num_rx_queues,
850                                sizeof(struct ixgbe_ring), GFP_KERNEL);
851         if ((!temp_rx_ring) && (need_update)) {
852                 for (i = 0; i < adapter->num_tx_queues; i++)
853                         ixgbe_free_tx_resources(adapter, &temp_tx_ring[i]);
854                 kfree(temp_tx_ring);
855                 err = -ENOMEM;
856                 goto err_setup;
857         }
858
859         if (new_rx_count != adapter->rx_ring_count) {
860                 memcpy(temp_rx_ring, adapter->rx_ring,
861                        adapter->num_rx_queues * sizeof(struct ixgbe_ring));
862                 for (i = 0; i < adapter->num_rx_queues; i++) {
863                         temp_rx_ring[i].count = new_rx_count;
864                         err = ixgbe_setup_rx_resources(adapter,
865                                                        &temp_rx_ring[i]);
866                         if (err) {
867                                 while (i) {
868                                         i--;
869                                         ixgbe_free_rx_resources(adapter,
870                                                               &temp_rx_ring[i]);
871                                 }
872                                 goto err_setup;
873                         }
874                 }
875                 need_update = true;
876         }
877
878         /* if rings need to be updated, here's the place to do it in one shot */
879         if (need_update) {
880                 if (netif_running(netdev))
881                         ixgbe_down(adapter);
882
883                 /* tx */
884                 if (new_tx_count != adapter->tx_ring_count) {
885                         kfree(adapter->tx_ring);
886                         adapter->tx_ring = temp_tx_ring;
887                         temp_tx_ring = NULL;
888                         adapter->tx_ring_count = new_tx_count;
889                 }
890
891                 /* rx */
892                 if (new_rx_count != adapter->rx_ring_count) {
893                         kfree(adapter->rx_ring);
894                         adapter->rx_ring = temp_rx_ring;
895                         temp_rx_ring = NULL;
896                         adapter->rx_ring_count = new_rx_count;
897                 }
898         }
899
900         /* success! */
901         err = 0;
902         if (netif_running(netdev))
903                 ixgbe_up(adapter);
904
905 err_setup:
906         clear_bit(__IXGBE_RESETTING, &adapter->state);
907         return err;
908 }
909
910 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
911 {
912         switch (sset) {
913         case ETH_SS_TEST:
914                 return IXGBE_TEST_LEN;
915         case ETH_SS_STATS:
916                 return IXGBE_STATS_LEN;
917         default:
918                 return -EOPNOTSUPP;
919         }
920 }
921
922 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
923                                     struct ethtool_stats *stats, u64 *data)
924 {
925         struct ixgbe_adapter *adapter = netdev_priv(netdev);
926         u64 *queue_stat;
927         int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
928         int j, k;
929         int i;
930
931         ixgbe_update_stats(adapter);
932         for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
933                 char *p = (char *)adapter + ixgbe_gstrings_stats[i].stat_offset;
934                 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
935                            sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
936         }
937         for (j = 0; j < adapter->num_tx_queues; j++) {
938                 queue_stat = (u64 *)&adapter->tx_ring[j].stats;
939                 for (k = 0; k < stat_count; k++)
940                         data[i + k] = queue_stat[k];
941                 i += k;
942         }
943         for (j = 0; j < adapter->num_rx_queues; j++) {
944                 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
945                 for (k = 0; k < stat_count; k++)
946                         data[i + k] = queue_stat[k];
947                 i += k;
948         }
949         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
950                 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
951                         data[i++] = adapter->stats.pxontxc[j];
952                         data[i++] = adapter->stats.pxofftxc[j];
953                 }
954                 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
955                         data[i++] = adapter->stats.pxonrxc[j];
956                         data[i++] = adapter->stats.pxoffrxc[j];
957                 }
958         }
959 }
960
961 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
962                               u8 *data)
963 {
964         struct ixgbe_adapter *adapter = netdev_priv(netdev);
965         char *p = (char *)data;
966         int i;
967
968         switch (stringset) {
969         case ETH_SS_TEST:
970                 memcpy(data, *ixgbe_gstrings_test,
971                        IXGBE_TEST_LEN * ETH_GSTRING_LEN);
972                 break;
973         case ETH_SS_STATS:
974                 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
975                         memcpy(p, ixgbe_gstrings_stats[i].stat_string,
976                                ETH_GSTRING_LEN);
977                         p += ETH_GSTRING_LEN;
978                 }
979                 for (i = 0; i < adapter->num_tx_queues; i++) {
980                         sprintf(p, "tx_queue_%u_packets", i);
981                         p += ETH_GSTRING_LEN;
982                         sprintf(p, "tx_queue_%u_bytes", i);
983                         p += ETH_GSTRING_LEN;
984                 }
985                 for (i = 0; i < adapter->num_rx_queues; i++) {
986                         sprintf(p, "rx_queue_%u_packets", i);
987                         p += ETH_GSTRING_LEN;
988                         sprintf(p, "rx_queue_%u_bytes", i);
989                         p += ETH_GSTRING_LEN;
990                 }
991                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
992                         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
993                                 sprintf(p, "tx_pb_%u_pxon", i);
994                                 p += ETH_GSTRING_LEN;
995                                 sprintf(p, "tx_pb_%u_pxoff", i);
996                                 p += ETH_GSTRING_LEN;
997                         }
998                         for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
999                                 sprintf(p, "rx_pb_%u_pxon", i);
1000                                 p += ETH_GSTRING_LEN;
1001                                 sprintf(p, "rx_pb_%u_pxoff", i);
1002                                 p += ETH_GSTRING_LEN;
1003                         }
1004                 }
1005                 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1006                 break;
1007         }
1008 }
1009
1010 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1011 {
1012         struct ixgbe_hw *hw = &adapter->hw;
1013         bool link_up;
1014         u32 link_speed = 0;
1015         *data = 0;
1016
1017         hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1018         if (link_up)
1019                 return *data;
1020         else
1021                 *data = 1;
1022         return *data;
1023 }
1024
1025 /* ethtool register test data */
1026 struct ixgbe_reg_test {
1027         u16 reg;
1028         u8  array_len;
1029         u8  test_type;
1030         u32 mask;
1031         u32 write;
1032 };
1033
1034 /* In the hardware, registers are laid out either singly, in arrays
1035  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
1036  * most tests take place on arrays or single registers (handled
1037  * as a single-element array) and special-case the tables.
1038  * Table tests are always pattern tests.
1039  *
1040  * We also make provision for some required setup steps by specifying
1041  * registers to be written without any read-back testing.
1042  */
1043
1044 #define PATTERN_TEST    1
1045 #define SET_READ_TEST   2
1046 #define WRITE_NO_TEST   3
1047 #define TABLE32_TEST    4
1048 #define TABLE64_TEST_LO 5
1049 #define TABLE64_TEST_HI 6
1050
1051 /* default 82599 register test */
1052 static struct ixgbe_reg_test reg_test_82599[] = {
1053         { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1054         { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1055         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1056         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1057         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1058         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1059         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1060         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1061         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1062         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1063         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1064         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1065         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1066         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1067         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1068         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1069         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1070         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1071         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1072         { 0, 0, 0, 0 }
1073 };
1074
1075 /* default 82598 register test */
1076 static struct ixgbe_reg_test reg_test_82598[] = {
1077         { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1078         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1079         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1080         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1081         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1082         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1083         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1084         /* Enable all four RX queues before testing. */
1085         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1086         /* RDH is read-only for 82598, only test RDT. */
1087         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1088         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1089         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1090         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1091         { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1092         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1093         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1094         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1095         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1096         { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1097         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1098         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1099         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1100         { 0, 0, 0, 0 }
1101 };
1102
1103 #define REG_PATTERN_TEST(R, M, W)                                             \
1104 {                                                                             \
1105         u32 pat, val, before;                                                 \
1106         const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1107         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {                       \
1108                 before = readl(adapter->hw.hw_addr + R);                      \
1109                 writel((_test[pat] & W), (adapter->hw.hw_addr + R));          \
1110                 val = readl(adapter->hw.hw_addr + R);                         \
1111                 if (val != (_test[pat] & W & M)) {                            \
1112                         DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
1113                                           "0x%08X expected 0x%08X\n",         \
1114                                 R, val, (_test[pat] & W & M));                \
1115                         *data = R;                                            \
1116                         writel(before, adapter->hw.hw_addr + R);              \
1117                         return 1;                                             \
1118                 }                                                             \
1119                 writel(before, adapter->hw.hw_addr + R);                      \
1120         }                                                                     \
1121 }
1122
1123 #define REG_SET_AND_CHECK(R, M, W)                                            \
1124 {                                                                             \
1125         u32 val, before;                                                      \
1126         before = readl(adapter->hw.hw_addr + R);                              \
1127         writel((W & M), (adapter->hw.hw_addr + R));                           \
1128         val = readl(adapter->hw.hw_addr + R);                                 \
1129         if ((W & M) != (val & M)) {                                           \
1130                 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
1131                                  "expected 0x%08X\n", R, (val & M), (W & M)); \
1132                 *data = R;                                                    \
1133                 writel(before, (adapter->hw.hw_addr + R));                    \
1134                 return 1;                                                     \
1135         }                                                                     \
1136         writel(before, (adapter->hw.hw_addr + R));                            \
1137 }
1138
1139 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1140 {
1141         struct ixgbe_reg_test *test;
1142         u32 value, before, after;
1143         u32 i, toggle;
1144
1145         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1146                 toggle = 0x7FFFF30F;
1147                 test = reg_test_82599;
1148         } else {
1149                 toggle = 0x7FFFF3FF;
1150                 test = reg_test_82598;
1151         }
1152
1153         /*
1154          * Because the status register is such a special case,
1155          * we handle it separately from the rest of the register
1156          * tests.  Some bits are read-only, some toggle, and some
1157          * are writeable on newer MACs.
1158          */
1159         before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1160         value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1161         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1162         after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1163         if (value != after) {
1164                 DPRINTK(DRV, ERR, "failed STATUS register test got: "
1165                         "0x%08X expected: 0x%08X\n", after, value);
1166                 *data = 1;
1167                 return 1;
1168         }
1169         /* restore previous status */
1170         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1171
1172         /*
1173          * Perform the remainder of the register test, looping through
1174          * the test table until we either fail or reach the null entry.
1175          */
1176         while (test->reg) {
1177                 for (i = 0; i < test->array_len; i++) {
1178                         switch (test->test_type) {
1179                         case PATTERN_TEST:
1180                                 REG_PATTERN_TEST(test->reg + (i * 0x40),
1181                                                 test->mask,
1182                                                 test->write);
1183                                 break;
1184                         case SET_READ_TEST:
1185                                 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1186                                                 test->mask,
1187                                                 test->write);
1188                                 break;
1189                         case WRITE_NO_TEST:
1190                                 writel(test->write,
1191                                        (adapter->hw.hw_addr + test->reg)
1192                                        + (i * 0x40));
1193                                 break;
1194                         case TABLE32_TEST:
1195                                 REG_PATTERN_TEST(test->reg + (i * 4),
1196                                                 test->mask,
1197                                                 test->write);
1198                                 break;
1199                         case TABLE64_TEST_LO:
1200                                 REG_PATTERN_TEST(test->reg + (i * 8),
1201                                                 test->mask,
1202                                                 test->write);
1203                                 break;
1204                         case TABLE64_TEST_HI:
1205                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1206                                                 test->mask,
1207                                                 test->write);
1208                                 break;
1209                         }
1210                 }
1211                 test++;
1212         }
1213
1214         *data = 0;
1215         return 0;
1216 }
1217
1218 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1219 {
1220         struct ixgbe_hw *hw = &adapter->hw;
1221         if (hw->eeprom.ops.validate_checksum(hw, NULL))
1222                 *data = 1;
1223         else
1224                 *data = 0;
1225         return *data;
1226 }
1227
1228 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1229 {
1230         struct net_device *netdev = (struct net_device *) data;
1231         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1232
1233         adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1234
1235         return IRQ_HANDLED;
1236 }
1237
1238 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1239 {
1240         struct net_device *netdev = adapter->netdev;
1241         u32 mask, i = 0, shared_int = true;
1242         u32 irq = adapter->pdev->irq;
1243
1244         *data = 0;
1245
1246         /* Hook up test interrupt handler just for this test */
1247         if (adapter->msix_entries) {
1248                 /* NOTE: we don't test MSI-X interrupts here, yet */
1249                 return 0;
1250         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1251                 shared_int = false;
1252                 if (request_irq(irq, &ixgbe_test_intr, 0, netdev->name,
1253                                 netdev)) {
1254                         *data = 1;
1255                         return -1;
1256                 }
1257         } else if (!request_irq(irq, &ixgbe_test_intr, IRQF_PROBE_SHARED,
1258                                 netdev->name, netdev)) {
1259                 shared_int = false;
1260         } else if (request_irq(irq, &ixgbe_test_intr, IRQF_SHARED,
1261                                netdev->name, netdev)) {
1262                 *data = 1;
1263                 return -1;
1264         }
1265         DPRINTK(HW, INFO, "testing %s interrupt\n",
1266                 (shared_int ? "shared" : "unshared"));
1267
1268         /* Disable all the interrupts */
1269         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1270         msleep(10);
1271
1272         /* Test each interrupt */
1273         for (; i < 10; i++) {
1274                 /* Interrupt to test */
1275                 mask = 1 << i;
1276
1277                 if (!shared_int) {
1278                         /*
1279                          * Disable the interrupts to be reported in
1280                          * the cause register and then force the same
1281                          * interrupt and see if one gets posted.  If
1282                          * an interrupt was posted to the bus, the
1283                          * test failed.
1284                          */
1285                         adapter->test_icr = 0;
1286                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1287                                         ~mask & 0x00007FFF);
1288                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1289                                         ~mask & 0x00007FFF);
1290                         msleep(10);
1291
1292                         if (adapter->test_icr & mask) {
1293                                 *data = 3;
1294                                 break;
1295                         }
1296                 }
1297
1298                 /*
1299                  * Enable the interrupt to be reported in the cause
1300                  * register and then force the same interrupt and see
1301                  * if one gets posted.  If an interrupt was not posted
1302                  * to the bus, the test failed.
1303                  */
1304                 adapter->test_icr = 0;
1305                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1306                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1307                 msleep(10);
1308
1309                 if (!(adapter->test_icr &mask)) {
1310                         *data = 4;
1311                         break;
1312                 }
1313
1314                 if (!shared_int) {
1315                         /*
1316                          * Disable the other interrupts to be reported in
1317                          * the cause register and then force the other
1318                          * interrupts and see if any get posted.  If
1319                          * an interrupt was posted to the bus, the
1320                          * test failed.
1321                          */
1322                         adapter->test_icr = 0;
1323                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1324                                         ~mask & 0x00007FFF);
1325                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1326                                         ~mask & 0x00007FFF);
1327                         msleep(10);
1328
1329                         if (adapter->test_icr) {
1330                                 *data = 5;
1331                                 break;
1332                         }
1333                 }
1334         }
1335
1336         /* Disable all the interrupts */
1337         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1338         msleep(10);
1339
1340         /* Unhook test interrupt handler */
1341         free_irq(irq, netdev);
1342
1343         return *data;
1344 }
1345
1346 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1347 {
1348         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1349         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1350         struct ixgbe_hw *hw = &adapter->hw;
1351         struct pci_dev *pdev = adapter->pdev;
1352         u32 reg_ctl;
1353         int i;
1354
1355         /* shut down the DMA engines now so they can be reinitialized later */
1356
1357         /* first Rx */
1358         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1359         reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1360         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1361         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1362         reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1363         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1364
1365         /* now Tx */
1366         reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1367         reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1368         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1369         if (hw->mac.type == ixgbe_mac_82599EB) {
1370                 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1371                 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1372                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1373         }
1374
1375         ixgbe_reset(adapter);
1376
1377         if (tx_ring->desc && tx_ring->tx_buffer_info) {
1378                 for (i = 0; i < tx_ring->count; i++) {
1379                         struct ixgbe_tx_buffer *buf =
1380                                         &(tx_ring->tx_buffer_info[i]);
1381                         if (buf->dma)
1382                                 pci_unmap_single(pdev, buf->dma, buf->length,
1383                                                  PCI_DMA_TODEVICE);
1384                         if (buf->skb)
1385                                 dev_kfree_skb(buf->skb);
1386                 }
1387         }
1388
1389         if (rx_ring->desc && rx_ring->rx_buffer_info) {
1390                 for (i = 0; i < rx_ring->count; i++) {
1391                         struct ixgbe_rx_buffer *buf =
1392                                         &(rx_ring->rx_buffer_info[i]);
1393                         if (buf->dma)
1394                                 pci_unmap_single(pdev, buf->dma,
1395                                                  IXGBE_RXBUFFER_2048,
1396                                                  PCI_DMA_FROMDEVICE);
1397                         if (buf->skb)
1398                                 dev_kfree_skb(buf->skb);
1399                 }
1400         }
1401
1402         if (tx_ring->desc) {
1403                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1404                                     tx_ring->dma);
1405                 tx_ring->desc = NULL;
1406         }
1407         if (rx_ring->desc) {
1408                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1409                                     rx_ring->dma);
1410                 rx_ring->desc = NULL;
1411         }
1412
1413         kfree(tx_ring->tx_buffer_info);
1414         tx_ring->tx_buffer_info = NULL;
1415         kfree(rx_ring->rx_buffer_info);
1416         rx_ring->rx_buffer_info = NULL;
1417
1418         return;
1419 }
1420
1421 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1422 {
1423         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1424         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1425         struct pci_dev *pdev = adapter->pdev;
1426         u32 rctl, reg_data;
1427         int i, ret_val;
1428
1429         /* Setup Tx descriptor ring and Tx buffers */
1430
1431         if (!tx_ring->count)
1432                 tx_ring->count = IXGBE_DEFAULT_TXD;
1433
1434         tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1435                                           sizeof(struct ixgbe_tx_buffer),
1436                                           GFP_KERNEL);
1437         if (!(tx_ring->tx_buffer_info)) {
1438                 ret_val = 1;
1439                 goto err_nomem;
1440         }
1441
1442         tx_ring->size = tx_ring->count * sizeof(struct ixgbe_legacy_tx_desc);
1443         tx_ring->size = ALIGN(tx_ring->size, 4096);
1444         if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1445                                                    &tx_ring->dma))) {
1446                 ret_val = 2;
1447                 goto err_nomem;
1448         }
1449         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1450
1451         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1452                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1453         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1454                         ((u64) tx_ring->dma >> 32));
1455         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
1456                         tx_ring->count * sizeof(struct ixgbe_legacy_tx_desc));
1457         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1458         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1459
1460         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1461         reg_data |= IXGBE_HLREG0_TXPADEN;
1462         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1463
1464         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1465                 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1466                 reg_data |= IXGBE_DMATXCTL_TE;
1467                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1468         }
1469         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1470         reg_data |= IXGBE_TXDCTL_ENABLE;
1471         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1472
1473         for (i = 0; i < tx_ring->count; i++) {
1474                 struct ixgbe_legacy_tx_desc *desc = IXGBE_TX_DESC(*tx_ring, i);
1475                 struct sk_buff *skb;
1476                 unsigned int size = 1024;
1477
1478                 skb = alloc_skb(size, GFP_KERNEL);
1479                 if (!skb) {
1480                         ret_val = 3;
1481                         goto err_nomem;
1482                 }
1483                 skb_put(skb, size);
1484                 tx_ring->tx_buffer_info[i].skb = skb;
1485                 tx_ring->tx_buffer_info[i].length = skb->len;
1486                 tx_ring->tx_buffer_info[i].dma =
1487                         pci_map_single(pdev, skb->data, skb->len,
1488                                         PCI_DMA_TODEVICE);
1489                 desc->buffer_addr = cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1490                 desc->lower.data = cpu_to_le32(skb->len);
1491                 desc->lower.data |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1492                                                 IXGBE_TXD_CMD_IFCS |
1493                                                 IXGBE_TXD_CMD_RS);
1494                 desc->upper.data = 0;
1495         }
1496
1497         /* Setup Rx Descriptor ring and Rx buffers */
1498
1499         if (!rx_ring->count)
1500                 rx_ring->count = IXGBE_DEFAULT_RXD;
1501
1502         rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1503                                           sizeof(struct ixgbe_rx_buffer),
1504                                           GFP_KERNEL);
1505         if (!(rx_ring->rx_buffer_info)) {
1506                 ret_val = 4;
1507                 goto err_nomem;
1508         }
1509
1510         rx_ring->size = rx_ring->count * sizeof(struct ixgbe_legacy_rx_desc);
1511         rx_ring->size = ALIGN(rx_ring->size, 4096);
1512         if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1513                                                    &rx_ring->dma))) {
1514                 ret_val = 5;
1515                 goto err_nomem;
1516         }
1517         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1518
1519         rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1520         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1521         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1522                         ((u64)rx_ring->dma & 0xFFFFFFFF));
1523         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1524                         ((u64) rx_ring->dma >> 32));
1525         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1526         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1527         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1528
1529         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1530         reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1531         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1532
1533         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1534         reg_data &= ~IXGBE_HLREG0_LPBK;
1535         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1536
1537         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1538 #define IXGBE_RDRXCTL_RDMTS_MASK    0x00000003 /* Receive Descriptor Minimum
1539                                                   Threshold Size mask */
1540         reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1541         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1542
1543         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1544 #define IXGBE_MCSTCTRL_MO_MASK      0x00000003 /* Multicast Offset mask */
1545         reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1546         reg_data |= adapter->hw.mac.mc_filter_type;
1547         IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1548
1549         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1550         reg_data |= IXGBE_RXDCTL_ENABLE;
1551         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1552         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1553                 int j = adapter->rx_ring[0].reg_idx;
1554                 u32 k;
1555                 for (k = 0; k < 10; k++) {
1556                         if (IXGBE_READ_REG(&adapter->hw,
1557                                            IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1558                                 break;
1559                         else
1560                                 msleep(1);
1561                 }
1562         }
1563
1564         rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1565         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1566
1567         for (i = 0; i < rx_ring->count; i++) {
1568                 struct ixgbe_legacy_rx_desc *rx_desc =
1569                                         IXGBE_RX_DESC(*rx_ring, i);
1570                 struct sk_buff *skb;
1571
1572                 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1573                 if (!skb) {
1574                         ret_val = 6;
1575                         goto err_nomem;
1576                 }
1577                 skb_reserve(skb, NET_IP_ALIGN);
1578                 rx_ring->rx_buffer_info[i].skb = skb;
1579                 rx_ring->rx_buffer_info[i].dma =
1580                         pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
1581                                        PCI_DMA_FROMDEVICE);
1582                 rx_desc->buffer_addr =
1583                                 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1584                 memset(skb->data, 0x00, skb->len);
1585         }
1586
1587         return 0;
1588
1589 err_nomem:
1590         ixgbe_free_desc_rings(adapter);
1591         return ret_val;
1592 }
1593
1594 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1595 {
1596         struct ixgbe_hw *hw = &adapter->hw;
1597         u32 reg_data;
1598
1599         /* right now we only support MAC loopback in the driver */
1600
1601         /* Setup MAC loopback */
1602         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1603         reg_data |= IXGBE_HLREG0_LPBK;
1604         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1605
1606         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1607         reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1608         reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1609         IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1610
1611         /* Disable Atlas Tx lanes; re-enabled in reset path */
1612         if (hw->mac.type == ixgbe_mac_82598EB) {
1613                 u8 atlas;
1614
1615                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1616                 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1617                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1618
1619                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1620                 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1621                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1622
1623                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1624                 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1625                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1626
1627                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1628                 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1629                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1630         }
1631
1632         return 0;
1633 }
1634
1635 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1636 {
1637         u32 reg_data;
1638
1639         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1640         reg_data &= ~IXGBE_HLREG0_LPBK;
1641         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1642 }
1643
1644 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1645                                       unsigned int frame_size)
1646 {
1647         memset(skb->data, 0xFF, frame_size);
1648         frame_size &= ~1;
1649         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1650         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1651         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1652 }
1653
1654 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1655                                     unsigned int frame_size)
1656 {
1657         frame_size &= ~1;
1658         if (*(skb->data + 3) == 0xFF) {
1659                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1660                     (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1661                         return 0;
1662                 }
1663         }
1664         return 13;
1665 }
1666
1667 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1668 {
1669         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1670         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1671         struct pci_dev *pdev = adapter->pdev;
1672         int i, j, k, l, lc, good_cnt, ret_val = 0;
1673         unsigned long time;
1674
1675         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1676
1677         /*
1678          * Calculate the loop count based on the largest descriptor ring
1679          * The idea is to wrap the largest ring a number of times using 64
1680          * send/receive pairs during each loop
1681          */
1682
1683         if (rx_ring->count <= tx_ring->count)
1684                 lc = ((tx_ring->count / 64) * 2) + 1;
1685         else
1686                 lc = ((rx_ring->count / 64) * 2) + 1;
1687
1688         k = l = 0;
1689         for (j = 0; j <= lc; j++) {
1690                 for (i = 0; i < 64; i++) {
1691                         ixgbe_create_lbtest_frame(
1692                                         tx_ring->tx_buffer_info[k].skb,
1693                                         1024);
1694                         pci_dma_sync_single_for_device(pdev,
1695                                 tx_ring->tx_buffer_info[k].dma,
1696                                 tx_ring->tx_buffer_info[k].length,
1697                                 PCI_DMA_TODEVICE);
1698                         if (unlikely(++k == tx_ring->count))
1699                                 k = 0;
1700                 }
1701                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1702                 msleep(200);
1703                 /* set the start time for the receive */
1704                 time = jiffies;
1705                 good_cnt = 0;
1706                 do {
1707                         /* receive the sent packets */
1708                         pci_dma_sync_single_for_cpu(pdev,
1709                                         rx_ring->rx_buffer_info[l].dma,
1710                                         IXGBE_RXBUFFER_2048,
1711                                         PCI_DMA_FROMDEVICE);
1712                         ret_val = ixgbe_check_lbtest_frame(
1713                                         rx_ring->rx_buffer_info[l].skb, 1024);
1714                         if (!ret_val)
1715                                 good_cnt++;
1716                         if (++l == rx_ring->count)
1717                                 l = 0;
1718                         /*
1719                          * time + 20 msecs (200 msecs on 2.4) is more than
1720                          * enough time to complete the receives, if it's
1721                          * exceeded, break and error off
1722                          */
1723                 } while (good_cnt < 64 && jiffies < (time + 20));
1724                 if (good_cnt != 64) {
1725                         /* ret_val is the same as mis-compare */
1726                         ret_val = 13;
1727                         break;
1728                 }
1729                 if (jiffies >= (time + 20)) {
1730                         /* Error code for time out error */
1731                         ret_val = 14;
1732                         break;
1733                 }
1734         }
1735
1736         return ret_val;
1737 }
1738
1739 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1740 {
1741         *data = ixgbe_setup_desc_rings(adapter);
1742         if (*data)
1743                 goto out;
1744         *data = ixgbe_setup_loopback_test(adapter);
1745         if (*data)
1746                 goto err_loopback;
1747         *data = ixgbe_run_loopback_test(adapter);
1748         ixgbe_loopback_cleanup(adapter);
1749
1750 err_loopback:
1751         ixgbe_free_desc_rings(adapter);
1752 out:
1753         return *data;
1754 }
1755
1756 static void ixgbe_diag_test(struct net_device *netdev,
1757                             struct ethtool_test *eth_test, u64 *data)
1758 {
1759         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1760         bool if_running = netif_running(netdev);
1761
1762         set_bit(__IXGBE_TESTING, &adapter->state);
1763         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1764                 /* Offline tests */
1765
1766                 DPRINTK(HW, INFO, "offline testing starting\n");
1767
1768                 /* Link test performed before hardware reset so autoneg doesn't
1769                  * interfere with test result */
1770                 if (ixgbe_link_test(adapter, &data[4]))
1771                         eth_test->flags |= ETH_TEST_FL_FAILED;
1772
1773                 if (if_running)
1774                         /* indicate we're in test mode */
1775                         dev_close(netdev);
1776                 else
1777                         ixgbe_reset(adapter);
1778
1779                 DPRINTK(HW, INFO, "register testing starting\n");
1780                 if (ixgbe_reg_test(adapter, &data[0]))
1781                         eth_test->flags |= ETH_TEST_FL_FAILED;
1782
1783                 ixgbe_reset(adapter);
1784                 DPRINTK(HW, INFO, "eeprom testing starting\n");
1785                 if (ixgbe_eeprom_test(adapter, &data[1]))
1786                         eth_test->flags |= ETH_TEST_FL_FAILED;
1787
1788                 ixgbe_reset(adapter);
1789                 DPRINTK(HW, INFO, "interrupt testing starting\n");
1790                 if (ixgbe_intr_test(adapter, &data[2]))
1791                         eth_test->flags |= ETH_TEST_FL_FAILED;
1792
1793                 ixgbe_reset(adapter);
1794                 DPRINTK(HW, INFO, "loopback testing starting\n");
1795                 if (ixgbe_loopback_test(adapter, &data[3]))
1796                         eth_test->flags |= ETH_TEST_FL_FAILED;
1797
1798                 ixgbe_reset(adapter);
1799
1800                 clear_bit(__IXGBE_TESTING, &adapter->state);
1801                 if (if_running)
1802                         dev_open(netdev);
1803         } else {
1804                 DPRINTK(HW, INFO, "online testing starting\n");
1805                 /* Online tests */
1806                 if (ixgbe_link_test(adapter, &data[4]))
1807                         eth_test->flags |= ETH_TEST_FL_FAILED;
1808
1809                 /* Online tests aren't run; pass by default */
1810                 data[0] = 0;
1811                 data[1] = 0;
1812                 data[2] = 0;
1813                 data[3] = 0;
1814
1815                 clear_bit(__IXGBE_TESTING, &adapter->state);
1816         }
1817         msleep_interruptible(4 * 1000);
1818 }
1819
1820 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1821                                struct ethtool_wolinfo *wol)
1822 {
1823         struct ixgbe_hw *hw = &adapter->hw;
1824         int retval = 1;
1825
1826         switch(hw->device_id) {
1827         case IXGBE_DEV_ID_82599_KX4:
1828                 retval = 0;
1829                 break;
1830         default:
1831                 wol->supported = 0;
1832                 retval = 0;
1833         }
1834
1835         return retval;
1836 }
1837
1838 static void ixgbe_get_wol(struct net_device *netdev,
1839                           struct ethtool_wolinfo *wol)
1840 {
1841         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1842
1843         wol->supported = WAKE_UCAST | WAKE_MCAST |
1844                          WAKE_BCAST | WAKE_MAGIC;
1845         wol->wolopts = 0;
1846
1847         if (ixgbe_wol_exclusion(adapter, wol) ||
1848             !device_can_wakeup(&adapter->pdev->dev))
1849                 return;
1850
1851         if (adapter->wol & IXGBE_WUFC_EX)
1852                 wol->wolopts |= WAKE_UCAST;
1853         if (adapter->wol & IXGBE_WUFC_MC)
1854                 wol->wolopts |= WAKE_MCAST;
1855         if (adapter->wol & IXGBE_WUFC_BC)
1856                 wol->wolopts |= WAKE_BCAST;
1857         if (adapter->wol & IXGBE_WUFC_MAG)
1858                 wol->wolopts |= WAKE_MAGIC;
1859
1860         return;
1861 }
1862
1863 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1864 {
1865         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1866
1867         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1868                 return -EOPNOTSUPP;
1869
1870         if (ixgbe_wol_exclusion(adapter, wol))
1871                 return wol->wolopts ? -EOPNOTSUPP : 0;
1872
1873         adapter->wol = 0;
1874
1875         if (wol->wolopts & WAKE_UCAST)
1876                 adapter->wol |= IXGBE_WUFC_EX;
1877         if (wol->wolopts & WAKE_MCAST)
1878                 adapter->wol |= IXGBE_WUFC_MC;
1879         if (wol->wolopts & WAKE_BCAST)
1880                 adapter->wol |= IXGBE_WUFC_BC;
1881         if (wol->wolopts & WAKE_MAGIC)
1882                 adapter->wol |= IXGBE_WUFC_MAG;
1883
1884         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1885
1886         return 0;
1887 }
1888
1889 static int ixgbe_nway_reset(struct net_device *netdev)
1890 {
1891         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1892
1893         if (netif_running(netdev))
1894                 ixgbe_reinit_locked(adapter);
1895
1896         return 0;
1897 }
1898
1899 static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1900 {
1901         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1902         struct ixgbe_hw *hw = &adapter->hw;
1903         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1904         u32 i;
1905
1906         if (!data || data > 300)
1907                 data = 300;
1908
1909         for (i = 0; i < (data * 1000); i += 400) {
1910                 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
1911                 msleep_interruptible(200);
1912                 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
1913                 msleep_interruptible(200);
1914         }
1915
1916         /* Restore LED settings */
1917         IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1918
1919         return 0;
1920 }
1921
1922 static int ixgbe_get_coalesce(struct net_device *netdev,
1923                               struct ethtool_coalesce *ec)
1924 {
1925         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1926
1927         ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
1928
1929         /* only valid if in constant ITR mode */
1930         switch (adapter->itr_setting) {
1931         case 0:
1932                 /* throttling disabled */
1933                 ec->rx_coalesce_usecs = 0;
1934                 break;
1935         case 1:
1936                 /* dynamic ITR mode */
1937                 ec->rx_coalesce_usecs = 1;
1938                 break;
1939         default:
1940                 /* fixed interrupt rate mode */
1941                 ec->rx_coalesce_usecs = 1000000/adapter->eitr_param;
1942                 break;
1943         }
1944         return 0;
1945 }
1946
1947 static int ixgbe_set_coalesce(struct net_device *netdev,
1948                               struct ethtool_coalesce *ec)
1949 {
1950         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1951         int i;
1952
1953         if (ec->tx_max_coalesced_frames_irq)
1954                 adapter->tx_ring[0].work_limit = ec->tx_max_coalesced_frames_irq;
1955
1956         if (ec->rx_coalesce_usecs > 1) {
1957                 /* check the limits */
1958                 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
1959                     (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
1960                         return -EINVAL;
1961
1962                 /* store the value in ints/second */
1963                 adapter->eitr_param = 1000000/ec->rx_coalesce_usecs;
1964
1965                 /* static value of interrupt rate */
1966                 adapter->itr_setting = adapter->eitr_param;
1967                 /* clear the lower bit as its used for dynamic state */
1968                 adapter->itr_setting &= ~1;
1969         } else if (ec->rx_coalesce_usecs == 1) {
1970                 /* 1 means dynamic mode */
1971                 adapter->eitr_param = 20000;
1972                 adapter->itr_setting = 1;
1973         } else {
1974                 /*
1975                  * any other value means disable eitr, which is best
1976                  * served by setting the interrupt rate very high
1977                  */
1978                 adapter->eitr_param = IXGBE_MAX_INT_RATE;
1979                 adapter->itr_setting = 0;
1980         }
1981
1982         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
1983                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1984                 if (q_vector->txr_count && !q_vector->rxr_count)
1985                         /* tx vector gets half the rate */
1986                         q_vector->eitr = (adapter->eitr_param >> 1);
1987                 else
1988                         /* rx only or mixed */
1989                         q_vector->eitr = adapter->eitr_param;
1990                 ixgbe_write_eitr(q_vector);
1991         }
1992
1993         return 0;
1994 }
1995
1996 static int ixgbe_set_flags(struct net_device *netdev, u32 data)
1997 {
1998         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1999
2000         ethtool_op_set_flags(netdev, data);
2001
2002         if (!(adapter->flags & IXGBE_FLAG2_RSC_CAPABLE))
2003                 return 0;
2004
2005         /* if state changes we need to update adapter->flags and reset */
2006         if ((!!(data & ETH_FLAG_LRO)) != 
2007             (!!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED))) {
2008                 adapter->flags ^= IXGBE_FLAG2_RSC_ENABLED;
2009                 if (netif_running(netdev))
2010                         ixgbe_reinit_locked(adapter);
2011                 else
2012                         ixgbe_reset(adapter);
2013         }
2014         return 0;
2015
2016 }
2017
2018 static const struct ethtool_ops ixgbe_ethtool_ops = {
2019         .get_settings           = ixgbe_get_settings,
2020         .set_settings           = ixgbe_set_settings,
2021         .get_drvinfo            = ixgbe_get_drvinfo,
2022         .get_regs_len           = ixgbe_get_regs_len,
2023         .get_regs               = ixgbe_get_regs,
2024         .get_wol                = ixgbe_get_wol,
2025         .set_wol                = ixgbe_set_wol,
2026         .nway_reset             = ixgbe_nway_reset,
2027         .get_link               = ethtool_op_get_link,
2028         .get_eeprom_len         = ixgbe_get_eeprom_len,
2029         .get_eeprom             = ixgbe_get_eeprom,
2030         .get_ringparam          = ixgbe_get_ringparam,
2031         .set_ringparam          = ixgbe_set_ringparam,
2032         .get_pauseparam         = ixgbe_get_pauseparam,
2033         .set_pauseparam         = ixgbe_set_pauseparam,
2034         .get_rx_csum            = ixgbe_get_rx_csum,
2035         .set_rx_csum            = ixgbe_set_rx_csum,
2036         .get_tx_csum            = ixgbe_get_tx_csum,
2037         .set_tx_csum            = ixgbe_set_tx_csum,
2038         .get_sg                 = ethtool_op_get_sg,
2039         .set_sg                 = ethtool_op_set_sg,
2040         .get_msglevel           = ixgbe_get_msglevel,
2041         .set_msglevel           = ixgbe_set_msglevel,
2042         .get_tso                = ethtool_op_get_tso,
2043         .set_tso                = ixgbe_set_tso,
2044         .self_test              = ixgbe_diag_test,
2045         .get_strings            = ixgbe_get_strings,
2046         .phys_id                = ixgbe_phys_id,
2047         .get_sset_count         = ixgbe_get_sset_count,
2048         .get_ethtool_stats      = ixgbe_get_ethtool_stats,
2049         .get_coalesce           = ixgbe_get_coalesce,
2050         .set_coalesce           = ixgbe_set_coalesce,
2051         .get_flags              = ethtool_op_get_flags,
2052         .set_flags              = ixgbe_set_flags,
2053 };
2054
2055 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2056 {
2057         SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2058 }