3 # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4 # Licensed and distributed under the GPL
8 bool "EDAC - error detection and reporting"
12 EDAC is designed to report errors in the core system.
13 These are low-level errors that are reported in the CPU or
14 supporting chipset or other subsystems:
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
16 If unsure, select 'Y'.
18 If this code is reporting problems on your system, please
19 see the EDAC project web pages for more information at:
21 <http://bluesmoke.sourceforge.net/>
25 <http://buttersideup.com/edacwiki>
27 There is also a mailing list for the EDAC project, which can
28 be found via the sourceforge page.
32 comment "Reporting subsystems"
37 This turns on debugging information for the entire EDAC
38 sub-system. You can insert module with "debug_level=x", current
39 there're four debug levels (x=0,1,2,3 from low to high).
40 Usually you should select 'N'.
42 config EDAC_DEBUG_VERBOSE
43 bool "More verbose debugging"
46 This option makes debugging information more verbose.
47 Source file name and line number where debugging message
48 printed will be added to debugging message.
51 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
54 Some systems are able to detect and correct errors in main
55 memory. EDAC can report statistics on memory error
56 detection and correction (EDAC - or commonly referred to ECC
57 errors). EDAC will also try to decode where these errors
58 occurred so that a particular failing memory module can be
59 replaced. If unsure, select 'Y'.
62 tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
63 depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI
65 Support for error detection and correction on the AMD 64
66 Families of Memory Controllers (K8, F10h and F11h)
68 config EDAC_AMD64_ERROR_INJECTION
69 bool "Sysfs Error Injection facilities"
72 Recent Opterons (Family 10h and later) provide for Memory Error
73 Injection into the ECC detection circuits. The amd64_edac module
74 allows the operator/user to inject Uncorrectable and Correctable
77 When enabled, in each of the respective memory controller directories
78 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
80 - inject_section (0..3, 16-byte section of 64-byte cacheline),
81 - inject_word (0..8, 16-bit word of 16-byte section),
82 - inject_ecc_vector (hex ecc vector: select bits of inject word)
84 In addition, there are two control files, inject_read and inject_write,
85 which trigger the DRAM ECC Read and Write respectively.
88 tristate "AMD 76x (760, 762, 768)"
89 depends on EDAC_MM_EDAC && PCI && X86_32
91 Support for error detection and correction on the AMD 76x
92 series of chipsets used with the Athlon processor.
95 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
96 depends on EDAC_MM_EDAC && PCI && X86_32
98 Support for error detection and correction on the Intel
99 E7205, E7500, E7501 and E7505 server chipsets.
102 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
103 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
105 Support for error detection and correction on the Intel
106 E7520, E7525, E7320 server chipsets.
108 config EDAC_I82443BXGX
109 tristate "Intel 82443BX/GX (440BX/GX)"
110 depends on EDAC_MM_EDAC && PCI && X86_32
113 Support for error detection and correction on the Intel
114 82443BX/GX memory controllers (440BX/GX chipsets).
117 tristate "Intel 82875p (D82875P, E7210)"
118 depends on EDAC_MM_EDAC && PCI && X86_32
120 Support for error detection and correction on the Intel
121 DP82785P and E7210 server chipsets.
124 tristate "Intel 82975x (D82975x)"
125 depends on EDAC_MM_EDAC && PCI && X86
127 Support for error detection and correction on the Intel
128 DP82975x server chipsets.
131 tristate "Intel 3000/3010"
132 depends on EDAC_MM_EDAC && PCI && X86
134 Support for error detection and correction on the Intel
135 3000 and 3010 server chipsets.
139 depends on EDAC_MM_EDAC && PCI && X86
141 Support for error detection and correction on the Intel
145 tristate "Intel 5400 (Seaburg) chipsets"
146 depends on EDAC_MM_EDAC && PCI && X86
148 Support for error detection and correction the Intel
149 i5400 MCH chipset (Seaburg).
152 tristate "Intel 82860"
153 depends on EDAC_MM_EDAC && PCI && X86_32
155 Support for error detection and correction on the Intel
159 tristate "Radisys 82600 embedded chipset"
160 depends on EDAC_MM_EDAC && PCI && X86_32
162 Support for error detection and correction on the Radisys
163 82600 embedded chipset.
166 tristate "Intel Greencreek/Blackford chipset"
167 depends on EDAC_MM_EDAC && X86 && PCI
169 Support for error detection and correction the Intel
170 Greekcreek/Blackford chipsets.
173 tristate "Intel San Clemente MCH"
174 depends on EDAC_MM_EDAC && X86 && PCI
176 Support for error detection and correction the Intel
180 tristate "Freescale MPC85xx"
181 depends on EDAC_MM_EDAC && FSL_SOC && MPC85xx
183 Support for error detection and correction on the Freescale
184 MPC8560, MPC8540, MPC8548
187 tristate "Marvell MV64x60"
188 depends on EDAC_MM_EDAC && MV64X60
190 Support for error detection and correction on the Marvell
191 MV64360 and MV64460 chipsets.
194 tristate "PA Semi PWRficient"
195 depends on EDAC_MM_EDAC && PCI
196 depends on PPC_PASEMI
198 Support for error detection and correction on PA Semi
202 tristate "Cell Broadband Engine memory controller"
203 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
205 Support for error detection and correction on the
206 Cell Broadband Engine internal memory controller
207 on platform without a hypervisor
210 tristate "PPC4xx IBM DDR2 Memory Controller"
211 depends on EDAC_MM_EDAC && 4xx
213 This enables support for EDAC on the ECC memory used
214 with the IBM DDR2 memory controller found in various
215 PowerPC 4xx embedded processors such as the 405EX[r],
216 440SP, 440SPe, 460EX, 460GT and 460SX.
219 tristate "AMD8131 HyperTransport PCI-X Tunnel"
220 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
222 Support for error detection and correction on the
223 AMD8131 HyperTransport PCI-X Tunnel chip.
224 Note, add more Kconfig dependency if it's adopted
225 on some machine other than Maple.
228 tristate "AMD8111 HyperTransport I/O Hub"
229 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
231 Support for error detection and correction on the
232 AMD8111 HyperTransport I/O Hub chip.
233 Note, add more Kconfig dependency if it's adopted
234 on some machine other than Maple.