drm: add initial r500 drm support
[linux-2.6] / drivers / char / drm / via_dma.c
1 /* via_dma.c -- DMA support for the VIA Unichrome/Pro
2  *
3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4  * All Rights Reserved.
5  *
6  * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
7  * All Rights Reserved.
8  *
9  * Copyright 2004 The Unichrome project.
10  * All Rights Reserved.
11  *
12  * Permission is hereby granted, free of charge, to any person obtaining a
13  * copy of this software and associated documentation files (the "Software"),
14  * to deal in the Software without restriction, including without limitation
15  * the rights to use, copy, modify, merge, publish, distribute, sub license,
16  * and/or sell copies of the Software, and to permit persons to whom the
17  * Software is furnished to do so, subject to the following conditions:
18  *
19  * The above copyright notice and this permission notice (including the
20  * next paragraph) shall be included in all copies or substantial portions
21  * of the Software.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
26  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
27  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
28  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
29  * USE OR OTHER DEALINGS IN THE SOFTWARE.
30  *
31  * Authors:
32  *    Tungsten Graphics,
33  *    Erdi Chen,
34  *    Thomas Hellstrom.
35  */
36
37 #include "drmP.h"
38 #include "drm.h"
39 #include "via_drm.h"
40 #include "via_drv.h"
41 #include "via_3d_reg.h"
42
43 #define CMDBUF_ALIGNMENT_SIZE   (0x100)
44 #define CMDBUF_ALIGNMENT_MASK   (0x0ff)
45
46 /* defines for VIA 3D registers */
47 #define VIA_REG_STATUS          0x400
48 #define VIA_REG_TRANSET         0x43C
49 #define VIA_REG_TRANSPACE       0x440
50
51 /* VIA_REG_STATUS(0x400): Engine Status */
52 #define VIA_CMD_RGTR_BUSY       0x00000080      /* Command Regulator is busy */
53 #define VIA_2D_ENG_BUSY         0x00000001      /* 2D Engine is busy */
54 #define VIA_3D_ENG_BUSY         0x00000002      /* 3D Engine is busy */
55 #define VIA_VR_QUEUE_BUSY       0x00020000      /* Virtual Queue is busy */
56
57 #define SetReg2DAGP(nReg, nData) {                              \
58         *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1;  \
59         *((uint32_t *)(vb) + 1) = (nData);                      \
60         vb = ((uint32_t *)vb) + 2;                              \
61         dev_priv->dma_low +=8;                                  \
62 }
63
64 #define via_flush_write_combine() DRM_MEMORYBARRIER()
65
66 #define VIA_OUT_RING_QW(w1,w2)                  \
67         *vb++ = (w1);                           \
68         *vb++ = (w2);                           \
69         dev_priv->dma_low += 8;
70
71 static void via_cmdbuf_start(drm_via_private_t * dev_priv);
72 static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
73 static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
74 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
75 static int via_wait_idle(drm_via_private_t * dev_priv);
76 static void via_pad_cache(drm_via_private_t * dev_priv, int qwords);
77
78 /*
79  * Free space in command buffer.
80  */
81
82 static uint32_t via_cmdbuf_space(drm_via_private_t * dev_priv)
83 {
84         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
85         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
86
87         return ((hw_addr <= dev_priv->dma_low) ?
88                 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
89                 (hw_addr - dev_priv->dma_low));
90 }
91
92 /*
93  * How much does the command regulator lag behind?
94  */
95
96 static uint32_t via_cmdbuf_lag(drm_via_private_t * dev_priv)
97 {
98         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
99         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
100
101         return ((hw_addr <= dev_priv->dma_low) ?
102                 (dev_priv->dma_low - hw_addr) :
103                 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
104 }
105
106 /*
107  * Check that the given size fits in the buffer, otherwise wait.
108  */
109
110 static inline int
111 via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
112 {
113         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
114         uint32_t cur_addr, hw_addr, next_addr;
115         volatile uint32_t *hw_addr_ptr;
116         uint32_t count;
117         hw_addr_ptr = dev_priv->hw_addr_ptr;
118         cur_addr = dev_priv->dma_low;
119         next_addr = cur_addr + size + 512 * 1024;
120         count = 1000000;
121         do {
122                 hw_addr = *hw_addr_ptr - agp_base;
123                 if (count-- == 0) {
124                         DRM_ERROR
125                             ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
126                              hw_addr, cur_addr, next_addr);
127                         return -1;
128                 }
129         } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
130         return 0;
131 }
132
133 /*
134  * Checks whether buffer head has reach the end. Rewind the ring buffer
135  * when necessary.
136  *
137  * Returns virtual pointer to ring buffer.
138  */
139
140 static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
141                                       unsigned int size)
142 {
143         if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >
144             dev_priv->dma_high) {
145                 via_cmdbuf_rewind(dev_priv);
146         }
147         if (via_cmdbuf_wait(dev_priv, size) != 0) {
148                 return NULL;
149         }
150
151         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
152 }
153
154 int via_dma_cleanup(struct drm_device * dev)
155 {
156         if (dev->dev_private) {
157                 drm_via_private_t *dev_priv =
158                     (drm_via_private_t *) dev->dev_private;
159
160                 if (dev_priv->ring.virtual_start) {
161                         via_cmdbuf_reset(dev_priv);
162
163                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
164                         dev_priv->ring.virtual_start = NULL;
165                 }
166
167         }
168
169         return 0;
170 }
171
172 static int via_initialize(struct drm_device * dev,
173                           drm_via_private_t * dev_priv,
174                           drm_via_dma_init_t * init)
175 {
176         if (!dev_priv || !dev_priv->mmio) {
177                 DRM_ERROR("via_dma_init called before via_map_init\n");
178                 return -EFAULT;
179         }
180
181         if (dev_priv->ring.virtual_start != NULL) {
182                 DRM_ERROR("called again without calling cleanup\n");
183                 return -EFAULT;
184         }
185
186         if (!dev->agp || !dev->agp->base) {
187                 DRM_ERROR("called with no agp memory available\n");
188                 return -EFAULT;
189         }
190
191         if (dev_priv->chipset == VIA_DX9_0) {
192                 DRM_ERROR("AGP DMA is not supported on this chip\n");
193                 return -EINVAL;
194         }
195
196         dev_priv->ring.map.offset = dev->agp->base + init->offset;
197         dev_priv->ring.map.size = init->size;
198         dev_priv->ring.map.type = 0;
199         dev_priv->ring.map.flags = 0;
200         dev_priv->ring.map.mtrr = 0;
201
202         drm_core_ioremap(&dev_priv->ring.map, dev);
203
204         if (dev_priv->ring.map.handle == NULL) {
205                 via_dma_cleanup(dev);
206                 DRM_ERROR("can not ioremap virtual address for"
207                           " ring buffer\n");
208                 return -ENOMEM;
209         }
210
211         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
212
213         dev_priv->dma_ptr = dev_priv->ring.virtual_start;
214         dev_priv->dma_low = 0;
215         dev_priv->dma_high = init->size;
216         dev_priv->dma_wrap = init->size;
217         dev_priv->dma_offset = init->offset;
218         dev_priv->last_pause_ptr = NULL;
219         dev_priv->hw_addr_ptr =
220                 (volatile uint32_t *)((char *)dev_priv->mmio->handle +
221                 init->reg_pause_addr);
222
223         via_cmdbuf_start(dev_priv);
224
225         return 0;
226 }
227
228 static int via_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
229 {
230         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
231         drm_via_dma_init_t *init = data;
232         int retcode = 0;
233
234         switch (init->func) {
235         case VIA_INIT_DMA:
236                 if (!DRM_SUSER(DRM_CURPROC))
237                         retcode = -EPERM;
238                 else
239                         retcode = via_initialize(dev, dev_priv, init);
240                 break;
241         case VIA_CLEANUP_DMA:
242                 if (!DRM_SUSER(DRM_CURPROC))
243                         retcode = -EPERM;
244                 else
245                         retcode = via_dma_cleanup(dev);
246                 break;
247         case VIA_DMA_INITIALIZED:
248                 retcode = (dev_priv->ring.virtual_start != NULL) ?
249                         0 : -EFAULT;
250                 break;
251         default:
252                 retcode = -EINVAL;
253                 break;
254         }
255
256         return retcode;
257 }
258
259 static int via_dispatch_cmdbuffer(struct drm_device * dev, drm_via_cmdbuffer_t * cmd)
260 {
261         drm_via_private_t *dev_priv;
262         uint32_t *vb;
263         int ret;
264
265         dev_priv = (drm_via_private_t *) dev->dev_private;
266
267         if (dev_priv->ring.virtual_start == NULL) {
268                 DRM_ERROR("called without initializing AGP ring buffer.\n");
269                 return -EFAULT;
270         }
271
272         if (cmd->size > VIA_PCI_BUF_SIZE) {
273                 return -ENOMEM;
274         }
275
276         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
277                 return -EFAULT;
278
279         /*
280          * Running this function on AGP memory is dead slow. Therefore
281          * we run it on a temporary cacheable system memory buffer and
282          * copy it to AGP memory when ready.
283          */
284
285         if ((ret =
286              via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
287                                        cmd->size, dev, 1))) {
288                 return ret;
289         }
290
291         vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
292         if (vb == NULL) {
293                 return -EAGAIN;
294         }
295
296         memcpy(vb, dev_priv->pci_buf, cmd->size);
297
298         dev_priv->dma_low += cmd->size;
299
300         /*
301          * Small submissions somehow stalls the CPU. (AGP cache effects?)
302          * pad to greater size.
303          */
304
305         if (cmd->size < 0x100)
306                 via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);
307         via_cmdbuf_pause(dev_priv);
308
309         return 0;
310 }
311
312 int via_driver_dma_quiescent(struct drm_device * dev)
313 {
314         drm_via_private_t *dev_priv = dev->dev_private;
315
316         if (!via_wait_idle(dev_priv)) {
317                 return -EBUSY;
318         }
319         return 0;
320 }
321
322 static int via_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
323 {
324
325         LOCK_TEST_WITH_RETURN(dev, file_priv);
326
327         return via_driver_dma_quiescent(dev);
328 }
329
330 static int via_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)
331 {
332         drm_via_cmdbuffer_t *cmdbuf = data;
333         int ret;
334
335         LOCK_TEST_WITH_RETURN(dev, file_priv);
336
337         DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size);
338
339         ret = via_dispatch_cmdbuffer(dev, cmdbuf);
340         if (ret) {
341                 return ret;
342         }
343
344         return 0;
345 }
346
347 static int via_dispatch_pci_cmdbuffer(struct drm_device * dev,
348                                       drm_via_cmdbuffer_t * cmd)
349 {
350         drm_via_private_t *dev_priv = dev->dev_private;
351         int ret;
352
353         if (cmd->size > VIA_PCI_BUF_SIZE) {
354                 return -ENOMEM;
355         }
356         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
357                 return -EFAULT;
358
359         if ((ret =
360              via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
361                                        cmd->size, dev, 0))) {
362                 return ret;
363         }
364
365         ret =
366             via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
367                                      cmd->size);
368         return ret;
369 }
370
371 static int via_pci_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)
372 {
373         drm_via_cmdbuffer_t *cmdbuf = data;
374         int ret;
375
376         LOCK_TEST_WITH_RETURN(dev, file_priv);
377
378         DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size);
379
380         ret = via_dispatch_pci_cmdbuffer(dev, cmdbuf);
381         if (ret) {
382                 return ret;
383         }
384
385         return 0;
386 }
387
388 static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
389                                          uint32_t * vb, int qw_count)
390 {
391         for (; qw_count > 0; --qw_count) {
392                 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
393         }
394         return vb;
395 }
396
397 /*
398  * This function is used internally by ring buffer management code.
399  *
400  * Returns virtual pointer to ring buffer.
401  */
402 static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
403 {
404         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
405 }
406
407 /*
408  * Hooks a segment of data into the tail of the ring-buffer by
409  * modifying the pause address stored in the buffer itself. If
410  * the regulator has already paused, restart it.
411  */
412 static int via_hook_segment(drm_via_private_t * dev_priv,
413                             uint32_t pause_addr_hi, uint32_t pause_addr_lo,
414                             int no_pci_fire)
415 {
416         int paused, count;
417         volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
418         uint32_t reader,ptr;
419
420         paused = 0;
421         via_flush_write_combine();
422         (void) *(volatile uint32_t *)(via_get_dma(dev_priv) -1);
423         *paused_at = pause_addr_lo;
424         via_flush_write_combine();
425         (void) *paused_at;
426         reader = *(dev_priv->hw_addr_ptr);
427         ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
428                 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
429         dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
430
431         if ((ptr - reader) <= dev_priv->dma_diff ) {
432                 count = 10000000;
433                 while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--);
434         }
435
436         if (paused && !no_pci_fire) {
437                 reader = *(dev_priv->hw_addr_ptr);
438                 if ((ptr - reader) == dev_priv->dma_diff) {
439
440                         /*
441                          * There is a concern that these writes may stall the PCI bus
442                          * if the GPU is not idle. However, idling the GPU first
443                          * doesn't make a difference.
444                          */
445
446                         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
447                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
448                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
449                         VIA_READ(VIA_REG_TRANSPACE);
450                 }
451         }
452         return paused;
453 }
454
455 static int via_wait_idle(drm_via_private_t * dev_priv)
456 {
457         int count = 10000000;
458
459         while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && count--);
460
461         while (count-- && (VIA_READ(VIA_REG_STATUS) &
462                            (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
463                             VIA_3D_ENG_BUSY))) ;
464         return count;
465 }
466
467 static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
468                                uint32_t addr, uint32_t * cmd_addr_hi,
469                                uint32_t * cmd_addr_lo, int skip_wait)
470 {
471         uint32_t agp_base;
472         uint32_t cmd_addr, addr_lo, addr_hi;
473         uint32_t *vb;
474         uint32_t qw_pad_count;
475
476         if (!skip_wait)
477                 via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
478
479         vb = via_get_dma(dev_priv);
480         VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
481                         (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
482         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
483         qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
484             ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
485
486         cmd_addr = (addr) ? addr :
487             agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
488         addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
489                    (cmd_addr & HC_HAGPBpL_MASK));
490         addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
491
492         vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
493         VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);
494         return vb;
495 }
496
497 static void via_cmdbuf_start(drm_via_private_t * dev_priv)
498 {
499         uint32_t pause_addr_lo, pause_addr_hi;
500         uint32_t start_addr, start_addr_lo;
501         uint32_t end_addr, end_addr_lo;
502         uint32_t command;
503         uint32_t agp_base;
504         uint32_t ptr;
505         uint32_t reader;
506         int count;
507
508         dev_priv->dma_low = 0;
509
510         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
511         start_addr = agp_base;
512         end_addr = agp_base + dev_priv->dma_high;
513
514         start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
515         end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
516         command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
517                    ((end_addr & 0xff000000) >> 16));
518
519         dev_priv->last_pause_ptr =
520             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
521                           &pause_addr_hi, &pause_addr_lo, 1) - 1;
522
523         via_flush_write_combine();
524         (void) *(volatile uint32_t *)dev_priv->last_pause_ptr;
525
526         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
527         VIA_WRITE(VIA_REG_TRANSPACE, command);
528         VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
529         VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
530
531         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
532         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
533         DRM_WRITEMEMORYBARRIER();
534         VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
535         VIA_READ(VIA_REG_TRANSPACE);
536
537         dev_priv->dma_diff = 0;
538
539         count = 10000000;
540         while (!(VIA_READ(0x41c) & 0x80000000) && count--);
541
542         reader = *(dev_priv->hw_addr_ptr);
543         ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
544             dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
545
546         /*
547          * This is the difference between where we tell the
548          * command reader to pause and where it actually pauses.
549          * This differs between hw implementation so we need to
550          * detect it.
551          */
552
553         dev_priv->dma_diff = ptr - reader;
554 }
555
556 static void via_pad_cache(drm_via_private_t * dev_priv, int qwords)
557 {
558         uint32_t *vb;
559
560         via_cmdbuf_wait(dev_priv, qwords + 2);
561         vb = via_get_dma(dev_priv);
562         VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16);
563         via_align_buffer(dev_priv, vb, qwords);
564 }
565
566 static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
567 {
568         uint32_t *vb = via_get_dma(dev_priv);
569         SetReg2DAGP(0x0C, (0 | (0 << 16)));
570         SetReg2DAGP(0x10, 0 | (0 << 16));
571         SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
572 }
573
574 static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
575 {
576         uint32_t agp_base;
577         uint32_t pause_addr_lo, pause_addr_hi;
578         uint32_t jump_addr_lo, jump_addr_hi;
579         volatile uint32_t *last_pause_ptr;
580
581         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
582         via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
583                       &jump_addr_lo, 0);
584
585         dev_priv->dma_wrap = dev_priv->dma_low;
586
587         /*
588          * Wrap command buffer to the beginning.
589          */
590
591         dev_priv->dma_low = 0;
592         if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
593                 DRM_ERROR("via_cmdbuf_jump failed\n");
594         }
595
596         via_dummy_bitblt(dev_priv);
597         via_dummy_bitblt(dev_priv);
598
599         last_pause_ptr =
600             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
601                           &pause_addr_lo, 0) - 1;
602         via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
603                       &pause_addr_lo, 0);
604
605         *last_pause_ptr = pause_addr_lo;
606
607         via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0);
608 }
609
610
611 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
612 {
613         via_cmdbuf_jump(dev_priv);
614 }
615
616 static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
617 {
618         uint32_t pause_addr_lo, pause_addr_hi;
619
620         via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
621         via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
622 }
623
624 static void via_cmdbuf_pause(drm_via_private_t * dev_priv)
625 {
626         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
627 }
628
629 static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
630 {
631         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
632         via_wait_idle(dev_priv);
633 }
634
635 /*
636  * User interface to the space and lag functions.
637  */
638
639 static int via_cmdbuf_size(struct drm_device *dev, void *data, struct drm_file *file_priv)
640 {
641         drm_via_cmdbuf_size_t *d_siz = data;
642         int ret = 0;
643         uint32_t tmp_size, count;
644         drm_via_private_t *dev_priv;
645
646         DRM_DEBUG("\n");
647         LOCK_TEST_WITH_RETURN(dev, file_priv);
648
649         dev_priv = (drm_via_private_t *) dev->dev_private;
650
651         if (dev_priv->ring.virtual_start == NULL) {
652                 DRM_ERROR("called without initializing AGP ring buffer.\n");
653                 return -EFAULT;
654         }
655
656         count = 1000000;
657         tmp_size = d_siz->size;
658         switch (d_siz->func) {
659         case VIA_CMDBUF_SPACE:
660                 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz->size)
661                        && count--) {
662                         if (!d_siz->wait) {
663                                 break;
664                         }
665                 }
666                 if (!count) {
667                         DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
668                         ret = -EAGAIN;
669                 }
670                 break;
671         case VIA_CMDBUF_LAG:
672                 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz->size)
673                        && count--) {
674                         if (!d_siz->wait) {
675                                 break;
676                         }
677                 }
678                 if (!count) {
679                         DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
680                         ret = -EAGAIN;
681                 }
682                 break;
683         default:
684                 ret = -EFAULT;
685         }
686         d_siz->size = tmp_size;
687
688         return ret;
689 }
690
691 struct drm_ioctl_desc via_ioctls[] = {
692         DRM_IOCTL_DEF(DRM_VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH),
693         DRM_IOCTL_DEF(DRM_VIA_FREEMEM, via_mem_free, DRM_AUTH),
694         DRM_IOCTL_DEF(DRM_VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER),
695         DRM_IOCTL_DEF(DRM_VIA_FB_INIT, via_fb_init, DRM_AUTH|DRM_MASTER),
696         DRM_IOCTL_DEF(DRM_VIA_MAP_INIT, via_map_init, DRM_AUTH|DRM_MASTER),
697         DRM_IOCTL_DEF(DRM_VIA_DEC_FUTEX, via_decoder_futex, DRM_AUTH),
698         DRM_IOCTL_DEF(DRM_VIA_DMA_INIT, via_dma_init, DRM_AUTH),
699         DRM_IOCTL_DEF(DRM_VIA_CMDBUFFER, via_cmdbuffer, DRM_AUTH),
700         DRM_IOCTL_DEF(DRM_VIA_FLUSH, via_flush_ioctl, DRM_AUTH),
701         DRM_IOCTL_DEF(DRM_VIA_PCICMD, via_pci_cmdbuffer, DRM_AUTH),
702         DRM_IOCTL_DEF(DRM_VIA_CMDBUF_SIZE, via_cmdbuf_size, DRM_AUTH),
703         DRM_IOCTL_DEF(DRM_VIA_WAIT_IRQ, via_wait_irq, DRM_AUTH),
704         DRM_IOCTL_DEF(DRM_VIA_DMA_BLIT, via_dma_blit, DRM_AUTH),
705         DRM_IOCTL_DEF(DRM_VIA_BLIT_SYNC, via_dma_blit_sync, DRM_AUTH)
706 };
707
708 int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls);