2 * TQM 8560 Device Tree Source
4 * Copyright 2008 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
16 model = "tqc,tqm8560";
17 compatible = "tqc,tqm8560";
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
40 i-cache-size = <32768>;
41 timebase-frequency = <0>;
43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
49 device_type = "memory";
50 reg = <0x00000000 0x10000000>;
57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x200>;
60 compatible = "fsl,mpc8560-immr", "simple-bus";
62 memory-controller@2000 {
63 compatible = "fsl,8540-memory-controller";
64 reg = <0x2000 0x1000>;
65 interrupt-parent = <&mpic>;
69 L2: l2-cache-controller@20000 {
70 compatible = "fsl,8540-l2-cache-controller";
71 reg = <0x20000 0x1000>;
72 cache-line-size = <32>;
73 cache-size = <0x40000>; // L2, 256K
74 interrupt-parent = <&mpic>;
82 compatible = "fsl-i2c";
85 interrupt-parent = <&mpic>;
89 compatible = "dallas,ds1337";
97 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
99 ranges = <0x0 0x21100 0x200>;
102 compatible = "fsl,mpc8560-dma-channel",
103 "fsl,eloplus-dma-channel";
106 interrupt-parent = <&mpic>;
110 compatible = "fsl,mpc8560-dma-channel",
111 "fsl,eloplus-dma-channel";
114 interrupt-parent = <&mpic>;
118 compatible = "fsl,mpc8560-dma-channel",
119 "fsl,eloplus-dma-channel";
122 interrupt-parent = <&mpic>;
126 compatible = "fsl,mpc8560-dma-channel",
127 "fsl,eloplus-dma-channel";
130 interrupt-parent = <&mpic>;
136 #address-cells = <1>;
138 compatible = "fsl,gianfar-mdio";
139 reg = <0x24520 0x20>;
141 phy1: ethernet-phy@1 {
142 interrupt-parent = <&mpic>;
145 device_type = "ethernet-phy";
147 phy2: ethernet-phy@2 {
148 interrupt-parent = <&mpic>;
151 device_type = "ethernet-phy";
153 phy3: ethernet-phy@3 {
154 interrupt-parent = <&mpic>;
157 device_type = "ethernet-phy";
161 enet0: ethernet@24000 {
163 device_type = "network";
165 compatible = "gianfar";
166 reg = <0x24000 0x1000>;
167 local-mac-address = [ 00 00 00 00 00 00 ];
168 interrupts = <29 2 30 2 34 2>;
169 interrupt-parent = <&mpic>;
170 phy-handle = <&phy2>;
173 enet1: ethernet@25000 {
175 device_type = "network";
177 compatible = "gianfar";
178 reg = <0x25000 0x1000>;
179 local-mac-address = [ 00 00 00 00 00 00 ];
180 interrupts = <35 2 36 2 40 2>;
181 interrupt-parent = <&mpic>;
182 phy-handle = <&phy1>;
186 interrupt-controller;
187 #address-cells = <0>;
188 #interrupt-cells = <2>;
189 reg = <0x40000 0x40000>;
190 device_type = "open-pic";
191 compatible = "chrp,open-pic";
195 #address-cells = <1>;
197 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
198 reg = <0x919c0 0x30>;
202 #address-cells = <1>;
204 ranges = <0 0x80000 0x10000>;
207 compatible = "fsl,cpm-muram-data";
208 reg = <0 0x4000 0x9000 0x2000>;
213 compatible = "fsl,mpc8560-brg",
216 reg = <0x919f0 0x10 0x915f0 0x10>;
217 clock-frequency = <0>;
221 interrupt-controller;
222 #address-cells = <0>;
223 #interrupt-cells = <2>;
225 interrupt-parent = <&mpic>;
226 reg = <0x90c00 0x80>;
227 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
230 serial0: serial@91a00 {
231 device_type = "serial";
232 compatible = "fsl,mpc8560-scc-uart",
234 reg = <0x91a00 0x20 0x88000 0x100>;
236 fsl,cpm-command = <0x800000>;
237 current-speed = <115200>;
239 interrupt-parent = <&cpmpic>;
242 serial1: serial@91a20 {
243 device_type = "serial";
244 compatible = "fsl,mpc8560-scc-uart",
246 reg = <0x91a20 0x20 0x88100 0x100>;
248 fsl,cpm-command = <0x4a00000>;
249 current-speed = <115200>;
251 interrupt-parent = <&cpmpic>;
254 enet2: ethernet@91340 {
255 device_type = "network";
256 compatible = "fsl,mpc8560-fcc-enet",
258 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
259 local-mac-address = [ 00 00 00 00 00 00 ];
260 fsl,cpm-command = <0x1a400300>;
262 interrupt-parent = <&cpmpic>;
263 phy-handle = <&phy3>;
269 compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
271 #address-cells = <2>;
273 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
276 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
277 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
278 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
282 #address-cells = <1>;
284 compatible = "cfi-flash";
285 reg = <1 0x0 0x8000000>;
291 reg = <0x00000000 0x00200000>;
295 reg = <0x00200000 0x00300000>;
299 reg = <0x00500000 0x07a00000>;
303 reg = <0x07f00000 0x00040000>;
307 reg = <0x07f40000 0x00040000>;
311 reg = <0x07f80000 0x00080000>;
316 /* Note: CAN support needs be enabled in U-Boot */
318 compatible = "intel,82527"; // Bosch CC770
321 interrupt-parent = <&mpic>;
325 compatible = "intel,82527"; // Bosch CC770
326 reg = <2 0x100 0x100>;
328 interrupt-parent = <&mpic>;
334 #interrupt-cells = <1>;
336 #address-cells = <3>;
337 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
339 reg = <0xe0008000 0x1000>;
340 clock-frequency = <66666666>;
341 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
344 0xe000 0 0 1 &mpic 2 1
345 0xe000 0 0 2 &mpic 3 1>;
347 interrupt-parent = <&mpic>;
350 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
351 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;