2 * SGI UltraViolet TLB flush routines.
4 * (c) 2008 Cliff Wickman <cpw@sgi.com>, SGI.
6 * This code is released under the GNU General Public License version 2 or
9 #include <linux/seq_file.h>
10 #include <linux/proc_fs.h>
11 #include <linux/kernel.h>
13 #include <asm/mmu_context.h>
14 #include <asm/uv/uv.h>
15 #include <asm/uv/uv_mmrs.h>
16 #include <asm/uv/uv_hub.h>
17 #include <asm/uv/uv_bau.h>
18 #include <asm/genapic.h>
21 #include <asm/irq_vectors.h>
23 #include <mach_apic.h>
25 static struct bau_control **uv_bau_table_bases __read_mostly;
26 static int uv_bau_retry_limit __read_mostly;
28 /* position of pnode (which is nasid>>1): */
29 static int uv_nshift __read_mostly;
31 static unsigned long uv_mmask __read_mostly;
33 static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
34 static DEFINE_PER_CPU(struct bau_control, bau_control);
37 * Free a software acknowledge hardware resource by clearing its Pending
38 * bit. This will return a reply to the sender.
39 * If the message has timed out, a reply has already been sent by the
40 * hardware but the resource has not been released. In that case our
41 * clear of the Timeout bit (as well) will free the resource. No reply will
42 * be sent (the hardware will only do one reply per message).
44 static void uv_reply_to_message(int resource,
45 struct bau_payload_queue_entry *msg,
46 struct bau_msg_status *msp)
50 dw = (1 << (resource + UV_SW_ACK_NPENDING)) | (1 << resource);
52 msg->sw_ack_vector = 0;
54 msp->seen_by.bits = 0;
55 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw);
59 * Do all the things a cpu should do for a TLB shootdown message.
60 * Other cpu's may come here at the same time for this message.
62 static void uv_bau_process_message(struct bau_payload_queue_entry *msg,
63 int msg_slot, int sw_ack_slot)
65 unsigned long this_cpu_mask;
66 struct bau_msg_status *msp;
69 msp = __get_cpu_var(bau_control).msg_statuses + msg_slot;
70 cpu = uv_blade_processor_id();
72 uv_blade_nr_online_cpus(uv_node_to_blade_id(numa_node_id()));
73 this_cpu_mask = 1UL << cpu;
74 if (msp->seen_by.bits & this_cpu_mask)
76 atomic_or_long(&msp->seen_by.bits, this_cpu_mask);
78 if (msg->replied_to == 1)
81 if (msg->address == TLB_FLUSH_ALL) {
83 __get_cpu_var(ptcstats).alltlb++;
85 __flush_tlb_one(msg->address);
86 __get_cpu_var(ptcstats).onetlb++;
89 __get_cpu_var(ptcstats).requestee++;
91 atomic_inc_short(&msg->acknowledge_count);
92 if (msg->number_of_cpus == msg->acknowledge_count)
93 uv_reply_to_message(sw_ack_slot, msg, msp);
97 * Examine the payload queue on one distribution node to see
98 * which messages have not been seen, and which cpu(s) have not seen them.
100 * Returns the number of cpu's that have not responded.
102 static int uv_examine_destination(struct bau_control *bau_tablesp, int sender)
104 struct bau_payload_queue_entry *msg;
105 struct bau_msg_status *msp;
110 for (msg = bau_tablesp->va_queue_first, i = 0; i < DEST_Q_SIZE;
112 if ((msg->sending_cpu == sender) && (!msg->replied_to)) {
113 msp = bau_tablesp->msg_statuses + i;
115 "blade %d: address:%#lx %d of %d, not cpu(s): ",
116 i, msg->address, msg->acknowledge_count,
117 msg->number_of_cpus);
118 for (j = 0; j < msg->number_of_cpus; j++) {
119 if (!((1L << j) & msp->seen_by.bits)) {
131 * Examine the payload queue on all the distribution nodes to see
132 * which messages have not been seen, and which cpu(s) have not seen them.
134 * Returns the number of cpu's that have not responded.
136 static int uv_examine_destinations(struct bau_target_nodemask *distribution)
142 sender = smp_processor_id();
143 for (i = 0; i < sizeof(struct bau_target_nodemask) * BITSPERBYTE; i++) {
144 if (!bau_node_isset(i, distribution))
146 count += uv_examine_destination(uv_bau_table_bases[i], sender);
152 * wait for completion of a broadcast message
154 * return COMPLETE, RETRY or GIVEUP
156 static int uv_wait_completion(struct bau_desc *bau_desc,
157 unsigned long mmr_offset, int right_shift)
160 long destination_timeouts = 0;
161 long source_timeouts = 0;
162 unsigned long descriptor_status;
164 while ((descriptor_status = (((unsigned long)
165 uv_read_local_mmr(mmr_offset) >>
166 right_shift) & UV_ACT_STATUS_MASK)) !=
168 if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) {
170 if (source_timeouts > SOURCE_TIMEOUT_LIMIT)
172 __get_cpu_var(ptcstats).s_retry++;
176 * spin here looking for progress at the destinations
178 if (descriptor_status == DESC_STATUS_DESTINATION_TIMEOUT) {
179 destination_timeouts++;
180 if (destination_timeouts > DESTINATION_TIMEOUT_LIMIT) {
182 * returns number of cpus not responding
184 if (uv_examine_destinations
185 (&bau_desc->distribution) == 0) {
186 __get_cpu_var(ptcstats).d_retry++;
190 if (exams >= uv_bau_retry_limit) {
192 "uv_flush_tlb_others");
193 printk("giving up on cpu %d\n",
198 * delays can hang the simulator
201 destination_timeouts = 0;
205 return FLUSH_COMPLETE;
209 * uv_flush_send_and_wait
211 * Send a broadcast and wait for a broadcast message to complete.
213 * The flush_mask contains the cpus the broadcast was sent to.
215 * Returns NULL if all remote flushing was done. The mask is zeroed.
216 * Returns @flush_mask if some remote flushing remains to be done. The
217 * mask will have some bits still set.
219 const struct cpumask *uv_flush_send_and_wait(int cpu, int this_blade,
220 struct bau_desc *bau_desc,
221 struct cpumask *flush_mask)
223 int completion_status = 0;
228 unsigned long mmr_offset;
233 if (cpu < UV_CPUS_PER_ACT_STATUS) {
234 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
235 right_shift = cpu * UV_ACT_STATUS_SIZE;
237 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
239 ((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE);
241 time1 = get_cycles();
244 index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) |
246 uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
247 completion_status = uv_wait_completion(bau_desc, mmr_offset,
249 } while (completion_status == FLUSH_RETRY);
250 time2 = get_cycles();
251 __get_cpu_var(ptcstats).sflush += (time2 - time1);
253 __get_cpu_var(ptcstats).retriesok++;
255 if (completion_status == FLUSH_GIVEUP) {
257 * Cause the caller to do an IPI-style TLB shootdown on
258 * the cpu's, all of which are still in the mask.
260 __get_cpu_var(ptcstats).ptc_i++;
265 * Success, so clear the remote cpu's from the mask so we don't
266 * use the IPI method of shootdown on them.
268 for_each_cpu(bit, flush_mask) {
269 blade = uv_cpu_to_blade_id(bit);
270 if (blade == this_blade)
272 cpumask_clear_cpu(bit, flush_mask);
274 if (!cpumask_empty(flush_mask))
280 * uv_flush_tlb_others - globally purge translation cache of a virtual
281 * address or all TLB's
282 * @cpumask: mask of all cpu's in which the address is to be removed
283 * @mm: mm_struct containing virtual address range
284 * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu)
285 * @cpu: the current cpu
287 * This is the entry point for initiating any UV global TLB shootdown.
289 * Purges the translation caches of all specified processors of the given
290 * virtual address, or purges all TLB's on specified processors.
292 * The caller has derived the cpumask from the mm_struct. This function
293 * is called only if there are bits set in the mask. (e.g. flush_tlb_page())
295 * The cpumask is converted into a nodemask of the nodes containing
298 * Note that this function should be called with preemption disabled.
300 * Returns NULL if all remote flushing was done.
301 * Returns pointer to cpumask if some remote flushing remains to be
302 * done. The returned pointer is valid till preemption is re-enabled.
304 const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
305 struct mm_struct *mm,
306 unsigned long va, unsigned int cpu)
308 static DEFINE_PER_CPU(cpumask_t, flush_tlb_mask);
309 struct cpumask *flush_mask = &__get_cpu_var(flush_tlb_mask);
316 struct bau_desc *bau_desc;
318 WARN_ON(!in_atomic());
320 cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
322 uv_cpu = uv_blade_processor_id();
323 this_blade = uv_numa_blade_id();
324 bau_desc = __get_cpu_var(bau_control).descriptor_base;
325 bau_desc += UV_ITEMS_PER_DESCRIPTOR * uv_cpu;
327 bau_nodes_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
330 for_each_cpu(bit, flush_mask) {
331 blade = uv_cpu_to_blade_id(bit);
332 BUG_ON(blade > (UV_DISTRIBUTION_SIZE - 1));
333 if (blade == this_blade) {
337 bau_node_set(blade, &bau_desc->distribution);
342 * no off_node flushing; return status for local node
349 __get_cpu_var(ptcstats).requestor++;
350 __get_cpu_var(ptcstats).ntargeted += i;
352 bau_desc->payload.address = va;
353 bau_desc->payload.sending_cpu = cpu;
355 return uv_flush_send_and_wait(uv_cpu, this_blade, bau_desc, flush_mask);
359 * The BAU message interrupt comes here. (registered by set_intr_gate)
362 * We received a broadcast assist message.
364 * Interrupts may have been disabled; this interrupt could represent
365 * the receipt of several messages.
367 * All cores/threads on this node get this interrupt.
368 * The last one to see it does the s/w ack.
369 * (the resource will not be freed until noninterruptable cpus see this
370 * interrupt; hardware will timeout the s/w ack and reply ERROR)
372 void uv_bau_message_interrupt(struct pt_regs *regs)
374 struct bau_payload_queue_entry *va_queue_first;
375 struct bau_payload_queue_entry *va_queue_last;
376 struct bau_payload_queue_entry *msg;
377 struct pt_regs *old_regs = set_irq_regs(regs);
384 unsigned long local_pnode;
390 time1 = get_cycles();
392 local_pnode = uv_blade_to_pnode(uv_numa_blade_id());
394 va_queue_first = __get_cpu_var(bau_control).va_queue_first;
395 va_queue_last = __get_cpu_var(bau_control).va_queue_last;
397 msg = __get_cpu_var(bau_control).bau_msg_head;
398 while (msg->sw_ack_vector) {
400 fw = msg->sw_ack_vector;
401 msg_slot = msg - va_queue_first;
402 sw_ack_slot = ffs(fw) - 1;
404 uv_bau_process_message(msg, msg_slot, sw_ack_slot);
407 if (msg > va_queue_last)
408 msg = va_queue_first;
409 __get_cpu_var(bau_control).bau_msg_head = msg;
412 __get_cpu_var(ptcstats).nomsg++;
414 __get_cpu_var(ptcstats).multmsg++;
416 time2 = get_cycles();
417 __get_cpu_var(ptcstats).dflush += (time2 - time1);
420 set_irq_regs(old_regs);
423 static void uv_enable_timeouts(void)
430 unsigned long apicid;
433 for_each_online_node(i) {
434 blade = uv_node_to_blade_id(i);
435 if (blade == last_blade)
438 apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
439 pnode = uv_blade_to_pnode(blade);
440 cur_cpu += uv_blade_nr_possible_cpus(i);
444 static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset)
446 if (*offset < num_possible_cpus())
451 static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
454 if (*offset < num_possible_cpus())
459 static void uv_ptc_seq_stop(struct seq_file *file, void *data)
464 * Display the statistics thru /proc
465 * data points to the cpu number
467 static int uv_ptc_seq_show(struct seq_file *file, void *data)
469 struct ptc_stats *stat;
472 cpu = *(loff_t *)data;
476 "# cpu requestor requestee one all sretry dretry ptc_i ");
478 "sw_ack sflush dflush sok dnomsg dmult starget\n");
480 if (cpu < num_possible_cpus() && cpu_online(cpu)) {
481 stat = &per_cpu(ptcstats, cpu);
482 seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld ",
483 cpu, stat->requestor,
484 stat->requestee, stat->onetlb, stat->alltlb,
485 stat->s_retry, stat->d_retry, stat->ptc_i);
486 seq_printf(file, "%lx %ld %ld %ld %ld %ld %ld\n",
487 uv_read_global_mmr64(uv_blade_to_pnode
488 (uv_cpu_to_blade_id(cpu)),
489 UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE),
490 stat->sflush, stat->dflush,
491 stat->retriesok, stat->nomsg,
492 stat->multmsg, stat->ntargeted);
499 * 0: display meaning of the statistics
502 static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user,
503 size_t count, loff_t *data)
508 if (count == 0 || count > sizeof(optstr))
510 if (copy_from_user(optstr, user, count))
512 optstr[count - 1] = '\0';
513 if (strict_strtoul(optstr, 10, &newmode) < 0) {
514 printk(KERN_DEBUG "%s is invalid\n", optstr);
519 printk(KERN_DEBUG "# cpu: cpu number\n");
521 "requestor: times this cpu was the flush requestor\n");
523 "requestee: times this cpu was requested to flush its TLBs\n");
525 "one: times requested to flush a single address\n");
527 "all: times requested to flush all TLB's\n");
529 "sretry: number of retries of source-side timeouts\n");
531 "dretry: number of retries of destination-side timeouts\n");
533 "ptc_i: times UV fell through to IPI-style flushes\n");
535 "sw_ack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n");
537 "sflush_us: cycles spent in uv_flush_tlb_others()\n");
539 "dflush_us: cycles spent in handling flush requests\n");
540 printk(KERN_DEBUG "sok: successes on retry\n");
541 printk(KERN_DEBUG "dnomsg: interrupts with no message\n");
543 "dmult: interrupts with multiple messages\n");
544 printk(KERN_DEBUG "starget: nodes targeted\n");
546 uv_bau_retry_limit = newmode;
547 printk(KERN_DEBUG "timeout retry limit:%d\n",
554 static const struct seq_operations uv_ptc_seq_ops = {
555 .start = uv_ptc_seq_start,
556 .next = uv_ptc_seq_next,
557 .stop = uv_ptc_seq_stop,
558 .show = uv_ptc_seq_show
561 static int uv_ptc_proc_open(struct inode *inode, struct file *file)
563 return seq_open(file, &uv_ptc_seq_ops);
566 static const struct file_operations proc_uv_ptc_operations = {
567 .open = uv_ptc_proc_open,
569 .write = uv_ptc_proc_write,
571 .release = seq_release,
574 static int __init uv_ptc_init(void)
576 struct proc_dir_entry *proc_uv_ptc;
581 proc_uv_ptc = create_proc_entry(UV_PTC_BASENAME, 0444, NULL);
583 printk(KERN_ERR "unable to create %s proc entry\n",
587 proc_uv_ptc->proc_fops = &proc_uv_ptc_operations;
592 * begin the initialization of the per-blade control structures
594 static struct bau_control * __init uv_table_bases_init(int blade, int node)
597 struct bau_msg_status *msp;
598 struct bau_control *bau_tabp;
601 kmalloc_node(sizeof(struct bau_control), GFP_KERNEL, node);
604 bau_tabp->msg_statuses =
605 kmalloc_node(sizeof(struct bau_msg_status) *
606 DEST_Q_SIZE, GFP_KERNEL, node);
607 BUG_ON(!bau_tabp->msg_statuses);
609 for (i = 0, msp = bau_tabp->msg_statuses; i < DEST_Q_SIZE; i++, msp++)
610 bau_cpubits_clear(&msp->seen_by, (int)
611 uv_blade_nr_possible_cpus(blade));
613 uv_bau_table_bases[blade] = bau_tabp;
619 * finish the initialization of the per-blade control structures
622 uv_table_bases_finish(int blade, int node, int cur_cpu,
623 struct bau_control *bau_tablesp,
624 struct bau_desc *adp)
626 struct bau_control *bcp;
629 for (i = cur_cpu; i < cur_cpu + uv_blade_nr_possible_cpus(blade); i++) {
630 bcp = (struct bau_control *)&per_cpu(bau_control, i);
632 bcp->bau_msg_head = bau_tablesp->va_queue_first;
633 bcp->va_queue_first = bau_tablesp->va_queue_first;
634 bcp->va_queue_last = bau_tablesp->va_queue_last;
635 bcp->msg_statuses = bau_tablesp->msg_statuses;
636 bcp->descriptor_base = adp;
641 * initialize the sending side's sending buffers
643 static struct bau_desc * __init
644 uv_activation_descriptor_init(int node, int pnode)
650 unsigned long mmr_image;
651 struct bau_desc *adp;
652 struct bau_desc *ad2;
654 adp = (struct bau_desc *)
655 kmalloc_node(16384, GFP_KERNEL, node);
658 pa = __pa((unsigned long)adp);
662 mmr_image = uv_read_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE);
664 uv_write_global_mmr64(pnode, (unsigned long)
665 UVH_LB_BAU_SB_DESCRIPTOR_BASE,
666 (n << UV_DESC_BASE_PNODE_SHIFT | m));
669 for (i = 0, ad2 = adp; i < UV_ACTIVATION_DESCRIPTOR_SIZE; i++, ad2++) {
670 memset(ad2, 0, sizeof(struct bau_desc));
671 ad2->header.sw_ack_flag = 1;
672 ad2->header.base_dest_nodeid =
673 uv_blade_to_pnode(uv_cpu_to_blade_id(0));
674 ad2->header.command = UV_NET_ENDPOINT_INTD;
675 ad2->header.int_both = 1;
677 * all others need to be set to zero:
678 * fairness chaining multilevel count replied_to
685 * initialize the destination side's receiving buffers
687 static struct bau_payload_queue_entry * __init
688 uv_payload_queue_init(int node, int pnode, struct bau_control *bau_tablesp)
690 struct bau_payload_queue_entry *pqp;
693 pqp = (struct bau_payload_queue_entry *) kmalloc_node(
694 (DEST_Q_SIZE + 1) * sizeof(struct bau_payload_queue_entry),
698 cp = (char *)pqp + 31;
699 pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5);
700 bau_tablesp->va_queue_first = pqp;
701 uv_write_global_mmr64(pnode,
702 UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST,
703 ((unsigned long)pnode <<
704 UV_PAYLOADQ_PNODE_SHIFT) |
705 uv_physnodeaddr(pqp));
706 uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL,
707 uv_physnodeaddr(pqp));
708 bau_tablesp->va_queue_last = pqp + (DEST_Q_SIZE - 1);
709 uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST,
711 uv_physnodeaddr(bau_tablesp->va_queue_last));
712 memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE);
718 * Initialization of each UV blade's structures
720 static int __init uv_init_blade(int blade, int node, int cur_cpu)
724 unsigned long apicid;
725 struct bau_desc *adp;
726 struct bau_payload_queue_entry *pqp;
727 struct bau_control *bau_tablesp;
729 bau_tablesp = uv_table_bases_init(blade, node);
730 pnode = uv_blade_to_pnode(blade);
731 adp = uv_activation_descriptor_init(node, pnode);
732 pqp = uv_payload_queue_init(node, pnode, bau_tablesp);
733 uv_table_bases_finish(blade, node, cur_cpu, bau_tablesp, adp);
735 * the below initialization can't be in firmware because the
736 * messaging IRQ will be determined by the OS
738 apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
739 pa = uv_read_global_mmr64(pnode, UVH_BAU_DATA_CONFIG);
740 if ((pa & 0xff) != UV_BAU_MESSAGE) {
741 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG,
742 ((apicid << 32) | UV_BAU_MESSAGE));
748 * Initialization of BAU-related structures
750 static int __init uv_bau_init(void)
761 uv_bau_retry_limit = 1;
762 uv_nshift = uv_hub_info->n_val;
763 uv_mmask = (1UL << uv_hub_info->n_val) - 1;
766 for_each_online_node(node) {
767 blade = uv_node_to_blade_id(node);
768 if (blade == last_blade)
773 uv_bau_table_bases = (struct bau_control **)
774 kmalloc(nblades * sizeof(struct bau_control *), GFP_KERNEL);
775 BUG_ON(!uv_bau_table_bases);
778 for_each_online_node(node) {
779 blade = uv_node_to_blade_id(node);
780 if (blade == last_blade)
783 uv_init_blade(blade, node, cur_cpu);
784 cur_cpu += uv_blade_nr_possible_cpus(blade);
786 alloc_intr_gate(UV_BAU_MESSAGE, uv_bau_message_intr1);
787 uv_enable_timeouts();
791 __initcall(uv_bau_init);
792 __initcall(uv_ptc_init);