Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial
[linux-2.6] / drivers / video / ffb.c
1 /* ffb.c: Creator/Elite3D frame buffer driver
2  *
3  * Copyright (C) 2003 David S. Miller (davem@redhat.com)
4  * Copyright (C) 1997,1998,1999 Jakub Jelinek (jj@ultra.linux.cz)
5  *
6  * Driver layout based loosely on tgafb.c, see that file for credits.
7  */
8
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/errno.h>
12 #include <linux/string.h>
13 #include <linux/slab.h>
14 #include <linux/delay.h>
15 #include <linux/init.h>
16 #include <linux/fb.h>
17 #include <linux/mm.h>
18 #include <linux/timer.h>
19
20 #include <asm/io.h>
21 #include <asm/upa.h>
22 #include <asm/oplib.h>
23 #include <asm/fbio.h>
24
25 #include "sbuslib.h"
26
27 /*
28  * Local functions.
29  */
30
31 static int ffb_setcolreg(unsigned, unsigned, unsigned, unsigned,
32                          unsigned, struct fb_info *);
33 static int ffb_blank(int, struct fb_info *);
34 static void ffb_init_fix(struct fb_info *);
35
36 static void ffb_imageblit(struct fb_info *, const struct fb_image *);
37 static void ffb_fillrect(struct fb_info *, const struct fb_fillrect *);
38 static void ffb_copyarea(struct fb_info *, const struct fb_copyarea *);
39 static int ffb_sync(struct fb_info *);
40 static int ffb_mmap(struct fb_info *, struct vm_area_struct *);
41 static int ffb_ioctl(struct fb_info *, unsigned int, unsigned long);
42 static int ffb_pan_display(struct fb_var_screeninfo *, struct fb_info *);
43
44 /*
45  *  Frame buffer operations
46  */
47
48 static struct fb_ops ffb_ops = {
49         .owner                  = THIS_MODULE,
50         .fb_setcolreg           = ffb_setcolreg,
51         .fb_blank               = ffb_blank,
52         .fb_pan_display         = ffb_pan_display,
53         .fb_fillrect            = ffb_fillrect,
54         .fb_copyarea            = ffb_copyarea,
55         .fb_imageblit           = ffb_imageblit,
56         .fb_sync                = ffb_sync,
57         .fb_mmap                = ffb_mmap,
58         .fb_ioctl               = ffb_ioctl,
59 #ifdef CONFIG_COMPAT
60         .fb_compat_ioctl        = sbusfb_compat_ioctl,
61 #endif
62 };
63
64 /* Register layout and definitions */
65 #define FFB_SFB8R_VOFF          0x00000000
66 #define FFB_SFB8G_VOFF          0x00400000
67 #define FFB_SFB8B_VOFF          0x00800000
68 #define FFB_SFB8X_VOFF          0x00c00000
69 #define FFB_SFB32_VOFF          0x01000000
70 #define FFB_SFB64_VOFF          0x02000000
71 #define FFB_FBC_REGS_VOFF       0x04000000
72 #define FFB_BM_FBC_REGS_VOFF    0x04002000
73 #define FFB_DFB8R_VOFF          0x04004000
74 #define FFB_DFB8G_VOFF          0x04404000
75 #define FFB_DFB8B_VOFF          0x04804000
76 #define FFB_DFB8X_VOFF          0x04c04000
77 #define FFB_DFB24_VOFF          0x05004000
78 #define FFB_DFB32_VOFF          0x06004000
79 #define FFB_DFB422A_VOFF        0x07004000      /* DFB 422 mode write to A */
80 #define FFB_DFB422AD_VOFF       0x07804000      /* DFB 422 mode with line doubling */
81 #define FFB_DFB24B_VOFF         0x08004000      /* DFB 24bit mode write to B */
82 #define FFB_DFB422B_VOFF        0x09004000      /* DFB 422 mode write to B */
83 #define FFB_DFB422BD_VOFF       0x09804000      /* DFB 422 mode with line doubling */
84 #define FFB_SFB16Z_VOFF         0x0a004000      /* 16bit mode Z planes */
85 #define FFB_SFB8Z_VOFF          0x0a404000      /* 8bit mode Z planes */
86 #define FFB_SFB422_VOFF         0x0ac04000      /* SFB 422 mode write to A/B */
87 #define FFB_SFB422D_VOFF        0x0b404000      /* SFB 422 mode with line doubling */
88 #define FFB_FBC_KREGS_VOFF      0x0bc04000
89 #define FFB_DAC_VOFF            0x0bc06000
90 #define FFB_PROM_VOFF           0x0bc08000
91 #define FFB_EXP_VOFF            0x0bc18000
92
93 #define FFB_SFB8R_POFF          0x04000000UL
94 #define FFB_SFB8G_POFF          0x04400000UL
95 #define FFB_SFB8B_POFF          0x04800000UL
96 #define FFB_SFB8X_POFF          0x04c00000UL
97 #define FFB_SFB32_POFF          0x05000000UL
98 #define FFB_SFB64_POFF          0x06000000UL
99 #define FFB_FBC_REGS_POFF       0x00600000UL
100 #define FFB_BM_FBC_REGS_POFF    0x00600000UL
101 #define FFB_DFB8R_POFF          0x01000000UL
102 #define FFB_DFB8G_POFF          0x01400000UL
103 #define FFB_DFB8B_POFF          0x01800000UL
104 #define FFB_DFB8X_POFF          0x01c00000UL
105 #define FFB_DFB24_POFF          0x02000000UL
106 #define FFB_DFB32_POFF          0x03000000UL
107 #define FFB_FBC_KREGS_POFF      0x00610000UL
108 #define FFB_DAC_POFF            0x00400000UL
109 #define FFB_PROM_POFF           0x00000000UL
110 #define FFB_EXP_POFF            0x00200000UL
111 #define FFB_DFB422A_POFF        0x09000000UL
112 #define FFB_DFB422AD_POFF       0x09800000UL
113 #define FFB_DFB24B_POFF         0x0a000000UL
114 #define FFB_DFB422B_POFF        0x0b000000UL
115 #define FFB_DFB422BD_POFF       0x0b800000UL
116 #define FFB_SFB16Z_POFF         0x0c800000UL
117 #define FFB_SFB8Z_POFF          0x0c000000UL
118 #define FFB_SFB422_POFF         0x0d000000UL
119 #define FFB_SFB422D_POFF        0x0d800000UL
120
121 /* Draw operations */
122 #define FFB_DRAWOP_DOT          0x00
123 #define FFB_DRAWOP_AADOT        0x01
124 #define FFB_DRAWOP_BRLINECAP    0x02
125 #define FFB_DRAWOP_BRLINEOPEN   0x03
126 #define FFB_DRAWOP_DDLINE       0x04
127 #define FFB_DRAWOP_AALINE       0x05
128 #define FFB_DRAWOP_TRIANGLE     0x06
129 #define FFB_DRAWOP_POLYGON      0x07
130 #define FFB_DRAWOP_RECTANGLE    0x08
131 #define FFB_DRAWOP_FASTFILL     0x09
132 #define FFB_DRAWOP_BCOPY        0x0a
133 #define FFB_DRAWOP_VSCROLL      0x0b
134
135 /* Pixel processor control */
136 /* Force WID */
137 #define FFB_PPC_FW_DISABLE      0x800000
138 #define FFB_PPC_FW_ENABLE       0xc00000
139 /* Auxiliary clip */
140 #define FFB_PPC_ACE_DISABLE     0x040000
141 #define FFB_PPC_ACE_AUX_SUB     0x080000
142 #define FFB_PPC_ACE_AUX_ADD     0x0c0000
143 /* Depth cue */
144 #define FFB_PPC_DCE_DISABLE     0x020000
145 #define FFB_PPC_DCE_ENABLE      0x030000
146 /* Alpha blend */
147 #define FFB_PPC_ABE_DISABLE     0x008000
148 #define FFB_PPC_ABE_ENABLE      0x00c000
149 /* View clip */
150 #define FFB_PPC_VCE_DISABLE     0x001000
151 #define FFB_PPC_VCE_2D          0x002000
152 #define FFB_PPC_VCE_3D          0x003000
153 /* Area pattern */
154 #define FFB_PPC_APE_DISABLE     0x000800
155 #define FFB_PPC_APE_ENABLE      0x000c00
156 /* Transparent background */
157 #define FFB_PPC_TBE_OPAQUE      0x000200
158 #define FFB_PPC_TBE_TRANSPARENT 0x000300
159 /* Z source */
160 #define FFB_PPC_ZS_VAR          0x000080
161 #define FFB_PPC_ZS_CONST        0x0000c0
162 /* Y source */
163 #define FFB_PPC_YS_VAR          0x000020
164 #define FFB_PPC_YS_CONST        0x000030
165 /* X source */
166 #define FFB_PPC_XS_WID          0x000004
167 #define FFB_PPC_XS_VAR          0x000008
168 #define FFB_PPC_XS_CONST        0x00000c
169 /* Color (BGR) source */
170 #define FFB_PPC_CS_VAR          0x000002
171 #define FFB_PPC_CS_CONST        0x000003
172
173 #define FFB_ROP_NEW                  0x83
174 #define FFB_ROP_OLD                  0x85
175 #define FFB_ROP_NEW_XOR_OLD          0x86
176
177 #define FFB_UCSR_FIFO_MASK     0x00000fff
178 #define FFB_UCSR_FB_BUSY       0x01000000
179 #define FFB_UCSR_RP_BUSY       0x02000000
180 #define FFB_UCSR_ALL_BUSY      (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
181 #define FFB_UCSR_READ_ERR      0x40000000
182 #define FFB_UCSR_FIFO_OVFL     0x80000000
183 #define FFB_UCSR_ALL_ERRORS    (FFB_UCSR_READ_ERR|FFB_UCSR_FIFO_OVFL)
184
185 struct ffb_fbc {
186         /* Next vertex registers */
187         u32             xxx1[3];
188         volatile u32    alpha;
189         volatile u32    red;
190         volatile u32    green;
191         volatile u32    blue;
192         volatile u32    depth;
193         volatile u32    y;
194         volatile u32    x;
195         u32             xxx2[2];
196         volatile u32    ryf;
197         volatile u32    rxf;
198         u32             xxx3[2];
199         
200         volatile u32    dmyf;
201         volatile u32    dmxf;
202         u32             xxx4[2];
203         volatile u32    ebyi;
204         volatile u32    ebxi;
205         u32             xxx5[2];
206         volatile u32    by;
207         volatile u32    bx;
208         u32             dy;
209         u32             dx;
210         volatile u32    bh;
211         volatile u32    bw;
212         u32             xxx6[2];
213         
214         u32             xxx7[32];
215         
216         /* Setup unit vertex state register */
217         volatile u32    suvtx;
218         u32             xxx8[63];
219         
220         /* Control registers */
221         volatile u32    ppc;
222         volatile u32    wid;
223         volatile u32    fg;
224         volatile u32    bg;
225         volatile u32    consty;
226         volatile u32    constz;
227         volatile u32    xclip;
228         volatile u32    dcss;
229         volatile u32    vclipmin;
230         volatile u32    vclipmax;
231         volatile u32    vclipzmin;
232         volatile u32    vclipzmax;
233         volatile u32    dcsf;
234         volatile u32    dcsb;
235         volatile u32    dczf;
236         volatile u32    dczb;
237         
238         u32             xxx9;
239         volatile u32    blendc;
240         volatile u32    blendc1;
241         volatile u32    blendc2;
242         volatile u32    fbramitc;
243         volatile u32    fbc;
244         volatile u32    rop;
245         volatile u32    cmp;
246         volatile u32    matchab;
247         volatile u32    matchc;
248         volatile u32    magnab;
249         volatile u32    magnc;
250         volatile u32    fbcfg0;
251         volatile u32    fbcfg1;
252         volatile u32    fbcfg2;
253         volatile u32    fbcfg3;
254         
255         u32             ppcfg;
256         volatile u32    pick;
257         volatile u32    fillmode;
258         volatile u32    fbramwac;
259         volatile u32    pmask;
260         volatile u32    xpmask;
261         volatile u32    ypmask;
262         volatile u32    zpmask;
263         volatile u32    clip0min;
264         volatile u32    clip0max;
265         volatile u32    clip1min;
266         volatile u32    clip1max;
267         volatile u32    clip2min;
268         volatile u32    clip2max;
269         volatile u32    clip3min;
270         volatile u32    clip3max;
271         
272         /* New 3dRAM III support regs */
273         volatile u32    rawblend2;
274         volatile u32    rawpreblend;
275         volatile u32    rawstencil;
276         volatile u32    rawstencilctl;
277         volatile u32    threedram1;
278         volatile u32    threedram2;
279         volatile u32    passin;
280         volatile u32    rawclrdepth;
281         volatile u32    rawpmask;
282         volatile u32    rawcsrc;
283         volatile u32    rawmatch;
284         volatile u32    rawmagn;
285         volatile u32    rawropblend;
286         volatile u32    rawcmp;
287         volatile u32    rawwac;
288         volatile u32    fbramid;
289         
290         volatile u32    drawop;
291         u32             xxx10[2];
292         volatile u32    fontlpat;
293         u32             xxx11;
294         volatile u32    fontxy;
295         volatile u32    fontw;
296         volatile u32    fontinc;
297         volatile u32    font;
298         u32             xxx12[3];
299         volatile u32    blend2;
300         volatile u32    preblend;
301         volatile u32    stencil;
302         volatile u32    stencilctl;
303
304         u32             xxx13[4];       
305         volatile u32    dcss1;
306         volatile u32    dcss2;
307         volatile u32    dcss3;
308         volatile u32    widpmask;
309         volatile u32    dcs2;
310         volatile u32    dcs3;
311         volatile u32    dcs4;
312         u32             xxx14;
313         volatile u32    dcd2;
314         volatile u32    dcd3;
315         volatile u32    dcd4;
316         u32             xxx15;
317         
318         volatile u32    pattern[32];
319         
320         u32             xxx16[256];
321         
322         volatile u32    devid;
323         u32             xxx17[63];
324         
325         volatile u32    ucsr;
326         u32             xxx18[31];
327         
328         volatile u32    mer;
329 };
330
331 struct ffb_dac {
332         volatile u32    type;
333         volatile u32    value;
334         volatile u32    type2;
335         volatile u32    value2;
336 };
337
338 struct ffb_par {
339         spinlock_t              lock;
340         struct ffb_fbc          *fbc;
341         struct ffb_dac          *dac;
342
343         u32                     flags;
344 #define FFB_FLAG_AFB            0x00000001
345 #define FFB_FLAG_BLANKED        0x00000002
346
347         u32                     fg_cache __attribute__((aligned (8)));
348         u32                     bg_cache;
349         u32                     rop_cache;
350
351         int                     fifo_cache;
352
353         unsigned long           physbase;
354         unsigned long           fbsize;
355
356         char                    name[64];
357         int                     prom_node;
358         int                     prom_parent_node;
359         int                     dac_rev;
360         int                     board_type;
361 };
362
363 static void FFBFifo(struct ffb_par *par, int n)
364 {
365         struct ffb_fbc *fbc;
366         int cache = par->fifo_cache;
367
368         if (cache - n < 0) {
369                 fbc = par->fbc;
370                 do {    cache = (upa_readl(&fbc->ucsr) & FFB_UCSR_FIFO_MASK) - 8;
371                 } while (cache - n < 0);
372         }
373         par->fifo_cache = cache - n;
374 }
375
376 static void FFBWait(struct ffb_par *par)
377 {
378         struct ffb_fbc *fbc;
379         int limit = 10000;
380
381         fbc = par->fbc;
382         do {
383                 if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_BUSY) == 0)
384                         break;
385                 if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0) {
386                         upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
387                 }
388                 udelay(10);
389         } while(--limit > 0);
390 }
391
392 static int ffb_sync(struct fb_info *p)
393 {
394         struct ffb_par *par = (struct ffb_par *) p->par;
395
396         FFBWait(par);
397         return 0;
398 }
399
400 static __inline__ void ffb_rop(struct ffb_par *par, u32 rop)
401 {
402         if (par->rop_cache != rop) {
403                 FFBFifo(par, 1);
404                 upa_writel(rop, &par->fbc->rop);
405                 par->rop_cache = rop;
406         }
407 }
408
409 static void ffb_switch_from_graph(struct ffb_par *par)
410 {
411         struct ffb_fbc *fbc = par->fbc;
412         struct ffb_dac *dac = par->dac;
413         unsigned long flags;
414
415         spin_lock_irqsave(&par->lock, flags);
416         FFBWait(par);
417         par->fifo_cache = 0;
418         FFBFifo(par, 7);
419         upa_writel(FFB_PPC_VCE_DISABLE|FFB_PPC_TBE_OPAQUE|
420                    FFB_PPC_APE_DISABLE|FFB_PPC_CS_CONST,
421                    &fbc->ppc);
422         upa_writel(0x2000707f, &fbc->fbc);
423         upa_writel(par->rop_cache, &fbc->rop);
424         upa_writel(0xffffffff, &fbc->pmask);
425         upa_writel((1 << 16) | (0 << 0), &fbc->fontinc);
426         upa_writel(par->fg_cache, &fbc->fg);
427         upa_writel(par->bg_cache, &fbc->bg);
428         FFBWait(par);
429
430         /* Disable cursor.  */
431         upa_writel(0x100, &dac->type2);
432         if (par->dac_rev <= 2)
433                 upa_writel(0, &dac->value2);
434         else
435                 upa_writel(3, &dac->value2);
436
437         spin_unlock_irqrestore(&par->lock, flags);
438 }
439
440 static int ffb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
441 {
442         struct ffb_par *par = (struct ffb_par *) info->par;
443
444         /* We just use this to catch switches out of
445          * graphics mode.
446          */
447         ffb_switch_from_graph(par);
448
449         if (var->xoffset || var->yoffset || var->vmode)
450                 return -EINVAL;
451         return 0;
452 }
453
454 /**
455  *      ffb_fillrect - REQUIRED function. Can use generic routines if 
456  *                     non acclerated hardware and packed pixel based.
457  *                     Draws a rectangle on the screen.               
458  *
459  *      @info: frame buffer structure that represents a single frame buffer
460  *      @rect: structure defining the rectagle and operation.
461  */
462 static void ffb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
463 {
464         struct ffb_par *par = (struct ffb_par *) info->par;
465         struct ffb_fbc *fbc = par->fbc;
466         unsigned long flags;
467         u32 fg;
468
469         if (rect->rop != ROP_COPY && rect->rop != ROP_XOR)
470                 BUG();
471
472         fg = ((u32 *)info->pseudo_palette)[rect->color];
473
474         spin_lock_irqsave(&par->lock, flags);
475
476         if (fg != par->fg_cache) {
477                 FFBFifo(par, 1);
478                 upa_writel(fg, &fbc->fg);
479                 par->fg_cache = fg;
480         }
481
482         ffb_rop(par, (rect->rop == ROP_COPY ?
483                       FFB_ROP_NEW :
484                       FFB_ROP_NEW_XOR_OLD));
485
486         FFBFifo(par, 5);
487         upa_writel(FFB_DRAWOP_RECTANGLE, &fbc->drawop);
488         upa_writel(rect->dy, &fbc->by);
489         upa_writel(rect->dx, &fbc->bx);
490         upa_writel(rect->height, &fbc->bh);
491         upa_writel(rect->width, &fbc->bw);
492
493         spin_unlock_irqrestore(&par->lock, flags);
494 }
495
496 /**
497  *      ffb_copyarea - REQUIRED function. Can use generic routines if
498  *                     non acclerated hardware and packed pixel based.
499  *                     Copies on area of the screen to another area.
500  *
501  *      @info: frame buffer structure that represents a single frame buffer
502  *      @area: structure defining the source and destination.
503  */
504
505 static void
506 ffb_copyarea(struct fb_info *info, const struct fb_copyarea *area) 
507 {
508         struct ffb_par *par = (struct ffb_par *) info->par;
509         struct ffb_fbc *fbc = par->fbc;
510         unsigned long flags;
511
512         if (area->dx != area->sx ||
513             area->dy == area->sy) {
514                 cfb_copyarea(info, area);
515                 return;
516         }
517
518         spin_lock_irqsave(&par->lock, flags);
519
520         ffb_rop(par, FFB_ROP_OLD);
521
522         FFBFifo(par, 7);
523         upa_writel(FFB_DRAWOP_VSCROLL, &fbc->drawop);
524         upa_writel(area->sy, &fbc->by);
525         upa_writel(area->sx, &fbc->bx);
526         upa_writel(area->dy, &fbc->dy);
527         upa_writel(area->dx, &fbc->dx);
528         upa_writel(area->height, &fbc->bh);
529         upa_writel(area->width, &fbc->bw);
530
531         spin_unlock_irqrestore(&par->lock, flags);
532 }
533
534 /**
535  *      ffb_imageblit - REQUIRED function. Can use generic routines if
536  *                      non acclerated hardware and packed pixel based.
537  *                      Copies a image from system memory to the screen. 
538  *
539  *      @info: frame buffer structure that represents a single frame buffer
540  *      @image: structure defining the image.
541  */
542 static void ffb_imageblit(struct fb_info *info, const struct fb_image *image)
543 {
544         struct ffb_par *par = (struct ffb_par *) info->par;
545         struct ffb_fbc *fbc = par->fbc;
546         const u8 *data = image->data;
547         unsigned long flags;
548         u32 fg, bg, xy;
549         u64 fgbg;
550         int i, width, stride;
551
552         if (image->depth > 1) {
553                 cfb_imageblit(info, image);
554                 return;
555         }
556
557         fg = ((u32 *)info->pseudo_palette)[image->fg_color];
558         bg = ((u32 *)info->pseudo_palette)[image->bg_color];
559         fgbg = ((u64) fg << 32) | (u64) bg;
560         xy = (image->dy << 16) | image->dx;
561         width = image->width;
562         stride = ((width + 7) >> 3);
563
564         spin_lock_irqsave(&par->lock, flags);
565
566         if (fgbg != *(u64 *)&par->fg_cache) {
567                 FFBFifo(par, 2);
568                 upa_writeq(fgbg, &fbc->fg);
569                 *(u64 *)&par->fg_cache = fgbg;
570         }
571
572         if (width >= 32) {
573                 FFBFifo(par, 1);
574                 upa_writel(32, &fbc->fontw);
575         }
576
577         while (width >= 32) {
578                 const u8 *next_data = data + 4;
579
580                 FFBFifo(par, 1);
581                 upa_writel(xy, &fbc->fontxy);
582                 xy += (32 << 0);
583
584                 for (i = 0; i < image->height; i++) {
585                         u32 val = (((u32)data[0] << 24) |
586                                    ((u32)data[1] << 16) |
587                                    ((u32)data[2] <<  8) |
588                                    ((u32)data[3] <<  0));
589                         FFBFifo(par, 1);
590                         upa_writel(val, &fbc->font);
591
592                         data += stride;
593                 }
594
595                 data = next_data;
596                 width -= 32;
597         }
598
599         if (width) {
600                 FFBFifo(par, 2);
601                 upa_writel(width, &fbc->fontw);
602                 upa_writel(xy, &fbc->fontxy);
603
604                 for (i = 0; i < image->height; i++) {
605                         u32 val = (((u32)data[0] << 24) |
606                                    ((u32)data[1] << 16) |
607                                    ((u32)data[2] <<  8) |
608                                    ((u32)data[3] <<  0));
609                         FFBFifo(par, 1);
610                         upa_writel(val, &fbc->font);
611
612                         data += stride;
613                 }
614         }
615
616         spin_unlock_irqrestore(&par->lock, flags);
617 }
618
619 static void ffb_fixup_var_rgb(struct fb_var_screeninfo *var)
620 {
621         var->red.offset = 0;
622         var->red.length = 8;
623         var->green.offset = 8;
624         var->green.length = 8;
625         var->blue.offset = 16;
626         var->blue.length = 8;
627         var->transp.offset = 0;
628         var->transp.length = 0;
629 }
630
631 /**
632  *      ffb_setcolreg - Optional function. Sets a color register.
633  *      @regno: boolean, 0 copy local, 1 get_user() function
634  *      @red: frame buffer colormap structure
635  *      @green: The green value which can be up to 16 bits wide
636  *      @blue:  The blue value which can be up to 16 bits wide.
637  *      @transp: If supported the alpha value which can be up to 16 bits wide.
638  *      @info: frame buffer info structure
639  */
640 static int ffb_setcolreg(unsigned regno,
641                          unsigned red, unsigned green, unsigned blue,
642                          unsigned transp, struct fb_info *info)
643 {
644         u32 value;
645
646         if (regno >= 256)
647                 return 1;
648
649         red >>= 8;
650         green >>= 8;
651         blue >>= 8;
652
653         value = (blue << 16) | (green << 8) | red;
654         ((u32 *)info->pseudo_palette)[regno] = value;
655
656         return 0;
657 }
658
659 /**
660  *      ffb_blank - Optional function.  Blanks the display.
661  *      @blank_mode: the blank mode we want.
662  *      @info: frame buffer structure that represents a single frame buffer
663  */
664 static int
665 ffb_blank(int blank, struct fb_info *info)
666 {
667         struct ffb_par *par = (struct ffb_par *) info->par;
668         struct ffb_dac *dac = par->dac;
669         unsigned long flags;
670         u32 tmp;
671
672         spin_lock_irqsave(&par->lock, flags);
673
674         FFBWait(par);
675
676         switch (blank) {
677         case FB_BLANK_UNBLANK: /* Unblanking */
678                 upa_writel(0x6000, &dac->type);
679                 tmp = (upa_readl(&dac->value) | 0x1);
680                 upa_writel(0x6000, &dac->type);
681                 upa_writel(tmp, &dac->value);
682                 par->flags &= ~FFB_FLAG_BLANKED;
683                 break;
684
685         case FB_BLANK_NORMAL: /* Normal blanking */
686         case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
687         case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
688         case FB_BLANK_POWERDOWN: /* Poweroff */
689                 upa_writel(0x6000, &dac->type);
690                 tmp = (upa_readl(&dac->value) & ~0x1);
691                 upa_writel(0x6000, &dac->type);
692                 upa_writel(tmp, &dac->value);
693                 par->flags |= FFB_FLAG_BLANKED;
694                 break;
695         }
696
697         spin_unlock_irqrestore(&par->lock, flags);
698
699         return 0;
700 }
701
702 static struct sbus_mmap_map ffb_mmap_map[] = {
703         {
704                 .voff   = FFB_SFB8R_VOFF,
705                 .poff   = FFB_SFB8R_POFF,
706                 .size   = 0x0400000
707         },
708         {
709                 .voff   = FFB_SFB8G_VOFF,
710                 .poff   = FFB_SFB8G_POFF,
711                 .size   = 0x0400000
712         },
713         {
714                 .voff   = FFB_SFB8B_VOFF,
715                 .poff   = FFB_SFB8B_POFF,
716                 .size   = 0x0400000
717         },
718         {
719                 .voff   = FFB_SFB8X_VOFF,
720                 .poff   = FFB_SFB8X_POFF,
721                 .size   = 0x0400000
722         },
723         {
724                 .voff   = FFB_SFB32_VOFF,
725                 .poff   = FFB_SFB32_POFF,
726                 .size   = 0x1000000
727         },
728         {
729                 .voff   = FFB_SFB64_VOFF,
730                 .poff   = FFB_SFB64_POFF,
731                 .size   = 0x2000000
732         },
733         {
734                 .voff   = FFB_FBC_REGS_VOFF,
735                 .poff   = FFB_FBC_REGS_POFF,
736                 .size   = 0x0002000
737         },
738         {
739                 .voff   = FFB_BM_FBC_REGS_VOFF,
740                 .poff   = FFB_BM_FBC_REGS_POFF,
741                 .size   = 0x0002000
742         },
743         {
744                 .voff   = FFB_DFB8R_VOFF,
745                 .poff   = FFB_DFB8R_POFF,
746                 .size   = 0x0400000
747         },
748         {
749                 .voff   = FFB_DFB8G_VOFF,
750                 .poff   = FFB_DFB8G_POFF,
751                 .size   = 0x0400000
752         },
753         {
754                 .voff   = FFB_DFB8B_VOFF,
755                 .poff   = FFB_DFB8B_POFF,
756                 .size   = 0x0400000
757         },
758         {
759                 .voff   = FFB_DFB8X_VOFF,
760                 .poff   = FFB_DFB8X_POFF,
761                 .size   = 0x0400000
762         },
763         {
764                 .voff   = FFB_DFB24_VOFF,
765                 .poff   = FFB_DFB24_POFF,
766                 .size   = 0x1000000
767         },
768         {
769                 .voff   = FFB_DFB32_VOFF,
770                 .poff   = FFB_DFB32_POFF,
771                 .size   = 0x1000000
772         },
773         {
774                 .voff   = FFB_FBC_KREGS_VOFF,
775                 .poff   = FFB_FBC_KREGS_POFF,
776                 .size   = 0x0002000
777         },
778         {
779                 .voff   = FFB_DAC_VOFF,
780                 .poff   = FFB_DAC_POFF,
781                 .size   = 0x0002000
782         },
783         {
784                 .voff   = FFB_PROM_VOFF,
785                 .poff   = FFB_PROM_POFF,
786                 .size   = 0x0010000
787         },
788         {
789                 .voff   = FFB_EXP_VOFF,
790                 .poff   = FFB_EXP_POFF,
791                 .size   = 0x0002000
792         },
793         {
794                 .voff   = FFB_DFB422A_VOFF,
795                 .poff   = FFB_DFB422A_POFF,
796                 .size   = 0x0800000
797         },
798         {
799                 .voff   = FFB_DFB422AD_VOFF,
800                 .poff   = FFB_DFB422AD_POFF,
801                 .size   = 0x0800000
802         },
803         {
804                 .voff   = FFB_DFB24B_VOFF,
805                 .poff   = FFB_DFB24B_POFF,
806                 .size   = 0x1000000
807         },
808         {
809                 .voff   = FFB_DFB422B_VOFF,
810                 .poff   = FFB_DFB422B_POFF,
811                 .size   = 0x0800000
812         },
813         {
814                 .voff   = FFB_DFB422BD_VOFF,
815                 .poff   = FFB_DFB422BD_POFF,
816                 .size   = 0x0800000
817         },
818         {
819                 .voff   = FFB_SFB16Z_VOFF,
820                 .poff   = FFB_SFB16Z_POFF,
821                 .size   = 0x0800000
822         },
823         {
824                 .voff   = FFB_SFB8Z_VOFF,
825                 .poff   = FFB_SFB8Z_POFF,
826                 .size   = 0x0800000
827         },
828         {
829                 .voff   = FFB_SFB422_VOFF,
830                 .poff   = FFB_SFB422_POFF,
831                 .size   = 0x0800000
832         },
833         {
834                 .voff   = FFB_SFB422D_VOFF,
835                 .poff   = FFB_SFB422D_POFF,
836                 .size   = 0x0800000
837         },
838         { .size = 0 }
839 };
840
841 static int ffb_mmap(struct fb_info *info, struct vm_area_struct *vma)
842 {
843         struct ffb_par *par = (struct ffb_par *)info->par;
844
845         return sbusfb_mmap_helper(ffb_mmap_map,
846                                   par->physbase, par->fbsize,
847                                   0, vma);
848 }
849
850 static int ffb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
851 {
852         struct ffb_par *par = (struct ffb_par *) info->par;
853
854         return sbusfb_ioctl_helper(cmd, arg, info,
855                                    FBTYPE_CREATOR, 24, par->fbsize);
856 }
857
858 /*
859  *  Initialisation
860  */
861
862 static void
863 ffb_init_fix(struct fb_info *info)
864 {
865         struct ffb_par *par = (struct ffb_par *)info->par;
866         const char *ffb_type_name;
867
868         if (!(par->flags & FFB_FLAG_AFB)) {
869                 if ((par->board_type & 0x7) == 0x3)
870                         ffb_type_name = "Creator 3D";
871                 else
872                         ffb_type_name = "Creator";
873         } else
874                 ffb_type_name = "Elite 3D";
875
876         strlcpy(info->fix.id, ffb_type_name, sizeof(info->fix.id));
877
878         info->fix.type = FB_TYPE_PACKED_PIXELS;
879         info->fix.visual = FB_VISUAL_TRUECOLOR;
880
881         /* Framebuffer length is the same regardless of resolution. */
882         info->fix.line_length = 8192;
883
884         info->fix.accel = FB_ACCEL_SUN_CREATOR;
885 }
886
887 static int ffb_apply_upa_parent_ranges(int parent,
888                                        struct linux_prom64_registers *regs)
889 {
890         struct linux_prom64_ranges ranges[PROMREG_MAX];
891         char name[128];
892         int len, i;
893
894         prom_getproperty(parent, "name", name, sizeof(name));
895         if (strcmp(name, "upa") != 0)
896                 return 0;
897
898         len = prom_getproperty(parent, "ranges", (void *) ranges, sizeof(ranges));
899         if (len <= 0)
900                 return 1;
901
902         len /= sizeof(struct linux_prom64_ranges);
903         for (i = 0; i < len; i++) {
904                 struct linux_prom64_ranges *rng = &ranges[i];
905                 u64 phys_addr = regs->phys_addr;
906
907                 if (phys_addr >= rng->ot_child_base &&
908                     phys_addr < (rng->ot_child_base + rng->or_size)) {
909                         regs->phys_addr -= rng->ot_child_base;
910                         regs->phys_addr += rng->ot_parent_base;
911                         return 0;
912                 }
913         }
914
915         return 1;
916 }
917
918 struct all_info {
919         struct fb_info info;
920         struct ffb_par par;
921         u32 pseudo_palette[256];
922         struct list_head list;
923 };
924 static LIST_HEAD(ffb_list);
925
926 static void ffb_init_one(int node, int parent)
927 {
928         struct linux_prom64_registers regs[2*PROMREG_MAX];
929         struct ffb_fbc *fbc;
930         struct ffb_dac *dac;
931         struct all_info *all;
932
933         if (prom_getproperty(node, "reg", (void *) regs, sizeof(regs)) <= 0) {
934                 printk("ffb: Cannot get reg device node property.\n");
935                 return;
936         }
937
938         if (ffb_apply_upa_parent_ranges(parent, &regs[0])) {
939                 printk("ffb: Cannot apply parent ranges to regs.\n");
940                 return;
941         }
942
943         all = kmalloc(sizeof(*all), GFP_KERNEL);
944         if (!all) {
945                 printk(KERN_ERR "ffb: Cannot allocate memory.\n");
946                 return;
947         }
948         memset(all, 0, sizeof(*all));
949
950         INIT_LIST_HEAD(&all->list);     
951
952         spin_lock_init(&all->par.lock);
953         all->par.fbc = (struct ffb_fbc *)(regs[0].phys_addr + FFB_FBC_REGS_POFF);
954         all->par.dac = (struct ffb_dac *)(regs[0].phys_addr + FFB_DAC_POFF);
955         all->par.rop_cache = FFB_ROP_NEW;
956         all->par.physbase = regs[0].phys_addr;
957         all->par.prom_node = node;
958         all->par.prom_parent_node = parent;
959
960         /* Don't mention copyarea, so SCROLL_REDRAW is always
961          * used.  It is the fastest on this chip.
962          */
963         all->info.flags = (FBINFO_DEFAULT |
964                            /* FBINFO_HWACCEL_COPYAREA | */
965                            FBINFO_HWACCEL_FILLRECT |
966                            FBINFO_HWACCEL_IMAGEBLIT);
967         all->info.fbops = &ffb_ops;
968         all->info.screen_base = (char *) all->par.physbase + FFB_DFB24_POFF;
969         all->info.par = &all->par;
970         all->info.pseudo_palette = all->pseudo_palette;
971
972         sbusfb_fill_var(&all->info.var, all->par.prom_node, 32);
973         all->par.fbsize = PAGE_ALIGN(all->info.var.xres *
974                                      all->info.var.yres *
975                                      4);
976         ffb_fixup_var_rgb(&all->info.var);
977
978         all->info.var.accel_flags = FB_ACCELF_TEXT;
979
980         prom_getstring(node, "name", all->par.name, sizeof(all->par.name));
981         if (!strcmp(all->par.name, "SUNW,afb"))
982                 all->par.flags |= FFB_FLAG_AFB;
983
984         all->par.board_type = prom_getintdefault(node, "board_type", 0);
985
986         fbc = all->par.fbc;
987         if((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0)
988                 upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
989
990         ffb_switch_from_graph(&all->par);
991
992         dac = all->par.dac;
993         upa_writel(0x8000, &dac->type);
994         all->par.dac_rev = upa_readl(&dac->value) >> 0x1c;
995
996         /* Elite3D has different DAC revision numbering, and no DAC revisions
997          * have the reversed meaning of cursor enable.
998          */
999         if (all->par.flags & FFB_FLAG_AFB)
1000                 all->par.dac_rev = 10;
1001
1002         /* Unblank it just to be sure.  When there are multiple
1003          * FFB/AFB cards in the system, or it is not the OBP
1004          * chosen console, it will have video outputs off in
1005          * the DAC.
1006          */
1007         ffb_blank(0, &all->info);
1008
1009         if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
1010                 printk(KERN_ERR "ffb: Could not allocate color map.\n");
1011                 kfree(all);
1012                 return;
1013         }
1014
1015         ffb_init_fix(&all->info);
1016
1017         if (register_framebuffer(&all->info) < 0) {
1018                 printk(KERN_ERR "ffb: Could not register framebuffer.\n");
1019                 fb_dealloc_cmap(&all->info.cmap);
1020                 kfree(all);
1021                 return;
1022         }
1023
1024         list_add(&all->list, &ffb_list);
1025
1026         printk("ffb: %s at %016lx type %d DAC %d\n",
1027                ((all->par.flags & FFB_FLAG_AFB) ? "AFB" : "FFB"),
1028                regs[0].phys_addr, all->par.board_type, all->par.dac_rev);
1029 }
1030
1031 static void ffb_scan_siblings(int root)
1032 {
1033         int node, child;
1034
1035         child = prom_getchild(root);
1036         for (node = prom_searchsiblings(child, "SUNW,ffb"); node;
1037              node = prom_searchsiblings(prom_getsibling(node), "SUNW,ffb"))
1038                 ffb_init_one(node, root);
1039         for (node = prom_searchsiblings(child, "SUNW,afb"); node;
1040              node = prom_searchsiblings(prom_getsibling(node), "SUNW,afb"))
1041                 ffb_init_one(node, root);
1042 }
1043
1044 int __init ffb_init(void)
1045 {
1046         int root;
1047
1048         if (fb_get_options("ffb", NULL))
1049                 return -ENODEV;
1050
1051         ffb_scan_siblings(prom_root_node);
1052
1053         root = prom_getchild(prom_root_node);
1054         for (root = prom_searchsiblings(root, "upa"); root;
1055              root = prom_searchsiblings(prom_getsibling(root), "upa"))
1056                 ffb_scan_siblings(root);
1057
1058         return 0;
1059 }
1060
1061 void __exit ffb_exit(void)
1062 {
1063         struct list_head *pos, *tmp;
1064
1065         list_for_each_safe(pos, tmp, &ffb_list) {
1066                 struct all_info *all = list_entry(pos, typeof(*all), list);
1067
1068                 unregister_framebuffer(&all->info);
1069                 fb_dealloc_cmap(&all->info.cmap);
1070                 kfree(all);
1071         }
1072 }
1073
1074 int __init
1075 ffb_setup(char *arg)
1076 {
1077         /* No cmdline options yet... */
1078         return 0;
1079 }
1080
1081 module_init(ffb_init);
1082
1083 #ifdef MODULE
1084 module_exit(ffb_exit);
1085 #endif
1086
1087 MODULE_DESCRIPTION("framebuffer driver for Creator/Elite3D chipsets");
1088 MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
1089 MODULE_LICENSE("GPL");