2 * pata-cs5530.c - CS5530 PATA for new ATA layer
4 * Alan Cox <alan@redhat.com>
6 * based upon cs5530.c by Mark Lord.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 * Loosely based on the piix & svwks drivers.
24 * Available from AMD web site.
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/blkdev.h>
32 #include <linux/delay.h>
33 #include <scsi/scsi_host.h>
34 #include <linux/libata.h>
35 #include <linux/dmi.h>
37 #define DRV_NAME "pata_cs5530"
38 #define DRV_VERSION "0.6"
41 * cs5530_set_piomode - PIO setup
43 * @adev: device on the interface
45 * Set our PIO requirements. This is fairly simple on the CS5530
49 static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev)
51 static const unsigned int cs5530_pio_timings[2][5] = {
52 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
53 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
55 unsigned long base = ( ap->ioaddr.bmdma_addr & ~0x0F) + 0x20 + 0x10 * ap->port_no;
59 /* Find out which table to use */
60 tuning = inl(base + 0x04);
61 format = (tuning & 0x80000000UL) ? 1 : 0;
63 /* Now load the right timing register */
67 outl(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base);
71 * cs5530_set_dmamode - DMA timing setup
73 * @adev: Device being configured
75 * We cannot mix MWDMA and UDMA without reloading timings each switch
76 * master to slave. We track the last DMA setup in order to minimise
80 static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev)
82 unsigned long base = ( ap->ioaddr.bmdma_addr & ~0x0F) + 0x20 + 0x10 * ap->port_no;
83 u32 tuning, timing = 0;
86 /* Find out which table to use */
87 tuning = inl(base + 0x04);
89 switch(adev->dma_mode) {
91 timing = 0x00921250;break;
93 timing = 0x00911140;break;
95 timing = 0x00911030;break;
97 timing = 0x00077771;break;
99 timing = 0x00012121;break;
101 timing = 0x00002020;break;
105 /* Merge in the PIO format bit */
106 timing |= (tuning & 0x80000000UL);
107 if (adev->devno == 0) /* Master */
108 outl(timing, base + 0x04);
110 if (timing & 0x00100000)
111 tuning |= 0x00100000; /* UDMA for both */
113 tuning &= ~0x00100000; /* MWDMA for both */
114 outl(tuning, base + 0x04);
115 outl(timing, base + 0x0C);
118 /* Set the DMA capable bit in the BMDMA area */
119 reg = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
120 reg |= (1 << (5 + adev->devno));
121 outb(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
123 /* Remember the last DMA setup we did */
125 ap->private_data = adev;
129 * cs5530_qc_issue_prot - command issue
130 * @qc: command pending
132 * Called when the libata layer is about to issue a command. We wrap
133 * this interface so that we can load the correct ATA timings if
134 * neccessary. Specifically we have a problem that there is only
135 * one MWDMA/UDMA bit.
138 static unsigned int cs5530_qc_issue_prot(struct ata_queued_cmd *qc)
140 struct ata_port *ap = qc->ap;
141 struct ata_device *adev = qc->dev;
142 struct ata_device *prev = ap->private_data;
144 /* See if the DMA settings could be wrong */
145 if (adev->dma_mode != 0 && adev != prev && prev != NULL) {
146 /* Maybe, but do the channels match MWDMA/UDMA ? */
147 if ((adev->dma_mode >= XFER_UDMA_0 && prev->dma_mode < XFER_UDMA_0) ||
148 (adev->dma_mode < XFER_UDMA_0 && prev->dma_mode >= XFER_UDMA_0))
149 /* Switch the mode bits */
150 cs5530_set_dmamode(ap, adev);
153 return ata_qc_issue_prot(qc);
156 static int cs5530_pre_reset(struct ata_port *ap)
158 ap->cbl = ATA_CBL_PATA40;
159 return ata_std_prereset(ap);
162 static void cs5530_error_handler(struct ata_port *ap)
164 return ata_bmdma_drive_eh(ap, cs5530_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
168 static struct scsi_host_template cs5530_sht = {
169 .module = THIS_MODULE,
171 .ioctl = ata_scsi_ioctl,
172 .queuecommand = ata_scsi_queuecmd,
173 .can_queue = ATA_DEF_QUEUE,
174 .this_id = ATA_SHT_THIS_ID,
175 .sg_tablesize = LIBATA_MAX_PRD,
176 .max_sectors = ATA_MAX_SECTORS,
177 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
178 .emulated = ATA_SHT_EMULATED,
179 .use_clustering = ATA_SHT_USE_CLUSTERING,
180 .proc_name = DRV_NAME,
181 .dma_boundary = ATA_DMA_BOUNDARY,
182 .slave_configure = ata_scsi_slave_config,
183 .slave_destroy = ata_scsi_slave_destroy,
184 .bios_param = ata_std_bios_param,
187 static struct ata_port_operations cs5530_port_ops = {
188 .port_disable = ata_port_disable,
189 .set_piomode = cs5530_set_piomode,
190 .set_dmamode = cs5530_set_dmamode,
191 .mode_filter = ata_pci_default_filter,
193 .tf_load = ata_tf_load,
194 .tf_read = ata_tf_read,
195 .check_status = ata_check_status,
196 .exec_command = ata_exec_command,
197 .dev_select = ata_std_dev_select,
199 .bmdma_setup = ata_bmdma_setup,
200 .bmdma_start = ata_bmdma_start,
201 .bmdma_stop = ata_bmdma_stop,
202 .bmdma_status = ata_bmdma_status,
204 .freeze = ata_bmdma_freeze,
205 .thaw = ata_bmdma_thaw,
206 .error_handler = cs5530_error_handler,
207 .post_internal_cmd = ata_bmdma_post_internal_cmd,
209 .qc_prep = ata_qc_prep,
210 .qc_issue = cs5530_qc_issue_prot,
212 .data_xfer = ata_pio_data_xfer,
214 .irq_handler = ata_interrupt,
215 .irq_clear = ata_bmdma_irq_clear,
217 .port_start = ata_port_start,
218 .port_stop = ata_port_stop,
219 .host_stop = ata_host_stop
222 static struct dmi_system_id palmax_dmi_table[] = {
224 .ident = "Palmax PD1100",
226 DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"),
227 DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"),
233 static int cs5530_is_palmax(void)
235 if (dmi_check_system(palmax_dmi_table)) {
236 printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n");
243 * cs5530_init_one - Initialise a CS5530
245 * @id: Entry in match table
247 * Install a driver for the newly found CS5530 companion chip. Most of
248 * this is just housekeeping. We have to set the chip up correctly and
249 * turn off various bits of emulation magic.
252 static int cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
254 int compiler_warning_pointless_fix;
255 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
256 static struct ata_port_info info = {
258 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
262 .port_ops = &cs5530_port_ops
264 /* The docking connector doesn't do UDMA, and it seems not MWDMA */
265 static struct ata_port_info info_palmax_secondary = {
267 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
269 .port_ops = &cs5530_port_ops
271 static struct ata_port_info *port_info[2] = { &info, &info };
274 while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
275 switch (dev->device) {
276 case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
277 master_0 = pci_dev_get(dev);
279 case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
280 cs5530_0 = pci_dev_get(dev);
285 printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
289 printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
293 pci_set_master(cs5530_0);
294 compiler_warning_pointless_fix = pci_set_mwi(cs5530_0);
297 * Set PCI CacheLineSize to 16-bytes:
298 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
300 * Note: This value is constant because the 5530 is only a Geode companion
303 pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
306 * Disable trapping of UDMA register accesses (Win98 hack):
307 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
310 pci_write_config_word(cs5530_0, 0xd0, 0x5006);
313 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
314 * The other settings are what is necessary to get the register
315 * into a sane state for IDE DMA operation.
318 pci_write_config_byte(master_0, 0x40, 0x1e);
321 * Set max PCI burst size (16-bytes seems to work best):
322 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
323 * all others: clear bit-1 at 0x41, and do:
324 * 128bytes: OR 0x00 at 0x41
325 * 256bytes: OR 0x04 at 0x41
326 * 512bytes: OR 0x08 at 0x41
327 * 1024bytes: OR 0x0c at 0x41
330 pci_write_config_byte(master_0, 0x41, 0x14);
333 * These settings are necessary to get the chip
334 * into a sane state for IDE DMA operation.
337 pci_write_config_byte(master_0, 0x42, 0x00);
338 pci_write_config_byte(master_0, 0x43, 0xc1);
340 pci_dev_put(master_0);
341 pci_dev_put(cs5530_0);
343 if (cs5530_is_palmax())
344 port_info[1] = &info_palmax_secondary;
346 /* Now kick off ATA set up */
347 return ata_pci_init_one(dev, port_info, 2);
351 pci_dev_put(master_0);
353 pci_dev_put(cs5530_0);
357 static const struct pci_device_id cs5530[] = {
358 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },
363 static struct pci_driver cs5530_pci_driver = {
366 .probe = cs5530_init_one,
367 .remove = ata_pci_remove_one
370 static int __init cs5530_init(void)
372 return pci_register_driver(&cs5530_pci_driver);
375 static void __exit cs5530_exit(void)
377 pci_unregister_driver(&cs5530_pci_driver);
380 MODULE_AUTHOR("Alan Cox");
381 MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
382 MODULE_LICENSE("GPL");
383 MODULE_DEVICE_TABLE(pci, cs5530);
384 MODULE_VERSION(DRV_VERSION);
386 module_init(cs5530_init);
387 module_exit(cs5530_exit);