2 * cx18 driver PCI memory mapped IO access routines
4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
5 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
23 #include "cx18-driver.h"
27 void cx18_log_statistics(struct cx18 *cx)
31 if (!(cx18_debug & CX18_DBGFLG_INFO))
34 for (i = 0; i <= CX18_MAX_MB_ACK_DELAY; i++)
35 if (atomic_read(&cx->mbox_stats.mb_ack_delay[i]))
36 CX18_DEBUG_INFO("mb_ack_delay[%d] = %d\n", i,
37 atomic_read(&cx->mbox_stats.mb_ack_delay[i]));
41 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
43 u8 __iomem *dst = addr;
44 u16 val2 = val | (val << 8);
45 u32 val4 = val2 | (val2 << 16);
47 /* Align writes on the CX23418's addresses */
48 if ((count > 0) && ((unsigned long)dst & 1)) {
49 cx18_writeb(cx, (u8) val, dst);
53 if ((count > 1) && ((unsigned long)dst & 2)) {
54 cx18_writew(cx, val2, dst);
59 cx18_writel(cx, val4, dst);
64 cx18_writew(cx, val2, dst);
69 cx18_writeb(cx, (u8) val, dst);
72 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
75 cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
76 r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
77 cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI);
80 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
83 r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
84 cx18_write_reg(cx, r & ~val, SW1_INT_ENABLE_PCI);
87 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
90 cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
91 r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
92 cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI);
95 void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
98 r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
99 cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_PCI);
102 void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
105 r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
106 cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
109 void cx18_setup_page(struct cx18 *cx, u32 addr)
112 val = cx18_read_reg(cx, 0xD000F8);
113 val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
114 cx18_write_reg(cx, val, 0xD000F8);