git.oblomov.eu Git - linux-2.6/blob - arch/blackfin/mach-common/ints-priority.c

   1 /*
   2  * File:         arch/blackfin/mach-common/ints-priority.c
   3  *
   4  * Description:  Set up the interrupt priorities
   5  *
   6  * Modified:
   7  *               1996 Roman Zippel
   8  *               1999 D. Jeff Dionne <jeff@uclinux.org>
   9  *               2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
  10  *               2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
  11  *               2003 Metrowerks/Motorola
  12  *               2003 Bas Vermeulen <bas@buyways.nl>
  13  *               Copyright 2004-2008 Analog Devices Inc.
  14  *
  15  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License as published by
  19  * the Free Software Foundation; either version 2 of the License, or
  20  * (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, see the file COPYING, or write
  29  * to the Free Software Foundation, Inc.,
  30  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  31  */
  32
  33 #include <linux/module.h>
  34 #include <linux/kernel_stat.h>
  35 #include <linux/seq_file.h>
  36 #include <linux/irq.h>
  37 #ifdef CONFIG_KGDB
  38 #include <linux/kgdb.h>
  39 #endif
  40 #include <asm/traps.h>
  41 #include <asm/blackfin.h>
  42 #include <asm/gpio.h>
  43 #include <asm/irq_handler.h>
  44
  45 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
  46
  47 #ifdef BF537_FAMILY
  48 # define BF537_GENERIC_ERROR_INT_DEMUX
  49 #else
  50 # undef BF537_GENERIC_ERROR_INT_DEMUX
  51 #endif
  52
  53 /*
  54  * NOTES:
  55  * - we have separated the physical Hardware interrupt from the
  56  * levels that the LINUX kernel sees (see the description in irq.h)
  57  * -
  58  */
  59
  60 #ifndef CONFIG_SMP
  61 /* Initialize this to an actual value to force it into the .data
  62  * section so that we know it is properly initialized at entry into
  63  * the kernel but before bss is initialized to zero (which is where
  64  * it would live otherwise).  The 0x1f magic represents the IRQs we
  65  * cannot actually mask out in hardware.
  66  */
  67 unsigned long bfin_irq_flags = 0x1f;
  68 EXPORT_SYMBOL(bfin_irq_flags);
  69 #endif
  70
  71 /* The number of spurious interrupts */
  72 atomic_t num_spurious;
  73
  74 #ifdef CONFIG_PM
  75 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
  76 unsigned vr_wakeup;
  77 #endif
  78
  79 struct ivgx {
  80         /* irq number for request_irq, available in mach-bf5xx/irq.h */
  81         unsigned int irqno;
  82         /* corresponding bit in the SIC_ISR register */
  83         unsigned int isrflag;
  84 } ivg_table[NR_PERI_INTS];
  85
  86 struct ivg_slice {
  87         /* position of first irq in ivg_table for given ivg */
  88         struct ivgx *ifirst;
  89         struct ivgx *istop;
  90 } ivg7_13[IVG13 - IVG7 + 1];
  91
  92
  93 /*
  94  * Search SIC_IAR and fill tables with the irqvalues
  95  * and their positions in the SIC_ISR register.
  96  */
  97 static void __init search_IAR(void)
  98 {
  99         unsigned ivg, irq_pos = 0;
 100         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
 101                 int irqn;
 102
 103                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
 104
 105                 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
 106                         int iar_shift = (irqn & 7) * 4;
 107                                 if (ivg == (0xf &
 108 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
 109         || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
 110                              bfin_read32((unsigned long *)SIC_IAR0 +
 111                                          ((irqn % 32) >> 3) + ((irqn / 32) *
 112                                          ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
 113 #else
 114                              bfin_read32((unsigned long *)SIC_IAR0 +
 115                                          (irqn >> 3)) >> iar_shift)) {
 116 #endif
 117                                 ivg_table[irq_pos].irqno = IVG7 + irqn;
 118                                 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
 119                                 ivg7_13[ivg].istop++;
 120                                 irq_pos++;
 121                         }
 122                 }
 123         }
 124 }
 125
 126 /*
 127  * This is for core internal IRQs
 128  */
 129
 130 static void bfin_ack_noop(unsigned int irq)
 131 {
 132         /* Dummy function.  */
 133 }
 134
 135 static void bfin_core_mask_irq(unsigned int irq)
 136 {
 137         bfin_irq_flags &= ~(1 << irq);
 138         if (!irqs_disabled())
 139                 local_irq_enable();
 140 }
 141
 142 static void bfin_core_unmask_irq(unsigned int irq)
 143 {
 144         bfin_irq_flags |= 1 << irq;
 145         /*
 146          * If interrupts are enabled, IMASK must contain the same value
 147          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 148          * are currently disabled we need not do anything; one of the
 149          * callers will take care of setting IMASK to the proper value
 150          * when reenabling interrupts.
 151          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 152          * what we need.
 153          */
 154         if (!irqs_disabled())
 155                 local_irq_enable();
 156         return;
 157 }
 158
 159 static void bfin_internal_mask_irq(unsigned int irq)
 160 {
 161 #ifdef CONFIG_BF53x
 162         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 163                              ~(1 << SIC_SYSIRQ(irq)));
 164 #else
 165         unsigned mask_bank, mask_bit;
 166         mask_bank = SIC_SYSIRQ(irq) / 32;
 167         mask_bit = SIC_SYSIRQ(irq) % 32;
 168         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 169                              ~(1 << mask_bit));
 170 #ifdef CONFIG_SMP
 171         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
 172                              ~(1 << mask_bit));
 173 #endif
 174 #endif
 175 }
 176
 177 static void bfin_internal_unmask_irq(unsigned int irq)
 178 {
 179 #ifdef CONFIG_BF53x
 180         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 181                              (1 << SIC_SYSIRQ(irq)));
 182 #else
 183         unsigned mask_bank, mask_bit;
 184         mask_bank = SIC_SYSIRQ(irq) / 32;
 185         mask_bit = SIC_SYSIRQ(irq) % 32;
 186         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
 187                              (1 << mask_bit));
 188 #ifdef CONFIG_SMP
 189         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) |
 190                              (1 << mask_bit));
 191 #endif
 192 #endif
 193 }
 194
 195 #ifdef CONFIG_PM
 196 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 197 {
 198         u32 bank, bit, wakeup = 0;
 199         unsigned long flags;
 200         bank = SIC_SYSIRQ(irq) / 32;
 201         bit = SIC_SYSIRQ(irq) % 32;
 202
 203         switch (irq) {
 204 #ifdef IRQ_RTC
 205         case IRQ_RTC:
 206         wakeup |= WAKE;
 207         break;
 208 #endif
 209 #ifdef IRQ_CAN0_RX
 210         case IRQ_CAN0_RX:
 211         wakeup |= CANWE;
 212         break;
 213 #endif
 214 #ifdef IRQ_CAN1_RX
 215         case IRQ_CAN1_RX:
 216         wakeup |= CANWE;
 217         break;
 218 #endif
 219 #ifdef IRQ_USB_INT0
 220         case IRQ_USB_INT0:
 221         wakeup |= USBWE;
 222         break;
 223 #endif
 224 #ifdef IRQ_KEY
 225         case IRQ_KEY:
 226         wakeup |= KPADWE;
 227         break;
 228 #endif
 229 #ifdef CONFIG_BF54x
 230         case IRQ_CNT:
 231         wakeup |= ROTWE;
 232         break;
 233 #endif
 234         default:
 235         break;
 236         }
 237
 238         local_irq_save(flags);
 239
 240         if (state) {
 241                 bfin_sic_iwr[bank] |= (1 << bit);
 242                 vr_wakeup  |= wakeup;
 243
 244         } else {
 245                 bfin_sic_iwr[bank] &= ~(1 << bit);
 246                 vr_wakeup  &= ~wakeup;
 247         }
 248
 249         local_irq_restore(flags);
 250
 251         return 0;
 252 }
 253 #endif
 254
 255 static struct irq_chip bfin_core_irqchip = {
 256         .name = "CORE",
 257         .ack = bfin_ack_noop,
 258         .mask = bfin_core_mask_irq,
 259         .unmask = bfin_core_unmask_irq,
 260 };
 261
 262 static struct irq_chip bfin_internal_irqchip = {
 263         .name = "INTN",
 264         .ack = bfin_ack_noop,
 265         .mask = bfin_internal_mask_irq,
 266         .unmask = bfin_internal_unmask_irq,
 267         .mask_ack = bfin_internal_mask_irq,
 268         .disable = bfin_internal_mask_irq,
 269         .enable = bfin_internal_unmask_irq,
 270 #ifdef CONFIG_PM
 271         .set_wake = bfin_internal_set_wake,
 272 #endif
 273 };
 274
 275 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 276 static int error_int_mask;
 277
 278 static void bfin_generic_error_mask_irq(unsigned int irq)
 279 {
 280         error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
 281
 282         if (!error_int_mask)
 283                 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
 284 }
 285
 286 static void bfin_generic_error_unmask_irq(unsigned int irq)
 287 {
 288         bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
 289         error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
 290 }
 291
 292 static struct irq_chip bfin_generic_error_irqchip = {
 293         .name = "ERROR",
 294         .ack = bfin_ack_noop,
 295         .mask_ack = bfin_generic_error_mask_irq,
 296         .mask = bfin_generic_error_mask_irq,
 297         .unmask = bfin_generic_error_unmask_irq,
 298 };
 299
 300 static void bfin_demux_error_irq(unsigned int int_err_irq,
 301                                  struct irq_desc *inta_desc)
 302 {
 303         int irq = 0;
 304
 305 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 306         if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
 307                 irq = IRQ_MAC_ERROR;
 308         else
 309 #endif
 310         if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
 311                 irq = IRQ_SPORT0_ERROR;
 312         else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
 313                 irq = IRQ_SPORT1_ERROR;
 314         else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
 315                 irq = IRQ_PPI_ERROR;
 316         else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
 317                 irq = IRQ_CAN_ERROR;
 318         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
 319                 irq = IRQ_SPI_ERROR;
 320         else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
 321                  (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
 322                 irq = IRQ_UART0_ERROR;
 323         else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
 324                  (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
 325                 irq = IRQ_UART1_ERROR;
 326
 327         if (irq) {
 328                 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
 329                         struct irq_desc *desc = irq_desc + irq;
 330                         desc->handle_irq(irq, desc);
 331                 } else {
 332
 333                         switch (irq) {
 334                         case IRQ_PPI_ERROR:
 335                                 bfin_write_PPI_STATUS(PPI_ERR_MASK);
 336                                 break;
 337 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 338                         case IRQ_MAC_ERROR:
 339                                 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
 340                                 break;
 341 #endif
 342                         case IRQ_SPORT0_ERROR:
 343                                 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
 344                                 break;
 345
 346                         case IRQ_SPORT1_ERROR:
 347                                 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
 348                                 break;
 349
 350                         case IRQ_CAN_ERROR:
 351                                 bfin_write_CAN_GIS(CAN_ERR_MASK);
 352                                 break;
 353
 354                         case IRQ_SPI_ERROR:
 355                                 bfin_write_SPI_STAT(SPI_ERR_MASK);
 356                                 break;
 357
 358                         default:
 359                                 break;
 360                         }
 361
 362                         pr_debug("IRQ %d:"
 363                                  " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
 364                                  irq);
 365                 }
 366         } else
 367                 printk(KERN_ERR
 368                        "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
 369                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
 370                        __func__, __FILE__, __LINE__);
 371
 372 }
 373 #endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
 374
 375 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 376 {
 377         struct irq_desc *desc = irq_desc + irq;
 378         /* May not call generic set_irq_handler() due to spinlock
 379            recursion. */
 380         desc->handle_irq = handle;
 381 }
 382
 383 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 384 extern void bfin_gpio_irq_prepare(unsigned gpio);
 385
 386 #if !defined(CONFIG_BF54x)
 387
 388 static void bfin_gpio_ack_irq(unsigned int irq)
 389 {
 390         /* AFAIK ack_irq in case mask_ack is provided
 391          * get's only called for edge sense irqs
 392          */
 393         set_gpio_data(irq_to_gpio(irq), 0);
 394 }
 395
 396 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 397 {
 398         struct irq_desc *desc = irq_desc + irq;
 399         u32 gpionr = irq_to_gpio(irq);
 400
 401         if (desc->handle_irq == handle_edge_irq)
 402                 set_gpio_data(gpionr, 0);
 403
 404         set_gpio_maska(gpionr, 0);
 405 }
 406
 407 static void bfin_gpio_mask_irq(unsigned int irq)
 408 {
 409         set_gpio_maska(irq_to_gpio(irq), 0);
 410 }
 411
 412 static void bfin_gpio_unmask_irq(unsigned int irq)
 413 {
 414         set_gpio_maska(irq_to_gpio(irq), 1);
 415 }
 416
 417 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 418 {
 419         u32 gpionr = irq_to_gpio(irq);
 420
 421         if (__test_and_set_bit(gpionr, gpio_enabled))
 422                 bfin_gpio_irq_prepare(gpionr);
 423
 424         bfin_gpio_unmask_irq(irq);
 425
 426         return 0;
 427 }
 428
 429 static void bfin_gpio_irq_shutdown(unsigned int irq)
 430 {
 431         bfin_gpio_mask_irq(irq);
 432         __clear_bit(irq_to_gpio(irq), gpio_enabled);
 433 }
 434
 435 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 436 {
 437         u32 gpionr = irq_to_gpio(irq);
 438
 439         if (type == IRQ_TYPE_PROBE) {
 440                 /* only probe unenabled GPIO interrupt lines */
 441                 if (__test_bit(gpionr, gpio_enabled))
 442                         return 0;
 443                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 444         }
 445
 446         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 447                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 448
 449                 if (__test_and_set_bit(gpionr, gpio_enabled))
 450                         bfin_gpio_irq_prepare(gpionr);
 451
 452         } else {
 453                 __clear_bit(gpionr, gpio_enabled);
 454                 return 0;
 455         }
 456
 457         set_gpio_inen(gpionr, 0);
 458         set_gpio_dir(gpionr, 0);
 459
 460         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 461             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 462                 set_gpio_both(gpionr, 1);
 463         else
 464                 set_gpio_both(gpionr, 0);
 465
 466         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 467                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 468         else
 469                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 470
 471         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 472                 set_gpio_edge(gpionr, 1);
 473                 set_gpio_inen(gpionr, 1);
 474                 set_gpio_data(gpionr, 0);
 475
 476         } else {
 477                 set_gpio_edge(gpionr, 0);
 478                 set_gpio_inen(gpionr, 1);
 479         }
 480
 481         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 482                 bfin_set_irq_handler(irq, handle_edge_irq);
 483         else
 484                 bfin_set_irq_handler(irq, handle_level_irq);
 485
 486         return 0;
 487 }
 488
 489 #ifdef CONFIG_PM
 490 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 491 {
 492         unsigned gpio = irq_to_gpio(irq);
 493
 494         if (state)
 495                 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
 496         else
 497                 gpio_pm_wakeup_free(gpio);
 498
 499         return 0;
 500 }
 501 #endif
 502
 503 static void bfin_demux_gpio_irq(unsigned int inta_irq,
 504                                 struct irq_desc *desc)
 505 {
 506         unsigned int i, gpio, mask, irq, search = 0;
 507
 508         switch (inta_irq) {
 509 #if defined(CONFIG_BF53x)
 510         case IRQ_PROG_INTA:
 511                 irq = IRQ_PF0;
 512                 search = 1;
 513                 break;
 514 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
 515         case IRQ_MAC_RX:
 516                 irq = IRQ_PH0;
 517                 break;
 518 # endif
 519 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
 520         case IRQ_PORTF_INTA:
 521                 irq = IRQ_PF0;
 522                 break;
 523 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 524         case IRQ_PORTF_INTA:
 525                 irq = IRQ_PF0;
 526                 break;
 527         case IRQ_PORTG_INTA:
 528                 irq = IRQ_PG0;
 529                 break;
 530         case IRQ_PORTH_INTA:
 531                 irq = IRQ_PH0;
 532                 break;
 533 #elif defined(CONFIG_BF561)
 534         case IRQ_PROG0_INTA:
 535                 irq = IRQ_PF0;
 536                 break;
 537         case IRQ_PROG1_INTA:
 538                 irq = IRQ_PF16;
 539                 break;
 540         case IRQ_PROG2_INTA:
 541                 irq = IRQ_PF32;
 542                 break;
 543 #endif
 544         default:
 545                 BUG();
 546                 return;
 547         }
 548
 549         if (search) {
 550                 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
 551                         irq += i;
 552
 553                         mask = get_gpiop_data(i) & get_gpiop_maska(i);
 554
 555                         while (mask) {
 556                                 if (mask & 1) {
 557                                         desc = irq_desc + irq;
 558                                         desc->handle_irq(irq, desc);
 559                                 }
 560                                 irq++;
 561                                 mask >>= 1;
 562                         }
 563                 }
 564         } else {
 565                         gpio = irq_to_gpio(irq);
 566                         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 567
 568                         do {
 569                                 if (mask & 1) {
 570                                         desc = irq_desc + irq;
 571                                         desc->handle_irq(irq, desc);
 572                                 }
 573                                 irq++;
 574                                 mask >>= 1;
 575                         } while (mask);
 576         }
 577
 578 }
 579
 580 #else                           /* CONFIG_BF54x */
 581
 582 #define NR_PINT_SYS_IRQS        4
 583 #define NR_PINT_BITS            32
 584 #define NR_PINTS                160
 585 #define IRQ_NOT_AVAIL           0xFF
 586
 587 #define PINT_2_BANK(x)          ((x) >> 5)
 588 #define PINT_2_BIT(x)           ((x) & 0x1F)
 589 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
 590
 591 static unsigned char irq2pint_lut[NR_PINTS];
 592 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 593
 594 struct pin_int_t {
 595         unsigned int mask_set;
 596         unsigned int mask_clear;
 597         unsigned int request;
 598         unsigned int assign;
 599         unsigned int edge_set;
 600         unsigned int edge_clear;
 601         unsigned int invert_set;
 602         unsigned int invert_clear;
 603         unsigned int pinstate;
 604         unsigned int latch;
 605 };
 606
 607 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
 608         (struct pin_int_t *)PINT0_MASK_SET,
 609         (struct pin_int_t *)PINT1_MASK_SET,
 610         (struct pin_int_t *)PINT2_MASK_SET,
 611         (struct pin_int_t *)PINT3_MASK_SET,
 612 };
 613
 614 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 615 {
 616         unsigned int irq_base;
 617
 618         if (bank < 2) {         /*PA-PB */
 619                 irq_base = IRQ_PA0 + bmap * 16;
 620         } else {                /*PC-PJ */
 621                 irq_base = IRQ_PC0 + bmap * 16;
 622         }
 623
 624         return irq_base;
 625 }
 626
 627         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 628 void init_pint_lut(void)
 629 {
 630         u16 bank, bit, irq_base, bit_pos;
 631         u32 pint_assign;
 632         u8 bmap;
 633
 634         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
 635
 636         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
 637
 638                 pint_assign = pint[bank]->assign;
 639
 640                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
 641
 642                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
 643
 644                         irq_base = get_irq_base(bank, bmap);
 645
 646                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
 647                         bit_pos = bit + bank * NR_PINT_BITS;
 648
 649                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
 650                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
 651                 }
 652         }
 653 }
 654
 655 static void bfin_gpio_ack_irq(unsigned int irq)
 656 {
 657         struct irq_desc *desc = irq_desc + irq;
 658         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 659         u32 pintbit = PINT_BIT(pint_val);
 660         u32 bank = PINT_2_BANK(pint_val);
 661
 662         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 663                 if (pint[bank]->invert_set & pintbit)
 664                         pint[bank]->invert_clear = pintbit;
 665                 else
 666                         pint[bank]->invert_set = pintbit;
 667         }
 668         pint[bank]->request = pintbit;
 669
 670 }
 671
 672 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 673 {
 674         struct irq_desc *desc = irq_desc + irq;
 675         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 676         u32 pintbit = PINT_BIT(pint_val);
 677         u32 bank = PINT_2_BANK(pint_val);
 678
 679         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 680                 if (pint[bank]->invert_set & pintbit)
 681                         pint[bank]->invert_clear = pintbit;
 682                 else
 683                         pint[bank]->invert_set = pintbit;
 684         }
 685
 686         pint[bank]->request = pintbit;
 687         pint[bank]->mask_clear = pintbit;
 688 }
 689
 690 static void bfin_gpio_mask_irq(unsigned int irq)
 691 {
 692         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 693
 694         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
 695 }
 696
 697 static void bfin_gpio_unmask_irq(unsigned int irq)
 698 {
 699         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 700         u32 pintbit = PINT_BIT(pint_val);
 701         u32 bank = PINT_2_BANK(pint_val);
 702
 703         pint[bank]->request = pintbit;
 704         pint[bank]->mask_set = pintbit;
 705 }
 706
 707 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 708 {
 709         u32 gpionr = irq_to_gpio(irq);
 710         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 711
 712         if (pint_val == IRQ_NOT_AVAIL) {
 713                 printk(KERN_ERR
 714                 "GPIO IRQ %d :Not in PINT Assign table "
 715                 "Reconfigure Interrupt to Port Assignemt\n", irq);
 716                 return -ENODEV;
 717         }
 718
 719         if (__test_and_set_bit(gpionr, gpio_enabled))
 720                 bfin_gpio_irq_prepare(gpionr);
 721
 722         bfin_gpio_unmask_irq(irq);
 723
 724         return 0;
 725 }
 726
 727 static void bfin_gpio_irq_shutdown(unsigned int irq)
 728 {
 729         u32 gpionr = irq_to_gpio(irq);
 730
 731         bfin_gpio_mask_irq(irq);
 732         __clear_bit(gpionr, gpio_enabled);
 733 }
 734
 735 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 736 {
 737
 738         u32 gpionr = irq_to_gpio(irq);
 739         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 740         u32 pintbit = PINT_BIT(pint_val);
 741         u32 bank = PINT_2_BANK(pint_val);
 742
 743         if (pint_val == IRQ_NOT_AVAIL)
 744                 return -ENODEV;
 745
 746         if (type == IRQ_TYPE_PROBE) {
 747                 /* only probe unenabled GPIO interrupt lines */
 748                 if (__test_bit(gpionr, gpio_enabled))
 749                         return 0;
 750                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 751         }
 752
 753         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 754                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 755                 if (__test_and_set_bit(gpionr, gpio_enabled))
 756                         bfin_gpio_irq_prepare(gpionr);
 757
 758         } else {
 759                 __clear_bit(gpionr, gpio_enabled);
 760                 return 0;
 761         }
 762
 763         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 764                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
 765         else
 766                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
 767
 768         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 769             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 770                 if (gpio_get_value(gpionr))
 771                         pint[bank]->invert_set = pintbit;
 772                 else
 773                         pint[bank]->invert_clear = pintbit;
 774         }
 775
 776         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 777                 pint[bank]->edge_set = pintbit;
 778                 bfin_set_irq_handler(irq, handle_edge_irq);
 779         } else {
 780                 pint[bank]->edge_clear = pintbit;
 781                 bfin_set_irq_handler(irq, handle_level_irq);
 782         }
 783
 784         return 0;
 785 }
 786
 787 #ifdef CONFIG_PM
 788 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
 789 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
 790
 791 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 792 {
 793         u32 pint_irq;
 794         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 795         u32 bank = PINT_2_BANK(pint_val);
 796         u32 pintbit = PINT_BIT(pint_val);
 797
 798         switch (bank) {
 799         case 0:
 800                 pint_irq = IRQ_PINT0;
 801                 break;
 802         case 2:
 803                 pint_irq = IRQ_PINT2;
 804                 break;
 805         case 3:
 806                 pint_irq = IRQ_PINT3;
 807                 break;
 808         case 1:
 809                 pint_irq = IRQ_PINT1;
 810                 break;
 811         default:
 812                 return -EINVAL;
 813         }
 814
 815         bfin_internal_set_wake(pint_irq, state);
 816
 817         if (state)
 818                 pint_wakeup_masks[bank] |= pintbit;
 819         else
 820                 pint_wakeup_masks[bank] &= ~pintbit;
 821
 822         return 0;
 823 }
 824
 825 u32 bfin_pm_setup(void)
 826 {
 827         u32 val, i;
 828
 829         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
 830                 val = pint[i]->mask_clear;
 831                 pint_saved_masks[i] = val;
 832                 if (val ^ pint_wakeup_masks[i]) {
 833                         pint[i]->mask_clear = val;
 834                         pint[i]->mask_set = pint_wakeup_masks[i];
 835                 }
 836         }
 837
 838         return 0;
 839 }
 840
 841 void bfin_pm_restore(void)
 842 {
 843         u32 i, val;
 844
 845         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
 846                 val = pint_saved_masks[i];
 847                 if (val ^ pint_wakeup_masks[i]) {
 848                         pint[i]->mask_clear = pint[i]->mask_clear;
 849                         pint[i]->mask_set = val;
 850                 }
 851         }
 852 }
 853 #endif
 854
 855 static void bfin_demux_gpio_irq(unsigned int inta_irq,
 856                                 struct irq_desc *desc)
 857 {
 858         u32 bank, pint_val;
 859         u32 request, irq;
 860
 861         switch (inta_irq) {
 862         case IRQ_PINT0:
 863                 bank = 0;
 864                 break;
 865         case IRQ_PINT2:
 866                 bank = 2;
 867                 break;
 868         case IRQ_PINT3:
 869                 bank = 3;
 870                 break;
 871         case IRQ_PINT1:
 872                 bank = 1;
 873                 break;
 874         default:
 875                 return;
 876         }
 877
 878         pint_val = bank * NR_PINT_BITS;
 879
 880         request = pint[bank]->request;
 881
 882         while (request) {
 883                 if (request & 1) {
 884                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
 885                         desc = irq_desc + irq;
 886                         desc->handle_irq(irq, desc);
 887                 }
 888                 pint_val++;
 889                 request >>= 1;
 890         }
 891
 892 }
 893 #endif
 894
 895 static struct irq_chip bfin_gpio_irqchip = {
 896         .name = "GPIO",
 897         .ack = bfin_gpio_ack_irq,
 898         .mask = bfin_gpio_mask_irq,
 899         .mask_ack = bfin_gpio_mask_ack_irq,
 900         .unmask = bfin_gpio_unmask_irq,
 901         .disable = bfin_gpio_mask_irq,
 902         .enable = bfin_gpio_unmask_irq,
 903         .set_type = bfin_gpio_irq_type,
 904         .startup = bfin_gpio_irq_startup,
 905         .shutdown = bfin_gpio_irq_shutdown,
 906 #ifdef CONFIG_PM
 907         .set_wake = bfin_gpio_set_wake,
 908 #endif
 909 };
 910
 911 void __cpuinit init_exception_vectors(void)
 912 {
 913         /* cannot program in software:
 914          * evt0 - emulation (jtag)
 915          * evt1 - reset
 916          */
 917         bfin_write_EVT2(evt_nmi);
 918         bfin_write_EVT3(trap);
 919         bfin_write_EVT5(evt_ivhw);
 920         bfin_write_EVT6(evt_timer);
 921         bfin_write_EVT7(evt_evt7);
 922         bfin_write_EVT8(evt_evt8);
 923         bfin_write_EVT9(evt_evt9);
 924         bfin_write_EVT10(evt_evt10);
 925         bfin_write_EVT11(evt_evt11);
 926         bfin_write_EVT12(evt_evt12);
 927         bfin_write_EVT13(evt_evt13);
 928         bfin_write_EVT14(evt14_softirq);
 929         bfin_write_EVT15(evt_system_call);
 930         CSYNC();
 931 }
 932
 933 /*
 934  * This function should be called during kernel startup to initialize
 935  * the BFin IRQ handling routines.
 936  */
 937
 938 int __init init_arch_irq(void)
 939 {
 940         int irq;
 941         unsigned long ilat = 0;
 942         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
 943 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
 944         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
 945         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
 946         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
 947 # ifdef CONFIG_BF54x
 948         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
 949 # endif
 950 # ifdef CONFIG_SMP
 951         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
 952         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
 953 # endif
 954 #else
 955         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
 956 #endif
 957
 958         local_irq_disable();
 959
 960 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 961         /* Clear EMAC Interrupt Status bits so we can demux it later */
 962         bfin_write_EMAC_SYSTAT(-1);
 963 #endif
 964
 965 #ifdef CONFIG_BF54x
 966 # ifdef CONFIG_PINTx_REASSIGN
 967         pint[0]->assign = CONFIG_PINT0_ASSIGN;
 968         pint[1]->assign = CONFIG_PINT1_ASSIGN;
 969         pint[2]->assign = CONFIG_PINT2_ASSIGN;
 970         pint[3]->assign = CONFIG_PINT3_ASSIGN;
 971 # endif
 972         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 973         init_pint_lut();
 974 #endif
 975
 976         for (irq = 0; irq <= SYS_IRQS; irq++) {
 977                 if (irq <= IRQ_CORETMR)
 978                         set_irq_chip(irq, &bfin_core_irqchip);
 979                 else
 980                         set_irq_chip(irq, &bfin_internal_irqchip);
 981
 982                 switch (irq) {
 983 #if defined(CONFIG_BF53x)
 984                 case IRQ_PROG_INTA:
 985 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
 986                 case IRQ_MAC_RX:
 987 # endif
 988 #elif defined(CONFIG_BF54x)
 989                 case IRQ_PINT0:
 990                 case IRQ_PINT1:
 991                 case IRQ_PINT2:
 992                 case IRQ_PINT3:
 993 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 994                 case IRQ_PORTF_INTA:
 995                 case IRQ_PORTG_INTA:
 996                 case IRQ_PORTH_INTA:
 997 #elif defined(CONFIG_BF561)
 998                 case IRQ_PROG0_INTA:
 999                 case IRQ_PROG1_INTA:
1000                 case IRQ_PROG2_INTA:
1001 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1002                 case IRQ_PORTF_INTA:
1003 #endif
1004
1005                         set_irq_chained_handler(irq,
1006                                                 bfin_demux_gpio_irq);
1007                         break;
1008 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1009                 case IRQ_GENERIC_ERROR:
1010                         set_irq_handler(irq, bfin_demux_error_irq);
1011
1012                         break;
1013 #endif
1014 #ifdef CONFIG_TICK_SOURCE_SYSTMR0
1015                 case IRQ_TIMER0:
1016                         set_irq_handler(irq, handle_percpu_irq);
1017                         break;
1018 #endif
1019 #ifdef CONFIG_SMP
1020                 case IRQ_SUPPLE_0:
1021                 case IRQ_SUPPLE_1:
1022                         set_irq_handler(irq, handle_percpu_irq);
1023                         break;
1024 #endif
1025                 default:
1026                         set_irq_handler(irq, handle_simple_irq);
1027                         break;
1028                 }
1029         }
1030
1031 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1032         for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1033                 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1034                                          handle_level_irq);
1035 #endif
1036
1037         /* if configured as edge, then will be changed to do_edge_IRQ */
1038         for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1039                 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1040                                          handle_level_irq);
1041
1042
1043         bfin_write_IMASK(0);
1044         CSYNC();
1045         ilat = bfin_read_ILAT();
1046         CSYNC();
1047         bfin_write_ILAT(ilat);
1048         CSYNC();
1049
1050         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1051         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1052          * local_irq_enable()
1053          */
1054         program_IAR();
1055         /* Therefore it's better to setup IARs before interrupts enabled */
1056         search_IAR();
1057
1058         /* Enable interrupts IVG7-15 */
1059         bfin_irq_flags |= IMASK_IVG15 |
1060             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1061             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1062
1063 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1064         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1065         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1066 #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1067         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1068          * will screw up the bootrom as it relies on MDMA0/1 waking it
1069          * up from IDLE instructions.  See this report for more info:
1070          * http://blackfin.uclinux.org/gf/tracker/4323
1071          */
1072         bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1073 #else
1074         bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1075 #endif
1076 # ifdef CONFIG_BF54x
1077         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1078 # endif
1079 #else
1080         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1081 #endif
1082
1083         return 0;
1084 }
1085
1086 #ifdef CONFIG_DO_IRQ_L1
1087 __attribute__((l1_text))
1088 #endif
1089 void do_irq(int vec, struct pt_regs *fp)
1090 {
1091         if (vec == EVT_IVTMR_P) {
1092                 vec = IRQ_CORETMR;
1093         } else {
1094                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1095                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1096 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1097         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1098                 unsigned long sic_status[3];
1099
1100                 if (smp_processor_id()) {
1101 #ifdef CONFIG_SMP
1102                         /* This will be optimized out in UP mode. */
1103                         sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1104                         sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1105 #endif
1106                 } else {
1107                         sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1108                         sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1109                 }
1110 #ifdef CONFIG_BF54x
1111                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1112 #endif
1113                 for (;; ivg++) {
1114                         if (ivg >= ivg_stop) {
1115                                 atomic_inc(&num_spurious);
1116                                 return;
1117                         }
1118                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1119                                 break;
1120                 }
1121 #else
1122                 unsigned long sic_status;
1123
1124                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1125
1126                 for (;; ivg++) {
1127                         if (ivg >= ivg_stop) {
1128                                 atomic_inc(&num_spurious);
1129                                 return;
1130                         } else if (sic_status & ivg->isrflag)
1131                                 break;
1132                 }
1133 #endif
1134                 vec = ivg->irqno;
1135         }
1136         asm_do_IRQ(vec, fp);
1137 }