git.oblomov.eu Git - linux-2.6/blob - arch/arm/mach-omap1/serial.c

   1 /*
   2  * linux/arch/arm/mach-omap1/id.c
   3  *
   4  * OMAP1 CPU identification code
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/serial.h>
  17 #include <linux/tty.h>
  18 #include <linux/serial_8250.h>
  19 #include <linux/serial_reg.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/mach-types.h>
  23 #include <asm/hardware/clock.h>
  24
  25 #include <asm/arch/board.h>
  26 #include <asm/arch/mux.h>
  27 #include <asm/arch/gpio.h>
  28 #include <asm/arch/fpga.h>
  29 #ifdef CONFIG_PM
  30 #include <asm/arch/pm.h>
  31 #endif
  32
  33 static struct clk * uart1_ck = NULL;
  34 static struct clk * uart2_ck = NULL;
  35 static struct clk * uart3_ck = NULL;
  36
  37 static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
  38                                           int offset)
  39 {
  40         offset <<= up->regshift;
  41         return (unsigned int)__raw_readb(up->membase + offset);
  42 }
  43
  44 static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
  45                                     int value)
  46 {
  47         offset <<= p->regshift;
  48         __raw_writeb(value, p->membase + offset);
  49 }
  50
  51 /*
  52  * Internal UARTs need to be initialized for the 8250 autoconfig to work
  53  * properly. Note that the TX watermark initialization may not be needed
  54  * once the 8250.c watermark handling code is merged.
  55  */
  56 static void __init omap_serial_reset(struct plat_serial8250_port *p)
  57 {
  58         omap_serial_outp(p, UART_OMAP_MDR1, 0x07);      /* disable UART */
  59         omap_serial_outp(p, UART_OMAP_SCR, 0x08);       /* TX watermark */
  60         omap_serial_outp(p, UART_OMAP_MDR1, 0x00);      /* enable UART */
  61
  62         if (!cpu_is_omap1510()) {
  63                 omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
  64                 while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
  65         }
  66 }
  67
  68 static struct plat_serial8250_port serial_platform_data[] = {
  69         {
  70                 .membase        = (char*)IO_ADDRESS(OMAP_UART1_BASE),
  71                 .mapbase        = (unsigned long)OMAP_UART1_BASE,
  72                 .irq            = INT_UART1,
  73                 .flags          = UPF_BOOT_AUTOCONF,
  74                 .iotype         = UPIO_MEM,
  75                 .regshift       = 2,
  76                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
  77         },
  78         {
  79                 .membase        = (char*)IO_ADDRESS(OMAP_UART2_BASE),
  80                 .mapbase        = (unsigned long)OMAP_UART2_BASE,
  81                 .irq            = INT_UART2,
  82                 .flags          = UPF_BOOT_AUTOCONF,
  83                 .iotype         = UPIO_MEM,
  84                 .regshift       = 2,
  85                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
  86         },
  87         {
  88                 .membase        = (char*)IO_ADDRESS(OMAP_UART3_BASE),
  89                 .mapbase        = (unsigned long)OMAP_UART3_BASE,
  90                 .irq            = INT_UART3,
  91                 .flags          = UPF_BOOT_AUTOCONF,
  92                 .iotype         = UPIO_MEM,
  93                 .regshift       = 2,
  94                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
  95         },
  96         { },
  97 };
  98
  99 static struct platform_device serial_device = {
 100         .name                   = "serial8250",
 101         .id                     = PLAT8250_DEV_PLATFORM,
 102         .dev                    = {
 103                 .platform_data  = serial_platform_data,
 104         },
 105 };
 106
 107 /*
 108  * Note that on Innovator-1510 UART2 pins conflict with USB2.
 109  * By default UART2 does not work on Innovator-1510 if you have
 110  * USB OHCI enabled. To use UART2, you must disable USB2 first.
 111  */
 112 void __init omap_serial_init(void)
 113 {
 114         int i;
 115         const struct omap_uart_config *info;
 116
 117         if (cpu_is_omap730()) {
 118                 serial_platform_data[0].regshift = 0;
 119                 serial_platform_data[1].regshift = 0;
 120                 serial_platform_data[0].irq = INT_730_UART_MODEM_1;
 121                 serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
 122         }
 123
 124         if (cpu_is_omap1510()) {
 125                 serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
 126                 serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
 127                 serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
 128         }
 129
 130         info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
 131         if (info == NULL)
 132                 return;
 133
 134         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
 135                 unsigned char reg;
 136
 137                 if (!((1 << i) & info->enabled_uarts)) {
 138                         serial_platform_data[i].membase = NULL;
 139                         serial_platform_data[i].mapbase = 0;
 140                         continue;
 141                 }
 142
 143                 switch (i) {
 144                 case 0:
 145                         uart1_ck = clk_get(NULL, "uart1_ck");
 146                         if (IS_ERR(uart1_ck))
 147                                 printk("Could not get uart1_ck\n");
 148                         else {
 149                                 clk_use(uart1_ck);
 150                                 if (cpu_is_omap1510())
 151                                         clk_set_rate(uart1_ck, 12000000);
 152                         }
 153                         if (cpu_is_omap1510()) {
 154                                 omap_cfg_reg(UART1_TX);
 155                                 omap_cfg_reg(UART1_RTS);
 156                                 if (machine_is_omap_innovator()) {
 157                                         reg = fpga_read(OMAP1510_FPGA_POWER);
 158                                         reg |= OMAP1510_FPGA_PCR_COM1_EN;
 159                                         fpga_write(reg, OMAP1510_FPGA_POWER);
 160                                         udelay(10);
 161                                 }
 162                         }
 163                         break;
 164                 case 1:
 165                         uart2_ck = clk_get(NULL, "uart2_ck");
 166                         if (IS_ERR(uart2_ck))
 167                                 printk("Could not get uart2_ck\n");
 168                         else {
 169                                 clk_use(uart2_ck);
 170                                 if (cpu_is_omap1510())
 171                                         clk_set_rate(uart2_ck, 12000000);
 172                                 else
 173                                         clk_set_rate(uart2_ck, 48000000);
 174                         }
 175                         if (cpu_is_omap1510()) {
 176                                 omap_cfg_reg(UART2_TX);
 177                                 omap_cfg_reg(UART2_RTS);
 178                                 if (machine_is_omap_innovator()) {
 179                                         reg = fpga_read(OMAP1510_FPGA_POWER);
 180                                         reg |= OMAP1510_FPGA_PCR_COM2_EN;
 181                                         fpga_write(reg, OMAP1510_FPGA_POWER);
 182                                         udelay(10);
 183                                 }
 184                         }
 185                         break;
 186                 case 2:
 187                         uart3_ck = clk_get(NULL, "uart3_ck");
 188                         if (IS_ERR(uart3_ck))
 189                                 printk("Could not get uart3_ck\n");
 190                         else {
 191                                 clk_use(uart3_ck);
 192                                 if (cpu_is_omap1510())
 193                                         clk_set_rate(uart3_ck, 12000000);
 194                         }
 195                         if (cpu_is_omap1510()) {
 196                                 omap_cfg_reg(UART3_TX);
 197                                 omap_cfg_reg(UART3_RX);
 198                         }
 199                         break;
 200                 }
 201                 omap_serial_reset(&serial_platform_data[i]);
 202         }
 203 }
 204
 205 #ifdef CONFIG_OMAP_SERIAL_WAKE
 206
 207 static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id,
 208                                               struct pt_regs *regs)
 209 {
 210         /* Need to do something with serial port right after wake-up? */
 211         return IRQ_HANDLED;
 212 }
 213
 214 /*
 215  * Reroutes serial RX lines to GPIO lines for the duration of
 216  * sleep to allow waking up the device from serial port even
 217  * in deep sleep.
 218  */
 219 void omap_serial_wake_trigger(int enable)
 220 {
 221         if (!cpu_is_omap16xx())
 222                 return;
 223
 224         if (uart1_ck != NULL) {
 225                 if (enable)
 226                         omap_cfg_reg(V14_16XX_GPIO37);
 227                 else
 228                         omap_cfg_reg(V14_16XX_UART1_RX);
 229         }
 230         if (uart2_ck != NULL) {
 231                 if (enable)
 232                         omap_cfg_reg(R9_16XX_GPIO18);
 233                 else
 234                         omap_cfg_reg(R9_16XX_UART2_RX);
 235         }
 236         if (uart3_ck != NULL) {
 237                 if (enable)
 238                         omap_cfg_reg(L14_16XX_GPIO49);
 239                 else
 240                         omap_cfg_reg(L14_16XX_UART3_RX);
 241         }
 242 }
 243
 244 static void __init omap_serial_set_port_wakeup(int gpio_nr)
 245 {
 246         int ret;
 247
 248         ret = omap_request_gpio(gpio_nr);
 249         if (ret < 0) {
 250                 printk(KERN_ERR "Could not request UART wake GPIO: %i\n",
 251                        gpio_nr);
 252                 return;
 253         }
 254         omap_set_gpio_direction(gpio_nr, 1);
 255         set_irq_type(OMAP_GPIO_IRQ(gpio_nr), IRQT_RISING);
 256         ret = request_irq(OMAP_GPIO_IRQ(gpio_nr), &omap_serial_wake_interrupt,
 257                           0, "serial wakeup", NULL);
 258         if (ret) {
 259                 omap_free_gpio(gpio_nr);
 260                 printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n",
 261                        gpio_nr);
 262                 return;
 263         }
 264         enable_irq_wake(OMAP_GPIO_IRQ(gpio_nr));
 265 }
 266
 267 static int __init omap_serial_wakeup_init(void)
 268 {
 269         if (!cpu_is_omap16xx())
 270                 return 0;
 271
 272         if (uart1_ck != NULL)
 273                 omap_serial_set_port_wakeup(37);
 274         if (uart2_ck != NULL)
 275                 omap_serial_set_port_wakeup(18);
 276         if (uart3_ck != NULL)
 277                 omap_serial_set_port_wakeup(49);
 278
 279         return 0;
 280 }
 281 late_initcall(omap_serial_wakeup_init);
 282
 283 #endif  /* CONFIG_OMAP_SERIAL_WAKE */
 284
 285 static int __init omap_init(void)
 286 {
 287         return platform_device_register(&serial_device);
 288 }
 289 arch_initcall(omap_init);