2 * Blackfin CPLB initialization
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Bugs: Enter bugs at http://blackfin.uclinux.org/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see the file COPYING, or write
20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <linux/module.h>
25 #include <asm/blackfin.h>
27 #include <asm/cplbinit.h>
29 #define CPLB_MEM CONFIG_MAX_MEM_SIZE
32 * Number of required data CPLB switchtable entries
33 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
34 * approx 16 for smaller 1MB page size CPLBs for allignment purposes
35 * 1 for L1 Data Memory
36 * possibly 1 for L2 Data Memory
37 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
40 #define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
41 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
44 * Number of required instruction CPLB switchtable entries
45 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
46 * approx 12 for smaller 1MB page size CPLBs for allignment purposes
47 * 1 for L1 Instruction Memory
48 * possibly 1 for L2 Instruction Memory
49 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
51 #define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
54 u_long icplb_table[MAX_CPLBS + 1];
55 u_long dcplb_table[MAX_CPLBS + 1];
57 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
58 # define PDT_ATTR __attribute__((l1_data))
63 u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
64 u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;
66 #ifdef CONFIG_CPLB_INFO
67 u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR;
68 u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
72 struct cplb_tab init_i;
73 struct cplb_tab init_d;
74 struct cplb_tab switch_i;
75 struct cplb_tab switch_d;
78 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
79 static struct cplb_desc cplb_data[] = {
84 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
87 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
92 .name = "Zero Pointer Guard Page",
95 .start = L1_CODE_START,
96 .end = L1_CODE_START + L1_CODE_LENGTH,
98 .attr = INITIAL_T | SWITCH_T | I_CPLB,
102 .name = "L1 I-Memory",
105 .start = L1_DATA_A_START,
106 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
108 .attr = INITIAL_T | SWITCH_T | D_CPLB,
110 .d_conf = L1_DMEMORY,
111 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
116 .name = "L1 D-Memory",
120 .end = 0, /* dynamic */
122 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
123 .i_conf = SDRAM_IGENERIC,
124 .d_conf = SDRAM_DGENERIC,
126 .name = "Kernel Memory",
129 .start = 0, /* dynamic */
130 .end = 0, /* dynamic */
132 .attr = INITIAL_T | SWITCH_T | D_CPLB,
133 .i_conf = SDRAM_IGENERIC,
134 .d_conf = SDRAM_DNON_CHBL,
136 .name = "uClinux MTD Memory",
139 .start = 0, /* dynamic */
140 .end = 0, /* dynamic */
142 .attr = INITIAL_T | SWITCH_T | D_CPLB,
143 .d_conf = SDRAM_DNON_CHBL,
145 .name = "Uncached DMA Zone",
148 .start = 0, /* dynamic */
149 .end = 0, /* dynamic */
151 .attr = SWITCH_T | D_CPLB,
152 .i_conf = 0, /* dynamic */
153 .d_conf = 0, /* dynamic */
155 .name = "Reserved Memory",
158 .start = ASYNC_BANK0_BASE,
159 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
161 .attr = SWITCH_T | D_CPLB,
162 .d_conf = SDRAM_EBIU,
164 .name = "Asynchronous Memory Banks",
168 .end = L2_START + L2_LENGTH,
170 .attr = SWITCH_T | I_CPLB | D_CPLB,
173 .valid = (L2_LENGTH > 0),
177 .start = BOOT_ROM_START,
178 .end = BOOT_ROM_START + BOOT_ROM_LENGTH,
180 .attr = SWITCH_T | I_CPLB | D_CPLB,
181 .i_conf = SDRAM_IGENERIC,
182 .d_conf = SDRAM_DGENERIC,
184 .name = "On-Chip BootROM",
188 static u16 __init lock_kernel_check(u32 start, u32 end)
190 if ((end <= (u32) _end && end >= (u32)_stext) ||
191 (start <= (u32) _end && start >= (u32)_stext))
196 static unsigned short __init
197 fill_cplbtab(struct cplb_tab *table,
198 unsigned long start, unsigned long end,
199 unsigned long block_size, unsigned long cplb_data)
203 switch (block_size) {
219 cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
221 while ((start < end) && (table->pos < table->size)) {
223 table->tab[table->pos++] = start;
225 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
226 table->tab[table->pos++] =
227 cplb_data | CPLB_LOCK | CPLB_DIRTY;
229 table->tab[table->pos++] = cplb_data;
236 static unsigned short __init
237 close_cplbtab(struct cplb_tab *table)
240 while (table->pos < table->size) {
242 table->tab[table->pos++] = 0;
243 table->tab[table->pos++] = 0; /* !CPLB_VALID */
248 /* helper function */
250 __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
252 if (cplb_data[i].psize) {
257 cplb_data[i].i_conf);
259 #if defined(CONFIG_BFIN_ICACHE)
260 if (ANOMALY_05000263 && i == SDRAM_KERN) {
265 cplb_data[i].i_conf);
273 cplb_data[i].i_conf);
278 cplb_data[i].i_conf);
279 fill_cplbtab(t, a_end,
282 cplb_data[i].i_conf);
288 __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
290 if (cplb_data[i].psize) {
295 cplb_data[i].d_conf);
300 cplb_data[i].d_conf);
301 fill_cplbtab(t, a_start,
303 cplb_data[i].d_conf);
304 fill_cplbtab(t, a_end,
307 cplb_data[i].d_conf);
311 void __init generate_cpl_tables(void)
315 u32 a_start, a_end, as, ae, as_1m;
317 struct cplb_tab *t_i = NULL;
318 struct cplb_tab *t_d = NULL;
321 printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n");
323 cplb.init_i.size = MAX_CPLBS;
324 cplb.init_d.size = MAX_CPLBS;
325 cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
326 cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
330 cplb.switch_i.pos = 0;
331 cplb.switch_d.pos = 0;
333 cplb.init_i.tab = icplb_table;
334 cplb.init_d.tab = dcplb_table;
335 cplb.switch_i.tab = ipdt_table;
336 cplb.switch_d.tab = dpdt_table;
338 cplb_data[SDRAM_KERN].end = memory_end;
340 #ifdef CONFIG_MTD_UCLINUX
341 cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
342 cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
343 cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
344 # if defined(CONFIG_ROMFS_FS)
345 cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
348 * The ROMFS_FS size is often not multiple of 1MB.
349 * This can cause multiple CPLB sets covering the same memory area.
350 * This will then cause multiple CPLB hit exceptions.
351 * Workaround: We ensure a contiguous memory area by extending the kernel
352 * memory section over the mtd section.
353 * For ROMFS_FS memory must be covered with ICPLBs anyways.
354 * So there is no difference between kernel and mtd memory setup.
357 cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
358 cplb_data[SDRAM_RAM_MTD].valid = 0;
362 cplb_data[SDRAM_RAM_MTD].valid = 0;
365 cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
366 cplb_data[SDRAM_DMAZ].end = _ramend;
368 cplb_data[RES_MEM].start = _ramend;
369 cplb_data[RES_MEM].end = physical_mem_end;
371 if (reserved_mem_dcache_on)
372 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
374 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
376 if (reserved_mem_icache_on)
377 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
379 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
381 for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
382 if (!cplb_data[i].valid)
385 as_1m = cplb_data[i].start % SIZE_1M;
387 /* We need to make sure all sections are properly 1M aligned
388 * However between Kernel Memory and the Kernel mtd section, depending on the
389 * rootfs size, there can be overlapping memory areas.
392 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
393 #ifdef CONFIG_MTD_UCLINUX
394 if (i == SDRAM_RAM_MTD) {
395 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
396 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
398 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
401 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
402 cplb_data[i].name, cplb_data[i].start);
405 as = cplb_data[i].start % SIZE_4M;
406 ae = cplb_data[i].end % SIZE_4M;
409 a_start = cplb_data[i].start + (SIZE_4M - (as));
411 a_start = cplb_data[i].start;
413 a_end = cplb_data[i].end - ae;
415 for (j = INITIAL_T; j <= SWITCH_T; j++) {
419 if (cplb_data[i].attr & INITIAL_T) {
427 if (cplb_data[i].attr & SWITCH_T) {
428 t_i = &cplb.switch_i;
429 t_d = &cplb.switch_d;
441 if (cplb_data[i].attr & I_CPLB)
442 __fill_code_cplbtab(t_i, i, a_start, a_end);
444 if (cplb_data[i].attr & D_CPLB)
445 __fill_data_cplbtab(t_d, i, a_start, a_end);
451 close_cplbtab(&cplb.init_i);
452 close_cplbtab(&cplb.init_d);
454 cplb.init_i.tab[cplb.init_i.pos] = -1;
455 cplb.init_d.tab[cplb.init_d.pos] = -1;
456 cplb.switch_i.tab[cplb.switch_i.pos] = -1;
457 cplb.switch_d.tab[cplb.switch_d.pos] = -1;