Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc
[linux-2.6] / drivers / net / e1000e / es2lan.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2007 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
31  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
32  */
33
34 #include <linux/netdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/delay.h>
37 #include <linux/pci.h>
38
39 #include "e1000.h"
40
41 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
42 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
43 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
44
45 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
46 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
47 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
48
49 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
50 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
51
52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
54
55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
57
58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE   0x0002 /* 1=Reversal Disab. */
60 #define GG82563_PSCR_CROSSOVER_MODE_MASK         0x0060
61 #define GG82563_PSCR_CROSSOVER_MODE_MDI          0x0000 /* 00=Manual MDI */
62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX         0x0020 /* 01=Manual MDIX */
63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO         0x0060 /* 11=Auto crossover */
64
65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
66 #define GG82563_PSCR2_REVERSE_AUTO_NEG           0x2000
67                                                 /* 1=Reverse Auto-Negotiation */
68
69 /* MAC Specific Control Register (Page 2, Register 21) */
70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
71 #define GG82563_MSCR_TX_CLK_MASK                 0x0007
72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5           0x0004
73 #define GG82563_MSCR_TX_CLK_100MBPS_25           0x0005
74 #define GG82563_MSCR_TX_CLK_1000MBPS_25          0x0007
75
76 #define GG82563_MSCR_ASSERT_CRS_ON_TX            0x0010 /* 1=Assert */
77
78 /* DSP Distance Register (Page 5, Register 26) */
79 #define GG82563_DSPD_CABLE_LENGTH                0x0007 /* 0 = <50M
80                                                            1 = 50-80M
81                                                            2 = 80-110M
82                                                            3 = 110-140M
83                                                            4 = >140M */
84
85 /* Kumeran Mode Control Register (Page 193, Register 16) */
86 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
87
88 /* Power Management Control Register (Page 193, Register 20) */
89 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE      0x0001
90                                            /* 1=Enable SERDES Electrical Idle */
91
92 /* In-Band Control Register (Page 194, Register 18) */
93 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
94
95 /* A table for the GG82563 cable length where the range is defined
96  * with a lower bound at "index" and the upper bound at
97  * "index + 5".
98  */
99 static const u16 e1000_gg82563_cable_length_table[] =
100          { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
101
102 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
103 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
104 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
105 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
106 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
107 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
108 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
109
110 /**
111  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
112  *  @hw: pointer to the HW structure
113  *
114  *  This is a function pointer entry point called by the api module.
115  **/
116 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
117 {
118         struct e1000_phy_info *phy = &hw->phy;
119         s32 ret_val;
120
121         if (hw->media_type != e1000_media_type_copper) {
122                 phy->type       = e1000_phy_none;
123                 return 0;
124         }
125
126         phy->addr               = 1;
127         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
128         phy->reset_delay_us      = 100;
129         phy->type               = e1000_phy_gg82563;
130
131         /* This can only be done after all function pointers are setup. */
132         ret_val = e1000e_get_phy_id(hw);
133
134         /* Verify phy id */
135         if (phy->id != GG82563_E_PHY_ID)
136                 return -E1000_ERR_PHY;
137
138         return ret_val;
139 }
140
141 /**
142  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
143  *  @hw: pointer to the HW structure
144  *
145  *  This is a function pointer entry point called by the api module.
146  **/
147 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
148 {
149         struct e1000_nvm_info *nvm = &hw->nvm;
150         u32 eecd = er32(EECD);
151         u16 size;
152
153         nvm->opcode_bits        = 8;
154         nvm->delay_usec  = 1;
155         switch (nvm->override) {
156         case e1000_nvm_override_spi_large:
157                 nvm->page_size    = 32;
158                 nvm->address_bits = 16;
159                 break;
160         case e1000_nvm_override_spi_small:
161                 nvm->page_size    = 8;
162                 nvm->address_bits = 8;
163                 break;
164         default:
165                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
166                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
167                 break;
168         }
169
170         nvm->type              = e1000_nvm_eeprom_spi;
171
172         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
173                           E1000_EECD_SIZE_EX_SHIFT);
174
175         /* Added to a constant, "size" becomes the left-shift value
176          * for setting word_size.
177          */
178         size += NVM_WORD_SIZE_BASE_SHIFT;
179         nvm->word_size  = 1 << size;
180
181         return 0;
182 }
183
184 /**
185  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
186  *  @hw: pointer to the HW structure
187  *
188  *  This is a function pointer entry point called by the api module.
189  **/
190 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
191 {
192         struct e1000_hw *hw = &adapter->hw;
193         struct e1000_mac_info *mac = &hw->mac;
194         struct e1000_mac_operations *func = &mac->ops;
195
196         /* Set media type */
197         switch (adapter->pdev->device) {
198         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
199                 hw->media_type = e1000_media_type_internal_serdes;
200                 break;
201         default:
202                 hw->media_type = e1000_media_type_copper;
203                 break;
204         }
205
206         /* Set mta register count */
207         mac->mta_reg_count = 128;
208         /* Set rar entry count */
209         mac->rar_entry_count = E1000_RAR_ENTRIES;
210         /* Set if manageability features are enabled. */
211         mac->arc_subsystem_valid =
212                 (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
213
214         /* check for link */
215         switch (hw->media_type) {
216         case e1000_media_type_copper:
217                 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
218                 func->check_for_link = e1000e_check_for_copper_link;
219                 break;
220         case e1000_media_type_fiber:
221                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
222                 func->check_for_link = e1000e_check_for_fiber_link;
223                 break;
224         case e1000_media_type_internal_serdes:
225                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
226                 func->check_for_link = e1000e_check_for_serdes_link;
227                 break;
228         default:
229                 return -E1000_ERR_CONFIG;
230                 break;
231         }
232
233         return 0;
234 }
235
236 static s32 e1000_get_invariants_80003es2lan(struct e1000_adapter *adapter)
237 {
238         struct e1000_hw *hw = &adapter->hw;
239         s32 rc;
240
241         rc = e1000_init_mac_params_80003es2lan(adapter);
242         if (rc)
243                 return rc;
244
245         rc = e1000_init_nvm_params_80003es2lan(hw);
246         if (rc)
247                 return rc;
248
249         rc = e1000_init_phy_params_80003es2lan(hw);
250         if (rc)
251                 return rc;
252
253         return 0;
254 }
255
256 /**
257  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
258  *  @hw: pointer to the HW structure
259  *
260  *  A wrapper to acquire access rights to the correct PHY.  This is a
261  *  function pointer entry point called by the api module.
262  **/
263 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
264 {
265         u16 mask;
266
267         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
268
269         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
270 }
271
272 /**
273  *  e1000_release_phy_80003es2lan - Release rights to access PHY
274  *  @hw: pointer to the HW structure
275  *
276  *  A wrapper to release access rights to the correct PHY.  This is a
277  *  function pointer entry point called by the api module.
278  **/
279 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
280 {
281         u16 mask;
282
283         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
284         e1000_release_swfw_sync_80003es2lan(hw, mask);
285 }
286
287 /**
288  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
289  *  @hw: pointer to the HW structure
290  *
291  *  Acquire the semaphore to access the EEPROM.  This is a function
292  *  pointer entry point called by the api module.
293  **/
294 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
295 {
296         s32 ret_val;
297
298         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
299         if (ret_val)
300                 return ret_val;
301
302         ret_val = e1000e_acquire_nvm(hw);
303
304         if (ret_val)
305                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
306
307         return ret_val;
308 }
309
310 /**
311  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
312  *  @hw: pointer to the HW structure
313  *
314  *  Release the semaphore used to access the EEPROM.  This is a
315  *  function pointer entry point called by the api module.
316  **/
317 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
318 {
319         e1000e_release_nvm(hw);
320         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
321 }
322
323 /**
324  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
325  *  @hw: pointer to the HW structure
326  *  @mask: specifies which semaphore to acquire
327  *
328  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
329  *  will also specify which port we're acquiring the lock for.
330  **/
331 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
332 {
333         u32 swfw_sync;
334         u32 swmask = mask;
335         u32 fwmask = mask << 16;
336         s32 i = 0;
337         s32 timeout = 200;
338
339         while (i < timeout) {
340                 if (e1000e_get_hw_semaphore(hw))
341                         return -E1000_ERR_SWFW_SYNC;
342
343                 swfw_sync = er32(SW_FW_SYNC);
344                 if (!(swfw_sync & (fwmask | swmask)))
345                         break;
346
347                 /* Firmware currently using resource (fwmask)
348                  * or other software thread using resource (swmask) */
349                 e1000e_put_hw_semaphore(hw);
350                 mdelay(5);
351                 i++;
352         }
353
354         if (i == timeout) {
355                 hw_dbg(hw,
356                        "Driver can't access resource, SW_FW_SYNC timeout.\n");
357                 return -E1000_ERR_SWFW_SYNC;
358         }
359
360         swfw_sync |= swmask;
361         ew32(SW_FW_SYNC, swfw_sync);
362
363         e1000e_put_hw_semaphore(hw);
364
365         return 0;
366 }
367
368 /**
369  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
370  *  @hw: pointer to the HW structure
371  *  @mask: specifies which semaphore to acquire
372  *
373  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
374  *  will also specify which port we're releasing the lock for.
375  **/
376 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
377 {
378         u32 swfw_sync;
379
380         while (e1000e_get_hw_semaphore(hw) != 0);
381         /* Empty */
382
383         swfw_sync = er32(SW_FW_SYNC);
384         swfw_sync &= ~mask;
385         ew32(SW_FW_SYNC, swfw_sync);
386
387         e1000e_put_hw_semaphore(hw);
388 }
389
390 /**
391  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
392  *  @hw: pointer to the HW structure
393  *  @offset: offset of the register to read
394  *  @data: pointer to the data returned from the operation
395  *
396  *  Read the GG82563 PHY register.  This is a function pointer entry
397  *  point called by the api module.
398  **/
399 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
400                                                   u32 offset, u16 *data)
401 {
402         s32 ret_val;
403         u32 page_select;
404         u16 temp;
405
406         /* Select Configuration Page */
407         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
408                 page_select = GG82563_PHY_PAGE_SELECT;
409         else
410                 /* Use Alternative Page Select register to access
411                  * registers 30 and 31
412                  */
413                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
414
415         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
416         ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp);
417         if (ret_val)
418                 return ret_val;
419
420         /* The "ready" bit in the MDIC register may be incorrectly set
421          * before the device has completed the "Page Select" MDI
422          * transaction.  So we wait 200us after each MDI command...
423          */
424         udelay(200);
425
426         /* ...and verify the command was successful. */
427         ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp);
428
429         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
430                 ret_val = -E1000_ERR_PHY;
431                 return ret_val;
432         }
433
434         udelay(200);
435
436         ret_val = e1000e_read_phy_reg_m88(hw,
437                                          MAX_PHY_REG_ADDRESS & offset,
438                                          data);
439
440         udelay(200);
441
442         return ret_val;
443 }
444
445 /**
446  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
447  *  @hw: pointer to the HW structure
448  *  @offset: offset of the register to read
449  *  @data: value to write to the register
450  *
451  *  Write to the GG82563 PHY register.  This is a function pointer entry
452  *  point called by the api module.
453  **/
454 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
455                                                    u32 offset, u16 data)
456 {
457         s32 ret_val;
458         u32 page_select;
459         u16 temp;
460
461         /* Select Configuration Page */
462         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
463                 page_select = GG82563_PHY_PAGE_SELECT;
464         else
465                 /* Use Alternative Page Select register to access
466                  * registers 30 and 31
467                  */
468                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
469
470         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
471         ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp);
472         if (ret_val)
473                 return ret_val;
474
475
476         /* The "ready" bit in the MDIC register may be incorrectly set
477          * before the device has completed the "Page Select" MDI
478          * transaction.  So we wait 200us after each MDI command...
479          */
480         udelay(200);
481
482         /* ...and verify the command was successful. */
483         ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp);
484
485         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp)
486                 return -E1000_ERR_PHY;
487
488         udelay(200);
489
490         ret_val = e1000e_write_phy_reg_m88(hw,
491                                           MAX_PHY_REG_ADDRESS & offset,
492                                           data);
493
494         udelay(200);
495
496         return ret_val;
497 }
498
499 /**
500  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
501  *  @hw: pointer to the HW structure
502  *  @offset: offset of the register to read
503  *  @words: number of words to write
504  *  @data: buffer of data to write to the NVM
505  *
506  *  Write "words" of data to the ESB2 NVM.  This is a function
507  *  pointer entry point called by the api module.
508  **/
509 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
510                                        u16 words, u16 *data)
511 {
512         return e1000e_write_nvm_spi(hw, offset, words, data);
513 }
514
515 /**
516  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
517  *  @hw: pointer to the HW structure
518  *
519  *  Wait a specific amount of time for manageability processes to complete.
520  *  This is a function pointer entry point called by the phy module.
521  **/
522 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
523 {
524         s32 timeout = PHY_CFG_TIMEOUT;
525         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
526
527         if (hw->bus.func == 1)
528                 mask = E1000_NVM_CFG_DONE_PORT_1;
529
530         while (timeout) {
531                 if (er32(EEMNGCTL) & mask)
532                         break;
533                 msleep(1);
534                 timeout--;
535         }
536         if (!timeout) {
537                 hw_dbg(hw, "MNG configuration cycle has not completed.\n");
538                 return -E1000_ERR_RESET;
539         }
540
541         return 0;
542 }
543
544 /**
545  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
546  *  @hw: pointer to the HW structure
547  *
548  *  Force the speed and duplex settings onto the PHY.  This is a
549  *  function pointer entry point called by the phy module.
550  **/
551 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
552 {
553         s32 ret_val;
554         u16 phy_data;
555         bool link;
556
557         /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
558          * forced whenever speed and duplex are forced.
559          */
560         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
561         if (ret_val)
562                 return ret_val;
563
564         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
565         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
566         if (ret_val)
567                 return ret_val;
568
569         hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data);
570
571         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
572         if (ret_val)
573                 return ret_val;
574
575         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
576
577         /* Reset the phy to commit changes. */
578         phy_data |= MII_CR_RESET;
579
580         ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
581         if (ret_val)
582                 return ret_val;
583
584         udelay(1);
585
586         if (hw->phy.wait_for_link) {
587                 hw_dbg(hw, "Waiting for forced speed/duplex link "
588                          "on GG82563 phy.\n");
589
590                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
591                                                      100000, &link);
592                 if (ret_val)
593                         return ret_val;
594
595                 if (!link) {
596                         /* We didn't get link.
597                          * Reset the DSP and cross our fingers.
598                          */
599                         ret_val = e1000e_phy_reset_dsp(hw);
600                         if (ret_val)
601                                 return ret_val;
602                 }
603
604                 /* Try once more */
605                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
606                                                      100000, &link);
607                 if (ret_val)
608                         return ret_val;
609         }
610
611         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
612         if (ret_val)
613                 return ret_val;
614
615         /* Resetting the phy means we need to verify the TX_CLK corresponds
616          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
617          */
618         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
619         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
620                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
621         else
622                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
623
624         /* In addition, we must re-enable CRS on Tx for both half and full
625          * duplex.
626          */
627         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
628         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
629
630         return ret_val;
631 }
632
633 /**
634  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
635  *  @hw: pointer to the HW structure
636  *
637  *  Find the approximate cable length as measured by the GG82563 PHY.
638  *  This is a function pointer entry point called by the phy module.
639  **/
640 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
641 {
642         struct e1000_phy_info *phy = &hw->phy;
643         s32 ret_val;
644         u16 phy_data;
645         u16 index;
646
647         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
648         if (ret_val)
649                 return ret_val;
650
651         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
652         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
653         phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
654
655         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
656
657         return 0;
658 }
659
660 /**
661  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
662  *  @hw: pointer to the HW structure
663  *  @speed: pointer to speed buffer
664  *  @duplex: pointer to duplex buffer
665  *
666  *  Retrieve the current speed and duplex configuration.
667  *  This is a function pointer entry point called by the api module.
668  **/
669 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
670                                               u16 *duplex)
671 {
672         s32 ret_val;
673
674         if (hw->media_type == e1000_media_type_copper) {
675                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
676                                                                     speed,
677                                                                     duplex);
678                 if (ret_val)
679                         return ret_val;
680                 if (*speed == SPEED_1000)
681                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
682                 else
683                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw,
684                                                               *duplex);
685         } else {
686                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
687                                                                   speed,
688                                                                   duplex);
689         }
690
691         return ret_val;
692 }
693
694 /**
695  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
696  *  @hw: pointer to the HW structure
697  *
698  *  Perform a global reset to the ESB2 controller.
699  *  This is a function pointer entry point called by the api module.
700  **/
701 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
702 {
703         u32 ctrl;
704         u32 icr;
705         s32 ret_val;
706
707         /* Prevent the PCI-E bus from sticking if there is no TLP connection
708          * on the last TLP read/write transaction when MAC is reset.
709          */
710         ret_val = e1000e_disable_pcie_master(hw);
711         if (ret_val)
712                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
713
714         hw_dbg(hw, "Masking off all interrupts\n");
715         ew32(IMC, 0xffffffff);
716
717         ew32(RCTL, 0);
718         ew32(TCTL, E1000_TCTL_PSP);
719         e1e_flush();
720
721         msleep(10);
722
723         ctrl = er32(CTRL);
724
725         hw_dbg(hw, "Issuing a global reset to MAC\n");
726         ew32(CTRL, ctrl | E1000_CTRL_RST);
727
728         ret_val = e1000e_get_auto_rd_done(hw);
729         if (ret_val)
730                 /* We don't want to continue accessing MAC registers. */
731                 return ret_val;
732
733         /* Clear any pending interrupt events. */
734         ew32(IMC, 0xffffffff);
735         icr = er32(ICR);
736
737         return 0;
738 }
739
740 /**
741  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
742  *  @hw: pointer to the HW structure
743  *
744  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
745  *  This is a function pointer entry point called by the api module.
746  **/
747 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
748 {
749         struct e1000_mac_info *mac = &hw->mac;
750         u32 reg_data;
751         s32 ret_val;
752         u16 i;
753
754         e1000_initialize_hw_bits_80003es2lan(hw);
755
756         /* Initialize identification LED */
757         ret_val = e1000e_id_led_init(hw);
758         if (ret_val) {
759                 hw_dbg(hw, "Error initializing identification LED\n");
760                 return ret_val;
761         }
762
763         /* Disabling VLAN filtering */
764         hw_dbg(hw, "Initializing the IEEE VLAN\n");
765         e1000e_clear_vfta(hw);
766
767         /* Setup the receive address. */
768         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
769
770         /* Zero out the Multicast HASH table */
771         hw_dbg(hw, "Zeroing the MTA\n");
772         for (i = 0; i < mac->mta_reg_count; i++)
773                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
774
775         /* Setup link and flow control */
776         ret_val = e1000e_setup_link(hw);
777
778         /* Set the transmit descriptor write-back policy */
779         reg_data = er32(TXDCTL);
780         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
781                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
782         ew32(TXDCTL, reg_data);
783
784         /* ...for both queues. */
785         reg_data = er32(TXDCTL1);
786         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
787                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
788         ew32(TXDCTL1, reg_data);
789
790         /* Enable retransmit on late collisions */
791         reg_data = er32(TCTL);
792         reg_data |= E1000_TCTL_RTLC;
793         ew32(TCTL, reg_data);
794
795         /* Configure Gigabit Carry Extend Padding */
796         reg_data = er32(TCTL_EXT);
797         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
798         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
799         ew32(TCTL_EXT, reg_data);
800
801         /* Configure Transmit Inter-Packet Gap */
802         reg_data = er32(TIPG);
803         reg_data &= ~E1000_TIPG_IPGT_MASK;
804         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
805         ew32(TIPG, reg_data);
806
807         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
808         reg_data &= ~0x00100000;
809         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
810
811         /* Clear all of the statistics registers (clear on read).  It is
812          * important that we do this after we have tried to establish link
813          * because the symbol error count will increment wildly if there
814          * is no link.
815          */
816         e1000_clear_hw_cntrs_80003es2lan(hw);
817
818         return ret_val;
819 }
820
821 /**
822  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
823  *  @hw: pointer to the HW structure
824  *
825  *  Initializes required hardware-dependent bits needed for normal operation.
826  **/
827 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
828 {
829         u32 reg;
830
831         /* Transmit Descriptor Control 0 */
832         reg = er32(TXDCTL);
833         reg |= (1 << 22);
834         ew32(TXDCTL, reg);
835
836         /* Transmit Descriptor Control 1 */
837         reg = er32(TXDCTL1);
838         reg |= (1 << 22);
839         ew32(TXDCTL1, reg);
840
841         /* Transmit Arbitration Control 0 */
842         reg = er32(TARC0);
843         reg &= ~(0xF << 27); /* 30:27 */
844         if (hw->media_type != e1000_media_type_copper)
845                 reg &= ~(1 << 20);
846         ew32(TARC0, reg);
847
848         /* Transmit Arbitration Control 1 */
849         reg = er32(TARC1);
850         if (er32(TCTL) & E1000_TCTL_MULR)
851                 reg &= ~(1 << 28);
852         else
853                 reg |= (1 << 28);
854         ew32(TARC1, reg);
855 }
856
857 /**
858  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
859  *  @hw: pointer to the HW structure
860  *
861  *  Setup some GG82563 PHY registers for obtaining link
862  **/
863 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
864 {
865         struct e1000_phy_info *phy = &hw->phy;
866         s32 ret_val;
867         u32 ctrl_ext;
868         u16 data;
869
870         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
871                                      &data);
872         if (ret_val)
873                 return ret_val;
874
875         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
876         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
877         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
878
879         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
880                                       data);
881         if (ret_val)
882                 return ret_val;
883
884         /* Options:
885          *   MDI/MDI-X = 0 (default)
886          *   0 - Auto for all speeds
887          *   1 - MDI mode
888          *   2 - MDI-X mode
889          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
890          */
891         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
892         if (ret_val)
893                 return ret_val;
894
895         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
896
897         switch (phy->mdix) {
898         case 1:
899                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
900                 break;
901         case 2:
902                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
903                 break;
904         case 0:
905         default:
906                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
907                 break;
908         }
909
910         /* Options:
911          *   disable_polarity_correction = 0 (default)
912          *       Automatic Correction for Reversed Cable Polarity
913          *   0 - Disabled
914          *   1 - Enabled
915          */
916         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
917         if (phy->disable_polarity_correction)
918                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
919
920         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
921         if (ret_val)
922                 return ret_val;
923
924         /* SW Reset the PHY so all changes take effect */
925         ret_val = e1000e_commit_phy(hw);
926         if (ret_val) {
927                 hw_dbg(hw, "Error Resetting the PHY\n");
928                 return ret_val;
929         }
930
931         /* Bypass RX and TX FIFO's */
932         ret_val = e1000e_write_kmrn_reg(hw,
933                                 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
934                                 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
935                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
936         if (ret_val)
937                 return ret_val;
938
939         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
940         if (ret_val)
941                 return ret_val;
942
943         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
944         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
945         if (ret_val)
946                 return ret_val;
947
948         ctrl_ext = er32(CTRL_EXT);
949         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
950         ew32(CTRL_EXT, ctrl_ext);
951
952         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
953         if (ret_val)
954                 return ret_val;
955
956         /* Do not init these registers when the HW is in IAMT mode, since the
957          * firmware will have already initialized them.  We only initialize
958          * them if the HW is not in IAMT mode.
959          */
960         if (!e1000e_check_mng_mode(hw)) {
961                 /* Enable Electrical Idle on the PHY */
962                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
963                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
964                 if (ret_val)
965                         return ret_val;
966
967                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
968                 if (ret_val)
969                         return ret_val;
970
971                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
972                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
973                 if (ret_val)
974                         return ret_val;
975         }
976
977         /* Workaround: Disable padding in Kumeran interface in the MAC
978          * and in the PHY to avoid CRC errors.
979          */
980         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
981         if (ret_val)
982                 return ret_val;
983
984         data |= GG82563_ICR_DIS_PADDING;
985         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
986         if (ret_val)
987                 return ret_val;
988
989         return 0;
990 }
991
992 /**
993  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
994  *  @hw: pointer to the HW structure
995  *
996  *  Essentially a wrapper for setting up all things "copper" related.
997  *  This is a function pointer entry point called by the mac module.
998  **/
999 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1000 {
1001         u32 ctrl;
1002         s32 ret_val;
1003         u16 reg_data;
1004
1005         ctrl = er32(CTRL);
1006         ctrl |= E1000_CTRL_SLU;
1007         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1008         ew32(CTRL, ctrl);
1009
1010         /* Set the mac to wait the maximum time between each
1011          * iteration and increase the max iterations when
1012          * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1013         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1014         if (ret_val)
1015                 return ret_val;
1016         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1017         if (ret_val)
1018                 return ret_val;
1019         reg_data |= 0x3F;
1020         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1021         if (ret_val)
1022                 return ret_val;
1023         ret_val = e1000e_read_kmrn_reg(hw,
1024                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1025                                       &reg_data);
1026         if (ret_val)
1027                 return ret_val;
1028         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1029         ret_val = e1000e_write_kmrn_reg(hw,
1030                                        E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1031                                        reg_data);
1032         if (ret_val)
1033                 return ret_val;
1034
1035         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1036         if (ret_val)
1037                 return ret_val;
1038
1039         ret_val = e1000e_setup_copper_link(hw);
1040
1041         return 0;
1042 }
1043
1044 /**
1045  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1046  *  @hw: pointer to the HW structure
1047  *  @duplex: current duplex setting
1048  *
1049  *  Configure the KMRN interface by applying last minute quirks for
1050  *  10/100 operation.
1051  **/
1052 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1053 {
1054         s32 ret_val;
1055         u32 tipg;
1056         u16 reg_data;
1057
1058         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1059         ret_val = e1000e_write_kmrn_reg(hw,
1060                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1061                                        reg_data);
1062         if (ret_val)
1063                 return ret_val;
1064
1065         /* Configure Transmit Inter-Packet Gap */
1066         tipg = er32(TIPG);
1067         tipg &= ~E1000_TIPG_IPGT_MASK;
1068         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1069         ew32(TIPG, tipg);
1070
1071         ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1072         if (ret_val)
1073                 return ret_val;
1074
1075         if (duplex == HALF_DUPLEX)
1076                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1077         else
1078                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1079
1080         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1081
1082         return 0;
1083 }
1084
1085 /**
1086  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1087  *  @hw: pointer to the HW structure
1088  *
1089  *  Configure the KMRN interface by applying last minute quirks for
1090  *  gigabit operation.
1091  **/
1092 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1093 {
1094         s32 ret_val;
1095         u16 reg_data;
1096         u32 tipg;
1097
1098         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1099         ret_val = e1000e_write_kmrn_reg(hw,
1100                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1101                                        reg_data);
1102         if (ret_val)
1103                 return ret_val;
1104
1105         /* Configure Transmit Inter-Packet Gap */
1106         tipg = er32(TIPG);
1107         tipg &= ~E1000_TIPG_IPGT_MASK;
1108         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1109         ew32(TIPG, tipg);
1110
1111         ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1112         if (ret_val)
1113                 return ret_val;
1114
1115         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1116         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1117
1118         return ret_val;
1119 }
1120
1121 /**
1122  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1123  *  @hw: pointer to the HW structure
1124  *
1125  *  Clears the hardware counters by reading the counter registers.
1126  **/
1127 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1128 {
1129         u32 temp;
1130
1131         e1000e_clear_hw_cntrs_base(hw);
1132
1133         temp = er32(PRC64);
1134         temp = er32(PRC127);
1135         temp = er32(PRC255);
1136         temp = er32(PRC511);
1137         temp = er32(PRC1023);
1138         temp = er32(PRC1522);
1139         temp = er32(PTC64);
1140         temp = er32(PTC127);
1141         temp = er32(PTC255);
1142         temp = er32(PTC511);
1143         temp = er32(PTC1023);
1144         temp = er32(PTC1522);
1145
1146         temp = er32(ALGNERRC);
1147         temp = er32(RXERRC);
1148         temp = er32(TNCRS);
1149         temp = er32(CEXTERR);
1150         temp = er32(TSCTC);
1151         temp = er32(TSCTFC);
1152
1153         temp = er32(MGTPRC);
1154         temp = er32(MGTPDC);
1155         temp = er32(MGTPTC);
1156
1157         temp = er32(IAC);
1158         temp = er32(ICRXOC);
1159
1160         temp = er32(ICRXPTC);
1161         temp = er32(ICRXATC);
1162         temp = er32(ICTXPTC);
1163         temp = er32(ICTXATC);
1164         temp = er32(ICTXQEC);
1165         temp = er32(ICTXQMTC);
1166         temp = er32(ICRXDMTC);
1167 }
1168
1169 static struct e1000_mac_operations es2_mac_ops = {
1170         .mng_mode_enab          = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
1171         /* check_for_link dependent on media type */
1172         .cleanup_led            = e1000e_cleanup_led_generic,
1173         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1174         .get_bus_info           = e1000e_get_bus_info_pcie,
1175         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1176         .led_on                 = e1000e_led_on_generic,
1177         .led_off                = e1000e_led_off_generic,
1178         .mc_addr_list_update    = e1000e_mc_addr_list_update_generic,
1179         .reset_hw               = e1000_reset_hw_80003es2lan,
1180         .init_hw                = e1000_init_hw_80003es2lan,
1181         .setup_link             = e1000e_setup_link,
1182         /* setup_physical_interface dependent on media type */
1183 };
1184
1185 static struct e1000_phy_operations es2_phy_ops = {
1186         .acquire_phy            = e1000_acquire_phy_80003es2lan,
1187         .check_reset_block      = e1000e_check_reset_block_generic,
1188         .commit_phy             = e1000e_phy_sw_reset,
1189         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1190         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1191         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1192         .get_phy_info           = e1000e_get_phy_info_m88,
1193         .read_phy_reg           = e1000_read_phy_reg_gg82563_80003es2lan,
1194         .release_phy            = e1000_release_phy_80003es2lan,
1195         .reset_phy              = e1000e_phy_hw_reset_generic,
1196         .set_d0_lplu_state      = NULL,
1197         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1198         .write_phy_reg          = e1000_write_phy_reg_gg82563_80003es2lan,
1199 };
1200
1201 static struct e1000_nvm_operations es2_nvm_ops = {
1202         .acquire_nvm            = e1000_acquire_nvm_80003es2lan,
1203         .read_nvm               = e1000e_read_nvm_eerd,
1204         .release_nvm            = e1000_release_nvm_80003es2lan,
1205         .update_nvm             = e1000e_update_nvm_checksum_generic,
1206         .valid_led_default      = e1000e_valid_led_default,
1207         .validate_nvm           = e1000e_validate_nvm_checksum_generic,
1208         .write_nvm              = e1000_write_nvm_80003es2lan,
1209 };
1210
1211 struct e1000_info e1000_es2_info = {
1212         .mac                    = e1000_80003es2lan,
1213         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1214                                   | FLAG_HAS_JUMBO_FRAMES
1215                                   | FLAG_HAS_STATS_PTC_PRC
1216                                   | FLAG_HAS_WOL
1217                                   | FLAG_APME_IN_CTRL3
1218                                   | FLAG_RX_CSUM_ENABLED
1219                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1220                                   | FLAG_HAS_STATS_ICR_ICT
1221                                   | FLAG_RX_NEEDS_RESTART /* errata */
1222                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1223                                   | FLAG_APME_CHECK_PORT_B
1224                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1225                                   | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1226         .pba                    = 38,
1227         .get_invariants         = e1000_get_invariants_80003es2lan,
1228         .mac_ops                = &es2_mac_ops,
1229         .phy_ops                = &es2_phy_ops,
1230         .nvm_ops                = &es2_nvm_ops,
1231 };
1232