3 * Purpose: Generic MCA handling layer
5 * Updated for latest kernel
6 * Copyright (C) 2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 2002 Dell Inc.
10 * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
12 * Copyright (C) 2002 Intel
13 * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
15 * Copyright (C) 2001 Intel
16 * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
18 * Copyright (C) 2000 Intel
19 * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
21 * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
22 * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
24 * 03/04/15 D. Mosberger Added INIT backtrace support.
25 * 02/03/25 M. Domsch GUID cleanups
27 * 02/01/04 J. Hall Aligned MCA stack to 16 bytes, added platform vs. CPU
28 * error flag, set SAL default return values, changed
29 * error record structure to linked list, added init call
30 * to sal_get_state_info_size().
32 * 01/01/03 F. Lewis Added setup of CMCI and CPEI IRQs, logging of corrected
33 * platform errors, completed code for logging of
34 * corrected & uncorrected machine check errors, and
35 * updated for conformance with Nov. 2000 revision of the
37 * 00/03/29 C. Fleckenstein Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
38 * added min save state dump, added INIT handler.
40 * 2003-12-08 Keith Owens <kaos@sgi.com>
41 * smp_call_function() must not be called from interrupt context (can
42 * deadlock on tasklist_lock). Use keventd to call smp_call_function().
44 * 2004-02-01 Keith Owens <kaos@sgi.com>
45 * Avoid deadlock when using printk() for MCA and INIT records.
46 * Delete all record printing code, moved to salinfo_decode in user space.
47 * Mark variables and functions static where possible.
48 * Delete dead variables and functions.
49 * Reorder to remove the need for forward declarations and to consolidate
52 * 2005-08-12 Keith Owens <kaos@sgi.com>
53 * Convert MCA/INIT handlers to use per event stacks and SAL/OS state.
55 * 2005-10-07 Keith Owens <kaos@sgi.com>
56 * Add notify_die() hooks.
58 #include <linux/config.h>
59 #include <linux/types.h>
60 #include <linux/init.h>
61 #include <linux/sched.h>
62 #include <linux/interrupt.h>
63 #include <linux/irq.h>
64 #include <linux/smp_lock.h>
65 #include <linux/bootmem.h>
66 #include <linux/acpi.h>
67 #include <linux/timer.h>
68 #include <linux/module.h>
69 #include <linux/kernel.h>
70 #include <linux/smp.h>
71 #include <linux/workqueue.h>
73 #include <asm/delay.h>
74 #include <asm/kdebug.h>
75 #include <asm/machvec.h>
76 #include <asm/meminit.h>
78 #include <asm/ptrace.h>
79 #include <asm/system.h>
84 #include <asm/hw_irq.h>
88 #if defined(IA64_MCA_DEBUG_INFO)
89 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
91 # define IA64_MCA_DEBUG(fmt...)
94 /* Used by mca_asm.S */
95 u32 ia64_mca_serialize;
96 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
97 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
98 DEFINE_PER_CPU(u64, ia64_mca_pal_pte); /* PTE to map PAL code */
99 DEFINE_PER_CPU(u64, ia64_mca_pal_base); /* vaddr PAL code granule */
101 unsigned long __per_cpu_mca[NR_CPUS];
104 extern void ia64_os_init_dispatch_monarch (void);
105 extern void ia64_os_init_dispatch_slave (void);
107 static int monarch_cpu = -1;
109 static ia64_mc_info_t ia64_mc_info;
111 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
112 #define MIN_CPE_POLL_INTERVAL (2*60*HZ) /* 2 minutes */
113 #define CMC_POLL_INTERVAL (1*60*HZ) /* 1 minute */
114 #define CPE_HISTORY_LENGTH 5
115 #define CMC_HISTORY_LENGTH 5
117 static struct timer_list cpe_poll_timer;
118 static struct timer_list cmc_poll_timer;
120 * This variable tells whether we are currently in polling mode.
121 * Start with this in the wrong state so we won't play w/ timers
122 * before the system is ready.
124 static int cmc_polling_enabled = 1;
127 * Clearing this variable prevents CPE polling from getting activated
128 * in mca_late_init. Use it if your system doesn't provide a CPEI,
129 * but encounters problems retrieving CPE logs. This should only be
130 * necessary for debugging.
132 static int cpe_poll_enabled = 1;
134 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
140 ia64_mca_spin(const char *func)
142 printk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func);
147 * IA64_MCA log support
149 #define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */
150 #define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */
152 typedef struct ia64_state_log_s
156 unsigned long isl_count;
157 ia64_err_rec_t *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
160 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
162 #define IA64_LOG_ALLOCATE(it, size) \
163 {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
164 (ia64_err_rec_t *)alloc_bootmem(size); \
165 ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
166 (ia64_err_rec_t *)alloc_bootmem(size);}
167 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
168 #define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
169 #define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
170 #define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index
171 #define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index
172 #define IA64_LOG_INDEX_INC(it) \
173 {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
174 ia64_state_log[it].isl_count++;}
175 #define IA64_LOG_INDEX_DEC(it) \
176 ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
177 #define IA64_LOG_NEXT_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
178 #define IA64_LOG_CURR_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
179 #define IA64_LOG_COUNT(it) ia64_state_log[it].isl_count
183 * Reset the OS ia64 log buffer
184 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
188 ia64_log_init(int sal_info_type)
192 IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
193 IA64_LOG_LOCK_INIT(sal_info_type);
195 // SAL will tell us the maximum size of any error record of this type
196 max_size = ia64_sal_get_state_info_size(sal_info_type);
198 /* alloc_bootmem() doesn't like zero-sized allocations! */
201 // set up OS data structures to hold error info
202 IA64_LOG_ALLOCATE(sal_info_type, max_size);
203 memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
204 memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
210 * Get the current MCA log from SAL and copy it into the OS log buffer.
212 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
213 * irq_safe whether you can use printk at this point
214 * Outputs : size (total record length)
215 * *buffer (ptr to error record)
219 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
221 sal_log_record_header_t *log_buffer;
225 IA64_LOG_LOCK(sal_info_type);
227 /* Get the process state information */
228 log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
230 total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
233 IA64_LOG_INDEX_INC(sal_info_type);
234 IA64_LOG_UNLOCK(sal_info_type);
236 IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
237 "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len);
239 *buffer = (u8 *) log_buffer;
242 IA64_LOG_UNLOCK(sal_info_type);
248 * ia64_mca_log_sal_error_record
250 * This function retrieves a specified error record type from SAL
251 * and wakes up any processes waiting for error records.
253 * Inputs : sal_info_type (Type of error record MCA/CMC/CPE)
254 * FIXME: remove MCA and irq_safe.
257 ia64_mca_log_sal_error_record(int sal_info_type)
260 sal_log_record_header_t *rh;
262 int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
263 #ifdef IA64_MCA_DEBUG_INFO
264 static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
267 size = ia64_log_get(sal_info_type, &buffer, irq_safe);
271 salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
274 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
276 sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
278 /* Clear logs from corrected errors in case there's no user-level logger */
279 rh = (sal_log_record_header_t *)buffer;
280 if (rh->severity == sal_log_severity_corrected)
281 ia64_sal_clear_state_info(sal_info_type);
285 * platform dependent error handling
287 #ifndef PLATFORM_MCA_HANDLERS
292 int ia64_cpe_irq = -1;
295 ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs)
297 static unsigned long cpe_history[CPE_HISTORY_LENGTH];
299 static DEFINE_SPINLOCK(cpe_history_lock);
301 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
302 __FUNCTION__, cpe_irq, smp_processor_id());
304 /* SAL spec states this should run w/ interrupts enabled */
307 /* Get the CPE error record and log it */
308 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
310 spin_lock(&cpe_history_lock);
311 if (!cpe_poll_enabled && cpe_vector >= 0) {
313 int i, count = 1; /* we know 1 happened now */
314 unsigned long now = jiffies;
316 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
317 if (now - cpe_history[i] <= HZ)
321 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
322 if (count >= CPE_HISTORY_LENGTH) {
324 cpe_poll_enabled = 1;
325 spin_unlock(&cpe_history_lock);
326 disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
329 * Corrected errors will still be corrected, but
330 * make sure there's a log somewhere that indicates
331 * something is generating more than we can handle.
333 printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
335 mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
337 /* lock already released, get out now */
340 cpe_history[index++] = now;
341 if (index == CPE_HISTORY_LENGTH)
345 spin_unlock(&cpe_history_lock);
349 #endif /* CONFIG_ACPI */
353 * ia64_mca_register_cpev
355 * Register the corrected platform error vector with SAL.
358 * cpev Corrected Platform Error Vector number
364 ia64_mca_register_cpev (int cpev)
366 /* Register the CPE interrupt vector with SAL */
367 struct ia64_sal_retval isrv;
369 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
371 printk(KERN_ERR "Failed to register Corrected Platform "
372 "Error interrupt vector with SAL (status %ld)\n", isrv.status);
376 IA64_MCA_DEBUG("%s: corrected platform error "
377 "vector %#x registered\n", __FUNCTION__, cpev);
379 #endif /* CONFIG_ACPI */
381 #endif /* PLATFORM_MCA_HANDLERS */
384 * ia64_mca_cmc_vector_setup
386 * Setup the corrected machine check vector register in the processor.
387 * (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
388 * This function is invoked on a per-processor basis.
397 ia64_mca_cmc_vector_setup (void)
401 cmcv.cmcv_regval = 0;
402 cmcv.cmcv_mask = 1; /* Mask/disable interrupt at first */
403 cmcv.cmcv_vector = IA64_CMC_VECTOR;
404 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
406 IA64_MCA_DEBUG("%s: CPU %d corrected "
407 "machine check vector %#x registered.\n",
408 __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR);
410 IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
411 __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
415 * ia64_mca_cmc_vector_disable
417 * Mask the corrected machine check vector register in the processor.
418 * This function is invoked on a per-processor basis.
427 ia64_mca_cmc_vector_disable (void *dummy)
431 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
433 cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
434 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
436 IA64_MCA_DEBUG("%s: CPU %d corrected "
437 "machine check vector %#x disabled.\n",
438 __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
442 * ia64_mca_cmc_vector_enable
444 * Unmask the corrected machine check vector register in the processor.
445 * This function is invoked on a per-processor basis.
454 ia64_mca_cmc_vector_enable (void *dummy)
458 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
460 cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
461 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
463 IA64_MCA_DEBUG("%s: CPU %d corrected "
464 "machine check vector %#x enabled.\n",
465 __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
469 * ia64_mca_cmc_vector_disable_keventd
471 * Called via keventd (smp_call_function() is not safe in interrupt context) to
472 * disable the cmc interrupt vector.
475 ia64_mca_cmc_vector_disable_keventd(void *unused)
477 on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0);
481 * ia64_mca_cmc_vector_enable_keventd
483 * Called via keventd (smp_call_function() is not safe in interrupt context) to
484 * enable the cmc interrupt vector.
487 ia64_mca_cmc_vector_enable_keventd(void *unused)
489 on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0);
495 * Send an inter-cpu interrupt to wake-up a particular cpu
496 * and mark that cpu to be out of rendez.
502 ia64_mca_wakeup(int cpu)
504 platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
505 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
510 * ia64_mca_wakeup_all
512 * Wakeup all the cpus which have rendez'ed previously.
518 ia64_mca_wakeup_all(void)
522 /* Clear the Rendez checkin flag for all cpus */
523 for_each_online_cpu(cpu) {
524 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
525 ia64_mca_wakeup(cpu);
531 * ia64_mca_rendez_interrupt_handler
533 * This is handler used to put slave processors into spinloop
534 * while the monarch processor does the mca handling and later
535 * wake each slave up once the monarch is done.
541 ia64_mca_rendez_int_handler(int rendez_irq, void *arg, struct pt_regs *regs)
544 int cpu = smp_processor_id();
546 /* Mask all interrupts */
547 local_irq_save(flags);
548 if (notify_die(DIE_MCA_RENDZVOUS_ENTER, "MCA", regs, 0, 0, 0)
550 ia64_mca_spin(__FUNCTION__);
552 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
553 /* Register with the SAL monarch that the slave has
556 ia64_sal_mc_rendez();
558 if (notify_die(DIE_MCA_RENDZVOUS_PROCESS, "MCA", regs, 0, 0, 0)
560 ia64_mca_spin(__FUNCTION__);
562 /* Wait for the monarch cpu to exit. */
563 while (monarch_cpu != -1)
564 cpu_relax(); /* spin until monarch leaves */
566 if (notify_die(DIE_MCA_RENDZVOUS_LEAVE, "MCA", regs, 0, 0, 0)
568 ia64_mca_spin(__FUNCTION__);
570 /* Enable all interrupts */
571 local_irq_restore(flags);
576 * ia64_mca_wakeup_int_handler
578 * The interrupt handler for processing the inter-cpu interrupt to the
579 * slave cpu which was spinning in the rendez loop.
580 * Since this spinning is done by turning off the interrupts and
581 * polling on the wakeup-interrupt bit in the IRR, there is
582 * nothing useful to be done in the handler.
584 * Inputs : wakeup_irq (Wakeup-interrupt bit)
585 * arg (Interrupt handler specific argument)
586 * ptregs (Exception frame at the time of the interrupt)
591 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg, struct pt_regs *ptregs)
596 /* Function pointer for extra MCA recovery */
597 int (*ia64_mca_ucmc_extension)
598 (void*,struct ia64_sal_os_state*)
602 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
604 if (ia64_mca_ucmc_extension)
607 ia64_mca_ucmc_extension = fn;
612 ia64_unreg_MCA_extension(void)
614 if (ia64_mca_ucmc_extension)
615 ia64_mca_ucmc_extension = NULL;
618 EXPORT_SYMBOL(ia64_reg_MCA_extension);
619 EXPORT_SYMBOL(ia64_unreg_MCA_extension);
623 copy_reg(const u64 *fr, u64 fnat, u64 *tr, u64 *tnat)
625 u64 fslot, tslot, nat;
627 fslot = ((unsigned long)fr >> 3) & 63;
628 tslot = ((unsigned long)tr >> 3) & 63;
629 *tnat &= ~(1UL << tslot);
630 nat = (fnat >> fslot) & 1;
631 *tnat |= (nat << tslot);
634 /* On entry to this routine, we are running on the per cpu stack, see
635 * mca_asm.h. The original stack has not been touched by this event. Some of
636 * the original stack's registers will be in the RBS on this stack. This stack
637 * also contains a partial pt_regs and switch_stack, the rest of the data is in
640 * The first thing to do is modify the original stack to look like a blocked
641 * task so we can run backtrace on the original task. Also mark the per cpu
642 * stack as current to ensure that we use the correct task state, it also means
643 * that we can do backtrace on the MCA/INIT handler code itself.
647 ia64_mca_modify_original_stack(struct pt_regs *regs,
648 const struct switch_stack *sw,
649 struct ia64_sal_os_state *sos,
652 char *p, comm[sizeof(current->comm)];
654 extern char ia64_leave_kernel[]; /* Need asm address, not function descriptor */
655 const pal_min_state_area_t *ms = sos->pal_min_state;
656 task_t *previous_current;
657 struct pt_regs *old_regs;
658 struct switch_stack *old_sw;
659 unsigned size = sizeof(struct pt_regs) +
660 sizeof(struct switch_stack) + 16;
661 u64 *old_bspstore, *old_bsp;
662 u64 *new_bspstore, *new_bsp;
663 u64 old_unat, old_rnat, new_rnat, nat;
664 u64 slots, loadrs = regs->loadrs;
665 u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
666 u64 ar_bspstore = regs->ar_bspstore;
667 u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
670 int cpu = smp_processor_id();
672 previous_current = curr_task(cpu);
673 set_curr_task(cpu, current);
674 if ((p = strchr(current->comm, ' ')))
677 /* Best effort attempt to cope with MCA/INIT delivered while in
680 regs->cr_ipsr = ms->pmsa_ipsr;
681 if (ia64_psr(regs)->dt == 0) {
693 if (ia64_psr(regs)->rt == 0) {
706 /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
707 * have been copied to the old stack, the old stack may fail the
708 * validation tests below. So ia64_old_stack() must restore the dirty
709 * registers from the new stack. The old and new bspstore probably
710 * have different alignments, so loadrs calculated on the old bsp
711 * cannot be used to restore from the new bsp. Calculate a suitable
712 * loadrs for the new stack and save it in the new pt_regs, where
713 * ia64_old_stack() can get it.
715 old_bspstore = (u64 *)ar_bspstore;
716 old_bsp = (u64 *)ar_bsp;
717 slots = ia64_rse_num_regs(old_bspstore, old_bsp);
718 new_bspstore = (u64 *)((u64)current + IA64_RBS_OFFSET);
719 new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
720 regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
722 /* Verify the previous stack state before we change it */
723 if (user_mode(regs)) {
724 msg = "occurred in user space";
727 if (r13 != sos->prev_IA64_KR_CURRENT) {
728 msg = "inconsistent previous current and r13";
731 if ((r12 - r13) >= KERNEL_STACK_SIZE) {
732 msg = "inconsistent r12 and r13";
735 if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
736 msg = "inconsistent ar.bspstore and r13";
741 msg = "old_bspstore is in the wrong region";
744 if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
745 msg = "inconsistent ar.bsp and r13";
748 size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
749 if (ar_bspstore + size > r12) {
750 msg = "no room for blocked state";
754 /* Change the comm field on the MCA/INT task to include the pid that
755 * was interrupted, it makes for easier debugging. If that pid was 0
756 * (swapper or nested MCA/INIT) then use the start of the previous comm
757 * field suffixed with its cpu.
759 if (previous_current->pid)
760 snprintf(comm, sizeof(comm), "%s %d",
761 current->comm, previous_current->pid);
764 if ((p = strchr(previous_current->comm, ' ')))
765 l = p - previous_current->comm;
767 l = strlen(previous_current->comm);
768 snprintf(comm, sizeof(comm), "%s %*s %d",
769 current->comm, l, previous_current->comm,
770 task_thread_info(previous_current)->cpu);
772 memcpy(current->comm, comm, sizeof(current->comm));
774 /* Make the original task look blocked. First stack a struct pt_regs,
775 * describing the state at the time of interrupt. mca_asm.S built a
776 * partial pt_regs, copy it and fill in the blanks using minstate.
778 p = (char *)r12 - sizeof(*regs);
779 old_regs = (struct pt_regs *)p;
780 memcpy(old_regs, regs, sizeof(*regs));
781 /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
782 * pmsa_{xip,xpsr,xfs}
784 if (ia64_psr(regs)->ic) {
785 old_regs->cr_iip = ms->pmsa_iip;
786 old_regs->cr_ipsr = ms->pmsa_ipsr;
787 old_regs->cr_ifs = ms->pmsa_ifs;
789 old_regs->cr_iip = ms->pmsa_xip;
790 old_regs->cr_ipsr = ms->pmsa_xpsr;
791 old_regs->cr_ifs = ms->pmsa_xfs;
793 old_regs->pr = ms->pmsa_pr;
794 old_regs->b0 = ms->pmsa_br0;
795 old_regs->loadrs = loadrs;
796 old_regs->ar_rsc = ms->pmsa_rsc;
797 old_unat = old_regs->ar_unat;
798 copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &old_regs->r1, &old_unat);
799 copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &old_regs->r2, &old_unat);
800 copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &old_regs->r3, &old_unat);
801 copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &old_regs->r8, &old_unat);
802 copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &old_regs->r9, &old_unat);
803 copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &old_regs->r10, &old_unat);
804 copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &old_regs->r11, &old_unat);
805 copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &old_regs->r12, &old_unat);
806 copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &old_regs->r13, &old_unat);
807 copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &old_regs->r14, &old_unat);
808 copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &old_regs->r15, &old_unat);
809 if (ia64_psr(old_regs)->bn)
810 bank = ms->pmsa_bank1_gr;
812 bank = ms->pmsa_bank0_gr;
813 copy_reg(&bank[16-16], ms->pmsa_nat_bits, &old_regs->r16, &old_unat);
814 copy_reg(&bank[17-16], ms->pmsa_nat_bits, &old_regs->r17, &old_unat);
815 copy_reg(&bank[18-16], ms->pmsa_nat_bits, &old_regs->r18, &old_unat);
816 copy_reg(&bank[19-16], ms->pmsa_nat_bits, &old_regs->r19, &old_unat);
817 copy_reg(&bank[20-16], ms->pmsa_nat_bits, &old_regs->r20, &old_unat);
818 copy_reg(&bank[21-16], ms->pmsa_nat_bits, &old_regs->r21, &old_unat);
819 copy_reg(&bank[22-16], ms->pmsa_nat_bits, &old_regs->r22, &old_unat);
820 copy_reg(&bank[23-16], ms->pmsa_nat_bits, &old_regs->r23, &old_unat);
821 copy_reg(&bank[24-16], ms->pmsa_nat_bits, &old_regs->r24, &old_unat);
822 copy_reg(&bank[25-16], ms->pmsa_nat_bits, &old_regs->r25, &old_unat);
823 copy_reg(&bank[26-16], ms->pmsa_nat_bits, &old_regs->r26, &old_unat);
824 copy_reg(&bank[27-16], ms->pmsa_nat_bits, &old_regs->r27, &old_unat);
825 copy_reg(&bank[28-16], ms->pmsa_nat_bits, &old_regs->r28, &old_unat);
826 copy_reg(&bank[29-16], ms->pmsa_nat_bits, &old_regs->r29, &old_unat);
827 copy_reg(&bank[30-16], ms->pmsa_nat_bits, &old_regs->r30, &old_unat);
828 copy_reg(&bank[31-16], ms->pmsa_nat_bits, &old_regs->r31, &old_unat);
830 /* Next stack a struct switch_stack. mca_asm.S built a partial
831 * switch_stack, copy it and fill in the blanks using pt_regs and
834 * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
835 * ar.pfs is set to 0.
837 * unwind.c::unw_unwind() does special processing for interrupt frames.
838 * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
839 * is clear then unw_unwind() does _not_ adjust bsp over pt_regs. Not
840 * that this is documented, of course. Set PRED_NON_SYSCALL in the
841 * switch_stack on the original stack so it will unwind correctly when
842 * unwind.c reads pt_regs.
844 * thread.ksp is updated to point to the synthesized switch_stack.
846 p -= sizeof(struct switch_stack);
847 old_sw = (struct switch_stack *)p;
848 memcpy(old_sw, sw, sizeof(*sw));
849 old_sw->caller_unat = old_unat;
850 old_sw->ar_fpsr = old_regs->ar_fpsr;
851 copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
852 copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
853 copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
854 copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
855 old_sw->b0 = (u64)ia64_leave_kernel;
856 old_sw->b1 = ms->pmsa_br1;
858 old_sw->ar_unat = old_unat;
859 old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
860 previous_current->thread.ksp = (u64)p - 16;
862 /* Finally copy the original stack's registers back to its RBS.
863 * Registers from ar.bspstore through ar.bsp at the time of the event
864 * are in the current RBS, copy them back to the original stack. The
865 * copy must be done register by register because the original bspstore
866 * and the current one have different alignments, so the saved RNAT
867 * data occurs at different places.
869 * mca_asm does cover, so the old_bsp already includes all registers at
870 * the time of MCA/INIT. It also does flushrs, so all registers before
871 * this function have been written to backing store on the MCA/INIT
874 new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
875 old_rnat = regs->ar_rnat;
877 if (ia64_rse_is_rnat_slot(new_bspstore)) {
878 new_rnat = ia64_get_rnat(new_bspstore++);
880 if (ia64_rse_is_rnat_slot(old_bspstore)) {
881 *old_bspstore++ = old_rnat;
884 nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
885 old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
886 old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
887 *old_bspstore++ = *new_bspstore++;
889 old_sw->ar_bspstore = (unsigned long)old_bspstore;
890 old_sw->ar_rnat = old_rnat;
892 sos->prev_task = previous_current;
893 return previous_current;
896 printk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
897 smp_processor_id(), type, msg);
898 return previous_current;
901 /* The monarch/slave interaction is based on monarch_cpu and requires that all
902 * slaves have entered rendezvous before the monarch leaves. If any cpu has
903 * not entered rendezvous yet then wait a bit. The assumption is that any
904 * slave that has not rendezvoused after a reasonable time is never going to do
905 * so. In this context, slave includes cpus that respond to the MCA rendezvous
906 * interrupt, as well as cpus that receive the INIT slave event.
910 ia64_wait_for_slaves(int monarch)
913 for_each_online_cpu(c) {
916 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
917 udelay(1000); /* short wait first */
924 for_each_online_cpu(c) {
927 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
928 udelay(5*1000000); /* wait 5 seconds for slaves (arbitrary) */
937 * This is uncorrectable machine check handler called from OS_MCA
938 * dispatch code which is in turn called from SAL_CHECK().
939 * This is the place where the core of OS MCA handling is done.
940 * Right now the logs are extracted and displayed in a well-defined
941 * format. This handler code is supposed to be run only on the
942 * monarch processor. Once the monarch is done with MCA handling
943 * further MCA logging is enabled by clearing logs.
944 * Monarch also has the duty of sending wakeup-IPIs to pull the
945 * slave processors out of rendezvous spinloop.
948 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
949 struct ia64_sal_os_state *sos)
951 pal_processor_state_info_t *psp = (pal_processor_state_info_t *)
952 &sos->proc_state_param;
953 int recover, cpu = smp_processor_id();
954 task_t *previous_current;
956 oops_in_progress = 1; /* FIXME: make printk NMI/MCA/INIT safe */
957 previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
959 if (notify_die(DIE_MCA_MONARCH_ENTER, "MCA", regs, 0, 0, 0)
961 ia64_mca_spin(__FUNCTION__);
962 ia64_wait_for_slaves(cpu);
964 /* Wakeup all the processors which are spinning in the rendezvous loop.
965 * They will leave SAL, then spin in the OS with interrupts disabled
966 * until this monarch cpu leaves the MCA handler. That gets control
967 * back to the OS so we can backtrace the other cpus, backtrace when
968 * spinning in SAL does not work.
970 ia64_mca_wakeup_all();
971 if (notify_die(DIE_MCA_MONARCH_PROCESS, "MCA", regs, 0, 0, 0)
973 ia64_mca_spin(__FUNCTION__);
975 /* Get the MCA error record and log it */
976 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
978 /* TLB error is only exist in this SAL error record */
979 recover = (psp->tc && !(psp->cc || psp->bc || psp->rc || psp->uc))
980 /* other error recovery */
981 || (ia64_mca_ucmc_extension
982 && ia64_mca_ucmc_extension(
983 IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
987 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
988 rh->severity = sal_log_severity_corrected;
989 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
990 sos->os_status = IA64_MCA_CORRECTED;
992 if (notify_die(DIE_MCA_MONARCH_LEAVE, "MCA", regs, 0, 0, recover)
994 ia64_mca_spin(__FUNCTION__);
996 set_curr_task(cpu, previous_current);
1000 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd, NULL);
1001 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd, NULL);
1004 * ia64_mca_cmc_int_handler
1006 * This is corrected machine check interrupt handler.
1007 * Right now the logs are extracted and displayed in a well-defined
1012 * client data arg ptr
1013 * saved registers ptr
1019 ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs)
1021 static unsigned long cmc_history[CMC_HISTORY_LENGTH];
1023 static DEFINE_SPINLOCK(cmc_history_lock);
1025 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1026 __FUNCTION__, cmc_irq, smp_processor_id());
1028 /* SAL spec states this should run w/ interrupts enabled */
1031 /* Get the CMC error record and log it */
1032 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
1034 spin_lock(&cmc_history_lock);
1035 if (!cmc_polling_enabled) {
1036 int i, count = 1; /* we know 1 happened now */
1037 unsigned long now = jiffies;
1039 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
1040 if (now - cmc_history[i] <= HZ)
1044 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
1045 if (count >= CMC_HISTORY_LENGTH) {
1047 cmc_polling_enabled = 1;
1048 spin_unlock(&cmc_history_lock);
1049 /* If we're being hit with CMC interrupts, we won't
1050 * ever execute the schedule_work() below. Need to
1051 * disable CMC interrupts on this processor now.
1053 ia64_mca_cmc_vector_disable(NULL);
1054 schedule_work(&cmc_disable_work);
1057 * Corrected errors will still be corrected, but
1058 * make sure there's a log somewhere that indicates
1059 * something is generating more than we can handle.
1061 printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
1063 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1065 /* lock already released, get out now */
1068 cmc_history[index++] = now;
1069 if (index == CMC_HISTORY_LENGTH)
1073 spin_unlock(&cmc_history_lock);
1078 * ia64_mca_cmc_int_caller
1080 * Triggered by sw interrupt from CMC polling routine. Calls
1081 * real interrupt handler and either triggers a sw interrupt
1082 * on the next cpu or does cleanup at the end.
1086 * client data arg ptr
1087 * saved registers ptr
1092 ia64_mca_cmc_int_caller(int cmc_irq, void *arg, struct pt_regs *ptregs)
1094 static int start_count = -1;
1097 cpuid = smp_processor_id();
1099 /* If first cpu, update count */
1100 if (start_count == -1)
1101 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
1103 ia64_mca_cmc_int_handler(cmc_irq, arg, ptregs);
1105 for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1107 if (cpuid < NR_CPUS) {
1108 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1110 /* If no log record, switch out of polling mode */
1111 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1113 printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1114 schedule_work(&cmc_enable_work);
1115 cmc_polling_enabled = 0;
1119 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1131 * Poll for Corrected Machine Checks (CMCs)
1133 * Inputs : dummy(unused)
1138 ia64_mca_cmc_poll (unsigned long dummy)
1140 /* Trigger a CMC interrupt cascade */
1141 platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1145 * ia64_mca_cpe_int_caller
1147 * Triggered by sw interrupt from CPE polling routine. Calls
1148 * real interrupt handler and either triggers a sw interrupt
1149 * on the next cpu or does cleanup at the end.
1153 * client data arg ptr
1154 * saved registers ptr
1161 ia64_mca_cpe_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs)
1163 static int start_count = -1;
1164 static int poll_time = MIN_CPE_POLL_INTERVAL;
1167 cpuid = smp_processor_id();
1169 /* If first cpu, update count */
1170 if (start_count == -1)
1171 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1173 ia64_mca_cpe_int_handler(cpe_irq, arg, ptregs);
1175 for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1177 if (cpuid < NR_CPUS) {
1178 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1181 * If a log was recorded, increase our polling frequency,
1182 * otherwise, backoff or return to interrupt mode.
1184 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1185 poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1186 } else if (cpe_vector < 0) {
1187 poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1189 poll_time = MIN_CPE_POLL_INTERVAL;
1191 printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1192 enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1193 cpe_poll_enabled = 0;
1196 if (cpe_poll_enabled)
1197 mod_timer(&cpe_poll_timer, jiffies + poll_time);
1207 * Poll for Corrected Platform Errors (CPEs), trigger interrupt
1208 * on first cpu, from there it will trickle through all the cpus.
1210 * Inputs : dummy(unused)
1215 ia64_mca_cpe_poll (unsigned long dummy)
1217 /* Trigger a CPE interrupt cascade */
1218 platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1221 #endif /* CONFIG_ACPI */
1224 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
1227 struct task_struct *g, *t;
1228 if (val != DIE_INIT_MONARCH_PROCESS)
1230 printk(KERN_ERR "Processes interrupted by INIT -");
1231 for_each_online_cpu(c) {
1232 struct ia64_sal_os_state *s;
1233 t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
1234 s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
1238 printk(" %d", g->pid);
1240 printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
1244 if (read_trylock(&tasklist_lock)) {
1245 do_each_thread (g, t) {
1246 printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
1247 show_stack(t, NULL);
1248 } while_each_thread (g, t);
1249 read_unlock(&tasklist_lock);
1255 * C portion of the OS INIT handler
1257 * Called from ia64_os_init_dispatch
1259 * Inputs: pointer to pt_regs where processor info was saved. SAL/OS state for
1260 * this event. This code is used for both monarch and slave INIT events, see
1263 * All INIT events switch to the INIT stack and change the previous process to
1264 * blocked status. If one of the INIT events is the monarch then we are
1265 * probably processing the nmi button/command. Use the monarch cpu to dump all
1266 * the processes. The slave INIT events all spin until the monarch cpu
1267 * returns. We can also get INIT slave events for MCA, in which case the MCA
1268 * process is the monarch.
1272 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
1273 struct ia64_sal_os_state *sos)
1275 static atomic_t slaves;
1276 static atomic_t monarchs;
1277 task_t *previous_current;
1278 int cpu = smp_processor_id();
1280 oops_in_progress = 1; /* FIXME: make printk NMI/MCA/INIT safe */
1281 console_loglevel = 15; /* make sure printks make it to console */
1283 printk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1284 sos->proc_state_param, cpu, sos->monarch);
1285 salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
1287 previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
1288 sos->os_status = IA64_INIT_RESUME;
1290 /* FIXME: Workaround for broken proms that drive all INIT events as
1291 * slaves. The last slave that enters is promoted to be a monarch.
1292 * Remove this code in September 2006, that gives platforms a year to
1293 * fix their proms and get their customers updated.
1295 if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
1296 printk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
1298 atomic_dec(&slaves);
1302 /* FIXME: Workaround for broken proms that drive all INIT events as
1303 * monarchs. Second and subsequent monarchs are demoted to slaves.
1304 * Remove this code in September 2006, that gives platforms a year to
1305 * fix their proms and get their customers updated.
1307 if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
1308 printk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
1310 atomic_dec(&monarchs);
1314 if (!sos->monarch) {
1315 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
1316 while (monarch_cpu == -1)
1317 cpu_relax(); /* spin until monarch enters */
1318 if (notify_die(DIE_INIT_SLAVE_ENTER, "INIT", regs, 0, 0, 0)
1320 ia64_mca_spin(__FUNCTION__);
1321 if (notify_die(DIE_INIT_SLAVE_PROCESS, "INIT", regs, 0, 0, 0)
1323 ia64_mca_spin(__FUNCTION__);
1324 while (monarch_cpu != -1)
1325 cpu_relax(); /* spin until monarch leaves */
1326 if (notify_die(DIE_INIT_SLAVE_LEAVE, "INIT", regs, 0, 0, 0)
1328 ia64_mca_spin(__FUNCTION__);
1329 printk("Slave on cpu %d returning to normal service.\n", cpu);
1330 set_curr_task(cpu, previous_current);
1331 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1332 atomic_dec(&slaves);
1337 if (notify_die(DIE_INIT_MONARCH_ENTER, "INIT", regs, 0, 0, 0)
1339 ia64_mca_spin(__FUNCTION__);
1342 * Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1343 * generated via the BMC's command-line interface, but since the console is on the
1344 * same serial line, the user will need some time to switch out of the BMC before
1347 printk("Delaying for 5 seconds...\n");
1349 ia64_wait_for_slaves(cpu);
1350 /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1351 * to default_monarch_init_process() above and just print all the
1354 if (notify_die(DIE_INIT_MONARCH_PROCESS, "INIT", regs, 0, 0, 0)
1356 ia64_mca_spin(__FUNCTION__);
1357 if (notify_die(DIE_INIT_MONARCH_LEAVE, "INIT", regs, 0, 0, 0)
1359 ia64_mca_spin(__FUNCTION__);
1360 printk("\nINIT dump complete. Monarch on cpu %d returning to normal service.\n", cpu);
1361 atomic_dec(&monarchs);
1362 set_curr_task(cpu, previous_current);
1368 ia64_mca_disable_cpe_polling(char *str)
1370 cpe_poll_enabled = 0;
1374 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1376 static struct irqaction cmci_irqaction = {
1377 .handler = ia64_mca_cmc_int_handler,
1378 .flags = SA_INTERRUPT,
1382 static struct irqaction cmcp_irqaction = {
1383 .handler = ia64_mca_cmc_int_caller,
1384 .flags = SA_INTERRUPT,
1388 static struct irqaction mca_rdzv_irqaction = {
1389 .handler = ia64_mca_rendez_int_handler,
1390 .flags = SA_INTERRUPT,
1394 static struct irqaction mca_wkup_irqaction = {
1395 .handler = ia64_mca_wakeup_int_handler,
1396 .flags = SA_INTERRUPT,
1401 static struct irqaction mca_cpe_irqaction = {
1402 .handler = ia64_mca_cpe_int_handler,
1403 .flags = SA_INTERRUPT,
1407 static struct irqaction mca_cpep_irqaction = {
1408 .handler = ia64_mca_cpe_int_caller,
1409 .flags = SA_INTERRUPT,
1412 #endif /* CONFIG_ACPI */
1414 /* Minimal format of the MCA/INIT stacks. The pseudo processes that run on
1415 * these stacks can never sleep, they cannot return from the kernel to user
1416 * space, they do not appear in a normal ps listing. So there is no need to
1417 * format most of the fields.
1421 format_mca_init_stack(void *mca_data, unsigned long offset,
1422 const char *type, int cpu)
1424 struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
1425 struct thread_info *ti;
1426 memset(p, 0, KERNEL_STACK_SIZE);
1427 ti = task_thread_info(p);
1428 ti->flags = _TIF_MCA_INIT;
1429 ti->preempt_count = 1;
1432 p->thread_info = ti;
1433 p->state = TASK_UNINTERRUPTIBLE;
1434 __set_bit(cpu, &p->cpus_allowed);
1435 INIT_LIST_HEAD(&p->tasks);
1436 p->parent = p->real_parent = p->group_leader = p;
1437 INIT_LIST_HEAD(&p->children);
1438 INIT_LIST_HEAD(&p->sibling);
1439 strncpy(p->comm, type, sizeof(p->comm)-1);
1442 /* Do per-CPU MCA-related initialization. */
1445 ia64_mca_cpu_init(void *cpu_data)
1448 static int first_time = 1;
1455 mca_data = alloc_bootmem(sizeof(struct ia64_mca_cpu)
1456 * NR_CPUS + KERNEL_STACK_SIZE);
1457 mca_data = (void *)(((unsigned long)mca_data +
1458 KERNEL_STACK_SIZE - 1) &
1459 (-KERNEL_STACK_SIZE));
1460 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1461 format_mca_init_stack(mca_data,
1462 offsetof(struct ia64_mca_cpu, mca_stack),
1464 format_mca_init_stack(mca_data,
1465 offsetof(struct ia64_mca_cpu, init_stack),
1467 __per_cpu_mca[cpu] = __pa(mca_data);
1468 mca_data += sizeof(struct ia64_mca_cpu);
1473 * The MCA info structure was allocated earlier and its
1474 * physical address saved in __per_cpu_mca[cpu]. Copy that
1475 * address * to ia64_mca_data so we can access it as a per-CPU
1478 __get_cpu_var(ia64_mca_data) = __per_cpu_mca[smp_processor_id()];
1481 * Stash away a copy of the PTE needed to map the per-CPU page.
1482 * We may need it during MCA recovery.
1484 __get_cpu_var(ia64_mca_per_cpu_pte) =
1485 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL));
1488 * Also, stash away a copy of the PAL address and the PTE
1491 pal_vaddr = efi_get_pal_addr();
1494 __get_cpu_var(ia64_mca_pal_base) =
1495 GRANULEROUNDDOWN((unsigned long) pal_vaddr);
1496 __get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr),
1503 * Do all the system level mca specific initialization.
1505 * 1. Register spinloop and wakeup request interrupt vectors
1507 * 2. Register OS_MCA handler entry point
1509 * 3. Register OS_INIT handler entry point
1511 * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1513 * Note that this initialization is done very early before some kernel
1514 * services are available.
1523 ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
1524 ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
1525 ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1528 struct ia64_sal_retval isrv;
1529 u64 timeout = IA64_MCA_RENDEZ_TIMEOUT; /* platform specific */
1530 static struct notifier_block default_init_monarch_nb = {
1531 .notifier_call = default_monarch_init_process,
1532 .priority = 0/* we need to notified last */
1535 IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__);
1537 /* Clear the Rendez checkin flag for all cpus */
1538 for(i = 0 ; i < NR_CPUS; i++)
1539 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1542 * Register the rendezvous spinloop and wakeup mechanism with SAL
1545 /* Register the rendezvous interrupt vector with SAL */
1547 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1548 SAL_MC_PARAM_MECHANISM_INT,
1549 IA64_MCA_RENDEZ_VECTOR,
1551 SAL_MC_PARAM_RZ_ALWAYS);
1556 printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1557 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1561 printk(KERN_ERR "Failed to register rendezvous interrupt "
1562 "with SAL (status %ld)\n", rc);
1566 /* Register the wakeup interrupt vector with SAL */
1567 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1568 SAL_MC_PARAM_MECHANISM_INT,
1569 IA64_MCA_WAKEUP_VECTOR,
1573 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1574 "(status %ld)\n", rc);
1578 IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__);
1580 ia64_mc_info.imi_mca_handler = ia64_tpa(mca_hldlr_ptr->fp);
1582 * XXX - disable SAL checksum by setting size to 0; should be
1583 * ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1585 ia64_mc_info.imi_mca_handler_size = 0;
1587 /* Register the os mca handler with SAL */
1588 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1589 ia64_mc_info.imi_mca_handler,
1590 ia64_tpa(mca_hldlr_ptr->gp),
1591 ia64_mc_info.imi_mca_handler_size,
1594 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1595 "(status %ld)\n", rc);
1599 IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__,
1600 ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1603 * XXX - disable SAL checksum by setting size to 0, should be
1604 * size of the actual init handler in mca_asm.S.
1606 ia64_mc_info.imi_monarch_init_handler = ia64_tpa(init_hldlr_ptr_monarch->fp);
1607 ia64_mc_info.imi_monarch_init_handler_size = 0;
1608 ia64_mc_info.imi_slave_init_handler = ia64_tpa(init_hldlr_ptr_slave->fp);
1609 ia64_mc_info.imi_slave_init_handler_size = 0;
1611 IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__,
1612 ia64_mc_info.imi_monarch_init_handler);
1614 /* Register the os init handler with SAL */
1615 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
1616 ia64_mc_info.imi_monarch_init_handler,
1617 ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1618 ia64_mc_info.imi_monarch_init_handler_size,
1619 ia64_mc_info.imi_slave_init_handler,
1620 ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1621 ia64_mc_info.imi_slave_init_handler_size)))
1623 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
1624 "(status %ld)\n", rc);
1627 if (register_die_notifier(&default_init_monarch_nb)) {
1628 printk(KERN_ERR "Failed to register default monarch INIT process\n");
1632 IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__);
1635 * Configure the CMCI/P vector and handler. Interrupts for CMC are
1636 * per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1638 register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
1639 register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
1640 ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */
1642 /* Setup the MCA rendezvous interrupt vector */
1643 register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
1645 /* Setup the MCA wakeup interrupt vector */
1646 register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
1649 /* Setup the CPEI/P handler */
1650 register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
1653 /* Initialize the areas set aside by the OS to buffer the
1654 * platform/processor error states for MCA/INIT/CMC
1657 ia64_log_init(SAL_INFO_TYPE_MCA);
1658 ia64_log_init(SAL_INFO_TYPE_INIT);
1659 ia64_log_init(SAL_INFO_TYPE_CMC);
1660 ia64_log_init(SAL_INFO_TYPE_CPE);
1663 printk(KERN_INFO "MCA related initialization done\n");
1667 * ia64_mca_late_init
1669 * Opportunity to setup things that require initialization later
1670 * than ia64_mca_init. Setup a timer to poll for CPEs if the
1671 * platform doesn't support an interrupt driven mechanism.
1677 ia64_mca_late_init(void)
1682 /* Setup the CMCI/P vector and handler */
1683 init_timer(&cmc_poll_timer);
1684 cmc_poll_timer.function = ia64_mca_cmc_poll;
1686 /* Unmask/enable the vector */
1687 cmc_polling_enabled = 0;
1688 schedule_work(&cmc_enable_work);
1690 IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__);
1693 /* Setup the CPEI/P vector and handler */
1694 cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
1695 init_timer(&cpe_poll_timer);
1696 cpe_poll_timer.function = ia64_mca_cpe_poll;
1702 if (cpe_vector >= 0) {
1703 /* If platform supports CPEI, enable the irq. */
1704 cpe_poll_enabled = 0;
1705 for (irq = 0; irq < NR_IRQS; ++irq)
1706 if (irq_to_vector(irq) == cpe_vector) {
1707 desc = irq_descp(irq);
1708 desc->status |= IRQ_PER_CPU;
1709 setup_irq(irq, &mca_cpe_irqaction);
1712 ia64_mca_register_cpev(cpe_vector);
1713 IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", __FUNCTION__);
1715 /* If platform doesn't support CPEI, get the timer going. */
1716 if (cpe_poll_enabled) {
1717 ia64_mca_cpe_poll(0UL);
1718 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__);
1727 device_initcall(ia64_mca_late_init);