Pull platform-drivers into test branch
[linux-2.6] / arch / arm / mach-sa1100 / jornada720.c
1 /*
2  * linux/arch/arm/mach-sa1100/jornada720.c
3  *
4  * HP Jornada720 init code
5  *
6  * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
7  *  Copyright (C) 2005 Michael Gernoth <michael@gernoth.net>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  *
13  */
14
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/tty.h>
18 #include <linux/delay.h>
19 #include <linux/platform_device.h>
20 #include <linux/ioport.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/partitions.h>
23 #include <video/s1d13xxxfb.h>
24
25 #include <asm/hardware.h>
26 #include <asm/hardware/sa1111.h>
27 #include <asm/irq.h>
28 #include <asm/mach-types.h>
29 #include <asm/setup.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/flash.h>
32 #include <asm/mach/map.h>
33 #include <asm/mach/serial_sa1100.h>
34
35 #include "generic.h"
36
37 /*
38  * HP Documentation referred in this file:
39  * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt
40  */
41
42 /* line 110 of HP's doc */
43 #define TUCR_VAL        0x20000400
44
45 /* memory space (line 52 of HP's doc) */
46 #define SA1111REGSTART  0x40000000
47 #define SA1111REGLEN    0x00001fff
48 #define EPSONREGSTART   0x48000000
49 #define EPSONREGLEN     0x00100000
50 #define EPSONFBSTART    0x48200000
51 /* 512kB framebuffer */
52 #define EPSONFBLEN      512*1024
53
54 static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
55         /* line 344 of HP's doc */
56         {0x0001,0x00},  // Miscellaneous Register
57         {0x01FC,0x00},  // Display Mode Register
58         {0x0004,0x00},  // General IO Pins Configuration Register 0
59         {0x0005,0x00},  // General IO Pins Configuration Register 1
60         {0x0008,0x00},  // General IO Pins Control Register 0
61         {0x0009,0x00},  // General IO Pins Control Register 1
62         {0x0010,0x01},  // Memory Clock Configuration Register
63         {0x0014,0x11},  // LCD Pixel Clock Configuration Register
64         {0x0018,0x01},  // CRT/TV Pixel Clock Configuration Register
65         {0x001C,0x01},  // MediaPlug Clock Configuration Register
66         {0x001E,0x01},  // CPU To Memory Wait State Select Register
67         {0x0020,0x00},  // Memory Configuration Register
68         {0x0021,0x45},  // DRAM Refresh Rate Register
69         {0x002A,0x01},  // DRAM Timings Control Register 0
70         {0x002B,0x03},  // DRAM Timings Control Register 1
71         {0x0030,0x1c},  // Panel Type Register
72         {0x0031,0x00},  // MOD Rate Register
73         {0x0032,0x4F},  // LCD Horizontal Display Width Register
74         {0x0034,0x07},  // LCD Horizontal Non-Display Period Register
75         {0x0035,0x01},  // TFT FPLINE Start Position Register
76         {0x0036,0x0B},  // TFT FPLINE Pulse Width Register
77         {0x0038,0xEF},  // LCD Vertical Display Height Register 0
78         {0x0039,0x00},  // LCD Vertical Display Height Register 1
79         {0x003A,0x13},  // LCD Vertical Non-Display Period Register
80         {0x003B,0x0B},  // TFT FPFRAME Start Position Register
81         {0x003C,0x01},  // TFT FPFRAME Pulse Width Register
82         {0x0040,0x05},  // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
83         {0x0041,0x00},  // LCD Miscellaneous Register
84         {0x0042,0x00},  // LCD Display Start Address Register 0
85         {0x0043,0x00},  // LCD Display Start Address Register 1
86         {0x0044,0x00},  // LCD Display Start Address Register 2
87         {0x0046,0x80},  // LCD Memory Address Offset Register 0
88         {0x0047,0x02},  // LCD Memory Address Offset Register 1
89         {0x0048,0x00},  // LCD Pixel Panning Register
90         {0x004A,0x00},  // LCD Display FIFO High Threshold Control Register
91         {0x004B,0x00},  // LCD Display FIFO Low Threshold Control Register
92         {0x0050,0x4F},  // CRT/TV Horizontal Display Width Register
93         {0x0052,0x13},  // CRT/TV Horizontal Non-Display Period Register
94         {0x0053,0x01},  // CRT/TV HRTC Start Position Register
95         {0x0054,0x0B},  // CRT/TV HRTC Pulse Width Register
96         {0x0056,0xDF},  // CRT/TV Vertical Display Height Register 0
97         {0x0057,0x01},  // CRT/TV Vertical Display Height Register 1
98         {0x0058,0x2B},  // CRT/TV Vertical Non-Display Period Register
99         {0x0059,0x09},  // CRT/TV VRTC Start Position Register
100         {0x005A,0x01},  // CRT/TV VRTC Pulse Width Register
101         {0x005B,0x10},  // TV Output Control Register
102         {0x0060,0x03},  // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
103         {0x0062,0x00},  // CRT/TV Display Start Address Register 0
104         {0x0063,0x00},  // CRT/TV Display Start Address Register 1
105         {0x0064,0x00},  // CRT/TV Display Start Address Register 2
106         {0x0066,0x40},  // CRT/TV Memory Address Offset Register 0
107         {0x0067,0x01},  // CRT/TV Memory Address Offset Register 1
108         {0x0068,0x00},  // CRT/TV Pixel Panning Register
109         {0x006A,0x00},  // CRT/TV Display FIFO High Threshold Control Register
110         {0x006B,0x00},  // CRT/TV Display FIFO Low Threshold Control Register
111         {0x0070,0x00},  // LCD Ink/Cursor Control Register
112         {0x0071,0x01},  // LCD Ink/Cursor Start Address Register
113         {0x0072,0x00},  // LCD Cursor X Position Register 0
114         {0x0073,0x00},  // LCD Cursor X Position Register 1
115         {0x0074,0x00},  // LCD Cursor Y Position Register 0
116         {0x0075,0x00},  // LCD Cursor Y Position Register 1
117         {0x0076,0x00},  // LCD Ink/Cursor Blue Color 0 Register
118         {0x0077,0x00},  // LCD Ink/Cursor Green Color 0 Register
119         {0x0078,0x00},  // LCD Ink/Cursor Red Color 0 Register
120         {0x007A,0x1F},  // LCD Ink/Cursor Blue Color 1 Register
121         {0x007B,0x3F},  // LCD Ink/Cursor Green Color 1 Register
122         {0x007C,0x1F},  // LCD Ink/Cursor Red Color 1 Register
123         {0x007E,0x00},  // LCD Ink/Cursor FIFO Threshold Register
124         {0x0080,0x00},  // CRT/TV Ink/Cursor Control Register
125         {0x0081,0x01},  // CRT/TV Ink/Cursor Start Address Register
126         {0x0082,0x00},  // CRT/TV Cursor X Position Register 0
127         {0x0083,0x00},  // CRT/TV Cursor X Position Register 1
128         {0x0084,0x00},  // CRT/TV Cursor Y Position Register 0
129         {0x0085,0x00},  // CRT/TV Cursor Y Position Register 1
130         {0x0086,0x00},  // CRT/TV Ink/Cursor Blue Color 0 Register
131         {0x0087,0x00},  // CRT/TV Ink/Cursor Green Color 0 Register
132         {0x0088,0x00},  // CRT/TV Ink/Cursor Red Color 0 Register
133         {0x008A,0x1F},  // CRT/TV Ink/Cursor Blue Color 1 Register
134         {0x008B,0x3F},  // CRT/TV Ink/Cursor Green Color 1 Register
135         {0x008C,0x1F},  // CRT/TV Ink/Cursor Red Color 1 Register
136         {0x008E,0x00},  // CRT/TV Ink/Cursor FIFO Threshold Register
137         {0x0100,0x00},  // BitBlt Control Register 0
138         {0x0101,0x00},  // BitBlt Control Register 1
139         {0x0102,0x00},  // BitBlt ROP Code/Color Expansion Register
140         {0x0103,0x00},  // BitBlt Operation Register
141         {0x0104,0x00},  // BitBlt Source Start Address Register 0
142         {0x0105,0x00},  // BitBlt Source Start Address Register 1
143         {0x0106,0x00},  // BitBlt Source Start Address Register 2
144         {0x0108,0x00},  // BitBlt Destination Start Address Register 0
145         {0x0109,0x00},  // BitBlt Destination Start Address Register 1
146         {0x010A,0x00},  // BitBlt Destination Start Address Register 2
147         {0x010C,0x00},  // BitBlt Memory Address Offset Register 0
148         {0x010D,0x00},  // BitBlt Memory Address Offset Register 1
149         {0x0110,0x00},  // BitBlt Width Register 0
150         {0x0111,0x00},  // BitBlt Width Register 1
151         {0x0112,0x00},  // BitBlt Height Register 0
152         {0x0113,0x00},  // BitBlt Height Register 1
153         {0x0114,0x00},  // BitBlt Background Color Register 0
154         {0x0115,0x00},  // BitBlt Background Color Register 1
155         {0x0118,0x00},  // BitBlt Foreground Color Register 0
156         {0x0119,0x00},  // BitBlt Foreground Color Register 1
157         {0x01E0,0x00},  // Look-Up Table Mode Register
158         {0x01E2,0x00},  // Look-Up Table Address Register
159         /* not sure, wouldn't like to mess with the driver */
160         {0x01E4,0x00},  // Look-Up Table Data Register
161         /* jornada doc says 0x00, but I trust the driver */
162         {0x01F0,0x10},  // Power Save Configuration Register
163         {0x01F1,0x00},  // Power Save Status Register
164         {0x01F4,0x00},  // CPU-to-Memory Access Watchdog Timer Register
165         {0x01FC,0x01},  // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
166 };
167
168 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
169         .initregs               = s1d13xxxfb_initregs,
170         .initregssize           = ARRAY_SIZE(s1d13xxxfb_initregs),
171         .platform_init_video    = NULL
172 };
173
174 static struct resource s1d13xxxfb_resources[] = {
175         [0] = {
176                 .start  = EPSONFBSTART,
177                 .end    = EPSONFBSTART + EPSONFBLEN,
178                 .flags  = IORESOURCE_MEM,
179         },
180         [1] = {
181                 .start  = EPSONREGSTART,
182                 .end    = EPSONREGSTART + EPSONREGLEN,
183                 .flags  = IORESOURCE_MEM,
184         }
185 };
186
187 static struct platform_device s1d13xxxfb_device = {
188         .name           = S1D_DEVICENAME,
189         .id             = 0,
190         .dev            = {
191                 .platform_data  = &s1d13xxxfb_data,
192         },
193         .num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
194         .resource       = s1d13xxxfb_resources,
195 };
196
197 static struct resource sa1111_resources[] = {
198         [0] = {
199                 .start          = SA1111REGSTART,
200                 .end            = SA1111REGSTART + SA1111REGLEN,
201                 .flags          = IORESOURCE_MEM,
202         },
203         [1] = {
204                 .start          = IRQ_GPIO1,
205                 .end            = IRQ_GPIO1,
206                 .flags          = IORESOURCE_IRQ,
207         },
208 };
209
210 static u64 sa1111_dmamask = 0xffffffffUL;
211
212 static struct platform_device sa1111_device = {
213         .name           = "sa1111",
214         .id             = 0,
215         .dev            = {
216                 .dma_mask = &sa1111_dmamask,
217                 .coherent_dma_mask = 0xffffffff,
218         },
219         .num_resources  = ARRAY_SIZE(sa1111_resources),
220         .resource       = sa1111_resources,
221 };
222
223 static struct platform_device jornada720_mcu_device = {
224         .name           = "jornada720_mcu",
225         .id             = -1,
226 };
227
228 static struct platform_device *devices[] __initdata = {
229         &sa1111_device,
230         &jornada720_mcu_device,
231         &s1d13xxxfb_device,
232 };
233
234 /* a stub for now, we theoretically cannot suspend without a flashboard */
235 int pm_suspend(suspend_state_t state)
236 {
237         return -1;
238 }
239
240 static int __init jornada720_init(void)
241 {
242         int ret = -ENODEV;
243
244         if (machine_is_jornada720()) {
245                 GPDR |= GPIO_GPIO20;
246                 /* oscillator setup (line 116 of HP's doc) */
247                 TUCR = TUCR_VAL;
248                 /* resetting SA1111 (line 118 of HP's doc) */
249                 GPSR = GPIO_GPIO20;
250                 udelay(1);
251                 GPCR = GPIO_GPIO20;
252                 udelay(1);
253                 GPSR = GPIO_GPIO20;
254                 udelay(20);
255
256                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
257         }
258         return ret;
259 }
260
261 arch_initcall(jornada720_init);
262
263 static struct map_desc jornada720_io_desc[] __initdata = {
264         {       /* Epson registers */
265                 .virtual        = 0xf0000000,
266                 .pfn            = __phys_to_pfn(EPSONREGSTART),
267                 .length         = EPSONREGLEN,
268                 .type           = MT_DEVICE
269         }, {    /* Epson frame buffer */
270                 .virtual        = 0xf1000000,
271                 .pfn            = __phys_to_pfn(EPSONFBSTART),
272                 .length         = EPSONFBLEN,
273                 .type           = MT_DEVICE
274         }, {    /* SA-1111 */
275                 .virtual        = 0xf4000000,
276                 .pfn            = __phys_to_pfn(SA1111REGSTART),
277                 .length         = SA1111REGLEN,
278                 .type           = MT_DEVICE
279         }
280 };
281
282 static void __init jornada720_map_io(void)
283 {
284         sa1100_map_io();
285         iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc));
286
287         sa1100_register_uart(0, 3);
288         sa1100_register_uart(1, 1);
289 }
290
291 static struct mtd_partition jornada720_partitions[] = {
292         {
293                 .name           = "JORNADA720 boot firmware",
294                 .size           = 0x00040000,
295                 .offset         = 0,
296                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
297         }, {
298                 .name           = "JORNADA720 kernel",
299                 .size           = 0x000c0000,
300                 .offset         = 0x00040000,
301         }, {
302                 .name           = "JORNADA720 params",
303                 .size           = 0x00040000,
304                 .offset         = 0x00100000,
305         }, {
306                 .name           = "JORNADA720 initrd",
307                 .size           = 0x00100000,
308                 .offset         = 0x00140000,
309         }, {
310                 .name           = "JORNADA720 root cramfs",
311                 .size           = 0x00300000,
312                 .offset         = 0x00240000,
313         }, {
314                 .name           = "JORNADA720 usr cramfs",
315                 .size           = 0x00800000,
316                 .offset         = 0x00540000,
317         }, {
318                 .name           = "JORNADA720 usr local",
319                 .size           = 0, /* will expand to the end of the flash */
320                 .offset         = 0x00d00000,
321         }
322 };
323
324 static void jornada720_set_vpp(int vpp)
325 {
326         if (vpp)
327                 /* enabling flash write (line 470 of HP's doc) */
328                 PPSR |= PPC_LDD7;
329         else
330                 /* disabling flash write (line 470 of HP's doc) */
331                 PPSR &= ~PPC_LDD7;
332         PPDR |= PPC_LDD7;
333 }
334
335 static struct flash_platform_data jornada720_flash_data = {
336         .map_name       = "cfi_probe",
337         .set_vpp        = jornada720_set_vpp,
338         .parts          = jornada720_partitions,
339         .nr_parts       = ARRAY_SIZE(jornada720_partitions),
340 };
341
342 static struct resource jornada720_flash_resource = {
343         .start          = SA1100_CS0_PHYS,
344         .end            = SA1100_CS0_PHYS + SZ_32M - 1,
345         .flags          = IORESOURCE_MEM,
346 };
347
348 static void __init jornada720_mach_init(void)
349 {
350         sa11x0_set_flash_data(&jornada720_flash_data, &jornada720_flash_resource, 1);
351 }
352
353 MACHINE_START(JORNADA720, "HP Jornada 720")
354         /* Maintainer: Michael Gernoth <michael@gernoth.net> */
355         .phys_io        = 0x80000000,
356         .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
357         .boot_params    = 0xc0000100,
358         .map_io         = jornada720_map_io,
359         .init_irq       = sa1100_init_irq,
360         .timer          = &sa1100_timer,
361         .init_machine   = jornada720_mach_init,
362 MACHINE_END