git.oblomov.eu Git - linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43
  44 #include <asm/system.h>
  45 #include <asm/io.h>
  46 #include <asm/byteorder.h>
  47 #include <asm/uaccess.h>
  48
  49 #ifdef CONFIG_SPARC64
  50 #include <asm/idprom.h>
  51 #include <asm/oplib.h>
  52 #include <asm/pbm.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #ifdef NETIF_F_TSO
  62 #define TG3_TSO_SUPPORT 1
  63 #else
  64 #define TG3_TSO_SUPPORT 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.70"
  72 #define DRV_MODULE_RELDATE      "December 1, 2006"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                    TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 127
 128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 130
 131 /* minimum number of free TX descriptors required to wake up TX process */
 132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 133
 134 /* number of ETHTOOL_GSTATS u64's */
 135 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 136
 137 #define TG3_NUM_TEST            6
 138
 139 static char version[] __devinitdata =
 140         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 141
 142 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 143 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 144 MODULE_LICENSE("GPL");
 145 MODULE_VERSION(DRV_MODULE_VERSION);
 146
 147 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 148 module_param(tg3_debug, int, 0);
 149 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 150
 151 static struct pci_device_id tg3_pci_tbl[] = {
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 212         {}
 213 };
 214
 215 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 216
 217 static const struct {
 218         const char string[ETH_GSTRING_LEN];
 219 } ethtool_stats_keys[TG3_NUM_STATS] = {
 220         { "rx_octets" },
 221         { "rx_fragments" },
 222         { "rx_ucast_packets" },
 223         { "rx_mcast_packets" },
 224         { "rx_bcast_packets" },
 225         { "rx_fcs_errors" },
 226         { "rx_align_errors" },
 227         { "rx_xon_pause_rcvd" },
 228         { "rx_xoff_pause_rcvd" },
 229         { "rx_mac_ctrl_rcvd" },
 230         { "rx_xoff_entered" },
 231         { "rx_frame_too_long_errors" },
 232         { "rx_jabbers" },
 233         { "rx_undersize_packets" },
 234         { "rx_in_length_errors" },
 235         { "rx_out_length_errors" },
 236         { "rx_64_or_less_octet_packets" },
 237         { "rx_65_to_127_octet_packets" },
 238         { "rx_128_to_255_octet_packets" },
 239         { "rx_256_to_511_octet_packets" },
 240         { "rx_512_to_1023_octet_packets" },
 241         { "rx_1024_to_1522_octet_packets" },
 242         { "rx_1523_to_2047_octet_packets" },
 243         { "rx_2048_to_4095_octet_packets" },
 244         { "rx_4096_to_8191_octet_packets" },
 245         { "rx_8192_to_9022_octet_packets" },
 246
 247         { "tx_octets" },
 248         { "tx_collisions" },
 249
 250         { "tx_xon_sent" },
 251         { "tx_xoff_sent" },
 252         { "tx_flow_control" },
 253         { "tx_mac_errors" },
 254         { "tx_single_collisions" },
 255         { "tx_mult_collisions" },
 256         { "tx_deferred" },
 257         { "tx_excessive_collisions" },
 258         { "tx_late_collisions" },
 259         { "tx_collide_2times" },
 260         { "tx_collide_3times" },
 261         { "tx_collide_4times" },
 262         { "tx_collide_5times" },
 263         { "tx_collide_6times" },
 264         { "tx_collide_7times" },
 265         { "tx_collide_8times" },
 266         { "tx_collide_9times" },
 267         { "tx_collide_10times" },
 268         { "tx_collide_11times" },
 269         { "tx_collide_12times" },
 270         { "tx_collide_13times" },
 271         { "tx_collide_14times" },
 272         { "tx_collide_15times" },
 273         { "tx_ucast_packets" },
 274         { "tx_mcast_packets" },
 275         { "tx_bcast_packets" },
 276         { "tx_carrier_sense_errors" },
 277         { "tx_discards" },
 278         { "tx_errors" },
 279
 280         { "dma_writeq_full" },
 281         { "dma_write_prioq_full" },
 282         { "rxbds_empty" },
 283         { "rx_discards" },
 284         { "rx_errors" },
 285         { "rx_threshold_hit" },
 286
 287         { "dma_readq_full" },
 288         { "dma_read_prioq_full" },
 289         { "tx_comp_queue_full" },
 290
 291         { "ring_set_send_prod_index" },
 292         { "ring_status_update" },
 293         { "nic_irqs" },
 294         { "nic_avoided_irqs" },
 295         { "nic_tx_threshold_hit" }
 296 };
 297
 298 static const struct {
 299         const char string[ETH_GSTRING_LEN];
 300 } ethtool_test_keys[TG3_NUM_TEST] = {
 301         { "nvram test     (online) " },
 302         { "link test      (online) " },
 303         { "register test  (offline)" },
 304         { "memory test    (offline)" },
 305         { "loopback test  (offline)" },
 306         { "interrupt test (offline)" },
 307 };
 308
 309 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 310 {
 311         writel(val, tp->regs + off);
 312 }
 313
 314 static u32 tg3_read32(struct tg3 *tp, u32 off)
 315 {
 316         return (readl(tp->regs + off));
 317 }
 318
 319 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 320 {
 321         unsigned long flags;
 322
 323         spin_lock_irqsave(&tp->indirect_lock, flags);
 324         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 325         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 326         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 327 }
 328
 329 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 330 {
 331         writel(val, tp->regs + off);
 332         readl(tp->regs + off);
 333 }
 334
 335 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 336 {
 337         unsigned long flags;
 338         u32 val;
 339
 340         spin_lock_irqsave(&tp->indirect_lock, flags);
 341         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 342         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 343         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 344         return val;
 345 }
 346
 347 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 348 {
 349         unsigned long flags;
 350
 351         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 352                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 353                                        TG3_64BIT_REG_LOW, val);
 354                 return;
 355         }
 356         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 357                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 358                                        TG3_64BIT_REG_LOW, val);
 359                 return;
 360         }
 361
 362         spin_lock_irqsave(&tp->indirect_lock, flags);
 363         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 364         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 365         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 366
 367         /* In indirect mode when disabling interrupts, we also need
 368          * to clear the interrupt bit in the GRC local ctrl register.
 369          */
 370         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 371             (val == 0x1)) {
 372                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 373                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 374         }
 375 }
 376
 377 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 378 {
 379         unsigned long flags;
 380         u32 val;
 381
 382         spin_lock_irqsave(&tp->indirect_lock, flags);
 383         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 384         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 385         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 386         return val;
 387 }
 388
 389 /* usec_wait specifies the wait time in usec when writing to certain registers
 390  * where it is unsafe to read back the register without some delay.
 391  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 392  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 393  */
 394 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 395 {
 396         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 397             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 398                 /* Non-posted methods */
 399                 tp->write32(tp, off, val);
 400         else {
 401                 /* Posted method */
 402                 tg3_write32(tp, off, val);
 403                 if (usec_wait)
 404                         udelay(usec_wait);
 405                 tp->read32(tp, off);
 406         }
 407         /* Wait again after the read for the posted method to guarantee that
 408          * the wait time is met.
 409          */
 410         if (usec_wait)
 411                 udelay(usec_wait);
 412 }
 413
 414 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 415 {
 416         tp->write32_mbox(tp, off, val);
 417         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 418             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 419                 tp->read32_mbox(tp, off);
 420 }
 421
 422 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 423 {
 424         void __iomem *mbox = tp->regs + off;
 425         writel(val, mbox);
 426         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 427                 writel(val, mbox);
 428         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 429                 readl(mbox);
 430 }
 431
 432 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 433 {
 434         return (readl(tp->regs + off + GRCMBOX_BASE));
 435 }
 436
 437 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 438 {
 439         writel(val, tp->regs + off + GRCMBOX_BASE);
 440 }
 441
 442 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 443 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 444 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 445 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 446 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 447
 448 #define tw32(reg,val)           tp->write32(tp, reg, val)
 449 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 450 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 451 #define tr32(reg)               tp->read32(tp, reg)
 452
 453 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 454 {
 455         unsigned long flags;
 456
 457         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 458             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 459                 return;
 460
 461         spin_lock_irqsave(&tp->indirect_lock, flags);
 462         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 464                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 465
 466                 /* Always leave this as zero. */
 467                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 468         } else {
 469                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 470                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 471
 472                 /* Always leave this as zero. */
 473                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 474         }
 475         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 476 }
 477
 478 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 479 {
 480         unsigned long flags;
 481
 482         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 483             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 484                 *val = 0;
 485                 return;
 486         }
 487
 488         spin_lock_irqsave(&tp->indirect_lock, flags);
 489         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 490                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 491                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 492
 493                 /* Always leave this as zero. */
 494                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 495         } else {
 496                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 497                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 498
 499                 /* Always leave this as zero. */
 500                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 501         }
 502         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 503 }
 504
 505 static void tg3_disable_ints(struct tg3 *tp)
 506 {
 507         tw32(TG3PCI_MISC_HOST_CTRL,
 508              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 509         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 510 }
 511
 512 static inline void tg3_cond_int(struct tg3 *tp)
 513 {
 514         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 515             (tp->hw_status->status & SD_STATUS_UPDATED))
 516                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 517         else
 518                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 519                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 520 }
 521
 522 static void tg3_enable_ints(struct tg3 *tp)
 523 {
 524         tp->irq_sync = 0;
 525         wmb();
 526
 527         tw32(TG3PCI_MISC_HOST_CTRL,
 528              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 529         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 530                        (tp->last_tag << 24));
 531         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 532                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 533                                (tp->last_tag << 24));
 534         tg3_cond_int(tp);
 535 }
 536
 537 static inline unsigned int tg3_has_work(struct tg3 *tp)
 538 {
 539         struct tg3_hw_status *sblk = tp->hw_status;
 540         unsigned int work_exists = 0;
 541
 542         /* check for phy events */
 543         if (!(tp->tg3_flags &
 544               (TG3_FLAG_USE_LINKCHG_REG |
 545                TG3_FLAG_POLL_SERDES))) {
 546                 if (sblk->status & SD_STATUS_LINK_CHG)
 547                         work_exists = 1;
 548         }
 549         /* check for RX/TX work to do */
 550         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 551             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 552                 work_exists = 1;
 553
 554         return work_exists;
 555 }
 556
 557 /* tg3_restart_ints
 558  *  similar to tg3_enable_ints, but it accurately determines whether there
 559  *  is new work pending and can return without flushing the PIO write
 560  *  which reenables interrupts
 561  */
 562 static void tg3_restart_ints(struct tg3 *tp)
 563 {
 564         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 565                      tp->last_tag << 24);
 566         mmiowb();
 567
 568         /* When doing tagged status, this work check is unnecessary.
 569          * The last_tag we write above tells the chip which piece of
 570          * work we've completed.
 571          */
 572         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 573             tg3_has_work(tp))
 574                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 575                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 576 }
 577
 578 static inline void tg3_netif_stop(struct tg3 *tp)
 579 {
 580         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 581         netif_poll_disable(tp->dev);
 582         netif_tx_disable(tp->dev);
 583 }
 584
 585 static inline void tg3_netif_start(struct tg3 *tp)
 586 {
 587         netif_wake_queue(tp->dev);
 588         /* NOTE: unconditional netif_wake_queue is only appropriate
 589          * so long as all callers are assured to have free tx slots
 590          * (such as after tg3_init_hw)
 591          */
 592         netif_poll_enable(tp->dev);
 593         tp->hw_status->status |= SD_STATUS_UPDATED;
 594         tg3_enable_ints(tp);
 595 }
 596
 597 static void tg3_switch_clocks(struct tg3 *tp)
 598 {
 599         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 600         u32 orig_clock_ctrl;
 601
 602         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 603                 return;
 604
 605         orig_clock_ctrl = clock_ctrl;
 606         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 607                        CLOCK_CTRL_CLKRUN_OENABLE |
 608                        0x1f);
 609         tp->pci_clock_ctrl = clock_ctrl;
 610
 611         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 612                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 613                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 614                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 615                 }
 616         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 617                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 618                             clock_ctrl |
 619                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 620                             40);
 621                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 622                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 623                             40);
 624         }
 625         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 626 }
 627
 628 #define PHY_BUSY_LOOPS  5000
 629
 630 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 631 {
 632         u32 frame_val;
 633         unsigned int loops;
 634         int ret;
 635
 636         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 637                 tw32_f(MAC_MI_MODE,
 638                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 639                 udelay(80);
 640         }
 641
 642         *val = 0x0;
 643
 644         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 645                       MI_COM_PHY_ADDR_MASK);
 646         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 647                       MI_COM_REG_ADDR_MASK);
 648         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 649
 650         tw32_f(MAC_MI_COM, frame_val);
 651
 652         loops = PHY_BUSY_LOOPS;
 653         while (loops != 0) {
 654                 udelay(10);
 655                 frame_val = tr32(MAC_MI_COM);
 656
 657                 if ((frame_val & MI_COM_BUSY) == 0) {
 658                         udelay(5);
 659                         frame_val = tr32(MAC_MI_COM);
 660                         break;
 661                 }
 662                 loops -= 1;
 663         }
 664
 665         ret = -EBUSY;
 666         if (loops != 0) {
 667                 *val = frame_val & MI_COM_DATA_MASK;
 668                 ret = 0;
 669         }
 670
 671         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 672                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 673                 udelay(80);
 674         }
 675
 676         return ret;
 677 }
 678
 679 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 680 {
 681         u32 frame_val;
 682         unsigned int loops;
 683         int ret;
 684
 685         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 686             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 687                 return 0;
 688
 689         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 690                 tw32_f(MAC_MI_MODE,
 691                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 692                 udelay(80);
 693         }
 694
 695         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 696                       MI_COM_PHY_ADDR_MASK);
 697         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 698                       MI_COM_REG_ADDR_MASK);
 699         frame_val |= (val & MI_COM_DATA_MASK);
 700         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 701
 702         tw32_f(MAC_MI_COM, frame_val);
 703
 704         loops = PHY_BUSY_LOOPS;
 705         while (loops != 0) {
 706                 udelay(10);
 707                 frame_val = tr32(MAC_MI_COM);
 708                 if ((frame_val & MI_COM_BUSY) == 0) {
 709                         udelay(5);
 710                         frame_val = tr32(MAC_MI_COM);
 711                         break;
 712                 }
 713                 loops -= 1;
 714         }
 715
 716         ret = -EBUSY;
 717         if (loops != 0)
 718                 ret = 0;
 719
 720         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 721                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 722                 udelay(80);
 723         }
 724
 725         return ret;
 726 }
 727
 728 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 729 {
 730         u32 val;
 731
 732         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 733                 return;
 734
 735         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 736             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 737                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 738                              (val | (1 << 15) | (1 << 4)));
 739 }
 740
 741 static int tg3_bmcr_reset(struct tg3 *tp)
 742 {
 743         u32 phy_control;
 744         int limit, err;
 745
 746         /* OK, reset it, and poll the BMCR_RESET bit until it
 747          * clears or we time out.
 748          */
 749         phy_control = BMCR_RESET;
 750         err = tg3_writephy(tp, MII_BMCR, phy_control);
 751         if (err != 0)
 752                 return -EBUSY;
 753
 754         limit = 5000;
 755         while (limit--) {
 756                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 757                 if (err != 0)
 758                         return -EBUSY;
 759
 760                 if ((phy_control & BMCR_RESET) == 0) {
 761                         udelay(40);
 762                         break;
 763                 }
 764                 udelay(10);
 765         }
 766         if (limit <= 0)
 767                 return -EBUSY;
 768
 769         return 0;
 770 }
 771
 772 static int tg3_wait_macro_done(struct tg3 *tp)
 773 {
 774         int limit = 100;
 775
 776         while (limit--) {
 777                 u32 tmp32;
 778
 779                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 780                         if ((tmp32 & 0x1000) == 0)
 781                                 break;
 782                 }
 783         }
 784         if (limit <= 0)
 785                 return -EBUSY;
 786
 787         return 0;
 788 }
 789
 790 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 791 {
 792         static const u32 test_pat[4][6] = {
 793         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 794         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 795         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 796         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 797         };
 798         int chan;
 799
 800         for (chan = 0; chan < 4; chan++) {
 801                 int i;
 802
 803                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 804                              (chan * 0x2000) | 0x0200);
 805                 tg3_writephy(tp, 0x16, 0x0002);
 806
 807                 for (i = 0; i < 6; i++)
 808                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 809                                      test_pat[chan][i]);
 810
 811                 tg3_writephy(tp, 0x16, 0x0202);
 812                 if (tg3_wait_macro_done(tp)) {
 813                         *resetp = 1;
 814                         return -EBUSY;
 815                 }
 816
 817                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 818                              (chan * 0x2000) | 0x0200);
 819                 tg3_writephy(tp, 0x16, 0x0082);
 820                 if (tg3_wait_macro_done(tp)) {
 821                         *resetp = 1;
 822                         return -EBUSY;
 823                 }
 824
 825                 tg3_writephy(tp, 0x16, 0x0802);
 826                 if (tg3_wait_macro_done(tp)) {
 827                         *resetp = 1;
 828                         return -EBUSY;
 829                 }
 830
 831                 for (i = 0; i < 6; i += 2) {
 832                         u32 low, high;
 833
 834                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 835                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 836                             tg3_wait_macro_done(tp)) {
 837                                 *resetp = 1;
 838                                 return -EBUSY;
 839                         }
 840                         low &= 0x7fff;
 841                         high &= 0x000f;
 842                         if (low != test_pat[chan][i] ||
 843                             high != test_pat[chan][i+1]) {
 844                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 845                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 846                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 847
 848                                 return -EBUSY;
 849                         }
 850                 }
 851         }
 852
 853         return 0;
 854 }
 855
 856 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 857 {
 858         int chan;
 859
 860         for (chan = 0; chan < 4; chan++) {
 861                 int i;
 862
 863                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 864                              (chan * 0x2000) | 0x0200);
 865                 tg3_writephy(tp, 0x16, 0x0002);
 866                 for (i = 0; i < 6; i++)
 867                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 868                 tg3_writephy(tp, 0x16, 0x0202);
 869                 if (tg3_wait_macro_done(tp))
 870                         return -EBUSY;
 871         }
 872
 873         return 0;
 874 }
 875
 876 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 877 {
 878         u32 reg32, phy9_orig;
 879         int retries, do_phy_reset, err;
 880
 881         retries = 10;
 882         do_phy_reset = 1;
 883         do {
 884                 if (do_phy_reset) {
 885                         err = tg3_bmcr_reset(tp);
 886                         if (err)
 887                                 return err;
 888                         do_phy_reset = 0;
 889                 }
 890
 891                 /* Disable transmitter and interrupt.  */
 892                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 893                         continue;
 894
 895                 reg32 |= 0x3000;
 896                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 897
 898                 /* Set full-duplex, 1000 mbps.  */
 899                 tg3_writephy(tp, MII_BMCR,
 900                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 901
 902                 /* Set to master mode.  */
 903                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 904                         continue;
 905
 906                 tg3_writephy(tp, MII_TG3_CTRL,
 907                              (MII_TG3_CTRL_AS_MASTER |
 908                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 909
 910                 /* Enable SM_DSP_CLOCK and 6dB.  */
 911                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 912
 913                 /* Block the PHY control access.  */
 914                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 915                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 916
 917                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 918                 if (!err)
 919                         break;
 920         } while (--retries);
 921
 922         err = tg3_phy_reset_chanpat(tp);
 923         if (err)
 924                 return err;
 925
 926         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 927         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 928
 929         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 930         tg3_writephy(tp, 0x16, 0x0000);
 931
 932         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 933             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 934                 /* Set Extended packet length bit for jumbo frames */
 935                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 936         }
 937         else {
 938                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 939         }
 940
 941         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 942
 943         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 944                 reg32 &= ~0x3000;
 945                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 946         } else if (!err)
 947                 err = -EBUSY;
 948
 949         return err;
 950 }
 951
 952 static void tg3_link_report(struct tg3 *);
 953
 954 /* This will reset the tigon3 PHY if there is no valid
 955  * link unless the FORCE argument is non-zero.
 956  */
 957 static int tg3_phy_reset(struct tg3 *tp)
 958 {
 959         u32 phy_status;
 960         int err;
 961
 962         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 963         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 964         if (err != 0)
 965                 return -EBUSY;
 966
 967         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 968                 netif_carrier_off(tp->dev);
 969                 tg3_link_report(tp);
 970         }
 971
 972         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 973             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 974             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 975                 err = tg3_phy_reset_5703_4_5(tp);
 976                 if (err)
 977                         return err;
 978                 goto out;
 979         }
 980
 981         err = tg3_bmcr_reset(tp);
 982         if (err)
 983                 return err;
 984
 985 out:
 986         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 987                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 988                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 989                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 990                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 991                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 992                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 993         }
 994         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 995                 tg3_writephy(tp, 0x1c, 0x8d68);
 996                 tg3_writephy(tp, 0x1c, 0x8d68);
 997         }
 998         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
 999                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1000                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1001                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1002                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1003                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1004                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1005                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1006                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1007         }
1008         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1009                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1010                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1011                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1013         }
1014         /* Set Extended packet length bit (bit 14) on all chips that */
1015         /* support jumbo frames */
1016         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1017                 /* Cannot do read-modify-write on 5401 */
1018                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1019         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1020                 u32 phy_reg;
1021
1022                 /* Set bit 14 with read-modify-write to preserve other bits */
1023                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1024                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1025                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1026         }
1027
1028         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1029          * jumbo frames transmission.
1030          */
1031         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1032                 u32 phy_reg;
1033
1034                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1035                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1036                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1037         }
1038
1039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1040                 u32 phy_reg;
1041
1042                 /* adjust output voltage */
1043                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1044
1045                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1046                         u32 phy_reg2;
1047
1048                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1049                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1050                         /* Enable auto-MDIX */
1051                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1052                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1053                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1054                 }
1055         }
1056
1057         tg3_phy_set_wirespeed(tp);
1058         return 0;
1059 }
1060
1061 static void tg3_frob_aux_power(struct tg3 *tp)
1062 {
1063         struct tg3 *tp_peer = tp;
1064
1065         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1066                 return;
1067
1068         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1069             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1070                 struct net_device *dev_peer;
1071
1072                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1073                 /* remove_one() may have been run on the peer. */
1074                 if (!dev_peer)
1075                         tp_peer = tp;
1076                 else
1077                         tp_peer = netdev_priv(dev_peer);
1078         }
1079
1080         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1081             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1082             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1083             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1084                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1085                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1086                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1087                                     (GRC_LCLCTRL_GPIO_OE0 |
1088                                      GRC_LCLCTRL_GPIO_OE1 |
1089                                      GRC_LCLCTRL_GPIO_OE2 |
1090                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1091                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1092                                     100);
1093                 } else {
1094                         u32 no_gpio2;
1095                         u32 grc_local_ctrl = 0;
1096
1097                         if (tp_peer != tp &&
1098                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1099                                 return;
1100
1101                         /* Workaround to prevent overdrawing Amps. */
1102                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1103                             ASIC_REV_5714) {
1104                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1105                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1106                                             grc_local_ctrl, 100);
1107                         }
1108
1109                         /* On 5753 and variants, GPIO2 cannot be used. */
1110                         no_gpio2 = tp->nic_sram_data_cfg &
1111                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1112
1113                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1114                                          GRC_LCLCTRL_GPIO_OE1 |
1115                                          GRC_LCLCTRL_GPIO_OE2 |
1116                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1117                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1118                         if (no_gpio2) {
1119                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1120                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1121                         }
1122                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1123                                                     grc_local_ctrl, 100);
1124
1125                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1126
1127                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1128                                                     grc_local_ctrl, 100);
1129
1130                         if (!no_gpio2) {
1131                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1132                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1133                                             grc_local_ctrl, 100);
1134                         }
1135                 }
1136         } else {
1137                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1138                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1139                         if (tp_peer != tp &&
1140                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1141                                 return;
1142
1143                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1144                                     (GRC_LCLCTRL_GPIO_OE1 |
1145                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1146
1147                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1148                                     GRC_LCLCTRL_GPIO_OE1, 100);
1149
1150                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1151                                     (GRC_LCLCTRL_GPIO_OE1 |
1152                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1153                 }
1154         }
1155 }
1156
1157 static int tg3_setup_phy(struct tg3 *, int);
1158
1159 #define RESET_KIND_SHUTDOWN     0
1160 #define RESET_KIND_INIT         1
1161 #define RESET_KIND_SUSPEND      2
1162
1163 static void tg3_write_sig_post_reset(struct tg3 *, int);
1164 static int tg3_halt_cpu(struct tg3 *, u32);
1165 static int tg3_nvram_lock(struct tg3 *);
1166 static void tg3_nvram_unlock(struct tg3 *);
1167
1168 static void tg3_power_down_phy(struct tg3 *tp)
1169 {
1170         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
1171                 return;
1172
1173         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1174                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1175                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1176                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1177         }
1178
1179         /* The PHY should not be powered down on some chips because
1180          * of bugs.
1181          */
1182         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1183             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1184             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1185              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1186                 return;
1187         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1188 }
1189
1190 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1191 {
1192         u32 misc_host_ctrl;
1193         u16 power_control, power_caps;
1194         int pm = tp->pm_cap;
1195
1196         /* Make sure register accesses (indirect or otherwise)
1197          * will function correctly.
1198          */
1199         pci_write_config_dword(tp->pdev,
1200                                TG3PCI_MISC_HOST_CTRL,
1201                                tp->misc_host_ctrl);
1202
1203         pci_read_config_word(tp->pdev,
1204                              pm + PCI_PM_CTRL,
1205                              &power_control);
1206         power_control |= PCI_PM_CTRL_PME_STATUS;
1207         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1208         switch (state) {
1209         case PCI_D0:
1210                 power_control |= 0;
1211                 pci_write_config_word(tp->pdev,
1212                                       pm + PCI_PM_CTRL,
1213                                       power_control);
1214                 udelay(100);    /* Delay after power state change */
1215
1216                 /* Switch out of Vaux if it is a NIC */
1217                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1218                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1219
1220                 return 0;
1221
1222         case PCI_D1:
1223                 power_control |= 1;
1224                 break;
1225
1226         case PCI_D2:
1227                 power_control |= 2;
1228                 break;
1229
1230         case PCI_D3hot:
1231                 power_control |= 3;
1232                 break;
1233
1234         default:
1235                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1236                        "requested.\n",
1237                        tp->dev->name, state);
1238                 return -EINVAL;
1239         };
1240
1241         power_control |= PCI_PM_CTRL_PME_ENABLE;
1242
1243         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1244         tw32(TG3PCI_MISC_HOST_CTRL,
1245              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1246
1247         if (tp->link_config.phy_is_low_power == 0) {
1248                 tp->link_config.phy_is_low_power = 1;
1249                 tp->link_config.orig_speed = tp->link_config.speed;
1250                 tp->link_config.orig_duplex = tp->link_config.duplex;
1251                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1252         }
1253
1254         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1255                 tp->link_config.speed = SPEED_10;
1256                 tp->link_config.duplex = DUPLEX_HALF;
1257                 tp->link_config.autoneg = AUTONEG_ENABLE;
1258                 tg3_setup_phy(tp, 0);
1259         }
1260
1261         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1262                 u32 val;
1263
1264                 val = tr32(GRC_VCPU_EXT_CTRL);
1265                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1266         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1267                 int i;
1268                 u32 val;
1269
1270                 for (i = 0; i < 200; i++) {
1271                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1272                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1273                                 break;
1274                         msleep(1);
1275                 }
1276         }
1277         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1278                                              WOL_DRV_STATE_SHUTDOWN |
1279                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1280
1281         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1282
1283         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1284                 u32 mac_mode;
1285
1286                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1287                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1288                         udelay(40);
1289
1290                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1291                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1292                         else
1293                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1294
1295                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1296                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1297                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1298                 } else {
1299                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1300                 }
1301
1302                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1303                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1304
1305                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1306                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1307                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1308
1309                 tw32_f(MAC_MODE, mac_mode);
1310                 udelay(100);
1311
1312                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1313                 udelay(10);
1314         }
1315
1316         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1317             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1318              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1319                 u32 base_val;
1320
1321                 base_val = tp->pci_clock_ctrl;
1322                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1323                              CLOCK_CTRL_TXCLK_DISABLE);
1324
1325                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1326                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1327         } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1328                 /* do nothing */
1329         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1330                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1331                 u32 newbits1, newbits2;
1332
1333                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1334                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1335                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1336                                     CLOCK_CTRL_TXCLK_DISABLE |
1337                                     CLOCK_CTRL_ALTCLK);
1338                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1339                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1340                         newbits1 = CLOCK_CTRL_625_CORE;
1341                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1342                 } else {
1343                         newbits1 = CLOCK_CTRL_ALTCLK;
1344                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1345                 }
1346
1347                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1348                             40);
1349
1350                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1351                             40);
1352
1353                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1354                         u32 newbits3;
1355
1356                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1357                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1358                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1359                                             CLOCK_CTRL_TXCLK_DISABLE |
1360                                             CLOCK_CTRL_44MHZ_CORE);
1361                         } else {
1362                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1363                         }
1364
1365                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1366                                     tp->pci_clock_ctrl | newbits3, 40);
1367                 }
1368         }
1369
1370         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1371             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1372                 tg3_power_down_phy(tp);
1373
1374         tg3_frob_aux_power(tp);
1375
1376         /* Workaround for unstable PLL clock */
1377         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1378             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1379                 u32 val = tr32(0x7d00);
1380
1381                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1382                 tw32(0x7d00, val);
1383                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1384                         int err;
1385
1386                         err = tg3_nvram_lock(tp);
1387                         tg3_halt_cpu(tp, RX_CPU_BASE);
1388                         if (!err)
1389                                 tg3_nvram_unlock(tp);
1390                 }
1391         }
1392
1393         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1394
1395         /* Finally, set the new power state. */
1396         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1397         udelay(100);    /* Delay after power state change */
1398
1399         return 0;
1400 }
1401
1402 static void tg3_link_report(struct tg3 *tp)
1403 {
1404         if (!netif_carrier_ok(tp->dev)) {
1405                 if (netif_msg_link(tp))
1406                         printk(KERN_INFO PFX "%s: Link is down.\n",
1407                                tp->dev->name);
1408         } else if (netif_msg_link(tp)) {
1409                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1410                        tp->dev->name,
1411                        (tp->link_config.active_speed == SPEED_1000 ?
1412                         1000 :
1413                         (tp->link_config.active_speed == SPEED_100 ?
1414                          100 : 10)),
1415                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1416                         "full" : "half"));
1417
1418                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1419                        "%s for RX.\n",
1420                        tp->dev->name,
1421                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1422                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1423         }
1424 }
1425
1426 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1427 {
1428         u32 new_tg3_flags = 0;
1429         u32 old_rx_mode = tp->rx_mode;
1430         u32 old_tx_mode = tp->tx_mode;
1431
1432         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1433
1434                 /* Convert 1000BaseX flow control bits to 1000BaseT
1435                  * bits before resolving flow control.
1436                  */
1437                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1438                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1439                                        ADVERTISE_PAUSE_ASYM);
1440                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1441
1442                         if (local_adv & ADVERTISE_1000XPAUSE)
1443                                 local_adv |= ADVERTISE_PAUSE_CAP;
1444                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1445                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1446                         if (remote_adv & LPA_1000XPAUSE)
1447                                 remote_adv |= LPA_PAUSE_CAP;
1448                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1449                                 remote_adv |= LPA_PAUSE_ASYM;
1450                 }
1451
1452                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1453                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1454                                 if (remote_adv & LPA_PAUSE_CAP)
1455                                         new_tg3_flags |=
1456                                                 (TG3_FLAG_RX_PAUSE |
1457                                                 TG3_FLAG_TX_PAUSE);
1458                                 else if (remote_adv & LPA_PAUSE_ASYM)
1459                                         new_tg3_flags |=
1460                                                 (TG3_FLAG_RX_PAUSE);
1461                         } else {
1462                                 if (remote_adv & LPA_PAUSE_CAP)
1463                                         new_tg3_flags |=
1464                                                 (TG3_FLAG_RX_PAUSE |
1465                                                 TG3_FLAG_TX_PAUSE);
1466                         }
1467                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1468                         if ((remote_adv & LPA_PAUSE_CAP) &&
1469                         (remote_adv & LPA_PAUSE_ASYM))
1470                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1471                 }
1472
1473                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1474                 tp->tg3_flags |= new_tg3_flags;
1475         } else {
1476                 new_tg3_flags = tp->tg3_flags;
1477         }
1478
1479         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1480                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1481         else
1482                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1483
1484         if (old_rx_mode != tp->rx_mode) {
1485                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1486         }
1487
1488         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1489                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1490         else
1491                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1492
1493         if (old_tx_mode != tp->tx_mode) {
1494                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1495         }
1496 }
1497
1498 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1499 {
1500         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1501         case MII_TG3_AUX_STAT_10HALF:
1502                 *speed = SPEED_10;
1503                 *duplex = DUPLEX_HALF;
1504                 break;
1505
1506         case MII_TG3_AUX_STAT_10FULL:
1507                 *speed = SPEED_10;
1508                 *duplex = DUPLEX_FULL;
1509                 break;
1510
1511         case MII_TG3_AUX_STAT_100HALF:
1512                 *speed = SPEED_100;
1513                 *duplex = DUPLEX_HALF;
1514                 break;
1515
1516         case MII_TG3_AUX_STAT_100FULL:
1517                 *speed = SPEED_100;
1518                 *duplex = DUPLEX_FULL;
1519                 break;
1520
1521         case MII_TG3_AUX_STAT_1000HALF:
1522                 *speed = SPEED_1000;
1523                 *duplex = DUPLEX_HALF;
1524                 break;
1525
1526         case MII_TG3_AUX_STAT_1000FULL:
1527                 *speed = SPEED_1000;
1528                 *duplex = DUPLEX_FULL;
1529                 break;
1530
1531         default:
1532                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1533                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1534                                  SPEED_10;
1535                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1536                                   DUPLEX_HALF;
1537                         break;
1538                 }
1539                 *speed = SPEED_INVALID;
1540                 *duplex = DUPLEX_INVALID;
1541                 break;
1542         };
1543 }
1544
1545 static void tg3_phy_copper_begin(struct tg3 *tp)
1546 {
1547         u32 new_adv;
1548         int i;
1549
1550         if (tp->link_config.phy_is_low_power) {
1551                 /* Entering low power mode.  Disable gigabit and
1552                  * 100baseT advertisements.
1553                  */
1554                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1555
1556                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1557                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1558                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1559                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1560
1561                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1562         } else if (tp->link_config.speed == SPEED_INVALID) {
1563                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1564                         tp->link_config.advertising &=
1565                                 ~(ADVERTISED_1000baseT_Half |
1566                                   ADVERTISED_1000baseT_Full);
1567
1568                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1569                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1570                         new_adv |= ADVERTISE_10HALF;
1571                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1572                         new_adv |= ADVERTISE_10FULL;
1573                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1574                         new_adv |= ADVERTISE_100HALF;
1575                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1576                         new_adv |= ADVERTISE_100FULL;
1577                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1578
1579                 if (tp->link_config.advertising &
1580                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1581                         new_adv = 0;
1582                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1583                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1584                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1585                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1586                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1587                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1588                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1589                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1590                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1591                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1592                 } else {
1593                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1594                 }
1595         } else {
1596                 /* Asking for a specific link mode. */
1597                 if (tp->link_config.speed == SPEED_1000) {
1598                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1599                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1600
1601                         if (tp->link_config.duplex == DUPLEX_FULL)
1602                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1603                         else
1604                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1605                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1606                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1607                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1608                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1609                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1610                 } else {
1611                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1612
1613                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1614                         if (tp->link_config.speed == SPEED_100) {
1615                                 if (tp->link_config.duplex == DUPLEX_FULL)
1616                                         new_adv |= ADVERTISE_100FULL;
1617                                 else
1618                                         new_adv |= ADVERTISE_100HALF;
1619                         } else {
1620                                 if (tp->link_config.duplex == DUPLEX_FULL)
1621                                         new_adv |= ADVERTISE_10FULL;
1622                                 else
1623                                         new_adv |= ADVERTISE_10HALF;
1624                         }
1625                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1626                 }
1627         }
1628
1629         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1630             tp->link_config.speed != SPEED_INVALID) {
1631                 u32 bmcr, orig_bmcr;
1632
1633                 tp->link_config.active_speed = tp->link_config.speed;
1634                 tp->link_config.active_duplex = tp->link_config.duplex;
1635
1636                 bmcr = 0;
1637                 switch (tp->link_config.speed) {
1638                 default:
1639                 case SPEED_10:
1640                         break;
1641
1642                 case SPEED_100:
1643                         bmcr |= BMCR_SPEED100;
1644                         break;
1645
1646                 case SPEED_1000:
1647                         bmcr |= TG3_BMCR_SPEED1000;
1648                         break;
1649                 };
1650
1651                 if (tp->link_config.duplex == DUPLEX_FULL)
1652                         bmcr |= BMCR_FULLDPLX;
1653
1654                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1655                     (bmcr != orig_bmcr)) {
1656                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1657                         for (i = 0; i < 1500; i++) {
1658                                 u32 tmp;
1659
1660                                 udelay(10);
1661                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1662                                     tg3_readphy(tp, MII_BMSR, &tmp))
1663                                         continue;
1664                                 if (!(tmp & BMSR_LSTATUS)) {
1665                                         udelay(40);
1666                                         break;
1667                                 }
1668                         }
1669                         tg3_writephy(tp, MII_BMCR, bmcr);
1670                         udelay(40);
1671                 }
1672         } else {
1673                 tg3_writephy(tp, MII_BMCR,
1674                              BMCR_ANENABLE | BMCR_ANRESTART);
1675         }
1676 }
1677
1678 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1679 {
1680         int err;
1681
1682         /* Turn off tap power management. */
1683         /* Set Extended packet length bit */
1684         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1685
1686         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1687         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1688
1689         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1690         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1691
1692         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1693         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1694
1695         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1696         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1697
1698         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1699         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1700
1701         udelay(40);
1702
1703         return err;
1704 }
1705
1706 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1707 {
1708         u32 adv_reg, all_mask = 0;
1709
1710         if (mask & ADVERTISED_10baseT_Half)
1711                 all_mask |= ADVERTISE_10HALF;
1712         if (mask & ADVERTISED_10baseT_Full)
1713                 all_mask |= ADVERTISE_10FULL;
1714         if (mask & ADVERTISED_100baseT_Half)
1715                 all_mask |= ADVERTISE_100HALF;
1716         if (mask & ADVERTISED_100baseT_Full)
1717                 all_mask |= ADVERTISE_100FULL;
1718
1719         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1720                 return 0;
1721
1722         if ((adv_reg & all_mask) != all_mask)
1723                 return 0;
1724         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1725                 u32 tg3_ctrl;
1726
1727                 all_mask = 0;
1728                 if (mask & ADVERTISED_1000baseT_Half)
1729                         all_mask |= ADVERTISE_1000HALF;
1730                 if (mask & ADVERTISED_1000baseT_Full)
1731                         all_mask |= ADVERTISE_1000FULL;
1732
1733                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1734                         return 0;
1735
1736                 if ((tg3_ctrl & all_mask) != all_mask)
1737                         return 0;
1738         }
1739         return 1;
1740 }
1741
1742 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1743 {
1744         int current_link_up;
1745         u32 bmsr, dummy;
1746         u16 current_speed;
1747         u8 current_duplex;
1748         int i, err;
1749
1750         tw32(MAC_EVENT, 0);
1751
1752         tw32_f(MAC_STATUS,
1753              (MAC_STATUS_SYNC_CHANGED |
1754               MAC_STATUS_CFG_CHANGED |
1755               MAC_STATUS_MI_COMPLETION |
1756               MAC_STATUS_LNKSTATE_CHANGED));
1757         udelay(40);
1758
1759         tp->mi_mode = MAC_MI_MODE_BASE;
1760         tw32_f(MAC_MI_MODE, tp->mi_mode);
1761         udelay(80);
1762
1763         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1764
1765         /* Some third-party PHYs need to be reset on link going
1766          * down.
1767          */
1768         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1769              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1770              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1771             netif_carrier_ok(tp->dev)) {
1772                 tg3_readphy(tp, MII_BMSR, &bmsr);
1773                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1774                     !(bmsr & BMSR_LSTATUS))
1775                         force_reset = 1;
1776         }
1777         if (force_reset)
1778                 tg3_phy_reset(tp);
1779
1780         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1781                 tg3_readphy(tp, MII_BMSR, &bmsr);
1782                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1783                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1784                         bmsr = 0;
1785
1786                 if (!(bmsr & BMSR_LSTATUS)) {
1787                         err = tg3_init_5401phy_dsp(tp);
1788                         if (err)
1789                                 return err;
1790
1791                         tg3_readphy(tp, MII_BMSR, &bmsr);
1792                         for (i = 0; i < 1000; i++) {
1793                                 udelay(10);
1794                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1795                                     (bmsr & BMSR_LSTATUS)) {
1796                                         udelay(40);
1797                                         break;
1798                                 }
1799                         }
1800
1801                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1802                             !(bmsr & BMSR_LSTATUS) &&
1803                             tp->link_config.active_speed == SPEED_1000) {
1804                                 err = tg3_phy_reset(tp);
1805                                 if (!err)
1806                                         err = tg3_init_5401phy_dsp(tp);
1807                                 if (err)
1808                                         return err;
1809                         }
1810                 }
1811         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1812                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1813                 /* 5701 {A0,B0} CRC bug workaround */
1814                 tg3_writephy(tp, 0x15, 0x0a75);
1815                 tg3_writephy(tp, 0x1c, 0x8c68);
1816                 tg3_writephy(tp, 0x1c, 0x8d68);
1817                 tg3_writephy(tp, 0x1c, 0x8c68);
1818         }
1819
1820         /* Clear pending interrupts... */
1821         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1822         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1823
1824         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1825                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1826         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1827                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1828
1829         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1830             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1831                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1832                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1833                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1834                 else
1835                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1836         }
1837
1838         current_link_up = 0;
1839         current_speed = SPEED_INVALID;
1840         current_duplex = DUPLEX_INVALID;
1841
1842         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1843                 u32 val;
1844
1845                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1846                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1847                 if (!(val & (1 << 10))) {
1848                         val |= (1 << 10);
1849                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1850                         goto relink;
1851                 }
1852         }
1853
1854         bmsr = 0;
1855         for (i = 0; i < 100; i++) {
1856                 tg3_readphy(tp, MII_BMSR, &bmsr);
1857                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1858                     (bmsr & BMSR_LSTATUS))
1859                         break;
1860                 udelay(40);
1861         }
1862
1863         if (bmsr & BMSR_LSTATUS) {
1864                 u32 aux_stat, bmcr;
1865
1866                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1867                 for (i = 0; i < 2000; i++) {
1868                         udelay(10);
1869                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1870                             aux_stat)
1871                                 break;
1872                 }
1873
1874                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1875                                              &current_speed,
1876                                              &current_duplex);
1877
1878                 bmcr = 0;
1879                 for (i = 0; i < 200; i++) {
1880                         tg3_readphy(tp, MII_BMCR, &bmcr);
1881                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1882                                 continue;
1883                         if (bmcr && bmcr != 0x7fff)
1884                                 break;
1885                         udelay(10);
1886                 }
1887
1888                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1889                         if (bmcr & BMCR_ANENABLE) {
1890                                 current_link_up = 1;
1891
1892                                 /* Force autoneg restart if we are exiting
1893                                  * low power mode.
1894                                  */
1895                                 if (!tg3_copper_is_advertising_all(tp,
1896                                                 tp->link_config.advertising))
1897                                         current_link_up = 0;
1898                         } else {
1899                                 current_link_up = 0;
1900                         }
1901                 } else {
1902                         if (!(bmcr & BMCR_ANENABLE) &&
1903                             tp->link_config.speed == current_speed &&
1904                             tp->link_config.duplex == current_duplex) {
1905                                 current_link_up = 1;
1906                         } else {
1907                                 current_link_up = 0;
1908                         }
1909                 }
1910
1911                 tp->link_config.active_speed = current_speed;
1912                 tp->link_config.active_duplex = current_duplex;
1913         }
1914
1915         if (current_link_up == 1 &&
1916             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1917             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1918                 u32 local_adv, remote_adv;
1919
1920                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1921                         local_adv = 0;
1922                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1923
1924                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1925                         remote_adv = 0;
1926
1927                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1928
1929                 /* If we are not advertising full pause capability,
1930                  * something is wrong.  Bring the link down and reconfigure.
1931                  */
1932                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1933                         current_link_up = 0;
1934                 } else {
1935                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1936                 }
1937         }
1938 relink:
1939         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1940                 u32 tmp;
1941
1942                 tg3_phy_copper_begin(tp);
1943
1944                 tg3_readphy(tp, MII_BMSR, &tmp);
1945                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1946                     (tmp & BMSR_LSTATUS))
1947                         current_link_up = 1;
1948         }
1949
1950         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1951         if (current_link_up == 1) {
1952                 if (tp->link_config.active_speed == SPEED_100 ||
1953                     tp->link_config.active_speed == SPEED_10)
1954                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1955                 else
1956                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1957         } else
1958                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1959
1960         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1961         if (tp->link_config.active_duplex == DUPLEX_HALF)
1962                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1963
1964         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1965         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1966                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1967                     (current_link_up == 1 &&
1968                      tp->link_config.active_speed == SPEED_10))
1969                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1970         } else {
1971                 if (current_link_up == 1)
1972                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1973         }
1974
1975         /* ??? Without this setting Netgear GA302T PHY does not
1976          * ??? send/receive packets...
1977          */
1978         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1979             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1980                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1981                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1982                 udelay(80);
1983         }
1984
1985         tw32_f(MAC_MODE, tp->mac_mode);
1986         udelay(40);
1987
1988         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1989                 /* Polled via timer. */
1990                 tw32_f(MAC_EVENT, 0);
1991         } else {
1992                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1993         }
1994         udelay(40);
1995
1996         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1997             current_link_up == 1 &&
1998             tp->link_config.active_speed == SPEED_1000 &&
1999             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2000              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2001                 udelay(120);
2002                 tw32_f(MAC_STATUS,
2003                      (MAC_STATUS_SYNC_CHANGED |
2004                       MAC_STATUS_CFG_CHANGED));
2005                 udelay(40);
2006                 tg3_write_mem(tp,
2007                               NIC_SRAM_FIRMWARE_MBOX,
2008                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2009         }
2010
2011         if (current_link_up != netif_carrier_ok(tp->dev)) {
2012                 if (current_link_up)
2013                         netif_carrier_on(tp->dev);
2014                 else
2015                         netif_carrier_off(tp->dev);
2016                 tg3_link_report(tp);
2017         }
2018
2019         return 0;
2020 }
2021
2022 struct tg3_fiber_aneginfo {
2023         int state;
2024 #define ANEG_STATE_UNKNOWN              0
2025 #define ANEG_STATE_AN_ENABLE            1
2026 #define ANEG_STATE_RESTART_INIT         2
2027 #define ANEG_STATE_RESTART              3
2028 #define ANEG_STATE_DISABLE_LINK_OK      4
2029 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2030 #define ANEG_STATE_ABILITY_DETECT       6
2031 #define ANEG_STATE_ACK_DETECT_INIT      7
2032 #define ANEG_STATE_ACK_DETECT           8
2033 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2034 #define ANEG_STATE_COMPLETE_ACK         10
2035 #define ANEG_STATE_IDLE_DETECT_INIT     11
2036 #define ANEG_STATE_IDLE_DETECT          12
2037 #define ANEG_STATE_LINK_OK              13
2038 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2039 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2040
2041         u32 flags;
2042 #define MR_AN_ENABLE            0x00000001
2043 #define MR_RESTART_AN           0x00000002
2044 #define MR_AN_COMPLETE          0x00000004
2045 #define MR_PAGE_RX              0x00000008
2046 #define MR_NP_LOADED            0x00000010
2047 #define MR_TOGGLE_TX            0x00000020
2048 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2049 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2050 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2051 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2052 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2053 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2054 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2055 #define MR_TOGGLE_RX            0x00002000
2056 #define MR_NP_RX                0x00004000
2057
2058 #define MR_LINK_OK              0x80000000
2059
2060         unsigned long link_time, cur_time;
2061
2062         u32 ability_match_cfg;
2063         int ability_match_count;
2064
2065         char ability_match, idle_match, ack_match;
2066
2067         u32 txconfig, rxconfig;
2068 #define ANEG_CFG_NP             0x00000080
2069 #define ANEG_CFG_ACK            0x00000040
2070 #define ANEG_CFG_RF2            0x00000020
2071 #define ANEG_CFG_RF1            0x00000010
2072 #define ANEG_CFG_PS2            0x00000001
2073 #define ANEG_CFG_PS1            0x00008000
2074 #define ANEG_CFG_HD             0x00004000
2075 #define ANEG_CFG_FD             0x00002000
2076 #define ANEG_CFG_INVAL          0x00001f06
2077
2078 };
2079 #define ANEG_OK         0
2080 #define ANEG_DONE       1
2081 #define ANEG_TIMER_ENAB 2
2082 #define ANEG_FAILED     -1
2083
2084 #define ANEG_STATE_SETTLE_TIME  10000
2085
2086 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2087                                    struct tg3_fiber_aneginfo *ap)
2088 {
2089         unsigned long delta;
2090         u32 rx_cfg_reg;
2091         int ret;
2092
2093         if (ap->state == ANEG_STATE_UNKNOWN) {
2094                 ap->rxconfig = 0;
2095                 ap->link_time = 0;
2096                 ap->cur_time = 0;
2097                 ap->ability_match_cfg = 0;
2098                 ap->ability_match_count = 0;
2099                 ap->ability_match = 0;
2100                 ap->idle_match = 0;
2101                 ap->ack_match = 0;
2102         }
2103         ap->cur_time++;
2104
2105         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2106                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2107
2108                 if (rx_cfg_reg != ap->ability_match_cfg) {
2109                         ap->ability_match_cfg = rx_cfg_reg;
2110                         ap->ability_match = 0;
2111                         ap->ability_match_count = 0;
2112                 } else {
2113                         if (++ap->ability_match_count > 1) {
2114                                 ap->ability_match = 1;
2115                                 ap->ability_match_cfg = rx_cfg_reg;
2116                         }
2117                 }
2118                 if (rx_cfg_reg & ANEG_CFG_ACK)
2119                         ap->ack_match = 1;
2120                 else
2121                         ap->ack_match = 0;
2122
2123                 ap->idle_match = 0;
2124         } else {
2125                 ap->idle_match = 1;
2126                 ap->ability_match_cfg = 0;
2127                 ap->ability_match_count = 0;
2128                 ap->ability_match = 0;
2129                 ap->ack_match = 0;
2130
2131                 rx_cfg_reg = 0;
2132         }
2133
2134         ap->rxconfig = rx_cfg_reg;
2135         ret = ANEG_OK;
2136
2137         switch(ap->state) {
2138         case ANEG_STATE_UNKNOWN:
2139                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2140                         ap->state = ANEG_STATE_AN_ENABLE;
2141
2142                 /* fallthru */
2143         case ANEG_STATE_AN_ENABLE:
2144                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2145                 if (ap->flags & MR_AN_ENABLE) {
2146                         ap->link_time = 0;
2147                         ap->cur_time = 0;
2148                         ap->ability_match_cfg = 0;
2149                         ap->ability_match_count = 0;
2150                         ap->ability_match = 0;
2151                         ap->idle_match = 0;
2152                         ap->ack_match = 0;
2153
2154                         ap->state = ANEG_STATE_RESTART_INIT;
2155                 } else {
2156                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2157                 }
2158                 break;
2159
2160         case ANEG_STATE_RESTART_INIT:
2161                 ap->link_time = ap->cur_time;
2162                 ap->flags &= ~(MR_NP_LOADED);
2163                 ap->txconfig = 0;
2164                 tw32(MAC_TX_AUTO_NEG, 0);
2165                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2166                 tw32_f(MAC_MODE, tp->mac_mode);
2167                 udelay(40);
2168
2169                 ret = ANEG_TIMER_ENAB;
2170                 ap->state = ANEG_STATE_RESTART;
2171
2172                 /* fallthru */
2173         case ANEG_STATE_RESTART:
2174                 delta = ap->cur_time - ap->link_time;
2175                 if (delta > ANEG_STATE_SETTLE_TIME) {
2176                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2177                 } else {
2178                         ret = ANEG_TIMER_ENAB;
2179                 }
2180                 break;
2181
2182         case ANEG_STATE_DISABLE_LINK_OK:
2183                 ret = ANEG_DONE;
2184                 break;
2185
2186         case ANEG_STATE_ABILITY_DETECT_INIT:
2187                 ap->flags &= ~(MR_TOGGLE_TX);
2188                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2189                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2190                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2191                 tw32_f(MAC_MODE, tp->mac_mode);
2192                 udelay(40);
2193
2194                 ap->state = ANEG_STATE_ABILITY_DETECT;
2195                 break;
2196
2197         case ANEG_STATE_ABILITY_DETECT:
2198                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2199                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2200                 }
2201                 break;
2202
2203         case ANEG_STATE_ACK_DETECT_INIT:
2204                 ap->txconfig |= ANEG_CFG_ACK;
2205                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2206                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2207                 tw32_f(MAC_MODE, tp->mac_mode);
2208                 udelay(40);
2209
2210                 ap->state = ANEG_STATE_ACK_DETECT;
2211
2212                 /* fallthru */
2213         case ANEG_STATE_ACK_DETECT:
2214                 if (ap->ack_match != 0) {
2215                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2216                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2217                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2218                         } else {
2219                                 ap->state = ANEG_STATE_AN_ENABLE;
2220                         }
2221                 } else if (ap->ability_match != 0 &&
2222                            ap->rxconfig == 0) {
2223                         ap->state = ANEG_STATE_AN_ENABLE;
2224                 }
2225                 break;
2226
2227         case ANEG_STATE_COMPLETE_ACK_INIT:
2228                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2229                         ret = ANEG_FAILED;
2230                         break;
2231                 }
2232                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2233                                MR_LP_ADV_HALF_DUPLEX |
2234                                MR_LP_ADV_SYM_PAUSE |
2235                                MR_LP_ADV_ASYM_PAUSE |
2236                                MR_LP_ADV_REMOTE_FAULT1 |
2237                                MR_LP_ADV_REMOTE_FAULT2 |
2238                                MR_LP_ADV_NEXT_PAGE |
2239                                MR_TOGGLE_RX |
2240                                MR_NP_RX);
2241                 if (ap->rxconfig & ANEG_CFG_FD)
2242                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2243                 if (ap->rxconfig & ANEG_CFG_HD)
2244                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2245                 if (ap->rxconfig & ANEG_CFG_PS1)
2246                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2247                 if (ap->rxconfig & ANEG_CFG_PS2)
2248                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2249                 if (ap->rxconfig & ANEG_CFG_RF1)
2250                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2251                 if (ap->rxconfig & ANEG_CFG_RF2)
2252                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2253                 if (ap->rxconfig & ANEG_CFG_NP)
2254                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2255
2256                 ap->link_time = ap->cur_time;
2257
2258                 ap->flags ^= (MR_TOGGLE_TX);
2259                 if (ap->rxconfig & 0x0008)
2260                         ap->flags |= MR_TOGGLE_RX;
2261                 if (ap->rxconfig & ANEG_CFG_NP)
2262                         ap->flags |= MR_NP_RX;
2263                 ap->flags |= MR_PAGE_RX;
2264
2265                 ap->state = ANEG_STATE_COMPLETE_ACK;
2266                 ret = ANEG_TIMER_ENAB;
2267                 break;
2268
2269         case ANEG_STATE_COMPLETE_ACK:
2270                 if (ap->ability_match != 0 &&
2271                     ap->rxconfig == 0) {
2272                         ap->state = ANEG_STATE_AN_ENABLE;
2273                         break;
2274                 }
2275                 delta = ap->cur_time - ap->link_time;
2276                 if (delta > ANEG_STATE_SETTLE_TIME) {
2277                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2278                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2279                         } else {
2280                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2281                                     !(ap->flags & MR_NP_RX)) {
2282                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2283                                 } else {
2284                                         ret = ANEG_FAILED;
2285                                 }
2286                         }
2287                 }
2288                 break;
2289
2290         case ANEG_STATE_IDLE_DETECT_INIT:
2291                 ap->link_time = ap->cur_time;
2292                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2293                 tw32_f(MAC_MODE, tp->mac_mode);
2294                 udelay(40);
2295
2296                 ap->state = ANEG_STATE_IDLE_DETECT;
2297                 ret = ANEG_TIMER_ENAB;
2298                 break;
2299
2300         case ANEG_STATE_IDLE_DETECT:
2301                 if (ap->ability_match != 0 &&
2302                     ap->rxconfig == 0) {
2303                         ap->state = ANEG_STATE_AN_ENABLE;
2304                         break;
2305                 }
2306                 delta = ap->cur_time - ap->link_time;
2307                 if (delta > ANEG_STATE_SETTLE_TIME) {
2308                         /* XXX another gem from the Broadcom driver :( */
2309                         ap->state = ANEG_STATE_LINK_OK;
2310                 }
2311                 break;
2312
2313         case ANEG_STATE_LINK_OK:
2314                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2315                 ret = ANEG_DONE;
2316                 break;
2317
2318         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2319                 /* ??? unimplemented */
2320                 break;
2321
2322         case ANEG_STATE_NEXT_PAGE_WAIT:
2323                 /* ??? unimplemented */
2324                 break;
2325
2326         default:
2327                 ret = ANEG_FAILED;
2328                 break;
2329         };
2330
2331         return ret;
2332 }
2333
2334 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2335 {
2336         int res = 0;
2337         struct tg3_fiber_aneginfo aninfo;
2338         int status = ANEG_FAILED;
2339         unsigned int tick;
2340         u32 tmp;
2341
2342         tw32_f(MAC_TX_AUTO_NEG, 0);
2343
2344         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2345         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2346         udelay(40);
2347
2348         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2349         udelay(40);
2350
2351         memset(&aninfo, 0, sizeof(aninfo));
2352         aninfo.flags |= MR_AN_ENABLE;
2353         aninfo.state = ANEG_STATE_UNKNOWN;
2354         aninfo.cur_time = 0;
2355         tick = 0;
2356         while (++tick < 195000) {
2357                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2358                 if (status == ANEG_DONE || status == ANEG_FAILED)
2359                         break;
2360
2361                 udelay(1);
2362         }
2363
2364         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2365         tw32_f(MAC_MODE, tp->mac_mode);
2366         udelay(40);
2367
2368         *flags = aninfo.flags;
2369
2370         if (status == ANEG_DONE &&
2371             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2372                              MR_LP_ADV_FULL_DUPLEX)))
2373                 res = 1;
2374
2375         return res;
2376 }
2377
2378 static void tg3_init_bcm8002(struct tg3 *tp)
2379 {
2380         u32 mac_status = tr32(MAC_STATUS);
2381         int i;
2382
2383         /* Reset when initting first time or we have a link. */
2384         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2385             !(mac_status & MAC_STATUS_PCS_SYNCED))
2386                 return;
2387
2388         /* Set PLL lock range. */
2389         tg3_writephy(tp, 0x16, 0x8007);
2390
2391         /* SW reset */
2392         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2393
2394         /* Wait for reset to complete. */
2395         /* XXX schedule_timeout() ... */
2396         for (i = 0; i < 500; i++)
2397                 udelay(10);
2398
2399         /* Config mode; select PMA/Ch 1 regs. */
2400         tg3_writephy(tp, 0x10, 0x8411);
2401
2402         /* Enable auto-lock and comdet, select txclk for tx. */
2403         tg3_writephy(tp, 0x11, 0x0a10);
2404
2405         tg3_writephy(tp, 0x18, 0x00a0);
2406         tg3_writephy(tp, 0x16, 0x41ff);
2407
2408         /* Assert and deassert POR. */
2409         tg3_writephy(tp, 0x13, 0x0400);
2410         udelay(40);
2411         tg3_writephy(tp, 0x13, 0x0000);
2412
2413         tg3_writephy(tp, 0x11, 0x0a50);
2414         udelay(40);
2415         tg3_writephy(tp, 0x11, 0x0a10);
2416
2417         /* Wait for signal to stabilize */
2418         /* XXX schedule_timeout() ... */
2419         for (i = 0; i < 15000; i++)
2420                 udelay(10);
2421
2422         /* Deselect the channel register so we can read the PHYID
2423          * later.
2424          */
2425         tg3_writephy(tp, 0x10, 0x8011);
2426 }
2427
2428 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2429 {
2430         u32 sg_dig_ctrl, sg_dig_status;
2431         u32 serdes_cfg, expected_sg_dig_ctrl;
2432         int workaround, port_a;
2433         int current_link_up;
2434
2435         serdes_cfg = 0;
2436         expected_sg_dig_ctrl = 0;
2437         workaround = 0;
2438         port_a = 1;
2439         current_link_up = 0;
2440
2441         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2442             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2443                 workaround = 1;
2444                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2445                         port_a = 0;
2446
2447                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2448                 /* preserve bits 20-23 for voltage regulator */
2449                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2450         }
2451
2452         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2453
2454         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2455                 if (sg_dig_ctrl & (1 << 31)) {
2456                         if (workaround) {
2457                                 u32 val = serdes_cfg;
2458
2459                                 if (port_a)
2460                                         val |= 0xc010000;
2461                                 else
2462                                         val |= 0x4010000;
2463                                 tw32_f(MAC_SERDES_CFG, val);
2464                         }
2465                         tw32_f(SG_DIG_CTRL, 0x01388400);
2466                 }
2467                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2468                         tg3_setup_flow_control(tp, 0, 0);
2469                         current_link_up = 1;
2470                 }
2471                 goto out;
2472         }
2473
2474         /* Want auto-negotiation.  */
2475         expected_sg_dig_ctrl = 0x81388400;
2476
2477         /* Pause capability */
2478         expected_sg_dig_ctrl |= (1 << 11);
2479
2480         /* Asymettric pause */
2481         expected_sg_dig_ctrl |= (1 << 12);
2482
2483         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2484                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2485                     tp->serdes_counter &&
2486                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2487                                     MAC_STATUS_RCVD_CFG)) ==
2488                      MAC_STATUS_PCS_SYNCED)) {
2489                         tp->serdes_counter--;
2490                         current_link_up = 1;
2491                         goto out;
2492                 }
2493 restart_autoneg:
2494                 if (workaround)
2495                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2496                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2497                 udelay(5);
2498                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2499
2500                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2501                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2502         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2503                                  MAC_STATUS_SIGNAL_DET)) {
2504                 sg_dig_status = tr32(SG_DIG_STATUS);
2505                 mac_status = tr32(MAC_STATUS);
2506
2507                 if ((sg_dig_status & (1 << 1)) &&
2508                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2509                         u32 local_adv, remote_adv;
2510
2511                         local_adv = ADVERTISE_PAUSE_CAP;
2512                         remote_adv = 0;
2513                         if (sg_dig_status & (1 << 19))
2514                                 remote_adv |= LPA_PAUSE_CAP;
2515                         if (sg_dig_status & (1 << 20))
2516                                 remote_adv |= LPA_PAUSE_ASYM;
2517
2518                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2519                         current_link_up = 1;
2520                         tp->serdes_counter = 0;
2521                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2522                 } else if (!(sg_dig_status & (1 << 1))) {
2523                         if (tp->serdes_counter)
2524                                 tp->serdes_counter--;
2525                         else {
2526                                 if (workaround) {
2527                                         u32 val = serdes_cfg;
2528
2529                                         if (port_a)
2530                                                 val |= 0xc010000;
2531                                         else
2532                                                 val |= 0x4010000;
2533
2534                                         tw32_f(MAC_SERDES_CFG, val);
2535                                 }
2536
2537                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2538                                 udelay(40);
2539
2540                                 /* Link parallel detection - link is up */
2541                                 /* only if we have PCS_SYNC and not */
2542                                 /* receiving config code words */
2543                                 mac_status = tr32(MAC_STATUS);
2544                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2545                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2546                                         tg3_setup_flow_control(tp, 0, 0);
2547                                         current_link_up = 1;
2548                                         tp->tg3_flags2 |=
2549                                                 TG3_FLG2_PARALLEL_DETECT;
2550                                         tp->serdes_counter =
2551                                                 SERDES_PARALLEL_DET_TIMEOUT;
2552                                 } else
2553                                         goto restart_autoneg;
2554                         }
2555                 }
2556         } else {
2557                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2558                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2559         }
2560
2561 out:
2562         return current_link_up;
2563 }
2564
2565 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2566 {
2567         int current_link_up = 0;
2568
2569         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2570                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2571                 goto out;
2572         }
2573
2574         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2575                 u32 flags;
2576                 int i;
2577
2578                 if (fiber_autoneg(tp, &flags)) {
2579                         u32 local_adv, remote_adv;
2580
2581                         local_adv = ADVERTISE_PAUSE_CAP;
2582                         remote_adv = 0;
2583                         if (flags & MR_LP_ADV_SYM_PAUSE)
2584                                 remote_adv |= LPA_PAUSE_CAP;
2585                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2586                                 remote_adv |= LPA_PAUSE_ASYM;
2587
2588                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2589
2590                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2591                         current_link_up = 1;
2592                 }
2593                 for (i = 0; i < 30; i++) {
2594                         udelay(20);
2595                         tw32_f(MAC_STATUS,
2596                                (MAC_STATUS_SYNC_CHANGED |
2597                                 MAC_STATUS_CFG_CHANGED));
2598                         udelay(40);
2599                         if ((tr32(MAC_STATUS) &
2600                              (MAC_STATUS_SYNC_CHANGED |
2601                               MAC_STATUS_CFG_CHANGED)) == 0)
2602                                 break;
2603                 }
2604
2605                 mac_status = tr32(MAC_STATUS);
2606                 if (current_link_up == 0 &&
2607                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2608                     !(mac_status & MAC_STATUS_RCVD_CFG))
2609                         current_link_up = 1;
2610         } else {
2611                 /* Forcing 1000FD link up. */
2612                 current_link_up = 1;
2613                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2614
2615                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2616                 udelay(40);
2617         }
2618
2619 out:
2620         return current_link_up;
2621 }
2622
2623 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2624 {
2625         u32 orig_pause_cfg;
2626         u16 orig_active_speed;
2627         u8 orig_active_duplex;
2628         u32 mac_status;
2629         int current_link_up;
2630         int i;
2631
2632         orig_pause_cfg =
2633                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2634                                   TG3_FLAG_TX_PAUSE));
2635         orig_active_speed = tp->link_config.active_speed;
2636         orig_active_duplex = tp->link_config.active_duplex;
2637
2638         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2639             netif_carrier_ok(tp->dev) &&
2640             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2641                 mac_status = tr32(MAC_STATUS);
2642                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2643                                MAC_STATUS_SIGNAL_DET |
2644                                MAC_STATUS_CFG_CHANGED |
2645                                MAC_STATUS_RCVD_CFG);
2646                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2647                                    MAC_STATUS_SIGNAL_DET)) {
2648                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2649                                             MAC_STATUS_CFG_CHANGED));
2650                         return 0;
2651                 }
2652         }
2653
2654         tw32_f(MAC_TX_AUTO_NEG, 0);
2655
2656         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2657         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2658         tw32_f(MAC_MODE, tp->mac_mode);
2659         udelay(40);
2660
2661         if (tp->phy_id == PHY_ID_BCM8002)
2662                 tg3_init_bcm8002(tp);
2663
2664         /* Enable link change event even when serdes polling.  */
2665         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2666         udelay(40);
2667
2668         current_link_up = 0;
2669         mac_status = tr32(MAC_STATUS);
2670
2671         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2672                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2673         else
2674                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2675
2676         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2677         tw32_f(MAC_MODE, tp->mac_mode);
2678         udelay(40);
2679
2680         tp->hw_status->status =
2681                 (SD_STATUS_UPDATED |
2682                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2683
2684         for (i = 0; i < 100; i++) {
2685                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2686                                     MAC_STATUS_CFG_CHANGED));
2687                 udelay(5);
2688                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2689                                          MAC_STATUS_CFG_CHANGED |
2690                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2691                         break;
2692         }
2693
2694         mac_status = tr32(MAC_STATUS);
2695         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2696                 current_link_up = 0;
2697                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2698                     tp->serdes_counter == 0) {
2699                         tw32_f(MAC_MODE, (tp->mac_mode |
2700                                           MAC_MODE_SEND_CONFIGS));
2701                         udelay(1);
2702                         tw32_f(MAC_MODE, tp->mac_mode);
2703                 }
2704         }
2705
2706         if (current_link_up == 1) {
2707                 tp->link_config.active_speed = SPEED_1000;
2708                 tp->link_config.active_duplex = DUPLEX_FULL;
2709                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2710                                     LED_CTRL_LNKLED_OVERRIDE |
2711                                     LED_CTRL_1000MBPS_ON));
2712         } else {
2713                 tp->link_config.active_speed = SPEED_INVALID;
2714                 tp->link_config.active_duplex = DUPLEX_INVALID;
2715                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2716                                     LED_CTRL_LNKLED_OVERRIDE |
2717                                     LED_CTRL_TRAFFIC_OVERRIDE));
2718         }
2719
2720         if (current_link_up != netif_carrier_ok(tp->dev)) {
2721                 if (current_link_up)
2722                         netif_carrier_on(tp->dev);
2723                 else
2724                         netif_carrier_off(tp->dev);
2725                 tg3_link_report(tp);
2726         } else {
2727                 u32 now_pause_cfg =
2728                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2729                                          TG3_FLAG_TX_PAUSE);
2730                 if (orig_pause_cfg != now_pause_cfg ||
2731                     orig_active_speed != tp->link_config.active_speed ||
2732                     orig_active_duplex != tp->link_config.active_duplex)
2733                         tg3_link_report(tp);
2734         }
2735
2736         return 0;
2737 }
2738
2739 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2740 {
2741         int current_link_up, err = 0;
2742         u32 bmsr, bmcr;
2743         u16 current_speed;
2744         u8 current_duplex;
2745
2746         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2747         tw32_f(MAC_MODE, tp->mac_mode);
2748         udelay(40);
2749
2750         tw32(MAC_EVENT, 0);
2751
2752         tw32_f(MAC_STATUS,
2753              (MAC_STATUS_SYNC_CHANGED |
2754               MAC_STATUS_CFG_CHANGED |
2755               MAC_STATUS_MI_COMPLETION |
2756               MAC_STATUS_LNKSTATE_CHANGED));
2757         udelay(40);
2758
2759         if (force_reset)
2760                 tg3_phy_reset(tp);
2761
2762         current_link_up = 0;
2763         current_speed = SPEED_INVALID;
2764         current_duplex = DUPLEX_INVALID;
2765
2766         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2767         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2768         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2769                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2770                         bmsr |= BMSR_LSTATUS;
2771                 else
2772                         bmsr &= ~BMSR_LSTATUS;
2773         }
2774
2775         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2776
2777         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2778             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2779                 /* do nothing, just check for link up at the end */
2780         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2781                 u32 adv, new_adv;
2782
2783                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2784                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2785                                   ADVERTISE_1000XPAUSE |
2786                                   ADVERTISE_1000XPSE_ASYM |
2787                                   ADVERTISE_SLCT);
2788
2789                 /* Always advertise symmetric PAUSE just like copper */
2790                 new_adv |= ADVERTISE_1000XPAUSE;
2791
2792                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2793                         new_adv |= ADVERTISE_1000XHALF;
2794                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2795                         new_adv |= ADVERTISE_1000XFULL;
2796
2797                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2798                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2799                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2800                         tg3_writephy(tp, MII_BMCR, bmcr);
2801
2802                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2803                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2804                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2805
2806                         return err;
2807                 }
2808         } else {
2809                 u32 new_bmcr;
2810
2811                 bmcr &= ~BMCR_SPEED1000;
2812                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2813
2814                 if (tp->link_config.duplex == DUPLEX_FULL)
2815                         new_bmcr |= BMCR_FULLDPLX;
2816
2817                 if (new_bmcr != bmcr) {
2818                         /* BMCR_SPEED1000 is a reserved bit that needs
2819                          * to be set on write.
2820                          */
2821                         new_bmcr |= BMCR_SPEED1000;
2822
2823                         /* Force a linkdown */
2824                         if (netif_carrier_ok(tp->dev)) {
2825                                 u32 adv;
2826
2827                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2828                                 adv &= ~(ADVERTISE_1000XFULL |
2829                                          ADVERTISE_1000XHALF |
2830                                          ADVERTISE_SLCT);
2831                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2832                                 tg3_writephy(tp, MII_BMCR, bmcr |
2833                                                            BMCR_ANRESTART |
2834                                                            BMCR_ANENABLE);
2835                                 udelay(10);
2836                                 netif_carrier_off(tp->dev);
2837                         }
2838                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2839                         bmcr = new_bmcr;
2840                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2841                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2842                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2843                             ASIC_REV_5714) {
2844                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2845                                         bmsr |= BMSR_LSTATUS;
2846                                 else
2847                                         bmsr &= ~BMSR_LSTATUS;
2848                         }
2849                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2850                 }
2851         }
2852
2853         if (bmsr & BMSR_LSTATUS) {
2854                 current_speed = SPEED_1000;
2855                 current_link_up = 1;
2856                 if (bmcr & BMCR_FULLDPLX)
2857                         current_duplex = DUPLEX_FULL;
2858                 else
2859                         current_duplex = DUPLEX_HALF;
2860
2861                 if (bmcr & BMCR_ANENABLE) {
2862                         u32 local_adv, remote_adv, common;
2863
2864                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2865                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2866                         common = local_adv & remote_adv;
2867                         if (common & (ADVERTISE_1000XHALF |
2868                                       ADVERTISE_1000XFULL)) {
2869                                 if (common & ADVERTISE_1000XFULL)
2870                                         current_duplex = DUPLEX_FULL;
2871                                 else
2872                                         current_duplex = DUPLEX_HALF;
2873
2874                                 tg3_setup_flow_control(tp, local_adv,
2875                                                        remote_adv);
2876                         }
2877                         else
2878                                 current_link_up = 0;
2879                 }
2880         }
2881
2882         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2883         if (tp->link_config.active_duplex == DUPLEX_HALF)
2884                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2885
2886         tw32_f(MAC_MODE, tp->mac_mode);
2887         udelay(40);
2888
2889         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2890
2891         tp->link_config.active_speed = current_speed;
2892         tp->link_config.active_duplex = current_duplex;
2893
2894         if (current_link_up != netif_carrier_ok(tp->dev)) {
2895                 if (current_link_up)
2896                         netif_carrier_on(tp->dev);
2897                 else {
2898                         netif_carrier_off(tp->dev);
2899                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2900                 }
2901                 tg3_link_report(tp);
2902         }
2903         return err;
2904 }
2905
2906 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2907 {
2908         if (tp->serdes_counter) {
2909                 /* Give autoneg time to complete. */
2910                 tp->serdes_counter--;
2911                 return;
2912         }
2913         if (!netif_carrier_ok(tp->dev) &&
2914             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2915                 u32 bmcr;
2916
2917                 tg3_readphy(tp, MII_BMCR, &bmcr);
2918                 if (bmcr & BMCR_ANENABLE) {
2919                         u32 phy1, phy2;
2920
2921                         /* Select shadow register 0x1f */
2922                         tg3_writephy(tp, 0x1c, 0x7c00);
2923                         tg3_readphy(tp, 0x1c, &phy1);
2924
2925                         /* Select expansion interrupt status register */
2926                         tg3_writephy(tp, 0x17, 0x0f01);
2927                         tg3_readphy(tp, 0x15, &phy2);
2928                         tg3_readphy(tp, 0x15, &phy2);
2929
2930                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2931                                 /* We have signal detect and not receiving
2932                                  * config code words, link is up by parallel
2933                                  * detection.
2934                                  */
2935
2936                                 bmcr &= ~BMCR_ANENABLE;
2937                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2938                                 tg3_writephy(tp, MII_BMCR, bmcr);
2939                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2940                         }
2941                 }
2942         }
2943         else if (netif_carrier_ok(tp->dev) &&
2944                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2945                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2946                 u32 phy2;
2947
2948                 /* Select expansion interrupt status register */
2949                 tg3_writephy(tp, 0x17, 0x0f01);
2950                 tg3_readphy(tp, 0x15, &phy2);
2951                 if (phy2 & 0x20) {
2952                         u32 bmcr;
2953
2954                         /* Config code words received, turn on autoneg. */
2955                         tg3_readphy(tp, MII_BMCR, &bmcr);
2956                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2957
2958                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2959
2960                 }
2961         }
2962 }
2963
2964 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2965 {
2966         int err;
2967
2968         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2969                 err = tg3_setup_fiber_phy(tp, force_reset);
2970         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2971                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2972         } else {
2973                 err = tg3_setup_copper_phy(tp, force_reset);
2974         }
2975
2976         if (tp->link_config.active_speed == SPEED_1000 &&
2977             tp->link_config.active_duplex == DUPLEX_HALF)
2978                 tw32(MAC_TX_LENGTHS,
2979                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2980                       (6 << TX_LENGTHS_IPG_SHIFT) |
2981                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2982         else
2983                 tw32(MAC_TX_LENGTHS,
2984                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2985                       (6 << TX_LENGTHS_IPG_SHIFT) |
2986                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2987
2988         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2989                 if (netif_carrier_ok(tp->dev)) {
2990                         tw32(HOSTCC_STAT_COAL_TICKS,
2991                              tp->coal.stats_block_coalesce_usecs);
2992                 } else {
2993                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2994                 }
2995         }
2996
2997         return err;
2998 }
2999
3000 /* This is called whenever we suspect that the system chipset is re-
3001  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3002  * is bogus tx completions. We try to recover by setting the
3003  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3004  * in the workqueue.
3005  */
3006 static void tg3_tx_recover(struct tg3 *tp)
3007 {
3008         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3009                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3010
3011         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3012                "mapped I/O cycles to the network device, attempting to "
3013                "recover. Please report the problem to the driver maintainer "
3014                "and include system chipset information.\n", tp->dev->name);
3015
3016         spin_lock(&tp->lock);
3017         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3018         spin_unlock(&tp->lock);
3019 }
3020
3021 static inline u32 tg3_tx_avail(struct tg3 *tp)
3022 {
3023         smp_mb();
3024         return (tp->tx_pending -
3025                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3026 }
3027
3028 /* Tigon3 never reports partial packet sends.  So we do not
3029  * need special logic to handle SKBs that have not had all
3030  * of their frags sent yet, like SunGEM does.
3031  */
3032 static void tg3_tx(struct tg3 *tp)
3033 {
3034         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3035         u32 sw_idx = tp->tx_cons;
3036
3037         while (sw_idx != hw_idx) {
3038                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3039                 struct sk_buff *skb = ri->skb;
3040                 int i, tx_bug = 0;
3041
3042                 if (unlikely(skb == NULL)) {
3043                         tg3_tx_recover(tp);
3044                         return;
3045                 }
3046
3047                 pci_unmap_single(tp->pdev,
3048                                  pci_unmap_addr(ri, mapping),
3049                                  skb_headlen(skb),
3050                                  PCI_DMA_TODEVICE);
3051
3052                 ri->skb = NULL;
3053
3054                 sw_idx = NEXT_TX(sw_idx);
3055
3056                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3057                         ri = &tp->tx_buffers[sw_idx];
3058                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3059                                 tx_bug = 1;
3060
3061                         pci_unmap_page(tp->pdev,
3062                                        pci_unmap_addr(ri, mapping),
3063                                        skb_shinfo(skb)->frags[i].size,
3064                                        PCI_DMA_TODEVICE);
3065
3066                         sw_idx = NEXT_TX(sw_idx);
3067                 }
3068
3069                 dev_kfree_skb(skb);
3070
3071                 if (unlikely(tx_bug)) {
3072                         tg3_tx_recover(tp);
3073                         return;
3074                 }
3075         }
3076
3077         tp->tx_cons = sw_idx;
3078
3079         /* Need to make the tx_cons update visible to tg3_start_xmit()
3080          * before checking for netif_queue_stopped().  Without the
3081          * memory barrier, there is a small possibility that tg3_start_xmit()
3082          * will miss it and cause the queue to be stopped forever.
3083          */
3084         smp_mb();
3085
3086         if (unlikely(netif_queue_stopped(tp->dev) &&
3087                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3088                 netif_tx_lock(tp->dev);
3089                 if (netif_queue_stopped(tp->dev) &&
3090                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3091                         netif_wake_queue(tp->dev);
3092                 netif_tx_unlock(tp->dev);
3093         }
3094 }
3095
3096 /* Returns size of skb allocated or < 0 on error.
3097  *
3098  * We only need to fill in the address because the other members
3099  * of the RX descriptor are invariant, see tg3_init_rings.
3100  *
3101  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3102  * posting buffers we only dirty the first cache line of the RX
3103  * descriptor (containing the address).  Whereas for the RX status
3104  * buffers the cpu only reads the last cacheline of the RX descriptor
3105  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3106  */
3107 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3108                             int src_idx, u32 dest_idx_unmasked)
3109 {
3110         struct tg3_rx_buffer_desc *desc;
3111         struct ring_info *map, *src_map;
3112         struct sk_buff *skb;
3113         dma_addr_t mapping;
3114         int skb_size, dest_idx;
3115
3116         src_map = NULL;
3117         switch (opaque_key) {
3118         case RXD_OPAQUE_RING_STD:
3119                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3120                 desc = &tp->rx_std[dest_idx];
3121                 map = &tp->rx_std_buffers[dest_idx];
3122                 if (src_idx >= 0)
3123                         src_map = &tp->rx_std_buffers[src_idx];
3124                 skb_size = tp->rx_pkt_buf_sz;
3125                 break;
3126
3127         case RXD_OPAQUE_RING_JUMBO:
3128                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3129                 desc = &tp->rx_jumbo[dest_idx];
3130                 map = &tp->rx_jumbo_buffers[dest_idx];
3131                 if (src_idx >= 0)
3132                         src_map = &tp->rx_jumbo_buffers[src_idx];
3133                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3134                 break;
3135
3136         default:
3137                 return -EINVAL;
3138         };
3139
3140         /* Do not overwrite any of the map or rp information
3141          * until we are sure we can commit to a new buffer.
3142          *
3143          * Callers depend upon this behavior and assume that
3144          * we leave everything unchanged if we fail.
3145          */
3146         skb = netdev_alloc_skb(tp->dev, skb_size);
3147         if (skb == NULL)
3148                 return -ENOMEM;
3149
3150         skb_reserve(skb, tp->rx_offset);
3151
3152         mapping = pci_map_single(tp->pdev, skb->data,
3153                                  skb_size - tp->rx_offset,
3154                                  PCI_DMA_FROMDEVICE);
3155
3156         map->skb = skb;
3157         pci_unmap_addr_set(map, mapping, mapping);
3158
3159         if (src_map != NULL)
3160                 src_map->skb = NULL;
3161
3162         desc->addr_hi = ((u64)mapping >> 32);
3163         desc->addr_lo = ((u64)mapping & 0xffffffff);
3164
3165         return skb_size;
3166 }
3167
3168 /* We only need to move over in the address because the other
3169  * members of the RX descriptor are invariant.  See notes above
3170  * tg3_alloc_rx_skb for full details.
3171  */
3172 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3173                            int src_idx, u32 dest_idx_unmasked)
3174 {
3175         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3176         struct ring_info *src_map, *dest_map;
3177         int dest_idx;
3178
3179         switch (opaque_key) {
3180         case RXD_OPAQUE_RING_STD:
3181                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3182                 dest_desc = &tp->rx_std[dest_idx];
3183                 dest_map = &tp->rx_std_buffers[dest_idx];
3184                 src_desc = &tp->rx_std[src_idx];
3185                 src_map = &tp->rx_std_buffers[src_idx];
3186                 break;
3187
3188         case RXD_OPAQUE_RING_JUMBO:
3189                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3190                 dest_desc = &tp->rx_jumbo[dest_idx];
3191                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3192                 src_desc = &tp->rx_jumbo[src_idx];
3193                 src_map = &tp->rx_jumbo_buffers[src_idx];
3194                 break;
3195
3196         default:
3197                 return;
3198         };
3199
3200         dest_map->skb = src_map->skb;
3201         pci_unmap_addr_set(dest_map, mapping,
3202                            pci_unmap_addr(src_map, mapping));
3203         dest_desc->addr_hi = src_desc->addr_hi;
3204         dest_desc->addr_lo = src_desc->addr_lo;
3205
3206         src_map->skb = NULL;
3207 }
3208
3209 #if TG3_VLAN_TAG_USED
3210 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3211 {
3212         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3213 }
3214 #endif
3215
3216 /* The RX ring scheme is composed of multiple rings which post fresh
3217  * buffers to the chip, and one special ring the chip uses to report
3218  * status back to the host.
3219  *
3220  * The special ring reports the status of received packets to the
3221  * host.  The chip does not write into the original descriptor the
3222  * RX buffer was obtained from.  The chip simply takes the original
3223  * descriptor as provided by the host, updates the status and length
3224  * field, then writes this into the next status ring entry.
3225  *
3226  * Each ring the host uses to post buffers to the chip is described
3227  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3228  * it is first placed into the on-chip ram.  When the packet's length
3229  * is known, it walks down the TG3_BDINFO entries to select the ring.
3230  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3231  * which is within the range of the new packet's length is chosen.
3232  *
3233  * The "separate ring for rx status" scheme may sound queer, but it makes
3234  * sense from a cache coherency perspective.  If only the host writes
3235  * to the buffer post rings, and only the chip writes to the rx status
3236  * rings, then cache lines never move beyond shared-modified state.
3237  * If both the host and chip were to write into the same ring, cache line
3238  * eviction could occur since both entities want it in an exclusive state.
3239  */
3240 static int tg3_rx(struct tg3 *tp, int budget)
3241 {
3242         u32 work_mask, rx_std_posted = 0;
3243         u32 sw_idx = tp->rx_rcb_ptr;
3244         u16 hw_idx;
3245         int received;
3246
3247         hw_idx = tp->hw_status->idx[0].rx_producer;
3248         /*
3249          * We need to order the read of hw_idx and the read of
3250          * the opaque cookie.
3251          */
3252         rmb();
3253         work_mask = 0;
3254         received = 0;
3255         while (sw_idx != hw_idx && budget > 0) {
3256                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3257                 unsigned int len;
3258                 struct sk_buff *skb;
3259                 dma_addr_t dma_addr;
3260                 u32 opaque_key, desc_idx, *post_ptr;
3261
3262                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3263                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3264                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3265                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3266                                                   mapping);
3267                         skb = tp->rx_std_buffers[desc_idx].skb;
3268                         post_ptr = &tp->rx_std_ptr;
3269                         rx_std_posted++;
3270                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3271                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3272                                                   mapping);
3273                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3274                         post_ptr = &tp->rx_jumbo_ptr;
3275                 }
3276                 else {
3277                         goto next_pkt_nopost;
3278                 }
3279
3280                 work_mask |= opaque_key;
3281
3282                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3283                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3284                 drop_it:
3285                         tg3_recycle_rx(tp, opaque_key,
3286                                        desc_idx, *post_ptr);
3287                 drop_it_no_recycle:
3288                         /* Other statistics kept track of by card. */
3289                         tp->net_stats.rx_dropped++;
3290                         goto next_pkt;
3291                 }
3292
3293                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3294
3295                 if (len > RX_COPY_THRESHOLD
3296                         && tp->rx_offset == 2
3297                         /* rx_offset != 2 iff this is a 5701 card running
3298                          * in PCI-X mode [see tg3_get_invariants()] */
3299                 ) {
3300                         int skb_size;
3301
3302                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3303                                                     desc_idx, *post_ptr);
3304                         if (skb_size < 0)
3305                                 goto drop_it;
3306
3307                         pci_unmap_single(tp->pdev, dma_addr,
3308                                          skb_size - tp->rx_offset,
3309                                          PCI_DMA_FROMDEVICE);
3310
3311                         skb_put(skb, len);
3312                 } else {
3313                         struct sk_buff *copy_skb;
3314
3315                         tg3_recycle_rx(tp, opaque_key,
3316                                        desc_idx, *post_ptr);
3317
3318                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3319                         if (copy_skb == NULL)
3320                                 goto drop_it_no_recycle;
3321
3322                         skb_reserve(copy_skb, 2);
3323                         skb_put(copy_skb, len);
3324                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3325                         memcpy(copy_skb->data, skb->data, len);
3326                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3327
3328                         /* We'll reuse the original ring buffer. */
3329                         skb = copy_skb;
3330                 }
3331
3332                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3333                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3334                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3335                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3336                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3337                 else
3338                         skb->ip_summed = CHECKSUM_NONE;
3339
3340                 skb->protocol = eth_type_trans(skb, tp->dev);
3341 #if TG3_VLAN_TAG_USED
3342                 if (tp->vlgrp != NULL &&
3343                     desc->type_flags & RXD_FLAG_VLAN) {
3344                         tg3_vlan_rx(tp, skb,
3345                                     desc->err_vlan & RXD_VLAN_MASK);
3346                 } else
3347 #endif
3348                         netif_receive_skb(skb);
3349
3350                 tp->dev->last_rx = jiffies;
3351                 received++;
3352                 budget--;
3353
3354 next_pkt:
3355                 (*post_ptr)++;
3356
3357                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3358                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3359
3360                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3361                                      TG3_64BIT_REG_LOW, idx);
3362                         work_mask &= ~RXD_OPAQUE_RING_STD;
3363                         rx_std_posted = 0;
3364                 }
3365 next_pkt_nopost:
3366                 sw_idx++;
3367                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3368
3369                 /* Refresh hw_idx to see if there is new work */
3370                 if (sw_idx == hw_idx) {
3371                         hw_idx = tp->hw_status->idx[0].rx_producer;
3372                         rmb();
3373                 }
3374         }
3375
3376         /* ACK the status ring. */
3377         tp->rx_rcb_ptr = sw_idx;
3378         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3379
3380         /* Refill RX ring(s). */
3381         if (work_mask & RXD_OPAQUE_RING_STD) {
3382                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3383                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3384                              sw_idx);
3385         }
3386         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3387                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3388                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3389                              sw_idx);
3390         }
3391         mmiowb();
3392
3393         return received;
3394 }
3395
3396 static int tg3_poll(struct net_device *netdev, int *budget)
3397 {
3398         struct tg3 *tp = netdev_priv(netdev);
3399         struct tg3_hw_status *sblk = tp->hw_status;
3400         int done;
3401
3402         /* handle link change and other phy events */
3403         if (!(tp->tg3_flags &
3404               (TG3_FLAG_USE_LINKCHG_REG |
3405                TG3_FLAG_POLL_SERDES))) {
3406                 if (sblk->status & SD_STATUS_LINK_CHG) {
3407                         sblk->status = SD_STATUS_UPDATED |
3408                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3409                         spin_lock(&tp->lock);
3410                         tg3_setup_phy(tp, 0);
3411                         spin_unlock(&tp->lock);
3412                 }
3413         }
3414
3415         /* run TX completion thread */
3416         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3417                 tg3_tx(tp);
3418                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3419                         netif_rx_complete(netdev);
3420                         schedule_work(&tp->reset_task);
3421                         return 0;
3422                 }
3423         }
3424
3425         /* run RX thread, within the bounds set by NAPI.
3426          * All RX "locking" is done by ensuring outside
3427          * code synchronizes with dev->poll()
3428          */
3429         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3430                 int orig_budget = *budget;
3431                 int work_done;
3432
3433                 if (orig_budget > netdev->quota)
3434                         orig_budget = netdev->quota;
3435
3436                 work_done = tg3_rx(tp, orig_budget);
3437
3438                 *budget -= work_done;
3439                 netdev->quota -= work_done;
3440         }
3441
3442         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3443                 tp->last_tag = sblk->status_tag;
3444                 rmb();
3445         } else
3446                 sblk->status &= ~SD_STATUS_UPDATED;
3447
3448         /* if no more work, tell net stack and NIC we're done */
3449         done = !tg3_has_work(tp);
3450         if (done) {
3451                 netif_rx_complete(netdev);
3452                 tg3_restart_ints(tp);
3453         }
3454
3455         return (done ? 0 : 1);
3456 }
3457
3458 static void tg3_irq_quiesce(struct tg3 *tp)
3459 {
3460         BUG_ON(tp->irq_sync);
3461
3462         tp->irq_sync = 1;
3463         smp_mb();
3464
3465         synchronize_irq(tp->pdev->irq);
3466 }
3467
3468 static inline int tg3_irq_sync(struct tg3 *tp)
3469 {
3470         return tp->irq_sync;
3471 }
3472
3473 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3474  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3475  * with as well.  Most of the time, this is not necessary except when
3476  * shutting down the device.
3477  */
3478 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3479 {
3480         if (irq_sync)
3481                 tg3_irq_quiesce(tp);
3482         spin_lock_bh(&tp->lock);
3483 }
3484
3485 static inline void tg3_full_unlock(struct tg3 *tp)
3486 {
3487         spin_unlock_bh(&tp->lock);
3488 }
3489
3490 /* One-shot MSI handler - Chip automatically disables interrupt
3491  * after sending MSI so driver doesn't have to do it.
3492  */
3493 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3494 {
3495         struct net_device *dev = dev_id;
3496         struct tg3 *tp = netdev_priv(dev);
3497
3498         prefetch(tp->hw_status);
3499         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3500
3501         if (likely(!tg3_irq_sync(tp)))
3502                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3503
3504         return IRQ_HANDLED;
3505 }
3506
3507 /* MSI ISR - No need to check for interrupt sharing and no need to
3508  * flush status block and interrupt mailbox. PCI ordering rules
3509  * guarantee that MSI will arrive after the status block.
3510  */
3511 static irqreturn_t tg3_msi(int irq, void *dev_id)
3512 {
3513         struct net_device *dev = dev_id;
3514         struct tg3 *tp = netdev_priv(dev);
3515
3516         prefetch(tp->hw_status);
3517         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3518         /*
3519          * Writing any value to intr-mbox-0 clears PCI INTA# and
3520          * chip-internal interrupt pending events.
3521          * Writing non-zero to intr-mbox-0 additional tells the
3522          * NIC to stop sending us irqs, engaging "in-intr-handler"
3523          * event coalescing.
3524          */
3525         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3526         if (likely(!tg3_irq_sync(tp)))
3527                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3528
3529         return IRQ_RETVAL(1);
3530 }
3531
3532 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3533 {
3534         struct net_device *dev = dev_id;
3535         struct tg3 *tp = netdev_priv(dev);
3536         struct tg3_hw_status *sblk = tp->hw_status;
3537         unsigned int handled = 1;
3538
3539         /* In INTx mode, it is possible for the interrupt to arrive at
3540          * the CPU before the status block posted prior to the interrupt.
3541          * Reading the PCI State register will confirm whether the
3542          * interrupt is ours and will flush the status block.
3543          */
3544         if ((sblk->status & SD_STATUS_UPDATED) ||
3545             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3546                 /*
3547                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3548                  * chip-internal interrupt pending events.
3549                  * Writing non-zero to intr-mbox-0 additional tells the
3550                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3551                  * event coalescing.
3552                  */
3553                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3554                              0x00000001);
3555                 if (tg3_irq_sync(tp))
3556                         goto out;
3557                 sblk->status &= ~SD_STATUS_UPDATED;
3558                 if (likely(tg3_has_work(tp))) {
3559                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3560                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3561                 } else {
3562                         /* No work, shared interrupt perhaps?  re-enable
3563                          * interrupts, and flush that PCI write
3564                          */
3565                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3566                                 0x00000000);
3567                 }
3568         } else {        /* shared interrupt */
3569                 handled = 0;
3570         }
3571 out:
3572         return IRQ_RETVAL(handled);
3573 }
3574
3575 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3576 {
3577         struct net_device *dev = dev_id;
3578         struct tg3 *tp = netdev_priv(dev);
3579         struct tg3_hw_status *sblk = tp->hw_status;
3580         unsigned int handled = 1;
3581
3582         /* In INTx mode, it is possible for the interrupt to arrive at
3583          * the CPU before the status block posted prior to the interrupt.
3584          * Reading the PCI State register will confirm whether the
3585          * interrupt is ours and will flush the status block.
3586          */
3587         if ((sblk->status_tag != tp->last_tag) ||
3588             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3589                 /*
3590                  * writing any value to intr-mbox-0 clears PCI INTA# and
3591                  * chip-internal interrupt pending events.
3592                  * writing non-zero to intr-mbox-0 additional tells the
3593                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3594                  * event coalescing.
3595                  */
3596                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3597                              0x00000001);
3598                 if (tg3_irq_sync(tp))
3599                         goto out;
3600                 if (netif_rx_schedule_prep(dev)) {
3601                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3602                         /* Update last_tag to mark that this status has been
3603                          * seen. Because interrupt may be shared, we may be
3604                          * racing with tg3_poll(), so only update last_tag
3605                          * if tg3_poll() is not scheduled.
3606                          */
3607                         tp->last_tag = sblk->status_tag;
3608                         __netif_rx_schedule(dev);
3609                 }
3610         } else {        /* shared interrupt */
3611                 handled = 0;
3612         }
3613 out:
3614         return IRQ_RETVAL(handled);
3615 }
3616
3617 /* ISR for interrupt test */
3618 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3619 {
3620         struct net_device *dev = dev_id;
3621         struct tg3 *tp = netdev_priv(dev);
3622         struct tg3_hw_status *sblk = tp->hw_status;
3623
3624         if ((sblk->status & SD_STATUS_UPDATED) ||
3625             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3626                 tg3_disable_ints(tp);
3627                 return IRQ_RETVAL(1);
3628         }
3629         return IRQ_RETVAL(0);
3630 }
3631
3632 static int tg3_init_hw(struct tg3 *, int);
3633 static int tg3_halt(struct tg3 *, int, int);
3634
3635 /* Restart hardware after configuration changes, self-test, etc.
3636  * Invoked with tp->lock held.
3637  */
3638 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3639 {
3640         int err;
3641
3642         err = tg3_init_hw(tp, reset_phy);
3643         if (err) {
3644                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3645                        "aborting.\n", tp->dev->name);
3646                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3647                 tg3_full_unlock(tp);
3648                 del_timer_sync(&tp->timer);
3649                 tp->irq_sync = 0;
3650                 netif_poll_enable(tp->dev);
3651                 dev_close(tp->dev);
3652                 tg3_full_lock(tp, 0);
3653         }
3654         return err;
3655 }
3656
3657 #ifdef CONFIG_NET_POLL_CONTROLLER
3658 static void tg3_poll_controller(struct net_device *dev)
3659 {
3660         struct tg3 *tp = netdev_priv(dev);
3661
3662         tg3_interrupt(tp->pdev->irq, dev);
3663 }
3664 #endif
3665
3666 static void tg3_reset_task(struct work_struct *work)
3667 {
3668         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3669         unsigned int restart_timer;
3670
3671         tg3_full_lock(tp, 0);
3672         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3673
3674         if (!netif_running(tp->dev)) {
3675                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3676                 tg3_full_unlock(tp);
3677                 return;
3678         }
3679
3680         tg3_full_unlock(tp);
3681
3682         tg3_netif_stop(tp);
3683
3684         tg3_full_lock(tp, 1);
3685
3686         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3687         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3688
3689         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3690                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3691                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3692                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3693                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3694         }
3695
3696         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3697         if (tg3_init_hw(tp, 1))
3698                 goto out;
3699
3700         tg3_netif_start(tp);
3701
3702         if (restart_timer)
3703                 mod_timer(&tp->timer, jiffies + 1);
3704
3705 out:
3706         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3707
3708         tg3_full_unlock(tp);
3709 }
3710
3711 static void tg3_tx_timeout(struct net_device *dev)
3712 {
3713         struct tg3 *tp = netdev_priv(dev);
3714
3715         if (netif_msg_tx_err(tp))
3716                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3717                        dev->name);
3718
3719         schedule_work(&tp->reset_task);
3720 }
3721
3722 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3723 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3724 {
3725         u32 base = (u32) mapping & 0xffffffff;
3726
3727         return ((base > 0xffffdcc0) &&
3728                 (base + len + 8 < base));
3729 }
3730
3731 /* Test for DMA addresses > 40-bit */
3732 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3733                                           int len)
3734 {
3735 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3736         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3737                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3738         return 0;
3739 #else
3740         return 0;
3741 #endif
3742 }
3743
3744 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3745
3746 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3747 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3748                                        u32 last_plus_one, u32 *start,
3749                                        u32 base_flags, u32 mss)
3750 {
3751         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3752         dma_addr_t new_addr = 0;
3753         u32 entry = *start;
3754         int i, ret = 0;
3755
3756         if (!new_skb) {
3757                 ret = -1;
3758         } else {
3759                 /* New SKB is guaranteed to be linear. */
3760                 entry = *start;
3761                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3762                                           PCI_DMA_TODEVICE);
3763                 /* Make sure new skb does not cross any 4G boundaries.
3764                  * Drop the packet if it does.
3765                  */
3766                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3767                         ret = -1;
3768                         dev_kfree_skb(new_skb);
3769                         new_skb = NULL;
3770                 } else {
3771                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3772                                     base_flags, 1 | (mss << 1));
3773                         *start = NEXT_TX(entry);
3774                 }
3775         }
3776
3777         /* Now clean up the sw ring entries. */
3778         i = 0;
3779         while (entry != last_plus_one) {
3780                 int len;
3781
3782                 if (i == 0)
3783                         len = skb_headlen(skb);
3784                 else
3785                         len = skb_shinfo(skb)->frags[i-1].size;
3786                 pci_unmap_single(tp->pdev,
3787                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3788                                  len, PCI_DMA_TODEVICE);
3789                 if (i == 0) {
3790                         tp->tx_buffers[entry].skb = new_skb;
3791                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3792                 } else {
3793                         tp->tx_buffers[entry].skb = NULL;
3794                 }
3795                 entry = NEXT_TX(entry);
3796                 i++;
3797         }
3798
3799         dev_kfree_skb(skb);
3800
3801         return ret;
3802 }
3803
3804 static void tg3_set_txd(struct tg3 *tp, int entry,
3805                         dma_addr_t mapping, int len, u32 flags,
3806                         u32 mss_and_is_end)
3807 {
3808         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3809         int is_end = (mss_and_is_end & 0x1);
3810         u32 mss = (mss_and_is_end >> 1);
3811         u32 vlan_tag = 0;
3812
3813         if (is_end)
3814                 flags |= TXD_FLAG_END;
3815         if (flags & TXD_FLAG_VLAN) {
3816                 vlan_tag = flags >> 16;
3817                 flags &= 0xffff;
3818         }
3819         vlan_tag |= (mss << TXD_MSS_SHIFT);
3820
3821         txd->addr_hi = ((u64) mapping >> 32);
3822         txd->addr_lo = ((u64) mapping & 0xffffffff);
3823         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3824         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3825 }
3826
3827 /* hard_start_xmit for devices that don't have any bugs and
3828  * support TG3_FLG2_HW_TSO_2 only.
3829  */
3830 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3831 {
3832         struct tg3 *tp = netdev_priv(dev);
3833         dma_addr_t mapping;
3834         u32 len, entry, base_flags, mss;
3835
3836         len = skb_headlen(skb);
3837
3838         /* We are running in BH disabled context with netif_tx_lock
3839          * and TX reclaim runs via tp->poll inside of a software
3840          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3841          * no IRQ context deadlocks to worry about either.  Rejoice!
3842          */
3843         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3844                 if (!netif_queue_stopped(dev)) {
3845                         netif_stop_queue(dev);
3846
3847                         /* This is a hard error, log it. */
3848                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3849                                "queue awake!\n", dev->name);
3850                 }
3851                 return NETDEV_TX_BUSY;
3852         }
3853
3854         entry = tp->tx_prod;
3855         base_flags = 0;
3856 #if TG3_TSO_SUPPORT != 0
3857         mss = 0;
3858         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3859             (mss = skb_shinfo(skb)->gso_size) != 0) {
3860                 int tcp_opt_len, ip_tcp_len;
3861
3862                 if (skb_header_cloned(skb) &&
3863                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3864                         dev_kfree_skb(skb);
3865                         goto out_unlock;
3866                 }
3867
3868                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3869                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3870                 else {
3871                         tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3872                         ip_tcp_len = (skb->nh.iph->ihl * 4) +
3873                                      sizeof(struct tcphdr);
3874
3875                         skb->nh.iph->check = 0;
3876                         skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3877                                                      tcp_opt_len);
3878                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3879                 }
3880
3881                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3882                                TXD_FLAG_CPU_POST_DMA);
3883
3884                 skb->h.th->check = 0;
3885
3886         }
3887         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3888                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3889 #else
3890         mss = 0;
3891         if (skb->ip_summed == CHECKSUM_PARTIAL)
3892                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3893 #endif
3894 #if TG3_VLAN_TAG_USED
3895         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3896                 base_flags |= (TXD_FLAG_VLAN |
3897                                (vlan_tx_tag_get(skb) << 16));
3898 #endif
3899
3900         /* Queue skb data, a.k.a. the main skb fragment. */
3901         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3902
3903         tp->tx_buffers[entry].skb = skb;
3904         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3905
3906         tg3_set_txd(tp, entry, mapping, len, base_flags,
3907                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3908
3909         entry = NEXT_TX(entry);
3910
3911         /* Now loop through additional data fragments, and queue them. */
3912         if (skb_shinfo(skb)->nr_frags > 0) {
3913                 unsigned int i, last;
3914
3915                 last = skb_shinfo(skb)->nr_frags - 1;
3916                 for (i = 0; i <= last; i++) {
3917                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3918
3919                         len = frag->size;
3920                         mapping = pci_map_page(tp->pdev,
3921                                                frag->page,
3922                                                frag->page_offset,
3923                                                len, PCI_DMA_TODEVICE);
3924
3925                         tp->tx_buffers[entry].skb = NULL;
3926                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3927
3928                         tg3_set_txd(tp, entry, mapping, len,
3929                                     base_flags, (i == last) | (mss << 1));
3930
3931                         entry = NEXT_TX(entry);
3932                 }
3933         }
3934
3935         /* Packets are ready, update Tx producer idx local and on card. */
3936         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3937
3938         tp->tx_prod = entry;
3939         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3940                 netif_stop_queue(dev);
3941                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3942                         netif_wake_queue(tp->dev);
3943         }
3944
3945 out_unlock:
3946         mmiowb();
3947
3948         dev->trans_start = jiffies;
3949
3950         return NETDEV_TX_OK;
3951 }
3952
3953 #if TG3_TSO_SUPPORT != 0
3954 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3955
3956 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3957  * TSO header is greater than 80 bytes.
3958  */
3959 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3960 {
3961         struct sk_buff *segs, *nskb;
3962
3963         /* Estimate the number of fragments in the worst case */
3964         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3965                 netif_stop_queue(tp->dev);
3966                 return NETDEV_TX_BUSY;
3967         }
3968
3969         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
3970         if (unlikely(IS_ERR(segs)))
3971                 goto tg3_tso_bug_end;
3972
3973         do {
3974                 nskb = segs;
3975                 segs = segs->next;
3976                 nskb->next = NULL;
3977                 tg3_start_xmit_dma_bug(nskb, tp->dev);
3978         } while (segs);
3979
3980 tg3_tso_bug_end:
3981         dev_kfree_skb(skb);
3982
3983         return NETDEV_TX_OK;
3984 }
3985 #endif
3986
3987 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3988  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3989  */
3990 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3991 {
3992         struct tg3 *tp = netdev_priv(dev);
3993         dma_addr_t mapping;
3994         u32 len, entry, base_flags, mss;
3995         int would_hit_hwbug;
3996
3997         len = skb_headlen(skb);
3998
3999         /* We are running in BH disabled context with netif_tx_lock
4000          * and TX reclaim runs via tp->poll inside of a software
4001          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4002          * no IRQ context deadlocks to worry about either.  Rejoice!
4003          */
4004         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4005                 if (!netif_queue_stopped(dev)) {
4006                         netif_stop_queue(dev);
4007
4008                         /* This is a hard error, log it. */
4009                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4010                                "queue awake!\n", dev->name);
4011                 }
4012                 return NETDEV_TX_BUSY;
4013         }
4014
4015         entry = tp->tx_prod;
4016         base_flags = 0;
4017         if (skb->ip_summed == CHECKSUM_PARTIAL)
4018                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4019 #if TG3_TSO_SUPPORT != 0
4020         mss = 0;
4021         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4022             (mss = skb_shinfo(skb)->gso_size) != 0) {
4023                 int tcp_opt_len, ip_tcp_len, hdr_len;
4024
4025                 if (skb_header_cloned(skb) &&
4026                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4027                         dev_kfree_skb(skb);
4028                         goto out_unlock;
4029                 }
4030
4031                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4032                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4033
4034                 hdr_len = ip_tcp_len + tcp_opt_len;
4035                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4036                              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
4037                         return (tg3_tso_bug(tp, skb));
4038
4039                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4040                                TXD_FLAG_CPU_POST_DMA);
4041
4042                 skb->nh.iph->check = 0;
4043                 skb->nh.iph->tot_len = htons(mss + hdr_len);
4044                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4045                         skb->h.th->check = 0;
4046                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4047                 }
4048                 else {
4049                         skb->h.th->check =
4050                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4051                                                    skb->nh.iph->daddr,
4052                                                    0, IPPROTO_TCP, 0);
4053                 }
4054
4055                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4056                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4057                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4058                                 int tsflags;
4059
4060                                 tsflags = ((skb->nh.iph->ihl - 5) +
4061                                            (tcp_opt_len >> 2));
4062                                 mss |= (tsflags << 11);
4063                         }
4064                 } else {
4065                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4066                                 int tsflags;
4067
4068                                 tsflags = ((skb->nh.iph->ihl - 5) +
4069                                            (tcp_opt_len >> 2));
4070                                 base_flags |= tsflags << 12;
4071                         }
4072                 }
4073         }
4074 #else
4075         mss = 0;
4076 #endif
4077 #if TG3_VLAN_TAG_USED
4078         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4079                 base_flags |= (TXD_FLAG_VLAN |
4080                                (vlan_tx_tag_get(skb) << 16));
4081 #endif
4082
4083         /* Queue skb data, a.k.a. the main skb fragment. */
4084         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4085
4086         tp->tx_buffers[entry].skb = skb;
4087         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4088
4089         would_hit_hwbug = 0;
4090
4091         if (tg3_4g_overflow_test(mapping, len))
4092                 would_hit_hwbug = 1;
4093
4094         tg3_set_txd(tp, entry, mapping, len, base_flags,
4095                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4096
4097         entry = NEXT_TX(entry);
4098
4099         /* Now loop through additional data fragments, and queue them. */
4100         if (skb_shinfo(skb)->nr_frags > 0) {
4101                 unsigned int i, last;
4102
4103                 last = skb_shinfo(skb)->nr_frags - 1;
4104                 for (i = 0; i <= last; i++) {
4105                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4106
4107                         len = frag->size;
4108                         mapping = pci_map_page(tp->pdev,
4109                                                frag->page,
4110                                                frag->page_offset,
4111                                                len, PCI_DMA_TODEVICE);
4112
4113                         tp->tx_buffers[entry].skb = NULL;
4114                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4115
4116                         if (tg3_4g_overflow_test(mapping, len))
4117                                 would_hit_hwbug = 1;
4118
4119                         if (tg3_40bit_overflow_test(tp, mapping, len))
4120                                 would_hit_hwbug = 1;
4121
4122                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4123                                 tg3_set_txd(tp, entry, mapping, len,
4124                                             base_flags, (i == last)|(mss << 1));
4125                         else
4126                                 tg3_set_txd(tp, entry, mapping, len,
4127                                             base_flags, (i == last));
4128
4129                         entry = NEXT_TX(entry);
4130                 }
4131         }
4132
4133         if (would_hit_hwbug) {
4134                 u32 last_plus_one = entry;
4135                 u32 start;
4136
4137                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4138                 start &= (TG3_TX_RING_SIZE - 1);
4139
4140                 /* If the workaround fails due to memory/mapping
4141                  * failure, silently drop this packet.
4142                  */
4143                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4144                                                 &start, base_flags, mss))
4145                         goto out_unlock;
4146
4147                 entry = start;
4148         }
4149
4150         /* Packets are ready, update Tx producer idx local and on card. */
4151         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4152
4153         tp->tx_prod = entry;
4154         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4155                 netif_stop_queue(dev);
4156                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4157                         netif_wake_queue(tp->dev);
4158         }
4159
4160 out_unlock:
4161         mmiowb();
4162
4163         dev->trans_start = jiffies;
4164
4165         return NETDEV_TX_OK;
4166 }
4167
4168 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4169                                int new_mtu)
4170 {
4171         dev->mtu = new_mtu;
4172
4173         if (new_mtu > ETH_DATA_LEN) {
4174                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4175                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4176                         ethtool_op_set_tso(dev, 0);
4177                 }
4178                 else
4179                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4180         } else {
4181                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4182                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4183                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4184         }
4185 }
4186
4187 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4188 {
4189         struct tg3 *tp = netdev_priv(dev);
4190         int err;
4191
4192         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4193                 return -EINVAL;
4194
4195         if (!netif_running(dev)) {
4196                 /* We'll just catch it later when the
4197                  * device is up'd.
4198                  */
4199                 tg3_set_mtu(dev, tp, new_mtu);
4200                 return 0;
4201         }
4202
4203         tg3_netif_stop(tp);
4204
4205         tg3_full_lock(tp, 1);
4206
4207         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4208
4209         tg3_set_mtu(dev, tp, new_mtu);
4210
4211         err = tg3_restart_hw(tp, 0);
4212
4213         if (!err)
4214                 tg3_netif_start(tp);
4215
4216         tg3_full_unlock(tp);
4217
4218         return err;
4219 }
4220
4221 /* Free up pending packets in all rx/tx rings.
4222  *
4223  * The chip has been shut down and the driver detached from
4224  * the networking, so no interrupts or new tx packets will
4225  * end up in the driver.  tp->{tx,}lock is not held and we are not
4226  * in an interrupt context and thus may sleep.
4227  */
4228 static void tg3_free_rings(struct tg3 *tp)
4229 {
4230         struct ring_info *rxp;
4231         int i;
4232
4233         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4234                 rxp = &tp->rx_std_buffers[i];
4235
4236                 if (rxp->skb == NULL)
4237                         continue;
4238                 pci_unmap_single(tp->pdev,
4239                                  pci_unmap_addr(rxp, mapping),
4240                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4241                                  PCI_DMA_FROMDEVICE);
4242                 dev_kfree_skb_any(rxp->skb);
4243                 rxp->skb = NULL;
4244         }
4245
4246         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4247                 rxp = &tp->rx_jumbo_buffers[i];
4248
4249                 if (rxp->skb == NULL)
4250                         continue;
4251                 pci_unmap_single(tp->pdev,
4252                                  pci_unmap_addr(rxp, mapping),
4253                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4254                                  PCI_DMA_FROMDEVICE);
4255                 dev_kfree_skb_any(rxp->skb);
4256                 rxp->skb = NULL;
4257         }
4258
4259         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4260                 struct tx_ring_info *txp;
4261                 struct sk_buff *skb;
4262                 int j;
4263
4264                 txp = &tp->tx_buffers[i];
4265                 skb = txp->skb;
4266
4267                 if (skb == NULL) {
4268                         i++;
4269                         continue;
4270                 }
4271
4272                 pci_unmap_single(tp->pdev,
4273                                  pci_unmap_addr(txp, mapping),
4274                                  skb_headlen(skb),
4275                                  PCI_DMA_TODEVICE);
4276                 txp->skb = NULL;
4277
4278                 i++;
4279
4280                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4281                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4282                         pci_unmap_page(tp->pdev,
4283                                        pci_unmap_addr(txp, mapping),
4284                                        skb_shinfo(skb)->frags[j].size,
4285                                        PCI_DMA_TODEVICE);
4286                         i++;
4287                 }
4288
4289                 dev_kfree_skb_any(skb);
4290         }
4291 }
4292
4293 /* Initialize tx/rx rings for packet processing.
4294  *
4295  * The chip has been shut down and the driver detached from
4296  * the networking, so no interrupts or new tx packets will
4297  * end up in the driver.  tp->{tx,}lock are held and thus
4298  * we may not sleep.
4299  */
4300 static int tg3_init_rings(struct tg3 *tp)
4301 {
4302         u32 i;
4303
4304         /* Free up all the SKBs. */
4305         tg3_free_rings(tp);
4306
4307         /* Zero out all descriptors. */
4308         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4309         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4310         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4311         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4312
4313         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4314         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4315             (tp->dev->mtu > ETH_DATA_LEN))
4316                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4317
4318         /* Initialize invariants of the rings, we only set this
4319          * stuff once.  This works because the card does not
4320          * write into the rx buffer posting rings.
4321          */
4322         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4323                 struct tg3_rx_buffer_desc *rxd;
4324
4325                 rxd = &tp->rx_std[i];
4326                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4327                         << RXD_LEN_SHIFT;
4328                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4329                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4330                                (i << RXD_OPAQUE_INDEX_SHIFT));
4331         }
4332
4333         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4334                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4335                         struct tg3_rx_buffer_desc *rxd;
4336
4337                         rxd = &tp->rx_jumbo[i];
4338                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4339                                 << RXD_LEN_SHIFT;
4340                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4341                                 RXD_FLAG_JUMBO;
4342                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4343                                (i << RXD_OPAQUE_INDEX_SHIFT));
4344                 }
4345         }
4346
4347         /* Now allocate fresh SKBs for each rx ring. */
4348         for (i = 0; i < tp->rx_pending; i++) {
4349                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4350                         printk(KERN_WARNING PFX
4351                                "%s: Using a smaller RX standard ring, "
4352                                "only %d out of %d buffers were allocated "
4353                                "successfully.\n",
4354                                tp->dev->name, i, tp->rx_pending);
4355                         if (i == 0)
4356                                 return -ENOMEM;
4357                         tp->rx_pending = i;
4358                         break;
4359                 }
4360         }
4361
4362         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4363                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4364                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4365                                              -1, i) < 0) {
4366                                 printk(KERN_WARNING PFX
4367                                        "%s: Using a smaller RX jumbo ring, "
4368                                        "only %d out of %d buffers were "
4369                                        "allocated successfully.\n",
4370                                        tp->dev->name, i, tp->rx_jumbo_pending);
4371                                 if (i == 0) {
4372                                         tg3_free_rings(tp);
4373                                         return -ENOMEM;
4374                                 }
4375                                 tp->rx_jumbo_pending = i;
4376                                 break;
4377                         }
4378                 }
4379         }
4380         return 0;
4381 }
4382
4383 /*
4384  * Must not be invoked with interrupt sources disabled and
4385  * the hardware shutdown down.
4386  */
4387 static void tg3_free_consistent(struct tg3 *tp)
4388 {
4389         kfree(tp->rx_std_buffers);
4390         tp->rx_std_buffers = NULL;
4391         if (tp->rx_std) {
4392                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4393                                     tp->rx_std, tp->rx_std_mapping);
4394                 tp->rx_std = NULL;
4395         }
4396         if (tp->rx_jumbo) {
4397                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4398                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4399                 tp->rx_jumbo = NULL;
4400         }
4401         if (tp->rx_rcb) {
4402                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4403                                     tp->rx_rcb, tp->rx_rcb_mapping);
4404                 tp->rx_rcb = NULL;
4405         }
4406         if (tp->tx_ring) {
4407                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4408                         tp->tx_ring, tp->tx_desc_mapping);
4409                 tp->tx_ring = NULL;
4410         }
4411         if (tp->hw_status) {
4412                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4413                                     tp->hw_status, tp->status_mapping);
4414                 tp->hw_status = NULL;
4415         }
4416         if (tp->hw_stats) {
4417                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4418                                     tp->hw_stats, tp->stats_mapping);
4419                 tp->hw_stats = NULL;
4420         }
4421 }
4422
4423 /*
4424  * Must not be invoked with interrupt sources disabled and
4425  * the hardware shutdown down.  Can sleep.
4426  */
4427 static int tg3_alloc_consistent(struct tg3 *tp)
4428 {
4429         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4430                                       (TG3_RX_RING_SIZE +
4431                                        TG3_RX_JUMBO_RING_SIZE)) +
4432                                      (sizeof(struct tx_ring_info) *
4433                                       TG3_TX_RING_SIZE),
4434                                      GFP_KERNEL);
4435         if (!tp->rx_std_buffers)
4436                 return -ENOMEM;
4437
4438         memset(tp->rx_std_buffers, 0,
4439                (sizeof(struct ring_info) *
4440                 (TG3_RX_RING_SIZE +
4441                  TG3_RX_JUMBO_RING_SIZE)) +
4442                (sizeof(struct tx_ring_info) *
4443                 TG3_TX_RING_SIZE));
4444
4445         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4446         tp->tx_buffers = (struct tx_ring_info *)
4447                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4448
4449         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4450                                           &tp->rx_std_mapping);
4451         if (!tp->rx_std)
4452                 goto err_out;
4453
4454         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4455                                             &tp->rx_jumbo_mapping);
4456
4457         if (!tp->rx_jumbo)
4458                 goto err_out;
4459
4460         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4461                                           &tp->rx_rcb_mapping);
4462         if (!tp->rx_rcb)
4463                 goto err_out;
4464
4465         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4466                                            &tp->tx_desc_mapping);
4467         if (!tp->tx_ring)
4468                 goto err_out;
4469
4470         tp->hw_status = pci_alloc_consistent(tp->pdev,
4471                                              TG3_HW_STATUS_SIZE,
4472                                              &tp->status_mapping);
4473         if (!tp->hw_status)
4474                 goto err_out;
4475
4476         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4477                                             sizeof(struct tg3_hw_stats),
4478                                             &tp->stats_mapping);
4479         if (!tp->hw_stats)
4480                 goto err_out;
4481
4482         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4483         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4484
4485         return 0;
4486
4487 err_out:
4488         tg3_free_consistent(tp);
4489         return -ENOMEM;
4490 }
4491
4492 #define MAX_WAIT_CNT 1000
4493
4494 /* To stop a block, clear the enable bit and poll till it
4495  * clears.  tp->lock is held.
4496  */
4497 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4498 {
4499         unsigned int i;
4500         u32 val;
4501
4502         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4503                 switch (ofs) {
4504                 case RCVLSC_MODE:
4505                 case DMAC_MODE:
4506                 case MBFREE_MODE:
4507                 case BUFMGR_MODE:
4508                 case MEMARB_MODE:
4509                         /* We can't enable/disable these bits of the
4510                          * 5705/5750, just say success.
4511                          */
4512                         return 0;
4513
4514                 default:
4515                         break;
4516                 };
4517         }
4518
4519         val = tr32(ofs);
4520         val &= ~enable_bit;
4521         tw32_f(ofs, val);
4522
4523         for (i = 0; i < MAX_WAIT_CNT; i++) {
4524                 udelay(100);
4525                 val = tr32(ofs);
4526                 if ((val & enable_bit) == 0)
4527                         break;
4528         }
4529
4530         if (i == MAX_WAIT_CNT && !silent) {
4531                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4532                        "ofs=%lx enable_bit=%x\n",
4533                        ofs, enable_bit);
4534                 return -ENODEV;
4535         }
4536
4537         return 0;
4538 }
4539
4540 /* tp->lock is held. */
4541 static int tg3_abort_hw(struct tg3 *tp, int silent)
4542 {
4543         int i, err;
4544
4545         tg3_disable_ints(tp);
4546
4547         tp->rx_mode &= ~RX_MODE_ENABLE;
4548         tw32_f(MAC_RX_MODE, tp->rx_mode);
4549         udelay(10);
4550
4551         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4552         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4553         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4554         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4555         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4556         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4557
4558         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4559         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4560         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4561         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4562         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4563         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4564         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4565
4566         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4567         tw32_f(MAC_MODE, tp->mac_mode);
4568         udelay(40);
4569
4570         tp->tx_mode &= ~TX_MODE_ENABLE;
4571         tw32_f(MAC_TX_MODE, tp->tx_mode);
4572
4573         for (i = 0; i < MAX_WAIT_CNT; i++) {
4574                 udelay(100);
4575                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4576                         break;
4577         }
4578         if (i >= MAX_WAIT_CNT) {
4579                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4580                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4581                        tp->dev->name, tr32(MAC_TX_MODE));
4582                 err |= -ENODEV;
4583         }
4584
4585         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4586         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4587         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4588
4589         tw32(FTQ_RESET, 0xffffffff);
4590         tw32(FTQ_RESET, 0x00000000);
4591
4592         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4593         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4594
4595         if (tp->hw_status)
4596                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4597         if (tp->hw_stats)
4598                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4599
4600         return err;
4601 }
4602
4603 /* tp->lock is held. */
4604 static int tg3_nvram_lock(struct tg3 *tp)
4605 {
4606         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4607                 int i;
4608
4609                 if (tp->nvram_lock_cnt == 0) {
4610                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4611                         for (i = 0; i < 8000; i++) {
4612                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4613                                         break;
4614                                 udelay(20);
4615                         }
4616                         if (i == 8000) {
4617                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4618                                 return -ENODEV;
4619                         }
4620                 }
4621                 tp->nvram_lock_cnt++;
4622         }
4623         return 0;
4624 }
4625
4626 /* tp->lock is held. */
4627 static void tg3_nvram_unlock(struct tg3 *tp)
4628 {
4629         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4630                 if (tp->nvram_lock_cnt > 0)
4631                         tp->nvram_lock_cnt--;
4632                 if (tp->nvram_lock_cnt == 0)
4633                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4634         }
4635 }
4636
4637 /* tp->lock is held. */
4638 static void tg3_enable_nvram_access(struct tg3 *tp)
4639 {
4640         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4641             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4642                 u32 nvaccess = tr32(NVRAM_ACCESS);
4643
4644                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4645         }
4646 }
4647
4648 /* tp->lock is held. */
4649 static void tg3_disable_nvram_access(struct tg3 *tp)
4650 {
4651         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4652             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4653                 u32 nvaccess = tr32(NVRAM_ACCESS);
4654
4655                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4656         }
4657 }
4658
4659 /* tp->lock is held. */
4660 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4661 {
4662         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4663                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4664
4665         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4666                 switch (kind) {
4667                 case RESET_KIND_INIT:
4668                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4669                                       DRV_STATE_START);
4670                         break;
4671
4672                 case RESET_KIND_SHUTDOWN:
4673                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4674                                       DRV_STATE_UNLOAD);
4675                         break;
4676
4677                 case RESET_KIND_SUSPEND:
4678                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4679                                       DRV_STATE_SUSPEND);
4680                         break;
4681
4682                 default:
4683                         break;
4684                 };
4685         }
4686 }
4687
4688 /* tp->lock is held. */
4689 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4690 {
4691         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4692                 switch (kind) {
4693                 case RESET_KIND_INIT:
4694                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4695                                       DRV_STATE_START_DONE);
4696                         break;
4697
4698                 case RESET_KIND_SHUTDOWN:
4699                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4700                                       DRV_STATE_UNLOAD_DONE);
4701                         break;
4702
4703                 default:
4704                         break;
4705                 };
4706         }
4707 }
4708
4709 /* tp->lock is held. */
4710 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4711 {
4712         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4713                 switch (kind) {
4714                 case RESET_KIND_INIT:
4715                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4716                                       DRV_STATE_START);
4717                         break;
4718
4719                 case RESET_KIND_SHUTDOWN:
4720                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4721                                       DRV_STATE_UNLOAD);
4722                         break;
4723
4724                 case RESET_KIND_SUSPEND:
4725                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4726                                       DRV_STATE_SUSPEND);
4727                         break;
4728
4729                 default:
4730                         break;
4731                 };
4732         }
4733 }
4734
4735 static int tg3_poll_fw(struct tg3 *tp)
4736 {
4737         int i;
4738         u32 val;
4739
4740         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4741                 /* Wait up to 20ms for init done. */
4742                 for (i = 0; i < 200; i++) {
4743                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4744                                 return 0;
4745                         udelay(100);
4746                 }
4747                 return -ENODEV;
4748         }
4749
4750         /* Wait for firmware initialization to complete. */
4751         for (i = 0; i < 100000; i++) {
4752                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4753                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4754                         break;
4755                 udelay(10);
4756         }
4757
4758         /* Chip might not be fitted with firmware.  Some Sun onboard
4759          * parts are configured like that.  So don't signal the timeout
4760          * of the above loop as an error, but do report the lack of
4761          * running firmware once.
4762          */
4763         if (i >= 100000 &&
4764             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4765                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4766
4767                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4768                        tp->dev->name);
4769         }
4770
4771         return 0;
4772 }
4773
4774 static void tg3_stop_fw(struct tg3 *);
4775
4776 /* tp->lock is held. */
4777 static int tg3_chip_reset(struct tg3 *tp)
4778 {
4779         u32 val;
4780         void (*write_op)(struct tg3 *, u32, u32);
4781         int err;
4782
4783         tg3_nvram_lock(tp);
4784
4785         /* No matching tg3_nvram_unlock() after this because
4786          * chip reset below will undo the nvram lock.
4787          */
4788         tp->nvram_lock_cnt = 0;
4789
4790         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4791             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4792             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4793                 tw32(GRC_FASTBOOT_PC, 0);
4794
4795         /*
4796          * We must avoid the readl() that normally takes place.
4797          * It locks machines, causes machine checks, and other
4798          * fun things.  So, temporarily disable the 5701
4799          * hardware workaround, while we do the reset.
4800          */
4801         write_op = tp->write32;
4802         if (write_op == tg3_write_flush_reg32)
4803                 tp->write32 = tg3_write32;
4804
4805         /* do the reset */
4806         val = GRC_MISC_CFG_CORECLK_RESET;
4807
4808         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4809                 if (tr32(0x7e2c) == 0x60) {
4810                         tw32(0x7e2c, 0x20);
4811                 }
4812                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4813                         tw32(GRC_MISC_CFG, (1 << 29));
4814                         val |= (1 << 29);
4815                 }
4816         }
4817
4818         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4819                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4820                 tw32(GRC_VCPU_EXT_CTRL,
4821                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4822         }
4823
4824         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4825                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4826         tw32(GRC_MISC_CFG, val);
4827
4828         /* restore 5701 hardware bug workaround write method */
4829         tp->write32 = write_op;
4830
4831         /* Unfortunately, we have to delay before the PCI read back.
4832          * Some 575X chips even will not respond to a PCI cfg access
4833          * when the reset command is given to the chip.
4834          *
4835          * How do these hardware designers expect things to work
4836          * properly if the PCI write is posted for a long period
4837          * of time?  It is always necessary to have some method by
4838          * which a register read back can occur to push the write
4839          * out which does the reset.
4840          *
4841          * For most tg3 variants the trick below was working.
4842          * Ho hum...
4843          */
4844         udelay(120);
4845
4846         /* Flush PCI posted writes.  The normal MMIO registers
4847          * are inaccessible at this time so this is the only
4848          * way to make this reliably (actually, this is no longer
4849          * the case, see above).  I tried to use indirect
4850          * register read/write but this upset some 5701 variants.
4851          */
4852         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4853
4854         udelay(120);
4855
4856         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4857                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4858                         int i;
4859                         u32 cfg_val;
4860
4861                         /* Wait for link training to complete.  */
4862                         for (i = 0; i < 5000; i++)
4863                                 udelay(100);
4864
4865                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4866                         pci_write_config_dword(tp->pdev, 0xc4,
4867                                                cfg_val | (1 << 15));
4868                 }
4869                 /* Set PCIE max payload size and clear error status.  */
4870                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4871         }
4872
4873         /* Re-enable indirect register accesses. */
4874         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4875                                tp->misc_host_ctrl);
4876
4877         /* Set MAX PCI retry to zero. */
4878         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4879         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4880             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4881                 val |= PCISTATE_RETRY_SAME_DMA;
4882         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4883
4884         pci_restore_state(tp->pdev);
4885
4886         /* Make sure PCI-X relaxed ordering bit is clear. */
4887         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4888         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4889         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4890
4891         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4892                 u32 val;
4893
4894                 /* Chip reset on 5780 will reset MSI enable bit,
4895                  * so need to restore it.
4896                  */
4897                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4898                         u16 ctrl;
4899
4900                         pci_read_config_word(tp->pdev,
4901                                              tp->msi_cap + PCI_MSI_FLAGS,
4902                                              &ctrl);
4903                         pci_write_config_word(tp->pdev,
4904                                               tp->msi_cap + PCI_MSI_FLAGS,
4905                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4906                         val = tr32(MSGINT_MODE);
4907                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4908                 }
4909
4910                 val = tr32(MEMARB_MODE);
4911                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4912
4913         } else
4914                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4915
4916         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4917                 tg3_stop_fw(tp);
4918                 tw32(0x5000, 0x400);
4919         }
4920
4921         tw32(GRC_MODE, tp->grc_mode);
4922
4923         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4924                 u32 val = tr32(0xc4);
4925
4926                 tw32(0xc4, val | (1 << 15));
4927         }
4928
4929         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4930             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4931                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4932                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4933                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4934                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4935         }
4936
4937         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4938                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4939                 tw32_f(MAC_MODE, tp->mac_mode);
4940         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4941                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4942                 tw32_f(MAC_MODE, tp->mac_mode);
4943         } else
4944                 tw32_f(MAC_MODE, 0);
4945         udelay(40);
4946
4947         err = tg3_poll_fw(tp);
4948         if (err)
4949                 return err;
4950
4951         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4952             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4953                 u32 val = tr32(0x7c00);
4954
4955                 tw32(0x7c00, val | (1 << 25));
4956         }
4957
4958         /* Reprobe ASF enable state.  */
4959         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4960         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4961         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4962         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4963                 u32 nic_cfg;
4964
4965                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4966                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4967                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4968                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4969                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4970                 }
4971         }
4972
4973         return 0;
4974 }
4975
4976 /* tp->lock is held. */
4977 static void tg3_stop_fw(struct tg3 *tp)
4978 {
4979         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4980                 u32 val;
4981                 int i;
4982
4983                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4984                 val = tr32(GRC_RX_CPU_EVENT);
4985                 val |= (1 << 14);
4986                 tw32(GRC_RX_CPU_EVENT, val);
4987
4988                 /* Wait for RX cpu to ACK the event.  */
4989                 for (i = 0; i < 100; i++) {
4990                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4991                                 break;
4992                         udelay(1);
4993                 }
4994         }
4995 }
4996
4997 /* tp->lock is held. */
4998 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4999 {
5000         int err;
5001
5002         tg3_stop_fw(tp);
5003
5004         tg3_write_sig_pre_reset(tp, kind);
5005
5006         tg3_abort_hw(tp, silent);
5007         err = tg3_chip_reset(tp);
5008
5009         tg3_write_sig_legacy(tp, kind);
5010         tg3_write_sig_post_reset(tp, kind);
5011
5012         if (err)
5013                 return err;
5014
5015         return 0;
5016 }
5017
5018 #define TG3_FW_RELEASE_MAJOR    0x0
5019 #define TG3_FW_RELASE_MINOR     0x0
5020 #define TG3_FW_RELEASE_FIX      0x0
5021 #define TG3_FW_START_ADDR       0x08000000
5022 #define TG3_FW_TEXT_ADDR        0x08000000
5023 #define TG3_FW_TEXT_LEN         0x9c0
5024 #define TG3_FW_RODATA_ADDR      0x080009c0
5025 #define TG3_FW_RODATA_LEN       0x60
5026 #define TG3_FW_DATA_ADDR        0x08000a40
5027 #define TG3_FW_DATA_LEN         0x20
5028 #define TG3_FW_SBSS_ADDR        0x08000a60
5029 #define TG3_FW_SBSS_LEN         0xc
5030 #define TG3_FW_BSS_ADDR         0x08000a70
5031 #define TG3_FW_BSS_LEN          0x10
5032
5033 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5034         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5035         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5036         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5037         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5038         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5039         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5040         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5041         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5042         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5043         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5044         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5045         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5046         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5047         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5048         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5049         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5050         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5051         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5052         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5053         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5054         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5055         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5056         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5057         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5058         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5059         0, 0, 0, 0, 0, 0,
5060         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5061         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5062         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5063         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5064         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5065         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5066         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5067         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5068         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5069         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5070         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5071         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5072         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5073         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5074         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5075         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5076         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5077         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5078         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5079         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5080         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5081         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5082         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5083         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5084         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5085         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5086         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5087         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5088         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5089         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5090         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5091         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5092         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5093         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5094         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5095         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5096         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5097         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5098         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5099         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5100         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5101         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5102         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5103         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5104         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5105         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5106         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5107         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5108         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5109         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5110         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5111         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5112         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5113         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5114         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5115         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5116         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5117         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5118         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5119         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5120         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5121         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5122         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5123         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5124         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5125 };
5126
5127 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5128         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5129         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5130         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5131         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5132         0x00000000
5133 };
5134
5135 #if 0 /* All zeros, don't eat up space with it. */
5136 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5137         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5138         0x00000000, 0x00000000, 0x00000000, 0x00000000
5139 };
5140 #endif
5141
5142 #define RX_CPU_SCRATCH_BASE     0x30000
5143 #define RX_CPU_SCRATCH_SIZE     0x04000
5144 #define TX_CPU_SCRATCH_BASE     0x34000
5145 #define TX_CPU_SCRATCH_SIZE     0x04000
5146
5147 /* tp->lock is held. */
5148 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5149 {
5150         int i;
5151
5152         BUG_ON(offset == TX_CPU_BASE &&
5153             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5154
5155         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5156                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5157
5158                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5159                 return 0;
5160         }
5161         if (offset == RX_CPU_BASE) {
5162                 for (i = 0; i < 10000; i++) {
5163                         tw32(offset + CPU_STATE, 0xffffffff);
5164                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5165                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5166                                 break;
5167                 }
5168
5169                 tw32(offset + CPU_STATE, 0xffffffff);
5170                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5171                 udelay(10);
5172         } else {
5173                 for (i = 0; i < 10000; i++) {
5174                         tw32(offset + CPU_STATE, 0xffffffff);
5175                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5176                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5177                                 break;
5178                 }
5179         }
5180
5181         if (i >= 10000) {
5182                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5183                        "and %s CPU\n",
5184                        tp->dev->name,
5185                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5186                 return -ENODEV;
5187         }
5188
5189         /* Clear firmware's nvram arbitration. */
5190         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5191                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5192         return 0;
5193 }
5194
5195 struct fw_info {
5196         unsigned int text_base;
5197         unsigned int text_len;
5198         const u32 *text_data;
5199         unsigned int rodata_base;
5200         unsigned int rodata_len;
5201         const u32 *rodata_data;
5202         unsigned int data_base;
5203         unsigned int data_len;
5204         const u32 *data_data;
5205 };
5206
5207 /* tp->lock is held. */
5208 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5209                                  int cpu_scratch_size, struct fw_info *info)
5210 {
5211         int err, lock_err, i;
5212         void (*write_op)(struct tg3 *, u32, u32);
5213
5214         if (cpu_base == TX_CPU_BASE &&
5215             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5216                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5217                        "TX cpu firmware on %s which is 5705.\n",
5218                        tp->dev->name);
5219                 return -EINVAL;
5220         }
5221
5222         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5223                 write_op = tg3_write_mem;
5224         else
5225                 write_op = tg3_write_indirect_reg32;
5226
5227         /* It is possible that bootcode is still loading at this point.
5228          * Get the nvram lock first before halting the cpu.
5229          */
5230         lock_err = tg3_nvram_lock(tp);
5231         err = tg3_halt_cpu(tp, cpu_base);
5232         if (!lock_err)
5233                 tg3_nvram_unlock(tp);
5234         if (err)
5235                 goto out;
5236
5237         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5238                 write_op(tp, cpu_scratch_base + i, 0);
5239         tw32(cpu_base + CPU_STATE, 0xffffffff);
5240         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5241         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5242                 write_op(tp, (cpu_scratch_base +
5243                               (info->text_base & 0xffff) +
5244                               (i * sizeof(u32))),
5245                          (info->text_data ?
5246                           info->text_data[i] : 0));
5247         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5248                 write_op(tp, (cpu_scratch_base +
5249                               (info->rodata_base & 0xffff) +
5250                               (i * sizeof(u32))),
5251                          (info->rodata_data ?
5252                           info->rodata_data[i] : 0));
5253         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5254                 write_op(tp, (cpu_scratch_base +
5255                               (info->data_base & 0xffff) +
5256                               (i * sizeof(u32))),
5257                          (info->data_data ?
5258                           info->data_data[i] : 0));
5259
5260         err = 0;
5261
5262 out:
5263         return err;
5264 }
5265
5266 /* tp->lock is held. */
5267 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5268 {
5269         struct fw_info info;
5270         int err, i;
5271
5272         info.text_base = TG3_FW_TEXT_ADDR;
5273         info.text_len = TG3_FW_TEXT_LEN;
5274         info.text_data = &tg3FwText[0];
5275         info.rodata_base = TG3_FW_RODATA_ADDR;
5276         info.rodata_len = TG3_FW_RODATA_LEN;
5277         info.rodata_data = &tg3FwRodata[0];
5278         info.data_base = TG3_FW_DATA_ADDR;
5279         info.data_len = TG3_FW_DATA_LEN;
5280         info.data_data = NULL;
5281
5282         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5283                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5284                                     &info);
5285         if (err)
5286                 return err;
5287
5288         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5289                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5290                                     &info);
5291         if (err)
5292                 return err;
5293
5294         /* Now startup only the RX cpu. */
5295         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5296         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5297
5298         for (i = 0; i < 5; i++) {
5299                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5300                         break;
5301                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5302                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5303                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5304                 udelay(1000);
5305         }
5306         if (i >= 5) {
5307                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5308                        "to set RX CPU PC, is %08x should be %08x\n",
5309                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5310                        TG3_FW_TEXT_ADDR);
5311                 return -ENODEV;
5312         }
5313         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5314         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5315
5316         return 0;
5317 }
5318
5319 #if TG3_TSO_SUPPORT != 0
5320
5321 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5322 #define TG3_TSO_FW_RELASE_MINOR         0x6
5323 #define TG3_TSO_FW_RELEASE_FIX          0x0
5324 #define TG3_TSO_FW_START_ADDR           0x08000000
5325 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5326 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5327 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5328 #define TG3_TSO_FW_RODATA_LEN           0x60
5329 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5330 #define TG3_TSO_FW_DATA_LEN             0x30
5331 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5332 #define TG3_TSO_FW_SBSS_LEN             0x2c
5333 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5334 #define TG3_TSO_FW_BSS_LEN              0x894
5335
5336 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5337         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5338         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5339         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5340         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5341         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5342         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5343         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5344         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5345         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5346         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5347         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5348         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5349         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5350         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5351         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5352         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5353         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5354         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5355         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5356         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5357         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5358         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5359         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5360         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5361         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5362         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5363         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5364         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5365         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5366         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5367         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5368         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5369         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5370         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5371         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5372         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5373         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5374         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5375         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5376         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5377         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5378         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5379         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5380         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5381         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5382         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5383         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5384         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5385         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5386         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5387         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5388         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5389         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5390         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5391         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5392         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5393         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5394         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5395         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5396         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5397         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5398         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5399         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5400         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5401         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5402         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5403         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5404         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5405         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5406         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5407         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5408         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5409         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5410         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5411         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5412         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5413         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5414         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5415         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5416         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5417         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5418         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5419         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5420         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5421         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5422         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5423         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5424         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5425         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5426         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5427         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5428         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5429         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5430         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5431         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5432         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5433         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5434         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5435         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5436         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5437         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5438         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5439         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5440         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5441         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5442         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5443         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5444         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5445         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5446         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5447         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5448         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5449         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5450         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5451         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5452         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5453         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5454         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5455         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5456         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5457         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5458         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5459         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5460         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5461         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5462         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5463         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5464         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5465         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5466         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5467         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5468         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5469         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5470         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5471         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5472         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5473         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5474         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5475         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5476         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5477         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5478         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5479         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5480         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5481         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5482         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5483         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5484         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5485         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5486         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5487         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5488         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5489         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5490         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5491         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5492         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5493         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5494         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5495         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5496         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5497         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5498         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5499         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5500         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5501         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5502         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5503         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5504         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5505         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5506         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5507         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5508         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5509         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5510         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5511         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5512         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5513         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5514         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5515         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5516         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5517         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5518         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5519         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5520         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5521         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5522         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5523         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5524         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5525         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5526         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5527         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5528         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5529         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5530         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5531         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5532         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5533         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5534         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5535         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5536         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5537         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5538         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5539         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5540         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5541         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5542         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5543         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5544         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5545         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5546         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5547         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5548         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5549         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5550         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5551         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5552         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5553         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5554         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5555         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5556         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5557         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5558         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5559         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5560         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5561         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5562         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5563         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5564         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5565         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5566         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5567         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5568         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5569         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5570         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5571         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5572         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5573         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5574         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5575         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5576         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5577         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5578         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5579         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5580         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5581         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5582         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5583         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5584         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5585         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5586         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5587         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5588         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5589         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5590         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5591         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5592         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5593         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5594         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5595         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5596         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5597         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5598         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5599         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5600         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5601         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5602         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5603         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5604         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5605         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5606         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5607         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5608         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5609         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5610         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5611         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5612         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5613         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5614         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5615         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5616         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5617         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5618         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5619         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5620         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5621 };
5622
5623 static const u32 tg3TsoFwRodata[] = {
5624         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5625         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5626         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5627         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5628         0x00000000,
5629 };
5630
5631 static const u32 tg3TsoFwData[] = {
5632         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5633         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5634         0x00000000,
5635 };
5636
5637 /* 5705 needs a special version of the TSO firmware.  */
5638 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5639 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5640 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5641 #define TG3_TSO5_FW_START_ADDR          0x00010000
5642 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5643 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5644 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5645 #define TG3_TSO5_FW_RODATA_LEN          0x50
5646 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5647 #define TG3_TSO5_FW_DATA_LEN            0x20
5648 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5649 #define TG3_TSO5_FW_SBSS_LEN            0x28
5650 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5651 #define TG3_TSO5_FW_BSS_LEN             0x88
5652
5653 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5654         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5655         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5656         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5657         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5658         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5659         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5660         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5661         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5662         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5663         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5664         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5665         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5666         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5667         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5668         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5669         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5670         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5671         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5672         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5673         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5674         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5675         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5676         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5677         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5678         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5679         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5680         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5681         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5682         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5683         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5684         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5685         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5686         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5687         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5688         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5689         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5690         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5691         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5692         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5693         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5694         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5695         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5696         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5697         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5698         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5699         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5700         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5701         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5702         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5703         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5704         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5705         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5706         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5707         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5708         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5709         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5710         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5711         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5712         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5713         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5714         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5715         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5716         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5717         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5718         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5719         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5720         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5721         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5722         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5723         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5724         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5725         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5726         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5727         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5728         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5729         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5730         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5731         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5732         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5733         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5734         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5735         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5736         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5737         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5738         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5739         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5740         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5741         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5742         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5743         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5744         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5745         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5746         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5747         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5748         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5749         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5750         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5751         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5752         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5753         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5754         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5755         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5756         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5757         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5758         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5759         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5760         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5761         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5762         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5763         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5764         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5765         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5766         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5767         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5768         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5769         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5770         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5771         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5772         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5773         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5774         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5775         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5776         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5777         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5778         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5779         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5780         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5781         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5782         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5783         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5784         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5785         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5786         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5787         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5788         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5789         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5790         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5791         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5792         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5793         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5794         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5795         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5796         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5797         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5798         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5799         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5800         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5801         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5802         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5803         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5804         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5805         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5806         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5807         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5808         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5809         0x00000000, 0x00000000, 0x00000000,
5810 };
5811
5812 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5813         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5814         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5815         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5816         0x00000000, 0x00000000, 0x00000000,
5817 };
5818
5819 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5820         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5821         0x00000000, 0x00000000, 0x00000000,
5822 };
5823
5824 /* tp->lock is held. */
5825 static int tg3_load_tso_firmware(struct tg3 *tp)
5826 {
5827         struct fw_info info;
5828         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5829         int err, i;
5830
5831         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5832                 return 0;
5833
5834         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5835                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5836                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5837                 info.text_data = &tg3Tso5FwText[0];
5838                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5839                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5840                 info.rodata_data = &tg3Tso5FwRodata[0];
5841                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5842                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5843                 info.data_data = &tg3Tso5FwData[0];
5844                 cpu_base = RX_CPU_BASE;
5845                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5846                 cpu_scratch_size = (info.text_len +
5847                                     info.rodata_len +
5848                                     info.data_len +
5849                                     TG3_TSO5_FW_SBSS_LEN +
5850                                     TG3_TSO5_FW_BSS_LEN);
5851         } else {
5852                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5853                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5854                 info.text_data = &tg3TsoFwText[0];
5855                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5856                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5857                 info.rodata_data = &tg3TsoFwRodata[0];
5858                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5859                 info.data_len = TG3_TSO_FW_DATA_LEN;
5860                 info.data_data = &tg3TsoFwData[0];
5861                 cpu_base = TX_CPU_BASE;
5862                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5863                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5864         }
5865
5866         err = tg3_load_firmware_cpu(tp, cpu_base,
5867                                     cpu_scratch_base, cpu_scratch_size,
5868                                     &info);
5869         if (err)
5870                 return err;
5871
5872         /* Now startup the cpu. */
5873         tw32(cpu_base + CPU_STATE, 0xffffffff);
5874         tw32_f(cpu_base + CPU_PC,    info.text_base);
5875
5876         for (i = 0; i < 5; i++) {
5877                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5878                         break;
5879                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5880                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5881                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5882                 udelay(1000);
5883         }
5884         if (i >= 5) {
5885                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5886                        "to set CPU PC, is %08x should be %08x\n",
5887                        tp->dev->name, tr32(cpu_base + CPU_PC),
5888                        info.text_base);
5889                 return -ENODEV;
5890         }
5891         tw32(cpu_base + CPU_STATE, 0xffffffff);
5892         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5893         return 0;
5894 }
5895
5896 #endif /* TG3_TSO_SUPPORT != 0 */
5897
5898 /* tp->lock is held. */
5899 static void __tg3_set_mac_addr(struct tg3 *tp)
5900 {
5901         u32 addr_high, addr_low;
5902         int i;
5903
5904         addr_high = ((tp->dev->dev_addr[0] << 8) |
5905                      tp->dev->dev_addr[1]);
5906         addr_low = ((tp->dev->dev_addr[2] << 24) |
5907                     (tp->dev->dev_addr[3] << 16) |
5908                     (tp->dev->dev_addr[4] <<  8) |
5909                     (tp->dev->dev_addr[5] <<  0));
5910         for (i = 0; i < 4; i++) {
5911                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5912                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5913         }
5914
5915         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5916             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5917                 for (i = 0; i < 12; i++) {
5918                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5919                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5920                 }
5921         }
5922
5923         addr_high = (tp->dev->dev_addr[0] +
5924                      tp->dev->dev_addr[1] +
5925                      tp->dev->dev_addr[2] +
5926                      tp->dev->dev_addr[3] +
5927                      tp->dev->dev_addr[4] +
5928                      tp->dev->dev_addr[5]) &
5929                 TX_BACKOFF_SEED_MASK;
5930         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5931 }
5932
5933 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5934 {
5935         struct tg3 *tp = netdev_priv(dev);
5936         struct sockaddr *addr = p;
5937         int err = 0;
5938
5939         if (!is_valid_ether_addr(addr->sa_data))
5940                 return -EINVAL;
5941
5942         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5943
5944         if (!netif_running(dev))
5945                 return 0;
5946
5947         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5948                 /* Reset chip so that ASF can re-init any MAC addresses it
5949                  * needs.
5950                  */
5951                 tg3_netif_stop(tp);
5952                 tg3_full_lock(tp, 1);
5953
5954                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5955                 err = tg3_restart_hw(tp, 0);
5956                 if (!err)
5957                         tg3_netif_start(tp);
5958                 tg3_full_unlock(tp);
5959         } else {
5960                 spin_lock_bh(&tp->lock);
5961                 __tg3_set_mac_addr(tp);
5962                 spin_unlock_bh(&tp->lock);
5963         }
5964
5965         return err;
5966 }
5967
5968 /* tp->lock is held. */
5969 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5970                            dma_addr_t mapping, u32 maxlen_flags,
5971                            u32 nic_addr)
5972 {
5973         tg3_write_mem(tp,
5974                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5975                       ((u64) mapping >> 32));
5976         tg3_write_mem(tp,
5977                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5978                       ((u64) mapping & 0xffffffff));
5979         tg3_write_mem(tp,
5980                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5981                        maxlen_flags);
5982
5983         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5984                 tg3_write_mem(tp,
5985                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5986                               nic_addr);
5987 }
5988
5989 static void __tg3_set_rx_mode(struct net_device *);
5990 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5991 {
5992         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5993         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5994         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5995         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5996         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5997                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5998                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5999         }
6000         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6001         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6002         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6003                 u32 val = ec->stats_block_coalesce_usecs;
6004
6005                 if (!netif_carrier_ok(tp->dev))
6006                         val = 0;
6007
6008                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6009         }
6010 }
6011
6012 /* tp->lock is held. */
6013 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6014 {
6015         u32 val, rdmac_mode;
6016         int i, err, limit;
6017
6018         tg3_disable_ints(tp);
6019
6020         tg3_stop_fw(tp);
6021
6022         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6023
6024         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6025                 tg3_abort_hw(tp, 1);
6026         }
6027
6028         if (reset_phy)
6029                 tg3_phy_reset(tp);
6030
6031         err = tg3_chip_reset(tp);
6032         if (err)
6033                 return err;
6034
6035         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6036
6037         /* This works around an issue with Athlon chipsets on
6038          * B3 tigon3 silicon.  This bit has no effect on any
6039          * other revision.  But do not set this on PCI Express
6040          * chips.
6041          */
6042         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6043                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6044         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6045
6046         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6047             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6048                 val = tr32(TG3PCI_PCISTATE);
6049                 val |= PCISTATE_RETRY_SAME_DMA;
6050                 tw32(TG3PCI_PCISTATE, val);
6051         }
6052
6053         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6054                 /* Enable some hw fixes.  */
6055                 val = tr32(TG3PCI_MSI_DATA);
6056                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6057                 tw32(TG3PCI_MSI_DATA, val);
6058         }
6059
6060         /* Descriptor ring init may make accesses to the
6061          * NIC SRAM area to setup the TX descriptors, so we
6062          * can only do this after the hardware has been
6063          * successfully reset.
6064          */
6065         err = tg3_init_rings(tp);
6066         if (err)
6067                 return err;
6068
6069         /* This value is determined during the probe time DMA
6070          * engine test, tg3_test_dma.
6071          */
6072         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6073
6074         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6075                           GRC_MODE_4X_NIC_SEND_RINGS |
6076                           GRC_MODE_NO_TX_PHDR_CSUM |
6077                           GRC_MODE_NO_RX_PHDR_CSUM);
6078         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6079
6080         /* Pseudo-header checksum is done by hardware logic and not
6081          * the offload processers, so make the chip do the pseudo-
6082          * header checksums on receive.  For transmit it is more
6083          * convenient to do the pseudo-header checksum in software
6084          * as Linux does that on transmit for us in all cases.
6085          */
6086         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6087
6088         tw32(GRC_MODE,
6089              tp->grc_mode |
6090              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6091
6092         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6093         val = tr32(GRC_MISC_CFG);
6094         val &= ~0xff;
6095         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6096         tw32(GRC_MISC_CFG, val);
6097
6098         /* Initialize MBUF/DESC pool. */
6099         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6100                 /* Do nothing.  */
6101         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6102                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6103                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6104                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6105                 else
6106                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6107                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6108                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6109         }
6110 #if TG3_TSO_SUPPORT != 0
6111         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6112                 int fw_len;
6113
6114                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6115                           TG3_TSO5_FW_RODATA_LEN +
6116                           TG3_TSO5_FW_DATA_LEN +
6117                           TG3_TSO5_FW_SBSS_LEN +
6118                           TG3_TSO5_FW_BSS_LEN);
6119                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6120                 tw32(BUFMGR_MB_POOL_ADDR,
6121                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6122                 tw32(BUFMGR_MB_POOL_SIZE,
6123                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6124         }
6125 #endif
6126
6127         if (tp->dev->mtu <= ETH_DATA_LEN) {
6128                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6129                      tp->bufmgr_config.mbuf_read_dma_low_water);
6130                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6131                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6132                 tw32(BUFMGR_MB_HIGH_WATER,
6133                      tp->bufmgr_config.mbuf_high_water);
6134         } else {
6135                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6136                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6137                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6138                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6139                 tw32(BUFMGR_MB_HIGH_WATER,
6140                      tp->bufmgr_config.mbuf_high_water_jumbo);
6141         }
6142         tw32(BUFMGR_DMA_LOW_WATER,
6143              tp->bufmgr_config.dma_low_water);
6144         tw32(BUFMGR_DMA_HIGH_WATER,
6145              tp->bufmgr_config.dma_high_water);
6146
6147         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6148         for (i = 0; i < 2000; i++) {
6149                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6150                         break;
6151                 udelay(10);
6152         }
6153         if (i >= 2000) {
6154                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6155                        tp->dev->name);
6156                 return -ENODEV;
6157         }
6158
6159         /* Setup replenish threshold. */
6160         val = tp->rx_pending / 8;
6161         if (val == 0)
6162                 val = 1;
6163         else if (val > tp->rx_std_max_post)
6164                 val = tp->rx_std_max_post;
6165         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6166                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6167                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6168
6169                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6170                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6171         }
6172
6173         tw32(RCVBDI_STD_THRESH, val);
6174
6175         /* Initialize TG3_BDINFO's at:
6176          *  RCVDBDI_STD_BD:     standard eth size rx ring
6177          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6178          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6179          *
6180          * like so:
6181          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6182          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6183          *                              ring attribute flags
6184          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6185          *
6186          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6187          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6188          *
6189          * The size of each ring is fixed in the firmware, but the location is
6190          * configurable.
6191          */
6192         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6193              ((u64) tp->rx_std_mapping >> 32));
6194         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6195              ((u64) tp->rx_std_mapping & 0xffffffff));
6196         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6197              NIC_SRAM_RX_BUFFER_DESC);
6198
6199         /* Don't even try to program the JUMBO/MINI buffer descriptor
6200          * configs on 5705.
6201          */
6202         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6203                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6204                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6205         } else {
6206                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6207                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6208
6209                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6210                      BDINFO_FLAGS_DISABLED);
6211
6212                 /* Setup replenish threshold. */
6213                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6214
6215                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6216                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6217                              ((u64) tp->rx_jumbo_mapping >> 32));
6218                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6219                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6220                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6221                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6222                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6223                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6224                 } else {
6225                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6226                              BDINFO_FLAGS_DISABLED);
6227                 }
6228
6229         }
6230
6231         /* There is only one send ring on 5705/5750, no need to explicitly
6232          * disable the others.
6233          */
6234         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6235                 /* Clear out send RCB ring in SRAM. */
6236                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6237                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6238                                       BDINFO_FLAGS_DISABLED);
6239         }
6240
6241         tp->tx_prod = 0;
6242         tp->tx_cons = 0;
6243         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6244         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6245
6246         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6247                        tp->tx_desc_mapping,
6248                        (TG3_TX_RING_SIZE <<
6249                         BDINFO_FLAGS_MAXLEN_SHIFT),
6250                        NIC_SRAM_TX_BUFFER_DESC);
6251
6252         /* There is only one receive return ring on 5705/5750, no need
6253          * to explicitly disable the others.
6254          */
6255         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6256                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6257                      i += TG3_BDINFO_SIZE) {
6258                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6259                                       BDINFO_FLAGS_DISABLED);
6260                 }
6261         }
6262
6263         tp->rx_rcb_ptr = 0;
6264         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6265
6266         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6267                        tp->rx_rcb_mapping,
6268                        (TG3_RX_RCB_RING_SIZE(tp) <<
6269                         BDINFO_FLAGS_MAXLEN_SHIFT),
6270                        0);
6271
6272         tp->rx_std_ptr = tp->rx_pending;
6273         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6274                      tp->rx_std_ptr);
6275
6276         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6277                                                 tp->rx_jumbo_pending : 0;
6278         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6279                      tp->rx_jumbo_ptr);
6280
6281         /* Initialize MAC address and backoff seed. */
6282         __tg3_set_mac_addr(tp);
6283
6284         /* MTU + ethernet header + FCS + optional VLAN tag */
6285         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6286
6287         /* The slot time is changed by tg3_setup_phy if we
6288          * run at gigabit with half duplex.
6289          */
6290         tw32(MAC_TX_LENGTHS,
6291              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6292              (6 << TX_LENGTHS_IPG_SHIFT) |
6293              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6294
6295         /* Receive rules. */
6296         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6297         tw32(RCVLPC_CONFIG, 0x0181);
6298
6299         /* Calculate RDMAC_MODE setting early, we need it to determine
6300          * the RCVLPC_STATE_ENABLE mask.
6301          */
6302         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6303                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6304                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6305                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6306                       RDMAC_MODE_LNGREAD_ENAB);
6307         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6308                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
6309
6310         /* If statement applies to 5705 and 5750 PCI devices only */
6311         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6312              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6313             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6314                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6315                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6316                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6317                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6318                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6319                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6320                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6321                 }
6322         }
6323
6324         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6325                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6326
6327 #if TG3_TSO_SUPPORT != 0
6328         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6329                 rdmac_mode |= (1 << 27);
6330 #endif
6331
6332         /* Receive/send statistics. */
6333         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6334                 val = tr32(RCVLPC_STATS_ENABLE);
6335                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6336                 tw32(RCVLPC_STATS_ENABLE, val);
6337         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6338                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6339                 val = tr32(RCVLPC_STATS_ENABLE);
6340                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6341                 tw32(RCVLPC_STATS_ENABLE, val);
6342         } else {
6343                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6344         }
6345         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6346         tw32(SNDDATAI_STATSENAB, 0xffffff);
6347         tw32(SNDDATAI_STATSCTRL,
6348              (SNDDATAI_SCTRL_ENABLE |
6349               SNDDATAI_SCTRL_FASTUPD));
6350
6351         /* Setup host coalescing engine. */
6352         tw32(HOSTCC_MODE, 0);
6353         for (i = 0; i < 2000; i++) {
6354                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6355                         break;
6356                 udelay(10);
6357         }
6358
6359         __tg3_set_coalesce(tp, &tp->coal);
6360
6361         /* set status block DMA address */
6362         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6363              ((u64) tp->status_mapping >> 32));
6364         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6365              ((u64) tp->status_mapping & 0xffffffff));
6366
6367         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6368                 /* Status/statistics block address.  See tg3_timer,
6369                  * the tg3_periodic_fetch_stats call there, and
6370                  * tg3_get_stats to see how this works for 5705/5750 chips.
6371                  */
6372                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6373                      ((u64) tp->stats_mapping >> 32));
6374                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6375                      ((u64) tp->stats_mapping & 0xffffffff));
6376                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6377                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6378         }
6379
6380         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6381
6382         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6383         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6384         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6385                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6386
6387         /* Clear statistics/status block in chip, and status block in ram. */
6388         for (i = NIC_SRAM_STATS_BLK;
6389              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6390              i += sizeof(u32)) {
6391                 tg3_write_mem(tp, i, 0);
6392                 udelay(40);
6393         }
6394         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6395
6396         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6397                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6398                 /* reset to prevent losing 1st rx packet intermittently */
6399                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6400                 udelay(10);
6401         }
6402
6403         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6404                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6405         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6406         udelay(40);
6407
6408         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6409          * If TG3_FLG2_IS_NIC is zero, we should read the
6410          * register to preserve the GPIO settings for LOMs. The GPIOs,
6411          * whether used as inputs or outputs, are set by boot code after
6412          * reset.
6413          */
6414         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6415                 u32 gpio_mask;
6416
6417                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6418                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6419                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6420
6421                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6422                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6423                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6424
6425                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6426                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6427
6428                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6429
6430                 /* GPIO1 must be driven high for eeprom write protect */
6431                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6432                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6433                                                GRC_LCLCTRL_GPIO_OUTPUT1);
6434         }
6435         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6436         udelay(100);
6437
6438         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6439         tp->last_tag = 0;
6440
6441         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6442                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6443                 udelay(40);
6444         }
6445
6446         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6447                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6448                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6449                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6450                WDMAC_MODE_LNGREAD_ENAB);
6451
6452         /* If statement applies to 5705 and 5750 PCI devices only */
6453         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6454              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6455             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6456                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6457                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6458                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6459                         /* nothing */
6460                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6461                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6462                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6463                         val |= WDMAC_MODE_RX_ACCEL;
6464                 }
6465         }
6466
6467         /* Enable host coalescing bug fix */
6468         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6469             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6470                 val |= (1 << 29);
6471
6472         tw32_f(WDMAC_MODE, val);
6473         udelay(40);
6474
6475         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6476                 val = tr32(TG3PCI_X_CAPS);
6477                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6478                         val &= ~PCIX_CAPS_BURST_MASK;
6479                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6480                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6481                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6482                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6483                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6484                                 val |= (tp->split_mode_max_reqs <<
6485                                         PCIX_CAPS_SPLIT_SHIFT);
6486                 }
6487                 tw32(TG3PCI_X_CAPS, val);
6488         }
6489
6490         tw32_f(RDMAC_MODE, rdmac_mode);
6491         udelay(40);
6492
6493         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6494         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6495                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6496         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6497         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6498         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6499         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6500         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6501 #if TG3_TSO_SUPPORT != 0
6502         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6503                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6504 #endif
6505         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6506         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6507
6508         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6509                 err = tg3_load_5701_a0_firmware_fix(tp);
6510                 if (err)
6511                         return err;
6512         }
6513
6514 #if TG3_TSO_SUPPORT != 0
6515         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6516                 err = tg3_load_tso_firmware(tp);
6517                 if (err)
6518                         return err;
6519         }
6520 #endif
6521
6522         tp->tx_mode = TX_MODE_ENABLE;
6523         tw32_f(MAC_TX_MODE, tp->tx_mode);
6524         udelay(100);
6525
6526         tp->rx_mode = RX_MODE_ENABLE;
6527         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6528                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6529
6530         tw32_f(MAC_RX_MODE, tp->rx_mode);
6531         udelay(10);
6532
6533         if (tp->link_config.phy_is_low_power) {
6534                 tp->link_config.phy_is_low_power = 0;
6535                 tp->link_config.speed = tp->link_config.orig_speed;
6536                 tp->link_config.duplex = tp->link_config.orig_duplex;
6537                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6538         }
6539
6540         tp->mi_mode = MAC_MI_MODE_BASE;
6541         tw32_f(MAC_MI_MODE, tp->mi_mode);
6542         udelay(80);
6543
6544         tw32(MAC_LED_CTRL, tp->led_ctrl);
6545
6546         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6547         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6548                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6549                 udelay(10);
6550         }
6551         tw32_f(MAC_RX_MODE, tp->rx_mode);
6552         udelay(10);
6553
6554         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6555                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6556                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6557                         /* Set drive transmission level to 1.2V  */
6558                         /* only if the signal pre-emphasis bit is not set  */
6559                         val = tr32(MAC_SERDES_CFG);
6560                         val &= 0xfffff000;
6561                         val |= 0x880;
6562                         tw32(MAC_SERDES_CFG, val);
6563                 }
6564                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6565                         tw32(MAC_SERDES_CFG, 0x616000);
6566         }
6567
6568         /* Prevent chip from dropping frames when flow control
6569          * is enabled.
6570          */
6571         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6572
6573         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6574             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6575                 /* Use hardware link auto-negotiation */
6576                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6577         }
6578
6579         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6580             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6581                 u32 tmp;
6582
6583                 tmp = tr32(SERDES_RX_CTRL);
6584                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6585                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6586                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6587                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6588         }
6589
6590         err = tg3_setup_phy(tp, 0);
6591         if (err)
6592                 return err;
6593
6594         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6595             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6596                 u32 tmp;
6597
6598                 /* Clear CRC stats. */
6599                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6600                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
6601                         tg3_readphy(tp, 0x14, &tmp);
6602                 }
6603         }
6604
6605         __tg3_set_rx_mode(tp->dev);
6606
6607         /* Initialize receive rules. */
6608         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6609         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6610         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6611         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6612
6613         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6614             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6615                 limit = 8;
6616         else
6617                 limit = 16;
6618         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6619                 limit -= 4;
6620         switch (limit) {
6621         case 16:
6622                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6623         case 15:
6624                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6625         case 14:
6626                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6627         case 13:
6628                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6629         case 12:
6630                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6631         case 11:
6632                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6633         case 10:
6634                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6635         case 9:
6636                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6637         case 8:
6638                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6639         case 7:
6640                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6641         case 6:
6642                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6643         case 5:
6644                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6645         case 4:
6646                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6647         case 3:
6648                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6649         case 2:
6650         case 1:
6651
6652         default:
6653                 break;
6654         };
6655
6656         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6657
6658         return 0;
6659 }
6660
6661 /* Called at device open time to get the chip ready for
6662  * packet processing.  Invoked with tp->lock held.
6663  */
6664 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6665 {
6666         int err;
6667
6668         /* Force the chip into D0. */
6669         err = tg3_set_power_state(tp, PCI_D0);
6670         if (err)
6671                 goto out;
6672
6673         tg3_switch_clocks(tp);
6674
6675         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6676
6677         err = tg3_reset_hw(tp, reset_phy);
6678
6679 out:
6680         return err;
6681 }
6682
6683 #define TG3_STAT_ADD32(PSTAT, REG) \
6684 do {    u32 __val = tr32(REG); \
6685         (PSTAT)->low += __val; \
6686         if ((PSTAT)->low < __val) \
6687                 (PSTAT)->high += 1; \
6688 } while (0)
6689
6690 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6691 {
6692         struct tg3_hw_stats *sp = tp->hw_stats;
6693
6694         if (!netif_carrier_ok(tp->dev))
6695                 return;
6696
6697         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6698         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6699         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6700         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6701         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6702         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6703         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6704         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6705         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6706         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6707         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6708         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6709         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6710
6711         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6712         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6713         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6714         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6715         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6716         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6717         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6718         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6719         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6720         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6721         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6722         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6723         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6724         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6725
6726         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6727         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6728         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6729 }
6730
6731 static void tg3_timer(unsigned long __opaque)
6732 {
6733         struct tg3 *tp = (struct tg3 *) __opaque;
6734
6735         if (tp->irq_sync)
6736                 goto restart_timer;
6737
6738         spin_lock(&tp->lock);
6739
6740         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6741                 /* All of this garbage is because when using non-tagged
6742                  * IRQ status the mailbox/status_block protocol the chip
6743                  * uses with the cpu is race prone.
6744                  */
6745                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6746                         tw32(GRC_LOCAL_CTRL,
6747                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6748                 } else {
6749                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6750                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6751                 }
6752
6753                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6754                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6755                         spin_unlock(&tp->lock);
6756                         schedule_work(&tp->reset_task);
6757                         return;
6758                 }
6759         }
6760
6761         /* This part only runs once per second. */
6762         if (!--tp->timer_counter) {
6763                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6764                         tg3_periodic_fetch_stats(tp);
6765
6766                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6767                         u32 mac_stat;
6768                         int phy_event;
6769
6770                         mac_stat = tr32(MAC_STATUS);
6771
6772                         phy_event = 0;
6773                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6774                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6775                                         phy_event = 1;
6776                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6777                                 phy_event = 1;
6778
6779                         if (phy_event)
6780                                 tg3_setup_phy(tp, 0);
6781                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6782                         u32 mac_stat = tr32(MAC_STATUS);
6783                         int need_setup = 0;
6784
6785                         if (netif_carrier_ok(tp->dev) &&
6786                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6787                                 need_setup = 1;
6788                         }
6789                         if (! netif_carrier_ok(tp->dev) &&
6790                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6791                                          MAC_STATUS_SIGNAL_DET))) {
6792                                 need_setup = 1;
6793                         }
6794                         if (need_setup) {
6795                                 if (!tp->serdes_counter) {
6796                                         tw32_f(MAC_MODE,
6797                                              (tp->mac_mode &
6798                                               ~MAC_MODE_PORT_MODE_MASK));
6799                                         udelay(40);
6800                                         tw32_f(MAC_MODE, tp->mac_mode);
6801                                         udelay(40);
6802                                 }
6803                                 tg3_setup_phy(tp, 0);
6804                         }
6805                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6806                         tg3_serdes_parallel_detect(tp);
6807
6808                 tp->timer_counter = tp->timer_multiplier;
6809         }
6810
6811         /* Heartbeat is only sent once every 2 seconds.
6812          *
6813          * The heartbeat is to tell the ASF firmware that the host
6814          * driver is still alive.  In the event that the OS crashes,
6815          * ASF needs to reset the hardware to free up the FIFO space
6816          * that may be filled with rx packets destined for the host.
6817          * If the FIFO is full, ASF will no longer function properly.
6818          *
6819          * Unintended resets have been reported on real time kernels
6820          * where the timer doesn't run on time.  Netpoll will also have
6821          * same problem.
6822          *
6823          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6824          * to check the ring condition when the heartbeat is expiring
6825          * before doing the reset.  This will prevent most unintended
6826          * resets.
6827          */
6828         if (!--tp->asf_counter) {
6829                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6830                         u32 val;
6831
6832                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6833                                       FWCMD_NICDRV_ALIVE3);
6834                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6835                         /* 5 seconds timeout */
6836                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6837                         val = tr32(GRC_RX_CPU_EVENT);
6838                         val |= (1 << 14);
6839                         tw32(GRC_RX_CPU_EVENT, val);
6840                 }
6841                 tp->asf_counter = tp->asf_multiplier;
6842         }
6843
6844         spin_unlock(&tp->lock);
6845
6846 restart_timer:
6847         tp->timer.expires = jiffies + tp->timer_offset;
6848         add_timer(&tp->timer);
6849 }
6850
6851 static int tg3_request_irq(struct tg3 *tp)
6852 {
6853         irq_handler_t fn;
6854         unsigned long flags;
6855         struct net_device *dev = tp->dev;
6856
6857         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6858                 fn = tg3_msi;
6859                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6860                         fn = tg3_msi_1shot;
6861                 flags = IRQF_SAMPLE_RANDOM;
6862         } else {
6863                 fn = tg3_interrupt;
6864                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6865                         fn = tg3_interrupt_tagged;
6866                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6867         }
6868         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6869 }
6870
6871 static int tg3_test_interrupt(struct tg3 *tp)
6872 {
6873         struct net_device *dev = tp->dev;
6874         int err, i, intr_ok = 0;
6875
6876         if (!netif_running(dev))
6877                 return -ENODEV;
6878
6879         tg3_disable_ints(tp);
6880
6881         free_irq(tp->pdev->irq, dev);
6882
6883         err = request_irq(tp->pdev->irq, tg3_test_isr,
6884                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6885         if (err)
6886                 return err;
6887
6888         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6889         tg3_enable_ints(tp);
6890
6891         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6892                HOSTCC_MODE_NOW);
6893
6894         for (i = 0; i < 5; i++) {
6895                 u32 int_mbox, misc_host_ctrl;
6896
6897                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6898                                         TG3_64BIT_REG_LOW);
6899                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6900
6901                 if ((int_mbox != 0) ||
6902                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6903                         intr_ok = 1;
6904                         break;
6905                 }
6906
6907                 msleep(10);
6908         }
6909
6910         tg3_disable_ints(tp);
6911
6912         free_irq(tp->pdev->irq, dev);
6913
6914         err = tg3_request_irq(tp);
6915
6916         if (err)
6917                 return err;
6918
6919         if (intr_ok)
6920                 return 0;
6921
6922         return -EIO;
6923 }
6924
6925 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6926  * successfully restored
6927  */
6928 static int tg3_test_msi(struct tg3 *tp)
6929 {
6930         struct net_device *dev = tp->dev;
6931         int err;
6932         u16 pci_cmd;
6933
6934         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6935                 return 0;
6936
6937         /* Turn off SERR reporting in case MSI terminates with Master
6938          * Abort.
6939          */
6940         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6941         pci_write_config_word(tp->pdev, PCI_COMMAND,
6942                               pci_cmd & ~PCI_COMMAND_SERR);
6943
6944         err = tg3_test_interrupt(tp);
6945
6946         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6947
6948         if (!err)
6949                 return 0;
6950
6951         /* other failures */
6952         if (err != -EIO)
6953                 return err;
6954
6955         /* MSI test failed, go back to INTx mode */
6956         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6957                "switching to INTx mode. Please report this failure to "
6958                "the PCI maintainer and include system chipset information.\n",
6959                        tp->dev->name);
6960
6961         free_irq(tp->pdev->irq, dev);
6962         pci_disable_msi(tp->pdev);
6963
6964         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6965
6966         err = tg3_request_irq(tp);
6967         if (err)
6968                 return err;
6969
6970         /* Need to reset the chip because the MSI cycle may have terminated
6971          * with Master Abort.
6972          */
6973         tg3_full_lock(tp, 1);
6974
6975         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6976         err = tg3_init_hw(tp, 1);
6977
6978         tg3_full_unlock(tp);
6979
6980         if (err)
6981                 free_irq(tp->pdev->irq, dev);
6982
6983         return err;
6984 }
6985
6986 static int tg3_open(struct net_device *dev)
6987 {
6988         struct tg3 *tp = netdev_priv(dev);
6989         int err;
6990
6991         tg3_full_lock(tp, 0);
6992
6993         err = tg3_set_power_state(tp, PCI_D0);
6994         if (err) {
6995                 tg3_full_unlock(tp);
6996                 return err;
6997         }
6998
6999         tg3_disable_ints(tp);
7000         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7001
7002         tg3_full_unlock(tp);
7003
7004         /* The placement of this call is tied
7005          * to the setup and use of Host TX descriptors.
7006          */
7007         err = tg3_alloc_consistent(tp);
7008         if (err)
7009                 return err;
7010
7011         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7012             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
7013             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7014             !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7015               (tp->pdev_peer == tp->pdev))) {
7016                 /* All MSI supporting chips should support tagged
7017                  * status.  Assert that this is the case.
7018                  */
7019                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7020                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7021                                "Not using MSI.\n", tp->dev->name);
7022                 } else if (pci_enable_msi(tp->pdev) == 0) {
7023                         u32 msi_mode;
7024
7025                         msi_mode = tr32(MSGINT_MODE);
7026                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7027                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7028                 }
7029         }
7030         err = tg3_request_irq(tp);
7031
7032         if (err) {
7033                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7034                         pci_disable_msi(tp->pdev);
7035                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7036                 }
7037                 tg3_free_consistent(tp);
7038                 return err;
7039         }
7040
7041         tg3_full_lock(tp, 0);
7042
7043         err = tg3_init_hw(tp, 1);
7044         if (err) {
7045                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7046                 tg3_free_rings(tp);
7047         } else {
7048                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7049                         tp->timer_offset = HZ;
7050                 else
7051                         tp->timer_offset = HZ / 10;
7052
7053                 BUG_ON(tp->timer_offset > HZ);
7054                 tp->timer_counter = tp->timer_multiplier =
7055                         (HZ / tp->timer_offset);
7056                 tp->asf_counter = tp->asf_multiplier =
7057                         ((HZ / tp->timer_offset) * 2);
7058
7059                 init_timer(&tp->timer);
7060                 tp->timer.expires = jiffies + tp->timer_offset;
7061                 tp->timer.data = (unsigned long) tp;
7062                 tp->timer.function = tg3_timer;
7063         }
7064
7065         tg3_full_unlock(tp);
7066
7067         if (err) {
7068                 free_irq(tp->pdev->irq, dev);
7069                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7070                         pci_disable_msi(tp->pdev);
7071                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7072                 }
7073                 tg3_free_consistent(tp);
7074                 return err;
7075         }
7076
7077         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7078                 err = tg3_test_msi(tp);
7079
7080                 if (err) {
7081                         tg3_full_lock(tp, 0);
7082
7083                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7084                                 pci_disable_msi(tp->pdev);
7085                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7086                         }
7087                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7088                         tg3_free_rings(tp);
7089                         tg3_free_consistent(tp);
7090
7091                         tg3_full_unlock(tp);
7092
7093                         return err;
7094                 }
7095
7096                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7097                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7098                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7099
7100                                 tw32(PCIE_TRANSACTION_CFG,
7101                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7102                         }
7103                 }
7104         }
7105
7106         tg3_full_lock(tp, 0);
7107
7108         add_timer(&tp->timer);
7109         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7110         tg3_enable_ints(tp);
7111
7112         tg3_full_unlock(tp);
7113
7114         netif_start_queue(dev);
7115
7116         return 0;
7117 }
7118
7119 #if 0
7120 /*static*/ void tg3_dump_state(struct tg3 *tp)
7121 {
7122         u32 val32, val32_2, val32_3, val32_4, val32_5;
7123         u16 val16;
7124         int i;
7125
7126         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7127         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7128         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7129                val16, val32);
7130
7131         /* MAC block */
7132         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7133                tr32(MAC_MODE), tr32(MAC_STATUS));
7134         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7135                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7136         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7137                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7138         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7139                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7140
7141         /* Send data initiator control block */
7142         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7143                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7144         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7145                tr32(SNDDATAI_STATSCTRL));
7146
7147         /* Send data completion control block */
7148         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7149
7150         /* Send BD ring selector block */
7151         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7152                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7153
7154         /* Send BD initiator control block */
7155         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7156                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7157
7158         /* Send BD completion control block */
7159         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7160
7161         /* Receive list placement control block */
7162         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7163                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7164         printk("       RCVLPC_STATSCTRL[%08x]\n",
7165                tr32(RCVLPC_STATSCTRL));
7166
7167         /* Receive data and receive BD initiator control block */
7168         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7169                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7170
7171         /* Receive data completion control block */
7172         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7173                tr32(RCVDCC_MODE));
7174
7175         /* Receive BD initiator control block */
7176         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7177                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7178
7179         /* Receive BD completion control block */
7180         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7181                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7182
7183         /* Receive list selector control block */
7184         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7185                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7186
7187         /* Mbuf cluster free block */
7188         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7189                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7190
7191         /* Host coalescing control block */
7192         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7193                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7194         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7195                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7196                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7197         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7198                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7199                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7200         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7201                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7202         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7203                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7204
7205         /* Memory arbiter control block */
7206         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7207                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7208
7209         /* Buffer manager control block */
7210         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7211                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7212         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7213                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7214         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7215                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7216                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7217                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7218
7219         /* Read DMA control block */
7220         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7221                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7222
7223         /* Write DMA control block */
7224         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7225                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7226
7227         /* DMA completion block */
7228         printk("DEBUG: DMAC_MODE[%08x]\n",
7229                tr32(DMAC_MODE));
7230
7231         /* GRC block */
7232         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7233                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7234         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7235                tr32(GRC_LOCAL_CTRL));
7236
7237         /* TG3_BDINFOs */
7238         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7239                tr32(RCVDBDI_JUMBO_BD + 0x0),
7240                tr32(RCVDBDI_JUMBO_BD + 0x4),
7241                tr32(RCVDBDI_JUMBO_BD + 0x8),
7242                tr32(RCVDBDI_JUMBO_BD + 0xc));
7243         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7244                tr32(RCVDBDI_STD_BD + 0x0),
7245                tr32(RCVDBDI_STD_BD + 0x4),
7246                tr32(RCVDBDI_STD_BD + 0x8),
7247                tr32(RCVDBDI_STD_BD + 0xc));
7248         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7249                tr32(RCVDBDI_MINI_BD + 0x0),
7250                tr32(RCVDBDI_MINI_BD + 0x4),
7251                tr32(RCVDBDI_MINI_BD + 0x8),
7252                tr32(RCVDBDI_MINI_BD + 0xc));
7253
7254         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7255         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7256         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7257         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7258         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7259                val32, val32_2, val32_3, val32_4);
7260
7261         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7262         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7263         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7264         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7265         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7266                val32, val32_2, val32_3, val32_4);
7267
7268         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7269         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7270         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7271         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7272         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7273         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7274                val32, val32_2, val32_3, val32_4, val32_5);
7275
7276         /* SW status block */
7277         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7278                tp->hw_status->status,
7279                tp->hw_status->status_tag,
7280                tp->hw_status->rx_jumbo_consumer,
7281                tp->hw_status->rx_consumer,
7282                tp->hw_status->rx_mini_consumer,
7283                tp->hw_status->idx[0].rx_producer,
7284                tp->hw_status->idx[0].tx_consumer);
7285
7286         /* SW statistics block */
7287         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7288                ((u32 *)tp->hw_stats)[0],
7289                ((u32 *)tp->hw_stats)[1],
7290                ((u32 *)tp->hw_stats)[2],
7291                ((u32 *)tp->hw_stats)[3]);
7292
7293         /* Mailboxes */
7294         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7295                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7296                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7297                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7298                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7299
7300         /* NIC side send descriptors. */
7301         for (i = 0; i < 6; i++) {
7302                 unsigned long txd;
7303
7304                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7305                         + (i * sizeof(struct tg3_tx_buffer_desc));
7306                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7307                        i,
7308                        readl(txd + 0x0), readl(txd + 0x4),
7309                        readl(txd + 0x8), readl(txd + 0xc));
7310         }
7311
7312         /* NIC side RX descriptors. */
7313         for (i = 0; i < 6; i++) {
7314                 unsigned long rxd;
7315
7316                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7317                         + (i * sizeof(struct tg3_rx_buffer_desc));
7318                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7319                        i,
7320                        readl(rxd + 0x0), readl(rxd + 0x4),
7321                        readl(rxd + 0x8), readl(rxd + 0xc));
7322                 rxd += (4 * sizeof(u32));
7323                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7324                        i,
7325                        readl(rxd + 0x0), readl(rxd + 0x4),
7326                        readl(rxd + 0x8), readl(rxd + 0xc));
7327         }
7328
7329         for (i = 0; i < 6; i++) {
7330                 unsigned long rxd;
7331
7332                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7333                         + (i * sizeof(struct tg3_rx_buffer_desc));
7334                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7335                        i,
7336                        readl(rxd + 0x0), readl(rxd + 0x4),
7337                        readl(rxd + 0x8), readl(rxd + 0xc));
7338                 rxd += (4 * sizeof(u32));
7339                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7340                        i,
7341                        readl(rxd + 0x0), readl(rxd + 0x4),
7342                        readl(rxd + 0x8), readl(rxd + 0xc));
7343         }
7344 }
7345 #endif
7346
7347 static struct net_device_stats *tg3_get_stats(struct net_device *);
7348 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7349
7350 static int tg3_close(struct net_device *dev)
7351 {
7352         struct tg3 *tp = netdev_priv(dev);
7353
7354         /* Calling flush_scheduled_work() may deadlock because
7355          * linkwatch_event() may be on the workqueue and it will try to get
7356          * the rtnl_lock which we are holding.
7357          */
7358         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7359                 msleep(1);
7360
7361         netif_stop_queue(dev);
7362
7363         del_timer_sync(&tp->timer);
7364
7365         tg3_full_lock(tp, 1);
7366 #if 0
7367         tg3_dump_state(tp);
7368 #endif
7369
7370         tg3_disable_ints(tp);
7371
7372         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7373         tg3_free_rings(tp);
7374         tp->tg3_flags &=
7375                 ~(TG3_FLAG_INIT_COMPLETE |
7376                   TG3_FLAG_GOT_SERDES_FLOWCTL);
7377
7378         tg3_full_unlock(tp);
7379
7380         free_irq(tp->pdev->irq, dev);
7381         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7382                 pci_disable_msi(tp->pdev);
7383                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7384         }
7385
7386         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7387                sizeof(tp->net_stats_prev));
7388         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7389                sizeof(tp->estats_prev));
7390
7391         tg3_free_consistent(tp);
7392
7393         tg3_set_power_state(tp, PCI_D3hot);
7394
7395         netif_carrier_off(tp->dev);
7396
7397         return 0;
7398 }
7399
7400 static inline unsigned long get_stat64(tg3_stat64_t *val)
7401 {
7402         unsigned long ret;
7403
7404 #if (BITS_PER_LONG == 32)
7405         ret = val->low;
7406 #else
7407         ret = ((u64)val->high << 32) | ((u64)val->low);
7408 #endif
7409         return ret;
7410 }
7411
7412 static unsigned long calc_crc_errors(struct tg3 *tp)
7413 {
7414         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7415
7416         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7417             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7418              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7419                 u32 val;
7420
7421                 spin_lock_bh(&tp->lock);
7422                 if (!tg3_readphy(tp, 0x1e, &val)) {
7423                         tg3_writephy(tp, 0x1e, val | 0x8000);
7424                         tg3_readphy(tp, 0x14, &val);
7425                 } else
7426                         val = 0;
7427                 spin_unlock_bh(&tp->lock);
7428
7429                 tp->phy_crc_errors += val;
7430
7431                 return tp->phy_crc_errors;
7432         }
7433
7434         return get_stat64(&hw_stats->rx_fcs_errors);
7435 }
7436
7437 #define ESTAT_ADD(member) \
7438         estats->member =        old_estats->member + \
7439                                 get_stat64(&hw_stats->member)
7440
7441 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7442 {
7443         struct tg3_ethtool_stats *estats = &tp->estats;
7444         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7445         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7446
7447         if (!hw_stats)
7448                 return old_estats;
7449
7450         ESTAT_ADD(rx_octets);
7451         ESTAT_ADD(rx_fragments);
7452         ESTAT_ADD(rx_ucast_packets);
7453         ESTAT_ADD(rx_mcast_packets);
7454         ESTAT_ADD(rx_bcast_packets);
7455         ESTAT_ADD(rx_fcs_errors);
7456         ESTAT_ADD(rx_align_errors);
7457         ESTAT_ADD(rx_xon_pause_rcvd);
7458         ESTAT_ADD(rx_xoff_pause_rcvd);
7459         ESTAT_ADD(rx_mac_ctrl_rcvd);
7460         ESTAT_ADD(rx_xoff_entered);
7461         ESTAT_ADD(rx_frame_too_long_errors);
7462         ESTAT_ADD(rx_jabbers);
7463         ESTAT_ADD(rx_undersize_packets);
7464         ESTAT_ADD(rx_in_length_errors);
7465         ESTAT_ADD(rx_out_length_errors);
7466         ESTAT_ADD(rx_64_or_less_octet_packets);
7467         ESTAT_ADD(rx_65_to_127_octet_packets);
7468         ESTAT_ADD(rx_128_to_255_octet_packets);
7469         ESTAT_ADD(rx_256_to_511_octet_packets);
7470         ESTAT_ADD(rx_512_to_1023_octet_packets);
7471         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7472         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7473         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7474         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7475         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7476
7477         ESTAT_ADD(tx_octets);
7478         ESTAT_ADD(tx_collisions);
7479         ESTAT_ADD(tx_xon_sent);
7480         ESTAT_ADD(tx_xoff_sent);
7481         ESTAT_ADD(tx_flow_control);
7482         ESTAT_ADD(tx_mac_errors);
7483         ESTAT_ADD(tx_single_collisions);
7484         ESTAT_ADD(tx_mult_collisions);
7485         ESTAT_ADD(tx_deferred);
7486         ESTAT_ADD(tx_excessive_collisions);
7487         ESTAT_ADD(tx_late_collisions);
7488         ESTAT_ADD(tx_collide_2times);
7489         ESTAT_ADD(tx_collide_3times);
7490         ESTAT_ADD(tx_collide_4times);
7491         ESTAT_ADD(tx_collide_5times);
7492         ESTAT_ADD(tx_collide_6times);
7493         ESTAT_ADD(tx_collide_7times);
7494         ESTAT_ADD(tx_collide_8times);
7495         ESTAT_ADD(tx_collide_9times);
7496         ESTAT_ADD(tx_collide_10times);
7497         ESTAT_ADD(tx_collide_11times);
7498         ESTAT_ADD(tx_collide_12times);
7499         ESTAT_ADD(tx_collide_13times);
7500         ESTAT_ADD(tx_collide_14times);
7501         ESTAT_ADD(tx_collide_15times);
7502         ESTAT_ADD(tx_ucast_packets);
7503         ESTAT_ADD(tx_mcast_packets);
7504         ESTAT_ADD(tx_bcast_packets);
7505         ESTAT_ADD(tx_carrier_sense_errors);
7506         ESTAT_ADD(tx_discards);
7507         ESTAT_ADD(tx_errors);
7508
7509         ESTAT_ADD(dma_writeq_full);
7510         ESTAT_ADD(dma_write_prioq_full);
7511         ESTAT_ADD(rxbds_empty);
7512         ESTAT_ADD(rx_discards);
7513         ESTAT_ADD(rx_errors);
7514         ESTAT_ADD(rx_threshold_hit);
7515
7516         ESTAT_ADD(dma_readq_full);
7517         ESTAT_ADD(dma_read_prioq_full);
7518         ESTAT_ADD(tx_comp_queue_full);
7519
7520         ESTAT_ADD(ring_set_send_prod_index);
7521         ESTAT_ADD(ring_status_update);
7522         ESTAT_ADD(nic_irqs);
7523         ESTAT_ADD(nic_avoided_irqs);
7524         ESTAT_ADD(nic_tx_threshold_hit);
7525
7526         return estats;
7527 }
7528
7529 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7530 {
7531         struct tg3 *tp = netdev_priv(dev);
7532         struct net_device_stats *stats = &tp->net_stats;
7533         struct net_device_stats *old_stats = &tp->net_stats_prev;
7534         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7535
7536         if (!hw_stats)
7537                 return old_stats;
7538
7539         stats->rx_packets = old_stats->rx_packets +
7540                 get_stat64(&hw_stats->rx_ucast_packets) +
7541                 get_stat64(&hw_stats->rx_mcast_packets) +
7542                 get_stat64(&hw_stats->rx_bcast_packets);
7543
7544         stats->tx_packets = old_stats->tx_packets +
7545                 get_stat64(&hw_stats->tx_ucast_packets) +
7546                 get_stat64(&hw_stats->tx_mcast_packets) +
7547                 get_stat64(&hw_stats->tx_bcast_packets);
7548
7549         stats->rx_bytes = old_stats->rx_bytes +
7550                 get_stat64(&hw_stats->rx_octets);
7551         stats->tx_bytes = old_stats->tx_bytes +
7552                 get_stat64(&hw_stats->tx_octets);
7553
7554         stats->rx_errors = old_stats->rx_errors +
7555                 get_stat64(&hw_stats->rx_errors);
7556         stats->tx_errors = old_stats->tx_errors +
7557                 get_stat64(&hw_stats->tx_errors) +
7558                 get_stat64(&hw_stats->tx_mac_errors) +
7559                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7560                 get_stat64(&hw_stats->tx_discards);
7561
7562         stats->multicast = old_stats->multicast +
7563                 get_stat64(&hw_stats->rx_mcast_packets);
7564         stats->collisions = old_stats->collisions +
7565                 get_stat64(&hw_stats->tx_collisions);
7566
7567         stats->rx_length_errors = old_stats->rx_length_errors +
7568                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7569                 get_stat64(&hw_stats->rx_undersize_packets);
7570
7571         stats->rx_over_errors = old_stats->rx_over_errors +
7572                 get_stat64(&hw_stats->rxbds_empty);
7573         stats->rx_frame_errors = old_stats->rx_frame_errors +
7574                 get_stat64(&hw_stats->rx_align_errors);
7575         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7576                 get_stat64(&hw_stats->tx_discards);
7577         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7578                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7579
7580         stats->rx_crc_errors = old_stats->rx_crc_errors +
7581                 calc_crc_errors(tp);
7582
7583         stats->rx_missed_errors = old_stats->rx_missed_errors +
7584                 get_stat64(&hw_stats->rx_discards);
7585
7586         return stats;
7587 }
7588
7589 static inline u32 calc_crc(unsigned char *buf, int len)
7590 {
7591         u32 reg;
7592         u32 tmp;
7593         int j, k;
7594
7595         reg = 0xffffffff;
7596
7597         for (j = 0; j < len; j++) {
7598                 reg ^= buf[j];
7599
7600                 for (k = 0; k < 8; k++) {
7601                         tmp = reg & 0x01;
7602
7603                         reg >>= 1;
7604
7605                         if (tmp) {
7606                                 reg ^= 0xedb88320;
7607                         }
7608                 }
7609         }
7610
7611         return ~reg;
7612 }
7613
7614 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7615 {
7616         /* accept or reject all multicast frames */
7617         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7618         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7619         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7620         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7621 }
7622
7623 static void __tg3_set_rx_mode(struct net_device *dev)
7624 {
7625         struct tg3 *tp = netdev_priv(dev);
7626         u32 rx_mode;
7627
7628         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7629                                   RX_MODE_KEEP_VLAN_TAG);
7630
7631         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7632          * flag clear.
7633          */
7634 #if TG3_VLAN_TAG_USED
7635         if (!tp->vlgrp &&
7636             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7637                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7638 #else
7639         /* By definition, VLAN is disabled always in this
7640          * case.
7641          */
7642         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7643                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7644 #endif
7645
7646         if (dev->flags & IFF_PROMISC) {
7647                 /* Promiscuous mode. */
7648                 rx_mode |= RX_MODE_PROMISC;
7649         } else if (dev->flags & IFF_ALLMULTI) {
7650                 /* Accept all multicast. */
7651                 tg3_set_multi (tp, 1);
7652         } else if (dev->mc_count < 1) {
7653                 /* Reject all multicast. */
7654                 tg3_set_multi (tp, 0);
7655         } else {
7656                 /* Accept one or more multicast(s). */
7657                 struct dev_mc_list *mclist;
7658                 unsigned int i;
7659                 u32 mc_filter[4] = { 0, };
7660                 u32 regidx;
7661                 u32 bit;
7662                 u32 crc;
7663
7664                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7665                      i++, mclist = mclist->next) {
7666
7667                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7668                         bit = ~crc & 0x7f;
7669                         regidx = (bit & 0x60) >> 5;
7670                         bit &= 0x1f;
7671                         mc_filter[regidx] |= (1 << bit);
7672                 }
7673
7674                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7675                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7676                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7677                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7678         }
7679
7680         if (rx_mode != tp->rx_mode) {
7681                 tp->rx_mode = rx_mode;
7682                 tw32_f(MAC_RX_MODE, rx_mode);
7683                 udelay(10);
7684         }
7685 }
7686
7687 static void tg3_set_rx_mode(struct net_device *dev)
7688 {
7689         struct tg3 *tp = netdev_priv(dev);
7690
7691         if (!netif_running(dev))
7692                 return;
7693
7694         tg3_full_lock(tp, 0);
7695         __tg3_set_rx_mode(dev);
7696         tg3_full_unlock(tp);
7697 }
7698
7699 #define TG3_REGDUMP_LEN         (32 * 1024)
7700
7701 static int tg3_get_regs_len(struct net_device *dev)
7702 {
7703         return TG3_REGDUMP_LEN;
7704 }
7705
7706 static void tg3_get_regs(struct net_device *dev,
7707                 struct ethtool_regs *regs, void *_p)
7708 {
7709         u32 *p = _p;
7710         struct tg3 *tp = netdev_priv(dev);
7711         u8 *orig_p = _p;
7712         int i;
7713
7714         regs->version = 0;
7715
7716         memset(p, 0, TG3_REGDUMP_LEN);
7717
7718         if (tp->link_config.phy_is_low_power)
7719                 return;
7720
7721         tg3_full_lock(tp, 0);
7722
7723 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7724 #define GET_REG32_LOOP(base,len)                \
7725 do {    p = (u32 *)(orig_p + (base));           \
7726         for (i = 0; i < len; i += 4)            \
7727                 __GET_REG32((base) + i);        \
7728 } while (0)
7729 #define GET_REG32_1(reg)                        \
7730 do {    p = (u32 *)(orig_p + (reg));            \
7731         __GET_REG32((reg));                     \
7732 } while (0)
7733
7734         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7735         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7736         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7737         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7738         GET_REG32_1(SNDDATAC_MODE);
7739         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7740         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7741         GET_REG32_1(SNDBDC_MODE);
7742         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7743         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7744         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7745         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7746         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7747         GET_REG32_1(RCVDCC_MODE);
7748         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7749         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7750         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7751         GET_REG32_1(MBFREE_MODE);
7752         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7753         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7754         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7755         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7756         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7757         GET_REG32_1(RX_CPU_MODE);
7758         GET_REG32_1(RX_CPU_STATE);
7759         GET_REG32_1(RX_CPU_PGMCTR);
7760         GET_REG32_1(RX_CPU_HWBKPT);
7761         GET_REG32_1(TX_CPU_MODE);
7762         GET_REG32_1(TX_CPU_STATE);
7763         GET_REG32_1(TX_CPU_PGMCTR);
7764         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7765         GET_REG32_LOOP(FTQ_RESET, 0x120);
7766         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7767         GET_REG32_1(DMAC_MODE);
7768         GET_REG32_LOOP(GRC_MODE, 0x4c);
7769         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7770                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7771
7772 #undef __GET_REG32
7773 #undef GET_REG32_LOOP
7774 #undef GET_REG32_1
7775
7776         tg3_full_unlock(tp);
7777 }
7778
7779 static int tg3_get_eeprom_len(struct net_device *dev)
7780 {
7781         struct tg3 *tp = netdev_priv(dev);
7782
7783         return tp->nvram_size;
7784 }
7785
7786 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7787 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7788
7789 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7790 {
7791         struct tg3 *tp = netdev_priv(dev);
7792         int ret;
7793         u8  *pd;
7794         u32 i, offset, len, val, b_offset, b_count;
7795
7796         if (tp->link_config.phy_is_low_power)
7797                 return -EAGAIN;
7798
7799         offset = eeprom->offset;
7800         len = eeprom->len;
7801         eeprom->len = 0;
7802
7803         eeprom->magic = TG3_EEPROM_MAGIC;
7804
7805         if (offset & 3) {
7806                 /* adjustments to start on required 4 byte boundary */
7807                 b_offset = offset & 3;
7808                 b_count = 4 - b_offset;
7809                 if (b_count > len) {
7810                         /* i.e. offset=1 len=2 */
7811                         b_count = len;
7812                 }
7813                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7814                 if (ret)
7815                         return ret;
7816                 val = cpu_to_le32(val);
7817                 memcpy(data, ((char*)&val) + b_offset, b_count);
7818                 len -= b_count;
7819                 offset += b_count;
7820                 eeprom->len += b_count;
7821         }
7822
7823         /* read bytes upto the last 4 byte boundary */
7824         pd = &data[eeprom->len];
7825         for (i = 0; i < (len - (len & 3)); i += 4) {
7826                 ret = tg3_nvram_read(tp, offset + i, &val);
7827                 if (ret) {
7828                         eeprom->len += i;
7829                         return ret;
7830                 }
7831                 val = cpu_to_le32(val);
7832                 memcpy(pd + i, &val, 4);
7833         }
7834         eeprom->len += i;
7835
7836         if (len & 3) {
7837                 /* read last bytes not ending on 4 byte boundary */
7838                 pd = &data[eeprom->len];
7839                 b_count = len & 3;
7840                 b_offset = offset + len - b_count;
7841                 ret = tg3_nvram_read(tp, b_offset, &val);
7842                 if (ret)
7843                         return ret;
7844                 val = cpu_to_le32(val);
7845                 memcpy(pd, ((char*)&val), b_count);
7846                 eeprom->len += b_count;
7847         }
7848         return 0;
7849 }
7850
7851 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7852
7853 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7854 {
7855         struct tg3 *tp = netdev_priv(dev);
7856         int ret;
7857         u32 offset, len, b_offset, odd_len, start, end;
7858         u8 *buf;
7859
7860         if (tp->link_config.phy_is_low_power)
7861                 return -EAGAIN;
7862
7863         if (eeprom->magic != TG3_EEPROM_MAGIC)
7864                 return -EINVAL;
7865
7866         offset = eeprom->offset;
7867         len = eeprom->len;
7868
7869         if ((b_offset = (offset & 3))) {
7870                 /* adjustments to start on required 4 byte boundary */
7871                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7872                 if (ret)
7873                         return ret;
7874                 start = cpu_to_le32(start);
7875                 len += b_offset;
7876                 offset &= ~3;
7877                 if (len < 4)
7878                         len = 4;
7879         }
7880
7881         odd_len = 0;
7882         if (len & 3) {
7883                 /* adjustments to end on required 4 byte boundary */
7884                 odd_len = 1;
7885                 len = (len + 3) & ~3;
7886                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7887                 if (ret)
7888                         return ret;
7889                 end = cpu_to_le32(end);
7890         }
7891
7892         buf = data;
7893         if (b_offset || odd_len) {
7894                 buf = kmalloc(len, GFP_KERNEL);
7895                 if (buf == 0)
7896                         return -ENOMEM;
7897                 if (b_offset)
7898                         memcpy(buf, &start, 4);
7899                 if (odd_len)
7900                         memcpy(buf+len-4, &end, 4);
7901                 memcpy(buf + b_offset, data, eeprom->len);
7902         }
7903
7904         ret = tg3_nvram_write_block(tp, offset, len, buf);
7905
7906         if (buf != data)
7907                 kfree(buf);
7908
7909         return ret;
7910 }
7911
7912 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7913 {
7914         struct tg3 *tp = netdev_priv(dev);
7915
7916         cmd->supported = (SUPPORTED_Autoneg);
7917
7918         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7919                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7920                                    SUPPORTED_1000baseT_Full);
7921
7922         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7923                 cmd->supported |= (SUPPORTED_100baseT_Half |
7924                                   SUPPORTED_100baseT_Full |
7925                                   SUPPORTED_10baseT_Half |
7926                                   SUPPORTED_10baseT_Full |
7927                                   SUPPORTED_MII);
7928                 cmd->port = PORT_TP;
7929         } else {
7930                 cmd->supported |= SUPPORTED_FIBRE;
7931                 cmd->port = PORT_FIBRE;
7932         }
7933
7934         cmd->advertising = tp->link_config.advertising;
7935         if (netif_running(dev)) {
7936                 cmd->speed = tp->link_config.active_speed;
7937                 cmd->duplex = tp->link_config.active_duplex;
7938         }
7939         cmd->phy_address = PHY_ADDR;
7940         cmd->transceiver = 0;
7941         cmd->autoneg = tp->link_config.autoneg;
7942         cmd->maxtxpkt = 0;
7943         cmd->maxrxpkt = 0;
7944         return 0;
7945 }
7946
7947 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7948 {
7949         struct tg3 *tp = netdev_priv(dev);
7950
7951         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7952                 /* These are the only valid advertisement bits allowed.  */
7953                 if (cmd->autoneg == AUTONEG_ENABLE &&
7954                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7955                                           ADVERTISED_1000baseT_Full |
7956                                           ADVERTISED_Autoneg |
7957                                           ADVERTISED_FIBRE)))
7958                         return -EINVAL;
7959                 /* Fiber can only do SPEED_1000.  */
7960                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7961                          (cmd->speed != SPEED_1000))
7962                         return -EINVAL;
7963         /* Copper cannot force SPEED_1000.  */
7964         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7965                    (cmd->speed == SPEED_1000))
7966                 return -EINVAL;
7967         else if ((cmd->speed == SPEED_1000) &&
7968                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7969                 return -EINVAL;
7970
7971         tg3_full_lock(tp, 0);
7972
7973         tp->link_config.autoneg = cmd->autoneg;
7974         if (cmd->autoneg == AUTONEG_ENABLE) {
7975                 tp->link_config.advertising = cmd->advertising;
7976                 tp->link_config.speed = SPEED_INVALID;
7977                 tp->link_config.duplex = DUPLEX_INVALID;
7978         } else {
7979                 tp->link_config.advertising = 0;
7980                 tp->link_config.speed = cmd->speed;
7981                 tp->link_config.duplex = cmd->duplex;
7982         }
7983
7984         if (netif_running(dev))
7985                 tg3_setup_phy(tp, 1);
7986
7987         tg3_full_unlock(tp);
7988
7989         return 0;
7990 }
7991
7992 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7993 {
7994         struct tg3 *tp = netdev_priv(dev);
7995
7996         strcpy(info->driver, DRV_MODULE_NAME);
7997         strcpy(info->version, DRV_MODULE_VERSION);
7998         strcpy(info->fw_version, tp->fw_ver);
7999         strcpy(info->bus_info, pci_name(tp->pdev));
8000 }
8001
8002 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8003 {
8004         struct tg3 *tp = netdev_priv(dev);
8005
8006         wol->supported = WAKE_MAGIC;
8007         wol->wolopts = 0;
8008         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8009                 wol->wolopts = WAKE_MAGIC;
8010         memset(&wol->sopass, 0, sizeof(wol->sopass));
8011 }
8012
8013 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8014 {
8015         struct tg3 *tp = netdev_priv(dev);
8016
8017         if (wol->wolopts & ~WAKE_MAGIC)
8018                 return -EINVAL;
8019         if ((wol->wolopts & WAKE_MAGIC) &&
8020             tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
8021             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8022                 return -EINVAL;
8023
8024         spin_lock_bh(&tp->lock);
8025         if (wol->wolopts & WAKE_MAGIC)
8026                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8027         else
8028                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8029         spin_unlock_bh(&tp->lock);
8030
8031         return 0;
8032 }
8033
8034 static u32 tg3_get_msglevel(struct net_device *dev)
8035 {
8036         struct tg3 *tp = netdev_priv(dev);
8037         return tp->msg_enable;
8038 }
8039
8040 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8041 {
8042         struct tg3 *tp = netdev_priv(dev);
8043         tp->msg_enable = value;
8044 }
8045
8046 #if TG3_TSO_SUPPORT != 0
8047 static int tg3_set_tso(struct net_device *dev, u32 value)
8048 {
8049         struct tg3 *tp = netdev_priv(dev);
8050
8051         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8052                 if (value)
8053                         return -EINVAL;
8054                 return 0;
8055         }
8056         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8057             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8058                 if (value)
8059                         dev->features |= NETIF_F_TSO6;
8060                 else
8061                         dev->features &= ~NETIF_F_TSO6;
8062         }
8063         return ethtool_op_set_tso(dev, value);
8064 }
8065 #endif
8066
8067 static int tg3_nway_reset(struct net_device *dev)
8068 {
8069         struct tg3 *tp = netdev_priv(dev);
8070         u32 bmcr;
8071         int r;
8072
8073         if (!netif_running(dev))
8074                 return -EAGAIN;
8075
8076         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8077                 return -EINVAL;
8078
8079         spin_lock_bh(&tp->lock);
8080         r = -EINVAL;
8081         tg3_readphy(tp, MII_BMCR, &bmcr);
8082         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8083             ((bmcr & BMCR_ANENABLE) ||
8084              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8085                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8086                                            BMCR_ANENABLE);
8087                 r = 0;
8088         }
8089         spin_unlock_bh(&tp->lock);
8090
8091         return r;
8092 }
8093
8094 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8095 {
8096         struct tg3 *tp = netdev_priv(dev);
8097
8098         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8099         ering->rx_mini_max_pending = 0;
8100         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8101                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8102         else
8103                 ering->rx_jumbo_max_pending = 0;
8104
8105         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8106
8107         ering->rx_pending = tp->rx_pending;
8108         ering->rx_mini_pending = 0;
8109         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8110                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8111         else
8112                 ering->rx_jumbo_pending = 0;
8113
8114         ering->tx_pending = tp->tx_pending;
8115 }
8116
8117 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8118 {
8119         struct tg3 *tp = netdev_priv(dev);
8120         int irq_sync = 0, err = 0;
8121
8122         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8123             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8124             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8125             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8126             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) &&
8127              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8128                 return -EINVAL;
8129
8130         if (netif_running(dev)) {
8131                 tg3_netif_stop(tp);
8132                 irq_sync = 1;
8133         }
8134
8135         tg3_full_lock(tp, irq_sync);
8136
8137         tp->rx_pending = ering->rx_pending;
8138
8139         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8140             tp->rx_pending > 63)
8141                 tp->rx_pending = 63;
8142         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8143         tp->tx_pending = ering->tx_pending;
8144
8145         if (netif_running(dev)) {
8146                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8147                 err = tg3_restart_hw(tp, 1);
8148                 if (!err)
8149                         tg3_netif_start(tp);
8150         }
8151
8152         tg3_full_unlock(tp);
8153
8154         return err;
8155 }
8156
8157 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8158 {
8159         struct tg3 *tp = netdev_priv(dev);
8160
8161         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8162         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8163         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8164 }
8165
8166 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8167 {
8168         struct tg3 *tp = netdev_priv(dev);
8169         int irq_sync = 0, err = 0;
8170
8171         if (netif_running(dev)) {
8172                 tg3_netif_stop(tp);
8173                 irq_sync = 1;
8174         }
8175
8176         tg3_full_lock(tp, irq_sync);
8177
8178         if (epause->autoneg)
8179                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8180         else
8181                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8182         if (epause->rx_pause)
8183                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8184         else
8185                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8186         if (epause->tx_pause)
8187                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8188         else
8189                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8190
8191         if (netif_running(dev)) {
8192                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8193                 err = tg3_restart_hw(tp, 1);
8194                 if (!err)
8195                         tg3_netif_start(tp);
8196         }
8197
8198         tg3_full_unlock(tp);
8199
8200         return err;
8201 }
8202
8203 static u32 tg3_get_rx_csum(struct net_device *dev)
8204 {
8205         struct tg3 *tp = netdev_priv(dev);
8206         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8207 }
8208
8209 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8210 {
8211         struct tg3 *tp = netdev_priv(dev);
8212
8213         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8214                 if (data != 0)
8215                         return -EINVAL;
8216                 return 0;
8217         }
8218
8219         spin_lock_bh(&tp->lock);
8220         if (data)
8221                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8222         else
8223                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8224         spin_unlock_bh(&tp->lock);
8225
8226         return 0;
8227 }
8228
8229 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8230 {
8231         struct tg3 *tp = netdev_priv(dev);
8232
8233         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8234                 if (data != 0)
8235                         return -EINVAL;
8236                 return 0;
8237         }
8238
8239         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8240             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8241                 ethtool_op_set_tx_hw_csum(dev, data);
8242         else
8243                 ethtool_op_set_tx_csum(dev, data);
8244
8245         return 0;
8246 }
8247
8248 static int tg3_get_stats_count (struct net_device *dev)
8249 {
8250         return TG3_NUM_STATS;
8251 }
8252
8253 static int tg3_get_test_count (struct net_device *dev)
8254 {
8255         return TG3_NUM_TEST;
8256 }
8257
8258 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8259 {
8260         switch (stringset) {
8261         case ETH_SS_STATS:
8262                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8263                 break;
8264         case ETH_SS_TEST:
8265                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8266                 break;
8267         default:
8268                 WARN_ON(1);     /* we need a WARN() */
8269                 break;
8270         }
8271 }
8272
8273 static int tg3_phys_id(struct net_device *dev, u32 data)
8274 {
8275         struct tg3 *tp = netdev_priv(dev);
8276         int i;
8277
8278         if (!netif_running(tp->dev))
8279                 return -EAGAIN;
8280
8281         if (data == 0)
8282                 data = 2;
8283
8284         for (i = 0; i < (data * 2); i++) {
8285                 if ((i % 2) == 0)
8286                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8287                                            LED_CTRL_1000MBPS_ON |
8288                                            LED_CTRL_100MBPS_ON |
8289                                            LED_CTRL_10MBPS_ON |
8290                                            LED_CTRL_TRAFFIC_OVERRIDE |
8291                                            LED_CTRL_TRAFFIC_BLINK |
8292                                            LED_CTRL_TRAFFIC_LED);
8293
8294                 else
8295                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8296                                            LED_CTRL_TRAFFIC_OVERRIDE);
8297
8298                 if (msleep_interruptible(500))
8299                         break;
8300         }
8301         tw32(MAC_LED_CTRL, tp->led_ctrl);
8302         return 0;
8303 }
8304
8305 static void tg3_get_ethtool_stats (struct net_device *dev,
8306                                    struct ethtool_stats *estats, u64 *tmp_stats)
8307 {
8308         struct tg3 *tp = netdev_priv(dev);
8309         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8310 }
8311
8312 #define NVRAM_TEST_SIZE 0x100
8313 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8314 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8315 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8316
8317 static int tg3_test_nvram(struct tg3 *tp)
8318 {
8319         u32 *buf, csum, magic;
8320         int i, j, err = 0, size;
8321
8322         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8323                 return -EIO;
8324
8325         if (magic == TG3_EEPROM_MAGIC)
8326                 size = NVRAM_TEST_SIZE;
8327         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8328                 if ((magic & 0xe00000) == 0x200000)
8329                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8330                 else
8331                         return 0;
8332         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8333                 size = NVRAM_SELFBOOT_HW_SIZE;
8334         else
8335                 return -EIO;
8336
8337         buf = kmalloc(size, GFP_KERNEL);
8338         if (buf == NULL)
8339                 return -ENOMEM;
8340
8341         err = -EIO;
8342         for (i = 0, j = 0; i < size; i += 4, j++) {
8343                 u32 val;
8344
8345                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8346                         break;
8347                 buf[j] = cpu_to_le32(val);
8348         }
8349         if (i < size)
8350                 goto out;
8351
8352         /* Selfboot format */
8353         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8354             TG3_EEPROM_MAGIC_FW) {
8355                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8356
8357                 for (i = 0; i < size; i++)
8358                         csum8 += buf8[i];
8359
8360                 if (csum8 == 0) {
8361                         err = 0;
8362                         goto out;
8363                 }
8364
8365                 err = -EIO;
8366                 goto out;
8367         }
8368
8369         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8370             TG3_EEPROM_MAGIC_HW) {
8371                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8372                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8373                 u8 *buf8 = (u8 *) buf;
8374                 int j, k;
8375
8376                 /* Separate the parity bits and the data bytes.  */
8377                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8378                         if ((i == 0) || (i == 8)) {
8379                                 int l;
8380                                 u8 msk;
8381
8382                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8383                                         parity[k++] = buf8[i] & msk;
8384                                 i++;
8385                         }
8386                         else if (i == 16) {
8387                                 int l;
8388                                 u8 msk;
8389
8390                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8391                                         parity[k++] = buf8[i] & msk;
8392                                 i++;
8393
8394                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8395                                         parity[k++] = buf8[i] & msk;
8396                                 i++;
8397                         }
8398                         data[j++] = buf8[i];
8399                 }
8400
8401                 err = -EIO;
8402                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8403                         u8 hw8 = hweight8(data[i]);
8404
8405                         if ((hw8 & 0x1) && parity[i])
8406                                 goto out;
8407                         else if (!(hw8 & 0x1) && !parity[i])
8408                                 goto out;
8409                 }
8410                 err = 0;
8411                 goto out;
8412         }
8413
8414         /* Bootstrap checksum at offset 0x10 */
8415         csum = calc_crc((unsigned char *) buf, 0x10);
8416         if(csum != cpu_to_le32(buf[0x10/4]))
8417                 goto out;
8418
8419         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8420         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8421         if (csum != cpu_to_le32(buf[0xfc/4]))
8422                  goto out;
8423
8424         err = 0;
8425
8426 out:
8427         kfree(buf);
8428         return err;
8429 }
8430
8431 #define TG3_SERDES_TIMEOUT_SEC  2
8432 #define TG3_COPPER_TIMEOUT_SEC  6
8433
8434 static int tg3_test_link(struct tg3 *tp)
8435 {
8436         int i, max;
8437
8438         if (!netif_running(tp->dev))
8439                 return -ENODEV;
8440
8441         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8442                 max = TG3_SERDES_TIMEOUT_SEC;
8443         else
8444                 max = TG3_COPPER_TIMEOUT_SEC;
8445
8446         for (i = 0; i < max; i++) {
8447                 if (netif_carrier_ok(tp->dev))
8448                         return 0;
8449
8450                 if (msleep_interruptible(1000))
8451                         break;
8452         }
8453
8454         return -EIO;
8455 }
8456
8457 /* Only test the commonly used registers */
8458 static int tg3_test_registers(struct tg3 *tp)
8459 {
8460         int i, is_5705, is_5750;
8461         u32 offset, read_mask, write_mask, val, save_val, read_val;
8462         static struct {
8463                 u16 offset;
8464                 u16 flags;
8465 #define TG3_FL_5705     0x1
8466 #define TG3_FL_NOT_5705 0x2
8467 #define TG3_FL_NOT_5788 0x4
8468 #define TG3_FL_NOT_5750 0x8
8469                 u32 read_mask;
8470                 u32 write_mask;
8471         } reg_tbl[] = {
8472                 /* MAC Control Registers */
8473                 { MAC_MODE, TG3_FL_NOT_5705,
8474                         0x00000000, 0x00ef6f8c },
8475                 { MAC_MODE, TG3_FL_5705,
8476                         0x00000000, 0x01ef6b8c },
8477                 { MAC_STATUS, TG3_FL_NOT_5705,
8478                         0x03800107, 0x00000000 },
8479                 { MAC_STATUS, TG3_FL_5705,
8480                         0x03800100, 0x00000000 },
8481                 { MAC_ADDR_0_HIGH, 0x0000,
8482                         0x00000000, 0x0000ffff },
8483                 { MAC_ADDR_0_LOW, 0x0000,
8484                         0x00000000, 0xffffffff },
8485                 { MAC_RX_MTU_SIZE, 0x0000,
8486                         0x00000000, 0x0000ffff },
8487                 { MAC_TX_MODE, 0x0000,
8488                         0x00000000, 0x00000070 },
8489                 { MAC_TX_LENGTHS, 0x0000,
8490                         0x00000000, 0x00003fff },
8491                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8492                         0x00000000, 0x000007fc },
8493                 { MAC_RX_MODE, TG3_FL_5705,
8494                         0x00000000, 0x000007dc },
8495                 { MAC_HASH_REG_0, 0x0000,
8496                         0x00000000, 0xffffffff },
8497                 { MAC_HASH_REG_1, 0x0000,
8498                         0x00000000, 0xffffffff },
8499                 { MAC_HASH_REG_2, 0x0000,
8500                         0x00000000, 0xffffffff },
8501                 { MAC_HASH_REG_3, 0x0000,
8502                         0x00000000, 0xffffffff },
8503
8504                 /* Receive Data and Receive BD Initiator Control Registers. */
8505                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8506                         0x00000000, 0xffffffff },
8507                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8508                         0x00000000, 0xffffffff },
8509                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8510                         0x00000000, 0x00000003 },
8511                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8512                         0x00000000, 0xffffffff },
8513                 { RCVDBDI_STD_BD+0, 0x0000,
8514                         0x00000000, 0xffffffff },
8515                 { RCVDBDI_STD_BD+4, 0x0000,
8516                         0x00000000, 0xffffffff },
8517                 { RCVDBDI_STD_BD+8, 0x0000,
8518                         0x00000000, 0xffff0002 },
8519                 { RCVDBDI_STD_BD+0xc, 0x0000,
8520                         0x00000000, 0xffffffff },
8521
8522                 /* Receive BD Initiator Control Registers. */
8523                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8524                         0x00000000, 0xffffffff },
8525                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8526                         0x00000000, 0x000003ff },
8527                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8528                         0x00000000, 0xffffffff },
8529
8530                 /* Host Coalescing Control Registers. */
8531                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8532                         0x00000000, 0x00000004 },
8533                 { HOSTCC_MODE, TG3_FL_5705,
8534                         0x00000000, 0x000000f6 },
8535                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8536                         0x00000000, 0xffffffff },
8537                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8538                         0x00000000, 0x000003ff },
8539                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8540                         0x00000000, 0xffffffff },
8541                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8542                         0x00000000, 0x000003ff },
8543                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8544                         0x00000000, 0xffffffff },
8545                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8546                         0x00000000, 0x000000ff },
8547                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8548                         0x00000000, 0xffffffff },
8549                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8550                         0x00000000, 0x000000ff },
8551                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8552                         0x00000000, 0xffffffff },
8553                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8554                         0x00000000, 0xffffffff },
8555                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8556                         0x00000000, 0xffffffff },
8557                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8558                         0x00000000, 0x000000ff },
8559                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8560                         0x00000000, 0xffffffff },
8561                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8562                         0x00000000, 0x000000ff },
8563                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8564                         0x00000000, 0xffffffff },
8565                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8566                         0x00000000, 0xffffffff },
8567                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8568                         0x00000000, 0xffffffff },
8569                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8570                         0x00000000, 0xffffffff },
8571                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8572                         0x00000000, 0xffffffff },
8573                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8574                         0xffffffff, 0x00000000 },
8575                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8576                         0xffffffff, 0x00000000 },
8577
8578                 /* Buffer Manager Control Registers. */
8579                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8580                         0x00000000, 0x007fff80 },
8581                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8582                         0x00000000, 0x007fffff },
8583                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8584                         0x00000000, 0x0000003f },
8585                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8586                         0x00000000, 0x000001ff },
8587                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8588                         0x00000000, 0x000001ff },
8589                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8590                         0xffffffff, 0x00000000 },
8591                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8592                         0xffffffff, 0x00000000 },
8593
8594                 /* Mailbox Registers */
8595                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8596                         0x00000000, 0x000001ff },
8597                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8598                         0x00000000, 0x000001ff },
8599                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8600                         0x00000000, 0x000007ff },
8601                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8602                         0x00000000, 0x000001ff },
8603
8604                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8605         };
8606
8607         is_5705 = is_5750 = 0;
8608         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8609                 is_5705 = 1;
8610                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8611                         is_5750 = 1;
8612         }
8613
8614         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8615                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8616                         continue;
8617
8618                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8619                         continue;
8620
8621                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8622                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8623                         continue;
8624
8625                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8626                         continue;
8627
8628                 offset = (u32) reg_tbl[i].offset;
8629                 read_mask = reg_tbl[i].read_mask;
8630                 write_mask = reg_tbl[i].write_mask;
8631
8632                 /* Save the original register content */
8633                 save_val = tr32(offset);
8634
8635                 /* Determine the read-only value. */
8636                 read_val = save_val & read_mask;
8637
8638                 /* Write zero to the register, then make sure the read-only bits
8639                  * are not changed and the read/write bits are all zeros.
8640                  */
8641                 tw32(offset, 0);
8642
8643                 val = tr32(offset);
8644
8645                 /* Test the read-only and read/write bits. */
8646                 if (((val & read_mask) != read_val) || (val & write_mask))
8647                         goto out;
8648
8649                 /* Write ones to all the bits defined by RdMask and WrMask, then
8650                  * make sure the read-only bits are not changed and the
8651                  * read/write bits are all ones.
8652                  */
8653                 tw32(offset, read_mask | write_mask);
8654
8655                 val = tr32(offset);
8656
8657                 /* Test the read-only bits. */
8658                 if ((val & read_mask) != read_val)
8659                         goto out;
8660
8661                 /* Test the read/write bits. */
8662                 if ((val & write_mask) != write_mask)
8663                         goto out;
8664
8665                 tw32(offset, save_val);
8666         }
8667
8668         return 0;
8669
8670 out:
8671         if (netif_msg_hw(tp))
8672                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8673                        offset);
8674         tw32(offset, save_val);
8675         return -EIO;
8676 }
8677
8678 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8679 {
8680         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8681         int i;
8682         u32 j;
8683
8684         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8685                 for (j = 0; j < len; j += 4) {
8686                         u32 val;
8687
8688                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8689                         tg3_read_mem(tp, offset + j, &val);
8690                         if (val != test_pattern[i])
8691                                 return -EIO;
8692                 }
8693         }
8694         return 0;
8695 }
8696
8697 static int tg3_test_memory(struct tg3 *tp)
8698 {
8699         static struct mem_entry {
8700                 u32 offset;
8701                 u32 len;
8702         } mem_tbl_570x[] = {
8703                 { 0x00000000, 0x00b50},
8704                 { 0x00002000, 0x1c000},
8705                 { 0xffffffff, 0x00000}
8706         }, mem_tbl_5705[] = {
8707                 { 0x00000100, 0x0000c},
8708                 { 0x00000200, 0x00008},
8709                 { 0x00004000, 0x00800},
8710                 { 0x00006000, 0x01000},
8711                 { 0x00008000, 0x02000},
8712                 { 0x00010000, 0x0e000},
8713                 { 0xffffffff, 0x00000}
8714         }, mem_tbl_5755[] = {
8715                 { 0x00000200, 0x00008},
8716                 { 0x00004000, 0x00800},
8717                 { 0x00006000, 0x00800},
8718                 { 0x00008000, 0x02000},
8719                 { 0x00010000, 0x0c000},
8720                 { 0xffffffff, 0x00000}
8721         }, mem_tbl_5906[] = {
8722                 { 0x00000200, 0x00008},
8723                 { 0x00004000, 0x00400},
8724                 { 0x00006000, 0x00400},
8725                 { 0x00008000, 0x01000},
8726                 { 0x00010000, 0x01000},
8727                 { 0xffffffff, 0x00000}
8728         };
8729         struct mem_entry *mem_tbl;
8730         int err = 0;
8731         int i;
8732
8733         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8734                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8735                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8736                         mem_tbl = mem_tbl_5755;
8737                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8738                         mem_tbl = mem_tbl_5906;
8739                 else
8740                         mem_tbl = mem_tbl_5705;
8741         } else
8742                 mem_tbl = mem_tbl_570x;
8743
8744         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8745                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8746                     mem_tbl[i].len)) != 0)
8747                         break;
8748         }
8749
8750         return err;
8751 }
8752
8753 #define TG3_MAC_LOOPBACK        0
8754 #define TG3_PHY_LOOPBACK        1
8755
8756 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8757 {
8758         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8759         u32 desc_idx;
8760         struct sk_buff *skb, *rx_skb;
8761         u8 *tx_data;
8762         dma_addr_t map;
8763         int num_pkts, tx_len, rx_len, i, err;
8764         struct tg3_rx_buffer_desc *desc;
8765
8766         if (loopback_mode == TG3_MAC_LOOPBACK) {
8767                 /* HW errata - mac loopback fails in some cases on 5780.
8768                  * Normal traffic and PHY loopback are not affected by
8769                  * errata.
8770                  */
8771                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8772                         return 0;
8773
8774                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8775                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8776                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8777                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8778                 else
8779                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8780                 tw32(MAC_MODE, mac_mode);
8781         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8782                 u32 val;
8783
8784                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8785                         u32 phytest;
8786
8787                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8788                                 u32 phy;
8789
8790                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8791                                              phytest | MII_TG3_EPHY_SHADOW_EN);
8792                                 if (!tg3_readphy(tp, 0x1b, &phy))
8793                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
8794                                 if (!tg3_readphy(tp, 0x10, &phy))
8795                                         tg3_writephy(tp, 0x10, phy & ~0x4000);
8796                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8797                         }
8798                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8799                 } else
8800                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8801
8802                 tg3_writephy(tp, MII_BMCR, val);
8803                 udelay(40);
8804
8805                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8806                            MAC_MODE_LINK_POLARITY;
8807                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8808                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8809                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8810                 } else
8811                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8812
8813                 /* reset to prevent losing 1st rx packet intermittently */
8814                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8815                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8816                         udelay(10);
8817                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8818                 }
8819                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8820                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8821                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8822                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8823                 }
8824                 tw32(MAC_MODE, mac_mode);
8825         }
8826         else
8827                 return -EINVAL;
8828
8829         err = -EIO;
8830
8831         tx_len = 1514;
8832         skb = netdev_alloc_skb(tp->dev, tx_len);
8833         if (!skb)
8834                 return -ENOMEM;
8835
8836         tx_data = skb_put(skb, tx_len);
8837         memcpy(tx_data, tp->dev->dev_addr, 6);
8838         memset(tx_data + 6, 0x0, 8);
8839
8840         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8841
8842         for (i = 14; i < tx_len; i++)
8843                 tx_data[i] = (u8) (i & 0xff);
8844
8845         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8846
8847         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8848              HOSTCC_MODE_NOW);
8849
8850         udelay(10);
8851
8852         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8853
8854         num_pkts = 0;
8855
8856         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8857
8858         tp->tx_prod++;
8859         num_pkts++;
8860
8861         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8862                      tp->tx_prod);
8863         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8864
8865         udelay(10);
8866
8867         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
8868         for (i = 0; i < 25; i++) {
8869                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8870                        HOSTCC_MODE_NOW);
8871
8872                 udelay(10);
8873
8874                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8875                 rx_idx = tp->hw_status->idx[0].rx_producer;
8876                 if ((tx_idx == tp->tx_prod) &&
8877                     (rx_idx == (rx_start_idx + num_pkts)))
8878                         break;
8879         }
8880
8881         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8882         dev_kfree_skb(skb);
8883
8884         if (tx_idx != tp->tx_prod)
8885                 goto out;
8886
8887         if (rx_idx != rx_start_idx + num_pkts)
8888                 goto out;
8889
8890         desc = &tp->rx_rcb[rx_start_idx];
8891         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8892         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8893         if (opaque_key != RXD_OPAQUE_RING_STD)
8894                 goto out;
8895
8896         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8897             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8898                 goto out;
8899
8900         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8901         if (rx_len != tx_len)
8902                 goto out;
8903
8904         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8905
8906         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8907         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8908
8909         for (i = 14; i < tx_len; i++) {
8910                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8911                         goto out;
8912         }
8913         err = 0;
8914
8915         /* tg3_free_rings will unmap and free the rx_skb */
8916 out:
8917         return err;
8918 }
8919
8920 #define TG3_MAC_LOOPBACK_FAILED         1
8921 #define TG3_PHY_LOOPBACK_FAILED         2
8922 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8923                                          TG3_PHY_LOOPBACK_FAILED)
8924
8925 static int tg3_test_loopback(struct tg3 *tp)
8926 {
8927         int err = 0;
8928
8929         if (!netif_running(tp->dev))
8930                 return TG3_LOOPBACK_FAILED;
8931
8932         err = tg3_reset_hw(tp, 1);
8933         if (err)
8934                 return TG3_LOOPBACK_FAILED;
8935
8936         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8937                 err |= TG3_MAC_LOOPBACK_FAILED;
8938         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8939                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8940                         err |= TG3_PHY_LOOPBACK_FAILED;
8941         }
8942
8943         return err;
8944 }
8945
8946 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8947                           u64 *data)
8948 {
8949         struct tg3 *tp = netdev_priv(dev);
8950
8951         if (tp->link_config.phy_is_low_power)
8952                 tg3_set_power_state(tp, PCI_D0);
8953
8954         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8955
8956         if (tg3_test_nvram(tp) != 0) {
8957                 etest->flags |= ETH_TEST_FL_FAILED;
8958                 data[0] = 1;
8959         }
8960         if (tg3_test_link(tp) != 0) {
8961                 etest->flags |= ETH_TEST_FL_FAILED;
8962                 data[1] = 1;
8963         }
8964         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8965                 int err, irq_sync = 0;
8966
8967                 if (netif_running(dev)) {
8968                         tg3_netif_stop(tp);
8969                         irq_sync = 1;
8970                 }
8971
8972                 tg3_full_lock(tp, irq_sync);
8973
8974                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8975                 err = tg3_nvram_lock(tp);
8976                 tg3_halt_cpu(tp, RX_CPU_BASE);
8977                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8978                         tg3_halt_cpu(tp, TX_CPU_BASE);
8979                 if (!err)
8980                         tg3_nvram_unlock(tp);
8981
8982                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8983                         tg3_phy_reset(tp);
8984
8985                 if (tg3_test_registers(tp) != 0) {
8986                         etest->flags |= ETH_TEST_FL_FAILED;
8987                         data[2] = 1;
8988                 }
8989                 if (tg3_test_memory(tp) != 0) {
8990                         etest->flags |= ETH_TEST_FL_FAILED;
8991                         data[3] = 1;
8992                 }
8993                 if ((data[4] = tg3_test_loopback(tp)) != 0)
8994                         etest->flags |= ETH_TEST_FL_FAILED;
8995
8996                 tg3_full_unlock(tp);
8997
8998                 if (tg3_test_interrupt(tp) != 0) {
8999                         etest->flags |= ETH_TEST_FL_FAILED;
9000                         data[5] = 1;
9001                 }
9002
9003                 tg3_full_lock(tp, 0);
9004
9005                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9006                 if (netif_running(dev)) {
9007                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9008                         if (!tg3_restart_hw(tp, 1))
9009                                 tg3_netif_start(tp);
9010                 }
9011
9012                 tg3_full_unlock(tp);
9013         }
9014         if (tp->link_config.phy_is_low_power)
9015                 tg3_set_power_state(tp, PCI_D3hot);
9016
9017 }
9018
9019 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9020 {
9021         struct mii_ioctl_data *data = if_mii(ifr);
9022         struct tg3 *tp = netdev_priv(dev);
9023         int err;
9024
9025         switch(cmd) {
9026         case SIOCGMIIPHY:
9027                 data->phy_id = PHY_ADDR;
9028
9029                 /* fallthru */
9030         case SIOCGMIIREG: {
9031                 u32 mii_regval;
9032
9033                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9034                         break;                  /* We have no PHY */
9035
9036                 if (tp->link_config.phy_is_low_power)
9037                         return -EAGAIN;
9038
9039                 spin_lock_bh(&tp->lock);
9040                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9041                 spin_unlock_bh(&tp->lock);
9042
9043                 data->val_out = mii_regval;
9044
9045                 return err;
9046         }
9047
9048         case SIOCSMIIREG:
9049                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9050                         break;                  /* We have no PHY */
9051
9052                 if (!capable(CAP_NET_ADMIN))
9053                         return -EPERM;
9054
9055                 if (tp->link_config.phy_is_low_power)
9056                         return -EAGAIN;
9057
9058                 spin_lock_bh(&tp->lock);
9059                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9060                 spin_unlock_bh(&tp->lock);
9061
9062                 return err;
9063
9064         default:
9065                 /* do nothing */
9066                 break;
9067         }
9068         return -EOPNOTSUPP;
9069 }
9070
9071 #if TG3_VLAN_TAG_USED
9072 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9073 {
9074         struct tg3 *tp = netdev_priv(dev);
9075
9076         if (netif_running(dev))
9077                 tg3_netif_stop(tp);
9078
9079         tg3_full_lock(tp, 0);
9080
9081         tp->vlgrp = grp;
9082
9083         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9084         __tg3_set_rx_mode(dev);
9085
9086         tg3_full_unlock(tp);
9087
9088         if (netif_running(dev))
9089                 tg3_netif_start(tp);
9090 }
9091
9092 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9093 {
9094         struct tg3 *tp = netdev_priv(dev);
9095
9096         if (netif_running(dev))
9097                 tg3_netif_stop(tp);
9098
9099         tg3_full_lock(tp, 0);
9100         if (tp->vlgrp)
9101                 tp->vlgrp->vlan_devices[vid] = NULL;
9102         tg3_full_unlock(tp);
9103
9104         if (netif_running(dev))
9105                 tg3_netif_start(tp);
9106 }
9107 #endif
9108
9109 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9110 {
9111         struct tg3 *tp = netdev_priv(dev);
9112
9113         memcpy(ec, &tp->coal, sizeof(*ec));
9114         return 0;
9115 }
9116
9117 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9118 {
9119         struct tg3 *tp = netdev_priv(dev);
9120         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9121         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9122
9123         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9124                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9125                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9126                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9127                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9128         }
9129
9130         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9131             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9132             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9133             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9134             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9135             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9136             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9137             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9138             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9139             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9140                 return -EINVAL;
9141
9142         /* No rx interrupts will be generated if both are zero */
9143         if ((ec->rx_coalesce_usecs == 0) &&
9144             (ec->rx_max_coalesced_frames == 0))
9145                 return -EINVAL;
9146
9147         /* No tx interrupts will be generated if both are zero */
9148         if ((ec->tx_coalesce_usecs == 0) &&
9149             (ec->tx_max_coalesced_frames == 0))
9150                 return -EINVAL;
9151
9152         /* Only copy relevant parameters, ignore all others. */
9153         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9154         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9155         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9156         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9157         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9158         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9159         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9160         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9161         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9162
9163         if (netif_running(dev)) {
9164                 tg3_full_lock(tp, 0);
9165                 __tg3_set_coalesce(tp, &tp->coal);
9166                 tg3_full_unlock(tp);
9167         }
9168         return 0;
9169 }
9170
9171 static const struct ethtool_ops tg3_ethtool_ops = {
9172         .get_settings           = tg3_get_settings,
9173         .set_settings           = tg3_set_settings,
9174         .get_drvinfo            = tg3_get_drvinfo,
9175         .get_regs_len           = tg3_get_regs_len,
9176         .get_regs               = tg3_get_regs,
9177         .get_wol                = tg3_get_wol,
9178         .set_wol                = tg3_set_wol,
9179         .get_msglevel           = tg3_get_msglevel,
9180         .set_msglevel           = tg3_set_msglevel,
9181         .nway_reset             = tg3_nway_reset,
9182         .get_link               = ethtool_op_get_link,
9183         .get_eeprom_len         = tg3_get_eeprom_len,
9184         .get_eeprom             = tg3_get_eeprom,
9185         .set_eeprom             = tg3_set_eeprom,
9186         .get_ringparam          = tg3_get_ringparam,
9187         .set_ringparam          = tg3_set_ringparam,
9188         .get_pauseparam         = tg3_get_pauseparam,
9189         .set_pauseparam         = tg3_set_pauseparam,
9190         .get_rx_csum            = tg3_get_rx_csum,
9191         .set_rx_csum            = tg3_set_rx_csum,
9192         .get_tx_csum            = ethtool_op_get_tx_csum,
9193         .set_tx_csum            = tg3_set_tx_csum,
9194         .get_sg                 = ethtool_op_get_sg,
9195         .set_sg                 = ethtool_op_set_sg,
9196 #if TG3_TSO_SUPPORT != 0
9197         .get_tso                = ethtool_op_get_tso,
9198         .set_tso                = tg3_set_tso,
9199 #endif
9200         .self_test_count        = tg3_get_test_count,
9201         .self_test              = tg3_self_test,
9202         .get_strings            = tg3_get_strings,
9203         .phys_id                = tg3_phys_id,
9204         .get_stats_count        = tg3_get_stats_count,
9205         .get_ethtool_stats      = tg3_get_ethtool_stats,
9206         .get_coalesce           = tg3_get_coalesce,
9207         .set_coalesce           = tg3_set_coalesce,
9208         .get_perm_addr          = ethtool_op_get_perm_addr,
9209 };
9210
9211 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9212 {
9213         u32 cursize, val, magic;
9214
9215         tp->nvram_size = EEPROM_CHIP_SIZE;
9216
9217         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9218                 return;
9219
9220         if ((magic != TG3_EEPROM_MAGIC) &&
9221             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9222             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9223                 return;
9224
9225         /*
9226          * Size the chip by reading offsets at increasing powers of two.
9227          * When we encounter our validation signature, we know the addressing
9228          * has wrapped around, and thus have our chip size.
9229          */
9230         cursize = 0x10;
9231
9232         while (cursize < tp->nvram_size) {
9233                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9234                         return;
9235
9236                 if (val == magic)
9237                         break;
9238
9239                 cursize <<= 1;
9240         }
9241
9242         tp->nvram_size = cursize;
9243 }
9244
9245 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9246 {
9247         u32 val;
9248
9249         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9250                 return;
9251
9252         /* Selfboot format */
9253         if (val != TG3_EEPROM_MAGIC) {
9254                 tg3_get_eeprom_size(tp);
9255                 return;
9256         }
9257
9258         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9259                 if (val != 0) {
9260                         tp->nvram_size = (val >> 16) * 1024;
9261                         return;
9262                 }
9263         }
9264         tp->nvram_size = 0x20000;
9265 }
9266
9267 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9268 {
9269         u32 nvcfg1;
9270
9271         nvcfg1 = tr32(NVRAM_CFG1);
9272         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9273                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9274         }
9275         else {
9276                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9277                 tw32(NVRAM_CFG1, nvcfg1);
9278         }
9279
9280         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9281             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9282                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9283                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9284                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9285                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9286                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9287                                 break;
9288                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9289                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9290                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9291                                 break;
9292                         case FLASH_VENDOR_ATMEL_EEPROM:
9293                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9294                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9295                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9296                                 break;
9297                         case FLASH_VENDOR_ST:
9298                                 tp->nvram_jedecnum = JEDEC_ST;
9299                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9300                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9301                                 break;
9302                         case FLASH_VENDOR_SAIFUN:
9303                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9304                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9305                                 break;
9306                         case FLASH_VENDOR_SST_SMALL:
9307                         case FLASH_VENDOR_SST_LARGE:
9308                                 tp->nvram_jedecnum = JEDEC_SST;
9309                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9310                                 break;
9311                 }
9312         }
9313         else {
9314                 tp->nvram_jedecnum = JEDEC_ATMEL;
9315                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9316                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9317         }
9318 }
9319
9320 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9321 {
9322         u32 nvcfg1;
9323
9324         nvcfg1 = tr32(NVRAM_CFG1);
9325
9326         /* NVRAM protection for TPM */
9327         if (nvcfg1 & (1 << 27))
9328                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9329
9330         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9331                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9332                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9333                         tp->nvram_jedecnum = JEDEC_ATMEL;
9334                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9335                         break;
9336                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9337                         tp->nvram_jedecnum = JEDEC_ATMEL;
9338                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9339                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9340                         break;
9341                 case FLASH_5752VENDOR_ST_M45PE10:
9342                 case FLASH_5752VENDOR_ST_M45PE20:
9343                 case FLASH_5752VENDOR_ST_M45PE40:
9344                         tp->nvram_jedecnum = JEDEC_ST;
9345                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9346                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9347                         break;
9348         }
9349
9350         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9351                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9352                         case FLASH_5752PAGE_SIZE_256:
9353                                 tp->nvram_pagesize = 256;
9354                                 break;
9355                         case FLASH_5752PAGE_SIZE_512:
9356                                 tp->nvram_pagesize = 512;
9357                                 break;
9358                         case FLASH_5752PAGE_SIZE_1K:
9359                                 tp->nvram_pagesize = 1024;
9360                                 break;
9361                         case FLASH_5752PAGE_SIZE_2K:
9362                                 tp->nvram_pagesize = 2048;
9363                                 break;
9364                         case FLASH_5752PAGE_SIZE_4K:
9365                                 tp->nvram_pagesize = 4096;
9366                                 break;
9367                         case FLASH_5752PAGE_SIZE_264:
9368                                 tp->nvram_pagesize = 264;
9369                                 break;
9370                 }
9371         }
9372         else {
9373                 /* For eeprom, set pagesize to maximum eeprom size */
9374                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9375
9376                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9377                 tw32(NVRAM_CFG1, nvcfg1);
9378         }
9379 }
9380
9381 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9382 {
9383         u32 nvcfg1;
9384
9385         nvcfg1 = tr32(NVRAM_CFG1);
9386
9387         /* NVRAM protection for TPM */
9388         if (nvcfg1 & (1 << 27))
9389                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9390
9391         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9392                 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9393                 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9394                         tp->nvram_jedecnum = JEDEC_ATMEL;
9395                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9396                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9397
9398                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9399                         tw32(NVRAM_CFG1, nvcfg1);
9400                         break;
9401                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9402                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9403                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9404                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9405                 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9406                         tp->nvram_jedecnum = JEDEC_ATMEL;
9407                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9408                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9409                         tp->nvram_pagesize = 264;
9410                         break;
9411                 case FLASH_5752VENDOR_ST_M45PE10:
9412                 case FLASH_5752VENDOR_ST_M45PE20:
9413                 case FLASH_5752VENDOR_ST_M45PE40:
9414                         tp->nvram_jedecnum = JEDEC_ST;
9415                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9416                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9417                         tp->nvram_pagesize = 256;
9418                         break;
9419         }
9420 }
9421
9422 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9423 {
9424         u32 nvcfg1;
9425
9426         nvcfg1 = tr32(NVRAM_CFG1);
9427
9428         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9429                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9430                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9431                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9432                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9433                         tp->nvram_jedecnum = JEDEC_ATMEL;
9434                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9435                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9436
9437                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9438                         tw32(NVRAM_CFG1, nvcfg1);
9439                         break;
9440                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9441                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9442                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9443                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9444                         tp->nvram_jedecnum = JEDEC_ATMEL;
9445                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9446                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9447                         tp->nvram_pagesize = 264;
9448                         break;
9449                 case FLASH_5752VENDOR_ST_M45PE10:
9450                 case FLASH_5752VENDOR_ST_M45PE20:
9451                 case FLASH_5752VENDOR_ST_M45PE40:
9452                         tp->nvram_jedecnum = JEDEC_ST;
9453                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9454                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9455                         tp->nvram_pagesize = 256;
9456                         break;
9457         }
9458 }
9459
9460 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9461 {
9462         tp->nvram_jedecnum = JEDEC_ATMEL;
9463         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9464         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9465 }
9466
9467 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9468 static void __devinit tg3_nvram_init(struct tg3 *tp)
9469 {
9470         tw32_f(GRC_EEPROM_ADDR,
9471              (EEPROM_ADDR_FSM_RESET |
9472               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9473                EEPROM_ADDR_CLKPERD_SHIFT)));
9474
9475         msleep(1);
9476
9477         /* Enable seeprom accesses. */
9478         tw32_f(GRC_LOCAL_CTRL,
9479              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9480         udelay(100);
9481
9482         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9483             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9484                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9485
9486                 if (tg3_nvram_lock(tp)) {
9487                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9488                                "tg3_nvram_init failed.\n", tp->dev->name);
9489                         return;
9490                 }
9491                 tg3_enable_nvram_access(tp);
9492
9493                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9494                         tg3_get_5752_nvram_info(tp);
9495                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9496                         tg3_get_5755_nvram_info(tp);
9497                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9498                         tg3_get_5787_nvram_info(tp);
9499                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9500                         tg3_get_5906_nvram_info(tp);
9501                 else
9502                         tg3_get_nvram_info(tp);
9503
9504                 tg3_get_nvram_size(tp);
9505
9506                 tg3_disable_nvram_access(tp);
9507                 tg3_nvram_unlock(tp);
9508
9509         } else {
9510                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9511
9512                 tg3_get_eeprom_size(tp);
9513         }
9514 }
9515
9516 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9517                                         u32 offset, u32 *val)
9518 {
9519         u32 tmp;
9520         int i;
9521
9522         if (offset > EEPROM_ADDR_ADDR_MASK ||
9523             (offset % 4) != 0)
9524                 return -EINVAL;
9525
9526         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9527                                         EEPROM_ADDR_DEVID_MASK |
9528                                         EEPROM_ADDR_READ);
9529         tw32(GRC_EEPROM_ADDR,
9530              tmp |
9531              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9532              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9533               EEPROM_ADDR_ADDR_MASK) |
9534              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9535
9536         for (i = 0; i < 1000; i++) {
9537                 tmp = tr32(GRC_EEPROM_ADDR);
9538
9539                 if (tmp & EEPROM_ADDR_COMPLETE)
9540                         break;
9541                 msleep(1);
9542         }
9543         if (!(tmp & EEPROM_ADDR_COMPLETE))
9544                 return -EBUSY;
9545
9546         *val = tr32(GRC_EEPROM_DATA);
9547         return 0;
9548 }
9549
9550 #define NVRAM_CMD_TIMEOUT 10000
9551
9552 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9553 {
9554         int i;
9555
9556         tw32(NVRAM_CMD, nvram_cmd);
9557         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9558                 udelay(10);
9559                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9560                         udelay(10);
9561                         break;
9562                 }
9563         }
9564         if (i == NVRAM_CMD_TIMEOUT) {
9565                 return -EBUSY;
9566         }
9567         return 0;
9568 }
9569
9570 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9571 {
9572         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9573             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9574             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9575             (tp->nvram_jedecnum == JEDEC_ATMEL))
9576
9577                 addr = ((addr / tp->nvram_pagesize) <<
9578                         ATMEL_AT45DB0X1B_PAGE_POS) +
9579                        (addr % tp->nvram_pagesize);
9580
9581         return addr;
9582 }
9583
9584 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9585 {
9586         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9587             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9588             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9589             (tp->nvram_jedecnum == JEDEC_ATMEL))
9590
9591                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9592                         tp->nvram_pagesize) +
9593                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9594
9595         return addr;
9596 }
9597
9598 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9599 {
9600         int ret;
9601
9602         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9603                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9604
9605         offset = tg3_nvram_phys_addr(tp, offset);
9606
9607         if (offset > NVRAM_ADDR_MSK)
9608                 return -EINVAL;
9609
9610         ret = tg3_nvram_lock(tp);
9611         if (ret)
9612                 return ret;
9613
9614         tg3_enable_nvram_access(tp);
9615
9616         tw32(NVRAM_ADDR, offset);
9617         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9618                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9619
9620         if (ret == 0)
9621                 *val = swab32(tr32(NVRAM_RDDATA));
9622
9623         tg3_disable_nvram_access(tp);
9624
9625         tg3_nvram_unlock(tp);
9626
9627         return ret;
9628 }
9629
9630 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9631 {
9632         int err;
9633         u32 tmp;
9634
9635         err = tg3_nvram_read(tp, offset, &tmp);
9636         *val = swab32(tmp);
9637         return err;
9638 }
9639
9640 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9641                                     u32 offset, u32 len, u8 *buf)
9642 {
9643         int i, j, rc = 0;
9644         u32 val;
9645
9646         for (i = 0; i < len; i += 4) {
9647                 u32 addr, data;
9648
9649                 addr = offset + i;
9650
9651                 memcpy(&data, buf + i, 4);
9652
9653                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9654
9655                 val = tr32(GRC_EEPROM_ADDR);
9656                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9657
9658                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9659                         EEPROM_ADDR_READ);
9660                 tw32(GRC_EEPROM_ADDR, val |
9661                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9662                         (addr & EEPROM_ADDR_ADDR_MASK) |
9663                         EEPROM_ADDR_START |
9664                         EEPROM_ADDR_WRITE);
9665
9666                 for (j = 0; j < 1000; j++) {
9667                         val = tr32(GRC_EEPROM_ADDR);
9668
9669                         if (val & EEPROM_ADDR_COMPLETE)
9670                                 break;
9671                         msleep(1);
9672                 }
9673                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9674                         rc = -EBUSY;
9675                         break;
9676                 }
9677         }
9678
9679         return rc;
9680 }
9681
9682 /* offset and length are dword aligned */
9683 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9684                 u8 *buf)
9685 {
9686         int ret = 0;
9687         u32 pagesize = tp->nvram_pagesize;
9688         u32 pagemask = pagesize - 1;
9689         u32 nvram_cmd;
9690         u8 *tmp;
9691
9692         tmp = kmalloc(pagesize, GFP_KERNEL);
9693         if (tmp == NULL)
9694                 return -ENOMEM;
9695
9696         while (len) {
9697                 int j;
9698                 u32 phy_addr, page_off, size;
9699
9700                 phy_addr = offset & ~pagemask;
9701
9702                 for (j = 0; j < pagesize; j += 4) {
9703                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9704                                                 (u32 *) (tmp + j))))
9705                                 break;
9706                 }
9707                 if (ret)
9708                         break;
9709
9710                 page_off = offset & pagemask;
9711                 size = pagesize;
9712                 if (len < size)
9713                         size = len;
9714
9715                 len -= size;
9716
9717                 memcpy(tmp + page_off, buf, size);
9718
9719                 offset = offset + (pagesize - page_off);
9720
9721                 tg3_enable_nvram_access(tp);
9722
9723                 /*
9724                  * Before we can erase the flash page, we need
9725                  * to issue a special "write enable" command.
9726                  */
9727                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9728
9729                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9730                         break;
9731
9732                 /* Erase the target page */
9733                 tw32(NVRAM_ADDR, phy_addr);
9734
9735                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9736                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9737
9738                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9739                         break;
9740
9741                 /* Issue another write enable to start the write. */
9742                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9743
9744                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9745                         break;
9746
9747                 for (j = 0; j < pagesize; j += 4) {
9748                         u32 data;
9749
9750                         data = *((u32 *) (tmp + j));
9751                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9752
9753                         tw32(NVRAM_ADDR, phy_addr + j);
9754
9755                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9756                                 NVRAM_CMD_WR;
9757
9758                         if (j == 0)
9759                                 nvram_cmd |= NVRAM_CMD_FIRST;
9760                         else if (j == (pagesize - 4))
9761                                 nvram_cmd |= NVRAM_CMD_LAST;
9762
9763                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9764                                 break;
9765                 }
9766                 if (ret)
9767                         break;
9768         }
9769
9770         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9771         tg3_nvram_exec_cmd(tp, nvram_cmd);
9772
9773         kfree(tmp);
9774
9775         return ret;
9776 }
9777
9778 /* offset and length are dword aligned */
9779 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9780                 u8 *buf)
9781 {
9782         int i, ret = 0;
9783
9784         for (i = 0; i < len; i += 4, offset += 4) {
9785                 u32 data, page_off, phy_addr, nvram_cmd;
9786
9787                 memcpy(&data, buf + i, 4);
9788                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9789
9790                 page_off = offset % tp->nvram_pagesize;
9791
9792                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9793
9794                 tw32(NVRAM_ADDR, phy_addr);
9795
9796                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9797
9798                 if ((page_off == 0) || (i == 0))
9799                         nvram_cmd |= NVRAM_CMD_FIRST;
9800                 if (page_off == (tp->nvram_pagesize - 4))
9801                         nvram_cmd |= NVRAM_CMD_LAST;
9802
9803                 if (i == (len - 4))
9804                         nvram_cmd |= NVRAM_CMD_LAST;
9805
9806                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9807                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9808                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9809                     (tp->nvram_jedecnum == JEDEC_ST) &&
9810                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9811
9812                         if ((ret = tg3_nvram_exec_cmd(tp,
9813                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9814                                 NVRAM_CMD_DONE)))
9815
9816                                 break;
9817                 }
9818                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9819                         /* We always do complete word writes to eeprom. */
9820                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9821                 }
9822
9823                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9824                         break;
9825         }
9826         return ret;
9827 }
9828
9829 /* offset and length are dword aligned */
9830 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9831 {
9832         int ret;
9833
9834         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9835                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9836                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9837                 udelay(40);
9838         }
9839
9840         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9841                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9842         }
9843         else {
9844                 u32 grc_mode;
9845
9846                 ret = tg3_nvram_lock(tp);
9847                 if (ret)
9848                         return ret;
9849
9850                 tg3_enable_nvram_access(tp);
9851                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9852                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9853                         tw32(NVRAM_WRITE1, 0x406);
9854
9855                 grc_mode = tr32(GRC_MODE);
9856                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9857
9858                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9859                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9860
9861                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9862                                 buf);
9863                 }
9864                 else {
9865                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9866                                 buf);
9867                 }
9868
9869                 grc_mode = tr32(GRC_MODE);
9870                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9871
9872                 tg3_disable_nvram_access(tp);
9873                 tg3_nvram_unlock(tp);
9874         }
9875
9876         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9877                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9878                 udelay(40);
9879         }
9880
9881         return ret;
9882 }
9883
9884 struct subsys_tbl_ent {
9885         u16 subsys_vendor, subsys_devid;
9886         u32 phy_id;
9887 };
9888
9889 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9890         /* Broadcom boards. */
9891         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9892         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9893         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9894         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9895         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9896         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9897         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9898         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9899         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9900         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9901         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9902
9903         /* 3com boards. */
9904         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9905         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9906         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9907         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9908         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9909
9910         /* DELL boards. */
9911         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9912         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9913         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9914         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9915
9916         /* Compaq boards. */
9917         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9918         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9919         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9920         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9921         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9922
9923         /* IBM boards. */
9924         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9925 };
9926
9927 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9928 {
9929         int i;
9930
9931         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9932                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9933                      tp->pdev->subsystem_vendor) &&
9934                     (subsys_id_to_phy_id[i].subsys_devid ==
9935                      tp->pdev->subsystem_device))
9936                         return &subsys_id_to_phy_id[i];
9937         }
9938         return NULL;
9939 }
9940
9941 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9942 {
9943         u32 val;
9944         u16 pmcsr;
9945
9946         /* On some early chips the SRAM cannot be accessed in D3hot state,
9947          * so need make sure we're in D0.
9948          */
9949         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9950         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9951         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9952         msleep(1);
9953
9954         /* Make sure register accesses (indirect or otherwise)
9955          * will function correctly.
9956          */
9957         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9958                                tp->misc_host_ctrl);
9959
9960         /* The memory arbiter has to be enabled in order for SRAM accesses
9961          * to succeed.  Normally on powerup the tg3 chip firmware will make
9962          * sure it is enabled, but other entities such as system netboot
9963          * code might disable it.
9964          */
9965         val = tr32(MEMARB_MODE);
9966         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9967
9968         tp->phy_id = PHY_ID_INVALID;
9969         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9970
9971         /* Assume an onboard device by default.  */
9972         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9973
9974         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9975                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
9976                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9977                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
9978                 }
9979                 return;
9980         }
9981
9982         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9983         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9984                 u32 nic_cfg, led_cfg;
9985                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9986                 int eeprom_phy_serdes = 0;
9987
9988                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9989                 tp->nic_sram_data_cfg = nic_cfg;
9990
9991                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9992                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9993                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9994                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9995                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9996                     (ver > 0) && (ver < 0x100))
9997                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9998
9999                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10000                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10001                         eeprom_phy_serdes = 1;
10002
10003                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10004                 if (nic_phy_id != 0) {
10005                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10006                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10007
10008                         eeprom_phy_id  = (id1 >> 16) << 10;
10009                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
10010                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10011                 } else
10012                         eeprom_phy_id = 0;
10013
10014                 tp->phy_id = eeprom_phy_id;
10015                 if (eeprom_phy_serdes) {
10016                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10017                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10018                         else
10019                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10020                 }
10021
10022                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10023                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10024                                     SHASTA_EXT_LED_MODE_MASK);
10025                 else
10026                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10027
10028                 switch (led_cfg) {
10029                 default:
10030                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10031                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10032                         break;
10033
10034                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10035                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10036                         break;
10037
10038                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10039                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10040
10041                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10042                          * read on some older 5700/5701 bootcode.
10043                          */
10044                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10045                             ASIC_REV_5700 ||
10046                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10047                             ASIC_REV_5701)
10048                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10049
10050                         break;
10051
10052                 case SHASTA_EXT_LED_SHARED:
10053                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10054                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10055                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10056                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10057                                                  LED_CTRL_MODE_PHY_2);
10058                         break;
10059
10060                 case SHASTA_EXT_LED_MAC:
10061                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10062                         break;
10063
10064                 case SHASTA_EXT_LED_COMBO:
10065                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10066                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10067                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10068                                                  LED_CTRL_MODE_PHY_2);
10069                         break;
10070
10071                 };
10072
10073                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10074                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10075                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10076                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10077
10078                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10079                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10080                         if ((tp->pdev->subsystem_vendor ==
10081                              PCI_VENDOR_ID_ARIMA) &&
10082                             (tp->pdev->subsystem_device == 0x205a ||
10083                              tp->pdev->subsystem_device == 0x2063))
10084                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10085                 } else {
10086                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10087                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10088                 }
10089
10090                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10091                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10092                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10093                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10094                 }
10095                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10096                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10097
10098                 if (cfg2 & (1 << 17))
10099                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10100
10101                 /* serdes signal pre-emphasis in register 0x590 set by */
10102                 /* bootcode if bit 18 is set */
10103                 if (cfg2 & (1 << 18))
10104                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10105         }
10106 }
10107
10108 static int __devinit tg3_phy_probe(struct tg3 *tp)
10109 {
10110         u32 hw_phy_id_1, hw_phy_id_2;
10111         u32 hw_phy_id, hw_phy_id_masked;
10112         int err;
10113
10114         /* Reading the PHY ID register can conflict with ASF
10115          * firwmare access to the PHY hardware.
10116          */
10117         err = 0;
10118         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10119                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10120         } else {
10121                 /* Now read the physical PHY_ID from the chip and verify
10122                  * that it is sane.  If it doesn't look good, we fall back
10123                  * to either the hard-coded table based PHY_ID and failing
10124                  * that the value found in the eeprom area.
10125                  */
10126                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10127                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10128
10129                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
10130                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10131                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
10132
10133                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10134         }
10135
10136         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10137                 tp->phy_id = hw_phy_id;
10138                 if (hw_phy_id_masked == PHY_ID_BCM8002)
10139                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10140                 else
10141                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10142         } else {
10143                 if (tp->phy_id != PHY_ID_INVALID) {
10144                         /* Do nothing, phy ID already set up in
10145                          * tg3_get_eeprom_hw_cfg().
10146                          */
10147                 } else {
10148                         struct subsys_tbl_ent *p;
10149
10150                         /* No eeprom signature?  Try the hardcoded
10151                          * subsys device table.
10152                          */
10153                         p = lookup_by_subsys(tp);
10154                         if (!p)
10155                                 return -ENODEV;
10156
10157                         tp->phy_id = p->phy_id;
10158                         if (!tp->phy_id ||
10159                             tp->phy_id == PHY_ID_BCM8002)
10160                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10161                 }
10162         }
10163
10164         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10165             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10166                 u32 bmsr, adv_reg, tg3_ctrl, mask;
10167
10168                 tg3_readphy(tp, MII_BMSR, &bmsr);
10169                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10170                     (bmsr & BMSR_LSTATUS))
10171                         goto skip_phy_reset;
10172
10173                 err = tg3_phy_reset(tp);
10174                 if (err)
10175                         return err;
10176
10177                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10178                            ADVERTISE_100HALF | ADVERTISE_100FULL |
10179                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10180                 tg3_ctrl = 0;
10181                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10182                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10183                                     MII_TG3_CTRL_ADV_1000_FULL);
10184                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10185                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10186                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10187                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
10188                 }
10189
10190                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10191                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10192                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10193                 if (!tg3_copper_is_advertising_all(tp, mask)) {
10194                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10195
10196                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10197                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10198
10199                         tg3_writephy(tp, MII_BMCR,
10200                                      BMCR_ANENABLE | BMCR_ANRESTART);
10201                 }
10202                 tg3_phy_set_wirespeed(tp);
10203
10204                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10205                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10206                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10207         }
10208
10209 skip_phy_reset:
10210         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10211                 err = tg3_init_5401phy_dsp(tp);
10212                 if (err)
10213                         return err;
10214         }
10215
10216         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10217                 err = tg3_init_5401phy_dsp(tp);
10218         }
10219
10220         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10221                 tp->link_config.advertising =
10222                         (ADVERTISED_1000baseT_Half |
10223                          ADVERTISED_1000baseT_Full |
10224                          ADVERTISED_Autoneg |
10225                          ADVERTISED_FIBRE);
10226         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10227                 tp->link_config.advertising &=
10228                         ~(ADVERTISED_1000baseT_Half |
10229                           ADVERTISED_1000baseT_Full);
10230
10231         return err;
10232 }
10233
10234 static void __devinit tg3_read_partno(struct tg3 *tp)
10235 {
10236         unsigned char vpd_data[256];
10237         unsigned int i;
10238         u32 magic;
10239
10240         if (tg3_nvram_read_swab(tp, 0x0, &magic))
10241                 goto out_not_found;
10242
10243         if (magic == TG3_EEPROM_MAGIC) {
10244                 for (i = 0; i < 256; i += 4) {
10245                         u32 tmp;
10246
10247                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10248                                 goto out_not_found;
10249
10250                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
10251                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
10252                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10253                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10254                 }
10255         } else {
10256                 int vpd_cap;
10257
10258                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10259                 for (i = 0; i < 256; i += 4) {
10260                         u32 tmp, j = 0;
10261                         u16 tmp16;
10262
10263                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10264                                               i);
10265                         while (j++ < 100) {
10266                                 pci_read_config_word(tp->pdev, vpd_cap +
10267                                                      PCI_VPD_ADDR, &tmp16);
10268                                 if (tmp16 & 0x8000)
10269                                         break;
10270                                 msleep(1);
10271                         }
10272                         if (!(tmp16 & 0x8000))
10273                                 goto out_not_found;
10274
10275                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10276                                               &tmp);
10277                         tmp = cpu_to_le32(tmp);
10278                         memcpy(&vpd_data[i], &tmp, 4);
10279                 }
10280         }
10281
10282         /* Now parse and find the part number. */
10283         for (i = 0; i < 254; ) {
10284                 unsigned char val = vpd_data[i];
10285                 unsigned int block_end;
10286
10287                 if (val == 0x82 || val == 0x91) {
10288                         i = (i + 3 +
10289                              (vpd_data[i + 1] +
10290                               (vpd_data[i + 2] << 8)));
10291                         continue;
10292                 }
10293
10294                 if (val != 0x90)
10295                         goto out_not_found;
10296
10297                 block_end = (i + 3 +
10298                              (vpd_data[i + 1] +
10299                               (vpd_data[i + 2] << 8)));
10300                 i += 3;
10301
10302                 if (block_end > 256)
10303                         goto out_not_found;
10304
10305                 while (i < (block_end - 2)) {
10306                         if (vpd_data[i + 0] == 'P' &&
10307                             vpd_data[i + 1] == 'N') {
10308                                 int partno_len = vpd_data[i + 2];
10309
10310                                 i += 3;
10311                                 if (partno_len > 24 || (partno_len + i) > 256)
10312                                         goto out_not_found;
10313
10314                                 memcpy(tp->board_part_number,
10315                                        &vpd_data[i], partno_len);
10316
10317                                 /* Success. */
10318                                 return;
10319                         }
10320                         i += 3 + vpd_data[i + 2];
10321                 }
10322
10323                 /* Part number not found. */
10324                 goto out_not_found;
10325         }
10326
10327 out_not_found:
10328         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10329                 strcpy(tp->board_part_number, "BCM95906");
10330         else
10331                 strcpy(tp->board_part_number, "none");
10332 }
10333
10334 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10335 {
10336         u32 val, offset, start;
10337
10338         if (tg3_nvram_read_swab(tp, 0, &val))
10339                 return;
10340
10341         if (val != TG3_EEPROM_MAGIC)
10342                 return;
10343
10344         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10345             tg3_nvram_read_swab(tp, 0x4, &start))
10346                 return;
10347
10348         offset = tg3_nvram_logical_addr(tp, offset);
10349         if (tg3_nvram_read_swab(tp, offset, &val))
10350                 return;
10351
10352         if ((val & 0xfc000000) == 0x0c000000) {
10353                 u32 ver_offset, addr;
10354                 int i;
10355
10356                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10357                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10358                         return;
10359
10360                 if (val != 0)
10361                         return;
10362
10363                 addr = offset + ver_offset - start;
10364                 for (i = 0; i < 16; i += 4) {
10365                         if (tg3_nvram_read(tp, addr + i, &val))
10366                                 return;
10367
10368                         val = cpu_to_le32(val);
10369                         memcpy(tp->fw_ver + i, &val, 4);
10370                 }
10371         }
10372 }
10373
10374 static int __devinit tg3_get_invariants(struct tg3 *tp)
10375 {
10376         static struct pci_device_id write_reorder_chipsets[] = {
10377                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10378                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10379                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10380                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10381                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10382                              PCI_DEVICE_ID_VIA_8385_0) },
10383                 { },
10384         };
10385         u32 misc_ctrl_reg;
10386         u32 cacheline_sz_reg;
10387         u32 pci_state_reg, grc_misc_cfg;
10388         u32 val;
10389         u16 pci_cmd;
10390         int err, pcie_cap;
10391
10392         /* Force memory write invalidate off.  If we leave it on,
10393          * then on 5700_BX chips we have to enable a workaround.
10394          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10395          * to match the cacheline size.  The Broadcom driver have this
10396          * workaround but turns MWI off all the times so never uses
10397          * it.  This seems to suggest that the workaround is insufficient.
10398          */
10399         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10400         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10401         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10402
10403         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10404          * has the register indirect write enable bit set before
10405          * we try to access any of the MMIO registers.  It is also
10406          * critical that the PCI-X hw workaround situation is decided
10407          * before that as well.
10408          */
10409         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10410                               &misc_ctrl_reg);
10411
10412         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10413                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10414
10415         /* Wrong chip ID in 5752 A0. This code can be removed later
10416          * as A0 is not in production.
10417          */
10418         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10419                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10420
10421         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10422          * we need to disable memory and use config. cycles
10423          * only to access all registers. The 5702/03 chips
10424          * can mistakenly decode the special cycles from the
10425          * ICH chipsets as memory write cycles, causing corruption
10426          * of register and memory space. Only certain ICH bridges
10427          * will drive special cycles with non-zero data during the
10428          * address phase which can fall within the 5703's address
10429          * range. This is not an ICH bug as the PCI spec allows
10430          * non-zero address during special cycles. However, only
10431          * these ICH bridges are known to drive non-zero addresses
10432          * during special cycles.
10433          *
10434          * Since special cycles do not cross PCI bridges, we only
10435          * enable this workaround if the 5703 is on the secondary
10436          * bus of these ICH bridges.
10437          */
10438         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10439             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10440                 static struct tg3_dev_id {
10441                         u32     vendor;
10442                         u32     device;
10443                         u32     rev;
10444                 } ich_chipsets[] = {
10445                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10446                           PCI_ANY_ID },
10447                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10448                           PCI_ANY_ID },
10449                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10450                           0xa },
10451                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10452                           PCI_ANY_ID },
10453                         { },
10454                 };
10455                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10456                 struct pci_dev *bridge = NULL;
10457
10458                 while (pci_id->vendor != 0) {
10459                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10460                                                 bridge);
10461                         if (!bridge) {
10462                                 pci_id++;
10463                                 continue;
10464                         }
10465                         if (pci_id->rev != PCI_ANY_ID) {
10466                                 u8 rev;
10467
10468                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10469                                                      &rev);
10470                                 if (rev > pci_id->rev)
10471                                         continue;
10472                         }
10473                         if (bridge->subordinate &&
10474                             (bridge->subordinate->number ==
10475                              tp->pdev->bus->number)) {
10476
10477                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10478                                 pci_dev_put(bridge);
10479                                 break;
10480                         }
10481                 }
10482         }
10483
10484         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10485          * DMA addresses > 40-bit. This bridge may have other additional
10486          * 57xx devices behind it in some 4-port NIC designs for example.
10487          * Any tg3 device found behind the bridge will also need the 40-bit
10488          * DMA workaround.
10489          */
10490         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10491             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10492                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10493                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10494                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10495         }
10496         else {
10497                 struct pci_dev *bridge = NULL;
10498
10499                 do {
10500                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10501                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10502                                                 bridge);
10503                         if (bridge && bridge->subordinate &&
10504                             (bridge->subordinate->number <=
10505                              tp->pdev->bus->number) &&
10506                             (bridge->subordinate->subordinate >=
10507                              tp->pdev->bus->number)) {
10508                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10509                                 pci_dev_put(bridge);
10510                                 break;
10511                         }
10512                 } while (bridge);
10513         }
10514
10515         /* Initialize misc host control in PCI block. */
10516         tp->misc_host_ctrl |= (misc_ctrl_reg &
10517                                MISC_HOST_CTRL_CHIPREV);
10518         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10519                                tp->misc_host_ctrl);
10520
10521         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10522                               &cacheline_sz_reg);
10523
10524         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10525         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10526         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10527         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10528
10529         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10530             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10531             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10532             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10533             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10534             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10535                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10536
10537         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10538             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10539                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10540
10541         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10542                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10543                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10544                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10545                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10546                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10547                 } else {
10548                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 |
10549                                           TG3_FLG2_HW_TSO_1_BUG;
10550                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10551                                 ASIC_REV_5750 &&
10552                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10553                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG;
10554                 }
10555         }
10556
10557         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10558             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10559             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10560             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10561             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10562             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10563                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10564
10565         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10566         if (pcie_cap != 0) {
10567                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10568                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10569                         u16 lnkctl;
10570
10571                         pci_read_config_word(tp->pdev,
10572                                              pcie_cap + PCI_EXP_LNKCTL,
10573                                              &lnkctl);
10574                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10575                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10576                 }
10577         }
10578
10579         /* If we have an AMD 762 or VIA K8T800 chipset, write
10580          * reordering to the mailbox registers done by the host
10581          * controller can cause major troubles.  We read back from
10582          * every mailbox register write to force the writes to be
10583          * posted to the chip in order.
10584          */
10585         if (pci_dev_present(write_reorder_chipsets) &&
10586             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10587                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10588
10589         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10590             tp->pci_lat_timer < 64) {
10591                 tp->pci_lat_timer = 64;
10592
10593                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10594                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10595                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10596                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10597
10598                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10599                                        cacheline_sz_reg);
10600         }
10601
10602         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10603                               &pci_state_reg);
10604
10605         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10606                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10607
10608                 /* If this is a 5700 BX chipset, and we are in PCI-X
10609                  * mode, enable register write workaround.
10610                  *
10611                  * The workaround is to use indirect register accesses
10612                  * for all chip writes not to mailbox registers.
10613                  */
10614                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10615                         u32 pm_reg;
10616                         u16 pci_cmd;
10617
10618                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10619
10620                         /* The chip can have it's power management PCI config
10621                          * space registers clobbered due to this bug.
10622                          * So explicitly force the chip into D0 here.
10623                          */
10624                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10625                                               &pm_reg);
10626                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10627                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10628                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10629                                                pm_reg);
10630
10631                         /* Also, force SERR#/PERR# in PCI command. */
10632                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10633                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10634                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10635                 }
10636         }
10637
10638         /* 5700 BX chips need to have their TX producer index mailboxes
10639          * written twice to workaround a bug.
10640          */
10641         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10642                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10643
10644         /* Back to back register writes can cause problems on this chip,
10645          * the workaround is to read back all reg writes except those to
10646          * mailbox regs.  See tg3_write_indirect_reg32().
10647          *
10648          * PCI Express 5750_A0 rev chips need this workaround too.
10649          */
10650         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10651             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10652              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10653                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10654
10655         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10656                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10657         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10658                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10659
10660         /* Chip-specific fixup from Broadcom driver */
10661         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10662             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10663                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10664                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10665         }
10666
10667         /* Default fast path register access methods */
10668         tp->read32 = tg3_read32;
10669         tp->write32 = tg3_write32;
10670         tp->read32_mbox = tg3_read32;
10671         tp->write32_mbox = tg3_write32;
10672         tp->write32_tx_mbox = tg3_write32;
10673         tp->write32_rx_mbox = tg3_write32;
10674
10675         /* Various workaround register access methods */
10676         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10677                 tp->write32 = tg3_write_indirect_reg32;
10678         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10679                 tp->write32 = tg3_write_flush_reg32;
10680
10681         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10682             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10683                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10684                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10685                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10686         }
10687
10688         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10689                 tp->read32 = tg3_read_indirect_reg32;
10690                 tp->write32 = tg3_write_indirect_reg32;
10691                 tp->read32_mbox = tg3_read_indirect_mbox;
10692                 tp->write32_mbox = tg3_write_indirect_mbox;
10693                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10694                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10695
10696                 iounmap(tp->regs);
10697                 tp->regs = NULL;
10698
10699                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10700                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10701                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10702         }
10703         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10704                 tp->read32_mbox = tg3_read32_mbox_5906;
10705                 tp->write32_mbox = tg3_write32_mbox_5906;
10706                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10707                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10708         }
10709
10710         if (tp->write32 == tg3_write_indirect_reg32 ||
10711             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10712              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10713               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10714                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10715
10716         /* Get eeprom hw config before calling tg3_set_power_state().
10717          * In particular, the TG3_FLG2_IS_NIC flag must be
10718          * determined before calling tg3_set_power_state() so that
10719          * we know whether or not to switch out of Vaux power.
10720          * When the flag is set, it means that GPIO1 is used for eeprom
10721          * write protect and also implies that it is a LOM where GPIOs
10722          * are not used to switch power.
10723          */
10724         tg3_get_eeprom_hw_cfg(tp);
10725
10726         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10727          * GPIO1 driven high will bring 5700's external PHY out of reset.
10728          * It is also used as eeprom write protect on LOMs.
10729          */
10730         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10731         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10732             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10733                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10734                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10735         /* Unused GPIO3 must be driven as output on 5752 because there
10736          * are no pull-up resistors on unused GPIO pins.
10737          */
10738         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10739                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10740
10741         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10742                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10743
10744         /* Force the chip into D0. */
10745         err = tg3_set_power_state(tp, PCI_D0);
10746         if (err) {
10747                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10748                        pci_name(tp->pdev));
10749                 return err;
10750         }
10751
10752         /* 5700 B0 chips do not support checksumming correctly due
10753          * to hardware bugs.
10754          */
10755         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10756                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10757
10758         /* Derive initial jumbo mode from MTU assigned in
10759          * ether_setup() via the alloc_etherdev() call
10760          */
10761         if (tp->dev->mtu > ETH_DATA_LEN &&
10762             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10763                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10764
10765         /* Determine WakeOnLan speed to use. */
10766         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10767             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10768             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10769             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10770                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10771         } else {
10772                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10773         }
10774
10775         /* A few boards don't want Ethernet@WireSpeed phy feature */
10776         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10777             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10778              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10779              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10780             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10781             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10782                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10783
10784         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10785             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10786                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10787         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10788                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10789
10790         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10791                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10792                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10793                         tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10794                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10795                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10796         }
10797
10798         tp->coalesce_mode = 0;
10799         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10800             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10801                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10802
10803         /* Initialize MAC MI mode, polling disabled. */
10804         tw32_f(MAC_MI_MODE, tp->mi_mode);
10805         udelay(80);
10806
10807         /* Initialize data/descriptor byte/word swapping. */
10808         val = tr32(GRC_MODE);
10809         val &= GRC_MODE_HOST_STACKUP;
10810         tw32(GRC_MODE, val | tp->grc_mode);
10811
10812         tg3_switch_clocks(tp);
10813
10814         /* Clear this out for sanity. */
10815         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10816
10817         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10818                               &pci_state_reg);
10819         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10820             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10821                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10822
10823                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10824                     chiprevid == CHIPREV_ID_5701_B0 ||
10825                     chiprevid == CHIPREV_ID_5701_B2 ||
10826                     chiprevid == CHIPREV_ID_5701_B5) {
10827                         void __iomem *sram_base;
10828
10829                         /* Write some dummy words into the SRAM status block
10830                          * area, see if it reads back correctly.  If the return
10831                          * value is bad, force enable the PCIX workaround.
10832                          */
10833                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10834
10835                         writel(0x00000000, sram_base);
10836                         writel(0x00000000, sram_base + 4);
10837                         writel(0xffffffff, sram_base + 4);
10838                         if (readl(sram_base) != 0x00000000)
10839                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10840                 }
10841         }
10842
10843         udelay(50);
10844         tg3_nvram_init(tp);
10845
10846         grc_misc_cfg = tr32(GRC_MISC_CFG);
10847         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10848
10849         /* Broadcom's driver says that CIOBE multisplit has a bug */
10850 #if 0
10851         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10852             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10853                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10854                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10855         }
10856 #endif
10857         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10858             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10859              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10860                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10861
10862         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10863             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10864                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10865         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10866                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10867                                       HOSTCC_MODE_CLRTICK_TXBD);
10868
10869                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10870                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10871                                        tp->misc_host_ctrl);
10872         }
10873
10874         /* these are limited to 10/100 only */
10875         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10876              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10877             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10878              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10879              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10880               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10881               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10882             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10883              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10884               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10885               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10886             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10887                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10888
10889         err = tg3_phy_probe(tp);
10890         if (err) {
10891                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10892                        pci_name(tp->pdev), err);
10893                 /* ... but do not return immediately ... */
10894         }
10895
10896         tg3_read_partno(tp);
10897         tg3_read_fw_ver(tp);
10898
10899         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10900                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10901         } else {
10902                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10903                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10904                 else
10905                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10906         }
10907
10908         /* 5700 {AX,BX} chips have a broken status block link
10909          * change bit implementation, so we must use the
10910          * status register in those cases.
10911          */
10912         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10913                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10914         else
10915                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10916
10917         /* The led_ctrl is set during tg3_phy_probe, here we might
10918          * have to force the link status polling mechanism based
10919          * upon subsystem IDs.
10920          */
10921         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10922             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10923                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10924                                   TG3_FLAG_USE_LINKCHG_REG);
10925         }
10926
10927         /* For all SERDES we poll the MAC status register. */
10928         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10929                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10930         else
10931                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10932
10933         /* All chips before 5787 can get confused if TX buffers
10934          * straddle the 4GB address boundary in some cases.
10935          */
10936         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10937             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10938             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10939                 tp->dev->hard_start_xmit = tg3_start_xmit;
10940         else
10941                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10942
10943         tp->rx_offset = 2;
10944         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10945             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10946                 tp->rx_offset = 0;
10947
10948         tp->rx_std_max_post = TG3_RX_RING_SIZE;
10949
10950         /* Increment the rx prod index on the rx std ring by at most
10951          * 8 for these chips to workaround hw errata.
10952          */
10953         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10954             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10955             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10956                 tp->rx_std_max_post = 8;
10957
10958         /* By default, disable wake-on-lan.  User can change this
10959          * using ETHTOOL_SWOL.
10960          */
10961         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10962
10963         return err;
10964 }
10965
10966 #ifdef CONFIG_SPARC64
10967 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10968 {
10969         struct net_device *dev = tp->dev;
10970         struct pci_dev *pdev = tp->pdev;
10971         struct pcidev_cookie *pcp = pdev->sysdata;
10972
10973         if (pcp != NULL) {
10974                 unsigned char *addr;
10975                 int len;
10976
10977                 addr = of_get_property(pcp->prom_node, "local-mac-address",
10978                                         &len);
10979                 if (addr && len == 6) {
10980                         memcpy(dev->dev_addr, addr, 6);
10981                         memcpy(dev->perm_addr, dev->dev_addr, 6);
10982                         return 0;
10983                 }
10984         }
10985         return -ENODEV;
10986 }
10987
10988 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10989 {
10990         struct net_device *dev = tp->dev;
10991
10992         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
10993         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
10994         return 0;
10995 }
10996 #endif
10997
10998 static int __devinit tg3_get_device_address(struct tg3 *tp)
10999 {
11000         struct net_device *dev = tp->dev;
11001         u32 hi, lo, mac_offset;
11002         int addr_ok = 0;
11003
11004 #ifdef CONFIG_SPARC64
11005         if (!tg3_get_macaddr_sparc(tp))
11006                 return 0;
11007 #endif
11008
11009         mac_offset = 0x7c;
11010         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11011             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11012                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11013                         mac_offset = 0xcc;
11014                 if (tg3_nvram_lock(tp))
11015                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11016                 else
11017                         tg3_nvram_unlock(tp);
11018         }
11019         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11020                 mac_offset = 0x10;
11021
11022         /* First try to get it from MAC address mailbox. */
11023         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11024         if ((hi >> 16) == 0x484b) {
11025                 dev->dev_addr[0] = (hi >>  8) & 0xff;
11026                 dev->dev_addr[1] = (hi >>  0) & 0xff;
11027
11028                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11029                 dev->dev_addr[2] = (lo >> 24) & 0xff;
11030                 dev->dev_addr[3] = (lo >> 16) & 0xff;
11031                 dev->dev_addr[4] = (lo >>  8) & 0xff;
11032                 dev->dev_addr[5] = (lo >>  0) & 0xff;
11033
11034                 /* Some old bootcode may report a 0 MAC address in SRAM */
11035                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11036         }
11037         if (!addr_ok) {
11038                 /* Next, try NVRAM. */
11039                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11040                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11041                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
11042                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
11043                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
11044                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
11045                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
11046                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
11047                 }
11048                 /* Finally just fetch it out of the MAC control regs. */
11049                 else {
11050                         hi = tr32(MAC_ADDR_0_HIGH);
11051                         lo = tr32(MAC_ADDR_0_LOW);
11052
11053                         dev->dev_addr[5] = lo & 0xff;
11054                         dev->dev_addr[4] = (lo >> 8) & 0xff;
11055                         dev->dev_addr[3] = (lo >> 16) & 0xff;
11056                         dev->dev_addr[2] = (lo >> 24) & 0xff;
11057                         dev->dev_addr[1] = hi & 0xff;
11058                         dev->dev_addr[0] = (hi >> 8) & 0xff;
11059                 }
11060         }
11061
11062         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11063 #ifdef CONFIG_SPARC64
11064                 if (!tg3_get_default_macaddr_sparc(tp))
11065                         return 0;
11066 #endif
11067                 return -EINVAL;
11068         }
11069         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11070         return 0;
11071 }
11072
11073 #define BOUNDARY_SINGLE_CACHELINE       1
11074 #define BOUNDARY_MULTI_CACHELINE        2
11075
11076 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11077 {
11078         int cacheline_size;
11079         u8 byte;
11080         int goal;
11081
11082         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11083         if (byte == 0)
11084                 cacheline_size = 1024;
11085         else
11086                 cacheline_size = (int) byte * 4;
11087
11088         /* On 5703 and later chips, the boundary bits have no
11089          * effect.
11090          */
11091         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11092             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11093             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11094                 goto out;
11095
11096 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11097         goal = BOUNDARY_MULTI_CACHELINE;
11098 #else
11099 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11100         goal = BOUNDARY_SINGLE_CACHELINE;
11101 #else
11102         goal = 0;
11103 #endif
11104 #endif
11105
11106         if (!goal)
11107                 goto out;
11108
11109         /* PCI controllers on most RISC systems tend to disconnect
11110          * when a device tries to burst across a cache-line boundary.
11111          * Therefore, letting tg3 do so just wastes PCI bandwidth.
11112          *
11113          * Unfortunately, for PCI-E there are only limited
11114          * write-side controls for this, and thus for reads
11115          * we will still get the disconnects.  We'll also waste
11116          * these PCI cycles for both read and write for chips
11117          * other than 5700 and 5701 which do not implement the
11118          * boundary bits.
11119          */
11120         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11121             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11122                 switch (cacheline_size) {
11123                 case 16:
11124                 case 32:
11125                 case 64:
11126                 case 128:
11127                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11128                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11129                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11130                         } else {
11131                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11132                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11133                         }
11134                         break;
11135
11136                 case 256:
11137                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11138                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11139                         break;
11140
11141                 default:
11142                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11143                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11144                         break;
11145                 };
11146         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11147                 switch (cacheline_size) {
11148                 case 16:
11149                 case 32:
11150                 case 64:
11151                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11152                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11153                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11154                                 break;
11155                         }
11156                         /* fallthrough */
11157                 case 128:
11158                 default:
11159                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11160                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11161                         break;
11162                 };
11163         } else {
11164                 switch (cacheline_size) {
11165                 case 16:
11166                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11167                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11168                                         DMA_RWCTRL_WRITE_BNDRY_16);
11169                                 break;
11170                         }
11171                         /* fallthrough */
11172                 case 32:
11173                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11174                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11175                                         DMA_RWCTRL_WRITE_BNDRY_32);
11176                                 break;
11177                         }
11178                         /* fallthrough */
11179                 case 64:
11180                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11181                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11182                                         DMA_RWCTRL_WRITE_BNDRY_64);
11183                                 break;
11184                         }
11185                         /* fallthrough */
11186                 case 128:
11187                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11188                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11189                                         DMA_RWCTRL_WRITE_BNDRY_128);
11190                                 break;
11191                         }
11192                         /* fallthrough */
11193                 case 256:
11194                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
11195                                 DMA_RWCTRL_WRITE_BNDRY_256);
11196                         break;
11197                 case 512:
11198                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
11199                                 DMA_RWCTRL_WRITE_BNDRY_512);
11200                         break;
11201                 case 1024:
11202                 default:
11203                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11204                                 DMA_RWCTRL_WRITE_BNDRY_1024);
11205                         break;
11206                 };
11207         }
11208
11209 out:
11210         return val;
11211 }
11212
11213 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11214 {
11215         struct tg3_internal_buffer_desc test_desc;
11216         u32 sram_dma_descs;
11217         int i, ret;
11218
11219         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11220
11221         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11222         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11223         tw32(RDMAC_STATUS, 0);
11224         tw32(WDMAC_STATUS, 0);
11225
11226         tw32(BUFMGR_MODE, 0);
11227         tw32(FTQ_RESET, 0);
11228
11229         test_desc.addr_hi = ((u64) buf_dma) >> 32;
11230         test_desc.addr_lo = buf_dma & 0xffffffff;
11231         test_desc.nic_mbuf = 0x00002100;
11232         test_desc.len = size;
11233
11234         /*
11235          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11236          * the *second* time the tg3 driver was getting loaded after an
11237          * initial scan.
11238          *
11239          * Broadcom tells me:
11240          *   ...the DMA engine is connected to the GRC block and a DMA
11241          *   reset may affect the GRC block in some unpredictable way...
11242          *   The behavior of resets to individual blocks has not been tested.
11243          *
11244          * Broadcom noted the GRC reset will also reset all sub-components.
11245          */
11246         if (to_device) {
11247                 test_desc.cqid_sqid = (13 << 8) | 2;
11248
11249                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11250                 udelay(40);
11251         } else {
11252                 test_desc.cqid_sqid = (16 << 8) | 7;
11253
11254                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11255                 udelay(40);
11256         }
11257         test_desc.flags = 0x00000005;
11258
11259         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11260                 u32 val;
11261
11262                 val = *(((u32 *)&test_desc) + i);
11263                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11264                                        sram_dma_descs + (i * sizeof(u32)));
11265                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11266         }
11267         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11268
11269         if (to_device) {
11270                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11271         } else {
11272                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11273         }
11274
11275         ret = -ENODEV;
11276         for (i = 0; i < 40; i++) {
11277                 u32 val;
11278
11279                 if (to_device)
11280                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11281                 else
11282                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11283                 if ((val & 0xffff) == sram_dma_descs) {
11284                         ret = 0;
11285                         break;
11286                 }
11287
11288                 udelay(100);
11289         }
11290
11291         return ret;
11292 }
11293
11294 #define TEST_BUFFER_SIZE        0x2000
11295
11296 static int __devinit tg3_test_dma(struct tg3 *tp)
11297 {
11298         dma_addr_t buf_dma;
11299         u32 *buf, saved_dma_rwctrl;
11300         int ret;
11301
11302         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11303         if (!buf) {
11304                 ret = -ENOMEM;
11305                 goto out_nofree;
11306         }
11307
11308         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11309                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11310
11311         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11312
11313         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11314                 /* DMA read watermark not used on PCIE */
11315                 tp->dma_rwctrl |= 0x00180000;
11316         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11317                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11318                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11319                         tp->dma_rwctrl |= 0x003f0000;
11320                 else
11321                         tp->dma_rwctrl |= 0x003f000f;
11322         } else {
11323                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11324                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11325                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11326
11327                         /* If the 5704 is behind the EPB bridge, we can
11328                          * do the less restrictive ONE_DMA workaround for
11329                          * better performance.
11330                          */
11331                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11332                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11333                                 tp->dma_rwctrl |= 0x8000;
11334                         else if (ccval == 0x6 || ccval == 0x7)
11335                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11336
11337                         /* Set bit 23 to enable PCIX hw bug fix */
11338                         tp->dma_rwctrl |= 0x009f0000;
11339                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11340                         /* 5780 always in PCIX mode */
11341                         tp->dma_rwctrl |= 0x00144000;
11342                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11343                         /* 5714 always in PCIX mode */
11344                         tp->dma_rwctrl |= 0x00148000;
11345                 } else {
11346                         tp->dma_rwctrl |= 0x001b000f;
11347                 }
11348         }
11349
11350         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11351             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11352                 tp->dma_rwctrl &= 0xfffffff0;
11353
11354         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11355             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11356                 /* Remove this if it causes problems for some boards. */
11357                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11358
11359                 /* On 5700/5701 chips, we need to set this bit.
11360                  * Otherwise the chip will issue cacheline transactions
11361                  * to streamable DMA memory with not all the byte
11362                  * enables turned on.  This is an error on several
11363                  * RISC PCI controllers, in particular sparc64.
11364                  *
11365                  * On 5703/5704 chips, this bit has been reassigned
11366                  * a different meaning.  In particular, it is used
11367                  * on those chips to enable a PCI-X workaround.
11368                  */
11369                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11370         }
11371
11372         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11373
11374 #if 0
11375         /* Unneeded, already done by tg3_get_invariants.  */
11376         tg3_switch_clocks(tp);
11377 #endif
11378
11379         ret = 0;
11380         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11381             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11382                 goto out;
11383
11384         /* It is best to perform DMA test with maximum write burst size
11385          * to expose the 5700/5701 write DMA bug.
11386          */
11387         saved_dma_rwctrl = tp->dma_rwctrl;
11388         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11389         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11390
11391         while (1) {
11392                 u32 *p = buf, i;
11393
11394                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11395                         p[i] = i;
11396
11397                 /* Send the buffer to the chip. */
11398                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11399                 if (ret) {
11400                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11401                         break;
11402                 }
11403
11404 #if 0
11405                 /* validate data reached card RAM correctly. */
11406                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11407                         u32 val;
11408                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
11409                         if (le32_to_cpu(val) != p[i]) {
11410                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
11411                                 /* ret = -ENODEV here? */
11412                         }
11413                         p[i] = 0;
11414                 }
11415 #endif
11416                 /* Now read it back. */
11417                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11418                 if (ret) {
11419                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11420
11421                         break;
11422                 }
11423
11424                 /* Verify it. */
11425                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11426                         if (p[i] == i)
11427                                 continue;
11428
11429                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11430                             DMA_RWCTRL_WRITE_BNDRY_16) {
11431                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11432                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11433                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11434                                 break;
11435                         } else {
11436                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11437                                 ret = -ENODEV;
11438                                 goto out;
11439                         }
11440                 }
11441
11442                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11443                         /* Success. */
11444                         ret = 0;
11445                         break;
11446                 }
11447         }
11448         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11449             DMA_RWCTRL_WRITE_BNDRY_16) {
11450                 static struct pci_device_id dma_wait_state_chipsets[] = {
11451                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11452                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11453                         { },
11454                 };
11455
11456                 /* DMA test passed without adjusting DMA boundary,
11457                  * now look for chipsets that are known to expose the
11458                  * DMA bug without failing the test.
11459                  */
11460                 if (pci_dev_present(dma_wait_state_chipsets)) {
11461                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11462                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11463                 }
11464                 else
11465                         /* Safe to use the calculated DMA boundary. */
11466                         tp->dma_rwctrl = saved_dma_rwctrl;
11467
11468                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11469         }
11470
11471 out:
11472         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11473 out_nofree:
11474         return ret;
11475 }
11476
11477 static void __devinit tg3_init_link_config(struct tg3 *tp)
11478 {
11479         tp->link_config.advertising =
11480                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11481                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11482                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11483                  ADVERTISED_Autoneg | ADVERTISED_MII);
11484         tp->link_config.speed = SPEED_INVALID;
11485         tp->link_config.duplex = DUPLEX_INVALID;
11486         tp->link_config.autoneg = AUTONEG_ENABLE;
11487         tp->link_config.active_speed = SPEED_INVALID;
11488         tp->link_config.active_duplex = DUPLEX_INVALID;
11489         tp->link_config.phy_is_low_power = 0;
11490         tp->link_config.orig_speed = SPEED_INVALID;
11491         tp->link_config.orig_duplex = DUPLEX_INVALID;
11492         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11493 }
11494
11495 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11496 {
11497         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11498                 tp->bufmgr_config.mbuf_read_dma_low_water =
11499                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11500                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11501                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11502                 tp->bufmgr_config.mbuf_high_water =
11503                         DEFAULT_MB_HIGH_WATER_5705;
11504                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11505                         tp->bufmgr_config.mbuf_mac_rx_low_water =
11506                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
11507                         tp->bufmgr_config.mbuf_high_water =
11508                                 DEFAULT_MB_HIGH_WATER_5906;
11509                 }
11510
11511                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11512                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11513                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11514                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11515                 tp->bufmgr_config.mbuf_high_water_jumbo =
11516                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11517         } else {
11518                 tp->bufmgr_config.mbuf_read_dma_low_water =
11519                         DEFAULT_MB_RDMA_LOW_WATER;
11520                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11521                         DEFAULT_MB_MACRX_LOW_WATER;
11522                 tp->bufmgr_config.mbuf_high_water =
11523                         DEFAULT_MB_HIGH_WATER;
11524
11525                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11526                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11527                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11528                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11529                 tp->bufmgr_config.mbuf_high_water_jumbo =
11530                         DEFAULT_MB_HIGH_WATER_JUMBO;
11531         }
11532
11533         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11534         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11535 }
11536
11537 static char * __devinit tg3_phy_string(struct tg3 *tp)
11538 {
11539         switch (tp->phy_id & PHY_ID_MASK) {
11540         case PHY_ID_BCM5400:    return "5400";
11541         case PHY_ID_BCM5401:    return "5401";
11542         case PHY_ID_BCM5411:    return "5411";
11543         case PHY_ID_BCM5701:    return "5701";
11544         case PHY_ID_BCM5703:    return "5703";
11545         case PHY_ID_BCM5704:    return "5704";
11546         case PHY_ID_BCM5705:    return "5705";
11547         case PHY_ID_BCM5750:    return "5750";
11548         case PHY_ID_BCM5752:    return "5752";
11549         case PHY_ID_BCM5714:    return "5714";
11550         case PHY_ID_BCM5780:    return "5780";
11551         case PHY_ID_BCM5755:    return "5755";
11552         case PHY_ID_BCM5787:    return "5787";
11553         case PHY_ID_BCM5756:    return "5722/5756";
11554         case PHY_ID_BCM5906:    return "5906";
11555         case PHY_ID_BCM8002:    return "8002/serdes";
11556         case 0:                 return "serdes";
11557         default:                return "unknown";
11558         };
11559 }
11560
11561 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11562 {
11563         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11564                 strcpy(str, "PCI Express");
11565                 return str;
11566         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11567                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11568
11569                 strcpy(str, "PCIX:");
11570
11571                 if ((clock_ctrl == 7) ||
11572                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11573                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11574                         strcat(str, "133MHz");
11575                 else if (clock_ctrl == 0)
11576                         strcat(str, "33MHz");
11577                 else if (clock_ctrl == 2)
11578                         strcat(str, "50MHz");
11579                 else if (clock_ctrl == 4)
11580                         strcat(str, "66MHz");
11581                 else if (clock_ctrl == 6)
11582                         strcat(str, "100MHz");
11583         } else {
11584                 strcpy(str, "PCI:");
11585                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11586                         strcat(str, "66MHz");
11587                 else
11588                         strcat(str, "33MHz");
11589         }
11590         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11591                 strcat(str, ":32-bit");
11592         else
11593                 strcat(str, ":64-bit");
11594         return str;
11595 }
11596
11597 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11598 {
11599         struct pci_dev *peer;
11600         unsigned int func, devnr = tp->pdev->devfn & ~7;
11601
11602         for (func = 0; func < 8; func++) {
11603                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11604                 if (peer && peer != tp->pdev)
11605                         break;
11606                 pci_dev_put(peer);
11607         }
11608         /* 5704 can be configured in single-port mode, set peer to
11609          * tp->pdev in that case.
11610          */
11611         if (!peer) {
11612                 peer = tp->pdev;
11613                 return peer;
11614         }
11615
11616         /*
11617          * We don't need to keep the refcount elevated; there's no way
11618          * to remove one half of this device without removing the other
11619          */
11620         pci_dev_put(peer);
11621
11622         return peer;
11623 }
11624
11625 static void __devinit tg3_init_coal(struct tg3 *tp)
11626 {
11627         struct ethtool_coalesce *ec = &tp->coal;
11628
11629         memset(ec, 0, sizeof(*ec));
11630         ec->cmd = ETHTOOL_GCOALESCE;
11631         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11632         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11633         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11634         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11635         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11636         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11637         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11638         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11639         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11640
11641         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11642                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11643                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11644                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11645                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11646                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11647         }
11648
11649         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11650                 ec->rx_coalesce_usecs_irq = 0;
11651                 ec->tx_coalesce_usecs_irq = 0;
11652                 ec->stats_block_coalesce_usecs = 0;
11653         }
11654 }
11655
11656 static int __devinit tg3_init_one(struct pci_dev *pdev,
11657                                   const struct pci_device_id *ent)
11658 {
11659         static int tg3_version_printed = 0;
11660         unsigned long tg3reg_base, tg3reg_len;
11661         struct net_device *dev;
11662         struct tg3 *tp;
11663         int i, err, pm_cap;
11664         char str[40];
11665         u64 dma_mask, persist_dma_mask;
11666
11667         if (tg3_version_printed++ == 0)
11668                 printk(KERN_INFO "%s", version);
11669
11670         err = pci_enable_device(pdev);
11671         if (err) {
11672                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11673                        "aborting.\n");
11674                 return err;
11675         }
11676
11677         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11678                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11679                        "base address, aborting.\n");
11680                 err = -ENODEV;
11681                 goto err_out_disable_pdev;
11682         }
11683
11684         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11685         if (err) {
11686                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11687                        "aborting.\n");
11688                 goto err_out_disable_pdev;
11689         }
11690
11691         pci_set_master(pdev);
11692
11693         /* Find power-management capability. */
11694         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11695         if (pm_cap == 0) {
11696                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11697                        "aborting.\n");
11698                 err = -EIO;
11699                 goto err_out_free_res;
11700         }
11701
11702         tg3reg_base = pci_resource_start(pdev, 0);
11703         tg3reg_len = pci_resource_len(pdev, 0);
11704
11705         dev = alloc_etherdev(sizeof(*tp));
11706         if (!dev) {
11707                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11708                 err = -ENOMEM;
11709                 goto err_out_free_res;
11710         }
11711
11712         SET_MODULE_OWNER(dev);
11713         SET_NETDEV_DEV(dev, &pdev->dev);
11714
11715 #if TG3_VLAN_TAG_USED
11716         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11717         dev->vlan_rx_register = tg3_vlan_rx_register;
11718         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11719 #endif
11720
11721         tp = netdev_priv(dev);
11722         tp->pdev = pdev;
11723         tp->dev = dev;
11724         tp->pm_cap = pm_cap;
11725         tp->mac_mode = TG3_DEF_MAC_MODE;
11726         tp->rx_mode = TG3_DEF_RX_MODE;
11727         tp->tx_mode = TG3_DEF_TX_MODE;
11728         tp->mi_mode = MAC_MI_MODE_BASE;
11729         if (tg3_debug > 0)
11730                 tp->msg_enable = tg3_debug;
11731         else
11732                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11733
11734         /* The word/byte swap controls here control register access byte
11735          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11736          * setting below.
11737          */
11738         tp->misc_host_ctrl =
11739                 MISC_HOST_CTRL_MASK_PCI_INT |
11740                 MISC_HOST_CTRL_WORD_SWAP |
11741                 MISC_HOST_CTRL_INDIR_ACCESS |
11742                 MISC_HOST_CTRL_PCISTATE_RW;
11743
11744         /* The NONFRM (non-frame) byte/word swap controls take effect
11745          * on descriptor entries, anything which isn't packet data.
11746          *
11747          * The StrongARM chips on the board (one for tx, one for rx)
11748          * are running in big-endian mode.
11749          */
11750         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11751                         GRC_MODE_WSWAP_NONFRM_DATA);
11752 #ifdef __BIG_ENDIAN
11753         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11754 #endif
11755         spin_lock_init(&tp->lock);
11756         spin_lock_init(&tp->indirect_lock);
11757         INIT_WORK(&tp->reset_task, tg3_reset_task);
11758
11759         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11760         if (tp->regs == 0UL) {
11761                 printk(KERN_ERR PFX "Cannot map device registers, "
11762                        "aborting.\n");
11763                 err = -ENOMEM;
11764                 goto err_out_free_dev;
11765         }
11766
11767         tg3_init_link_config(tp);
11768
11769         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11770         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11771         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11772
11773         dev->open = tg3_open;
11774         dev->stop = tg3_close;
11775         dev->get_stats = tg3_get_stats;
11776         dev->set_multicast_list = tg3_set_rx_mode;
11777         dev->set_mac_address = tg3_set_mac_addr;
11778         dev->do_ioctl = tg3_ioctl;
11779         dev->tx_timeout = tg3_tx_timeout;
11780         dev->poll = tg3_poll;
11781         dev->ethtool_ops = &tg3_ethtool_ops;
11782         dev->weight = 64;
11783         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11784         dev->change_mtu = tg3_change_mtu;
11785         dev->irq = pdev->irq;
11786 #ifdef CONFIG_NET_POLL_CONTROLLER
11787         dev->poll_controller = tg3_poll_controller;
11788 #endif
11789
11790         err = tg3_get_invariants(tp);
11791         if (err) {
11792                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11793                        "aborting.\n");
11794                 goto err_out_iounmap;
11795         }
11796
11797         /* The EPB bridge inside 5714, 5715, and 5780 and any
11798          * device behind the EPB cannot support DMA addresses > 40-bit.
11799          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11800          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11801          * do DMA address check in tg3_start_xmit().
11802          */
11803         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11804                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11805         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11806                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11807 #ifdef CONFIG_HIGHMEM
11808                 dma_mask = DMA_64BIT_MASK;
11809 #endif
11810         } else
11811                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11812
11813         /* Configure DMA attributes. */
11814         if (dma_mask > DMA_32BIT_MASK) {
11815                 err = pci_set_dma_mask(pdev, dma_mask);
11816                 if (!err) {
11817                         dev->features |= NETIF_F_HIGHDMA;
11818                         err = pci_set_consistent_dma_mask(pdev,
11819                                                           persist_dma_mask);
11820                         if (err < 0) {
11821                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11822                                        "DMA for consistent allocations\n");
11823                                 goto err_out_iounmap;
11824                         }
11825                 }
11826         }
11827         if (err || dma_mask == DMA_32BIT_MASK) {
11828                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11829                 if (err) {
11830                         printk(KERN_ERR PFX "No usable DMA configuration, "
11831                                "aborting.\n");
11832                         goto err_out_iounmap;
11833                 }
11834         }
11835
11836         tg3_init_bufmgr_config(tp);
11837
11838 #if TG3_TSO_SUPPORT != 0
11839         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11840                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11841         }
11842         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11843             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11844             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11845             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11846             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11847                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11848         } else {
11849                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11850         }
11851
11852         /* TSO is on by default on chips that support hardware TSO.
11853          * Firmware TSO on older chips gives lower performance, so it
11854          * is off by default, but can be enabled using ethtool.
11855          */
11856         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11857                 dev->features |= NETIF_F_TSO;
11858                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11859                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11860                         dev->features |= NETIF_F_TSO6;
11861         }
11862
11863 #endif
11864
11865         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11866             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11867             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11868                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11869                 tp->rx_pending = 63;
11870         }
11871
11872         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11873             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11874                 tp->pdev_peer = tg3_find_peer(tp);
11875
11876         err = tg3_get_device_address(tp);
11877         if (err) {
11878                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11879                        "aborting.\n");
11880                 goto err_out_iounmap;
11881         }
11882
11883         /*
11884          * Reset chip in case UNDI or EFI driver did not shutdown
11885          * DMA self test will enable WDMAC and we'll see (spurious)
11886          * pending DMA on the PCI bus at that point.
11887          */
11888         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11889             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11890                 pci_save_state(tp->pdev);
11891                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11892                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11893         }
11894
11895         err = tg3_test_dma(tp);
11896         if (err) {
11897                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11898                 goto err_out_iounmap;
11899         }
11900
11901         /* Tigon3 can do ipv4 only... and some chips have buggy
11902          * checksumming.
11903          */
11904         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11905                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11906                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11907                         dev->features |= NETIF_F_HW_CSUM;
11908                 else
11909                         dev->features |= NETIF_F_IP_CSUM;
11910                 dev->features |= NETIF_F_SG;
11911                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11912         } else
11913                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11914
11915         /* flow control autonegotiation is default behavior */
11916         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11917
11918         tg3_init_coal(tp);
11919
11920         /* Now that we have fully setup the chip, save away a snapshot
11921          * of the PCI config space.  We need to restore this after
11922          * GRC_MISC_CFG core clock resets and some resume events.
11923          */
11924         pci_save_state(tp->pdev);
11925
11926         err = register_netdev(dev);
11927         if (err) {
11928                 printk(KERN_ERR PFX "Cannot register net device, "
11929                        "aborting.\n");
11930                 goto err_out_iounmap;
11931         }
11932
11933         pci_set_drvdata(pdev, dev);
11934
11935         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
11936                dev->name,
11937                tp->board_part_number,
11938                tp->pci_chip_rev_id,
11939                tg3_phy_string(tp),
11940                tg3_bus_string(tp, str),
11941                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11942                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11943                  "10/100/1000Base-T")));
11944
11945         for (i = 0; i < 6; i++)
11946                 printk("%2.2x%c", dev->dev_addr[i],
11947                        i == 5 ? '\n' : ':');
11948
11949         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11950                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11951                "TSOcap[%d] \n",
11952                dev->name,
11953                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11954                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11955                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11956                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11957                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11958                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11959                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11960         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11961                dev->name, tp->dma_rwctrl,
11962                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11963                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11964
11965         netif_carrier_off(tp->dev);
11966
11967         return 0;
11968
11969 err_out_iounmap:
11970         if (tp->regs) {
11971                 iounmap(tp->regs);
11972                 tp->regs = NULL;
11973         }
11974
11975 err_out_free_dev:
11976         free_netdev(dev);
11977
11978 err_out_free_res:
11979         pci_release_regions(pdev);
11980
11981 err_out_disable_pdev:
11982         pci_disable_device(pdev);
11983         pci_set_drvdata(pdev, NULL);
11984         return err;
11985 }
11986
11987 static void __devexit tg3_remove_one(struct pci_dev *pdev)
11988 {
11989         struct net_device *dev = pci_get_drvdata(pdev);
11990
11991         if (dev) {
11992                 struct tg3 *tp = netdev_priv(dev);
11993
11994                 flush_scheduled_work();
11995                 unregister_netdev(dev);
11996                 if (tp->regs) {
11997                         iounmap(tp->regs);
11998                         tp->regs = NULL;
11999                 }
12000                 free_netdev(dev);
12001                 pci_release_regions(pdev);
12002                 pci_disable_device(pdev);
12003                 pci_set_drvdata(pdev, NULL);
12004         }
12005 }
12006
12007 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12008 {
12009         struct net_device *dev = pci_get_drvdata(pdev);
12010         struct tg3 *tp = netdev_priv(dev);
12011         int err;
12012
12013         if (!netif_running(dev))
12014                 return 0;
12015
12016         flush_scheduled_work();
12017         tg3_netif_stop(tp);
12018
12019         del_timer_sync(&tp->timer);
12020
12021         tg3_full_lock(tp, 1);
12022         tg3_disable_ints(tp);
12023         tg3_full_unlock(tp);
12024
12025         netif_device_detach(dev);
12026
12027         tg3_full_lock(tp, 0);
12028         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12029         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12030         tg3_full_unlock(tp);
12031
12032         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12033         if (err) {
12034                 tg3_full_lock(tp, 0);
12035
12036                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12037                 if (tg3_restart_hw(tp, 1))
12038                         goto out;
12039
12040                 tp->timer.expires = jiffies + tp->timer_offset;
12041                 add_timer(&tp->timer);
12042
12043                 netif_device_attach(dev);
12044                 tg3_netif_start(tp);
12045
12046 out:
12047                 tg3_full_unlock(tp);
12048         }
12049
12050         return err;
12051 }
12052
12053 static int tg3_resume(struct pci_dev *pdev)
12054 {
12055         struct net_device *dev = pci_get_drvdata(pdev);
12056         struct tg3 *tp = netdev_priv(dev);
12057         int err;
12058
12059         if (!netif_running(dev))
12060                 return 0;
12061
12062         pci_restore_state(tp->pdev);
12063
12064         err = tg3_set_power_state(tp, PCI_D0);
12065         if (err)
12066                 return err;
12067
12068         netif_device_attach(dev);
12069
12070         tg3_full_lock(tp, 0);
12071
12072         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12073         err = tg3_restart_hw(tp, 1);
12074         if (err)
12075                 goto out;
12076
12077         tp->timer.expires = jiffies + tp->timer_offset;
12078         add_timer(&tp->timer);
12079
12080         tg3_netif_start(tp);
12081
12082 out:
12083         tg3_full_unlock(tp);
12084
12085         return err;
12086 }
12087
12088 static struct pci_driver tg3_driver = {
12089         .name           = DRV_MODULE_NAME,
12090         .id_table       = tg3_pci_tbl,
12091         .probe          = tg3_init_one,
12092         .remove         = __devexit_p(tg3_remove_one),
12093         .suspend        = tg3_suspend,
12094         .resume         = tg3_resume
12095 };
12096
12097 static int __init tg3_init(void)
12098 {
12099         return pci_register_driver(&tg3_driver);
12100 }
12101
12102 static void __exit tg3_cleanup(void)
12103 {
12104         pci_unregister_driver(&tg3_driver);
12105 }
12106
12107 module_init(tg3_init);
12108 module_exit(tg3_cleanup);