2 * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "firmware_exports.h"
38 * t3_wait_op_done_val - wait until an operation is completed
39 * @adapter: the adapter performing the operation
40 * @reg: the register to check for completion
41 * @mask: a single-bit field within @reg that indicates completion
42 * @polarity: the value of the field when the operation is completed
43 * @attempts: number of check iterations
44 * @delay: delay in usecs between iterations
45 * @valp: where to store the value of the register at completion time
47 * Wait until an operation is completed by checking a bit in a register
48 * up to @attempts times. If @valp is not NULL the value of the register
49 * at the time it indicated completion is stored there. Returns 0 if the
50 * operation completes and -EAGAIN otherwise.
53 int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
54 int polarity, int attempts, int delay, u32 *valp)
57 u32 val = t3_read_reg(adapter, reg);
59 if (!!(val & mask) == polarity) {
72 * t3_write_regs - write a bunch of registers
73 * @adapter: the adapter to program
74 * @p: an array of register address/register value pairs
75 * @n: the number of address/value pairs
76 * @offset: register address offset
78 * Takes an array of register address/register value pairs and writes each
79 * value to the corresponding register. Register addresses are adjusted
80 * by the supplied offset.
82 void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
83 int n, unsigned int offset)
86 t3_write_reg(adapter, p->reg_addr + offset, p->val);
92 * t3_set_reg_field - set a register field to a value
93 * @adapter: the adapter to program
94 * @addr: the register address
95 * @mask: specifies the portion of the register to modify
96 * @val: the new value for the register field
98 * Sets a register field specified by the supplied mask to the
101 void t3_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
104 u32 v = t3_read_reg(adapter, addr) & ~mask;
106 t3_write_reg(adapter, addr, v | val);
107 t3_read_reg(adapter, addr); /* flush */
111 * t3_read_indirect - read indirectly addressed registers
113 * @addr_reg: register holding the indirect address
114 * @data_reg: register holding the value of the indirect register
115 * @vals: where the read register values are stored
116 * @start_idx: index of first indirect register to read
117 * @nregs: how many indirect registers to read
119 * Reads registers that are accessed indirectly through an address/data
122 void t3_read_indirect(struct adapter *adap, unsigned int addr_reg,
123 unsigned int data_reg, u32 *vals, unsigned int nregs,
124 unsigned int start_idx)
127 t3_write_reg(adap, addr_reg, start_idx);
128 *vals++ = t3_read_reg(adap, data_reg);
134 * t3_mc7_bd_read - read from MC7 through backdoor accesses
135 * @mc7: identifies MC7 to read from
136 * @start: index of first 64-bit word to read
137 * @n: number of 64-bit words to read
138 * @buf: where to store the read result
140 * Read n 64-bit words from MC7 starting at word start, using backdoor
143 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
146 static const int shift[] = { 0, 0, 16, 24 };
147 static const int step[] = { 0, 32, 16, 8 };
149 unsigned int size64 = mc7->size / 8; /* # of 64-bit words */
150 struct adapter *adap = mc7->adapter;
152 if (start >= size64 || start + n > size64)
155 start *= (8 << mc7->width);
160 for (i = (1 << mc7->width) - 1; i >= 0; --i) {
164 t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, start);
165 t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);
166 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);
167 while ((val & F_BUSY) && attempts--)
168 val = t3_read_reg(adap,
169 mc7->offset + A_MC7_BD_OP);
173 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);
174 if (mc7->width == 0) {
175 val64 = t3_read_reg(adap,
178 val64 |= (u64) val << 32;
181 val >>= shift[mc7->width];
182 val64 |= (u64) val << (step[mc7->width] * i);
194 static void mi1_init(struct adapter *adap, const struct adapter_info *ai)
196 u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1;
197 u32 val = F_PREEN | V_MDIINV(ai->mdiinv) | V_MDIEN(ai->mdien) |
200 if (!(ai->caps & SUPPORTED_10000baseT_Full))
202 t3_write_reg(adap, A_MI1_CFG, val);
205 #define MDIO_ATTEMPTS 10
208 * MI1 read/write operations for direct-addressed PHYs.
210 static int mi1_read(struct adapter *adapter, int phy_addr, int mmd_addr,
211 int reg_addr, unsigned int *valp)
214 u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);
219 mutex_lock(&adapter->mdio_lock);
220 t3_write_reg(adapter, A_MI1_ADDR, addr);
221 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2));
222 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 20);
224 *valp = t3_read_reg(adapter, A_MI1_DATA);
225 mutex_unlock(&adapter->mdio_lock);
229 static int mi1_write(struct adapter *adapter, int phy_addr, int mmd_addr,
230 int reg_addr, unsigned int val)
233 u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);
238 mutex_lock(&adapter->mdio_lock);
239 t3_write_reg(adapter, A_MI1_ADDR, addr);
240 t3_write_reg(adapter, A_MI1_DATA, val);
241 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
242 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 20);
243 mutex_unlock(&adapter->mdio_lock);
247 static const struct mdio_ops mi1_mdio_ops = {
253 * MI1 read/write operations for indirect-addressed PHYs.
255 static int mi1_ext_read(struct adapter *adapter, int phy_addr, int mmd_addr,
256 int reg_addr, unsigned int *valp)
259 u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr);
261 mutex_lock(&adapter->mdio_lock);
262 t3_write_reg(adapter, A_MI1_ADDR, addr);
263 t3_write_reg(adapter, A_MI1_DATA, reg_addr);
264 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
265 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 20);
267 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3));
268 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
271 *valp = t3_read_reg(adapter, A_MI1_DATA);
273 mutex_unlock(&adapter->mdio_lock);
277 static int mi1_ext_write(struct adapter *adapter, int phy_addr, int mmd_addr,
278 int reg_addr, unsigned int val)
281 u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr);
283 mutex_lock(&adapter->mdio_lock);
284 t3_write_reg(adapter, A_MI1_ADDR, addr);
285 t3_write_reg(adapter, A_MI1_DATA, reg_addr);
286 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
287 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 20);
289 t3_write_reg(adapter, A_MI1_DATA, val);
290 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
291 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
294 mutex_unlock(&adapter->mdio_lock);
298 static const struct mdio_ops mi1_mdio_ext_ops = {
304 * t3_mdio_change_bits - modify the value of a PHY register
305 * @phy: the PHY to operate on
306 * @mmd: the device address
307 * @reg: the register address
308 * @clear: what part of the register value to mask off
309 * @set: what part of the register value to set
311 * Changes the value of a PHY register by applying a mask to its current
312 * value and ORing the result with a new value.
314 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
320 ret = mdio_read(phy, mmd, reg, &val);
323 ret = mdio_write(phy, mmd, reg, val | set);
329 * t3_phy_reset - reset a PHY block
330 * @phy: the PHY to operate on
331 * @mmd: the device address of the PHY block to reset
332 * @wait: how long to wait for the reset to complete in 1ms increments
334 * Resets a PHY block and optionally waits for the reset to complete.
335 * @mmd should be 0 for 10/100/1000 PHYs and the device address to reset
338 int t3_phy_reset(struct cphy *phy, int mmd, int wait)
343 err = t3_mdio_change_bits(phy, mmd, MII_BMCR, BMCR_PDOWN, BMCR_RESET);
348 err = mdio_read(phy, mmd, MII_BMCR, &ctl);
354 } while (ctl && --wait);
360 * t3_phy_advertise - set the PHY advertisement registers for autoneg
361 * @phy: the PHY to operate on
362 * @advert: bitmap of capabilities the PHY should advertise
364 * Sets a 10/100/1000 PHY's advertisement registers to advertise the
365 * requested capabilities.
367 int t3_phy_advertise(struct cphy *phy, unsigned int advert)
370 unsigned int val = 0;
372 err = mdio_read(phy, 0, MII_CTRL1000, &val);
376 val &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
377 if (advert & ADVERTISED_1000baseT_Half)
378 val |= ADVERTISE_1000HALF;
379 if (advert & ADVERTISED_1000baseT_Full)
380 val |= ADVERTISE_1000FULL;
382 err = mdio_write(phy, 0, MII_CTRL1000, val);
387 if (advert & ADVERTISED_10baseT_Half)
388 val |= ADVERTISE_10HALF;
389 if (advert & ADVERTISED_10baseT_Full)
390 val |= ADVERTISE_10FULL;
391 if (advert & ADVERTISED_100baseT_Half)
392 val |= ADVERTISE_100HALF;
393 if (advert & ADVERTISED_100baseT_Full)
394 val |= ADVERTISE_100FULL;
395 if (advert & ADVERTISED_Pause)
396 val |= ADVERTISE_PAUSE_CAP;
397 if (advert & ADVERTISED_Asym_Pause)
398 val |= ADVERTISE_PAUSE_ASYM;
399 return mdio_write(phy, 0, MII_ADVERTISE, val);
403 * t3_set_phy_speed_duplex - force PHY speed and duplex
404 * @phy: the PHY to operate on
405 * @speed: requested PHY speed
406 * @duplex: requested PHY duplex
408 * Force a 10/100/1000 PHY's speed and duplex. This also disables
409 * auto-negotiation except for GigE, where auto-negotiation is mandatory.
411 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex)
416 err = mdio_read(phy, 0, MII_BMCR, &ctl);
421 ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
422 if (speed == SPEED_100)
423 ctl |= BMCR_SPEED100;
424 else if (speed == SPEED_1000)
425 ctl |= BMCR_SPEED1000;
428 ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE);
429 if (duplex == DUPLEX_FULL)
430 ctl |= BMCR_FULLDPLX;
432 if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */
433 ctl |= BMCR_ANENABLE;
434 return mdio_write(phy, 0, MII_BMCR, ctl);
437 static const struct adapter_info t3_adap_info[] = {
439 F_GPIO2_OEN | F_GPIO4_OEN |
440 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5,
442 &mi1_mdio_ops, "Chelsio PE9000"},
444 F_GPIO2_OEN | F_GPIO4_OEN |
445 F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5,
447 &mi1_mdio_ops, "Chelsio T302"},
449 F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN |
450 F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0,
451 SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
452 &mi1_mdio_ext_ops, "Chelsio T310"},
454 F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN |
455 F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL |
456 F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0,
457 SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
458 &mi1_mdio_ext_ops, "Chelsio T320"},
462 * Return the adapter_info structure with a given index. Out-of-range indices
465 const struct adapter_info *t3_get_adapter_info(unsigned int id)
467 return id < ARRAY_SIZE(t3_adap_info) ? &t3_adap_info[id] : NULL;
470 #define CAPS_1G (SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full | \
471 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_MII)
472 #define CAPS_10G (SUPPORTED_10000baseT_Full | SUPPORTED_AUI)
474 static const struct port_type_info port_types[] = {
476 {t3_ael1002_phy_prep, CAPS_10G | SUPPORTED_FIBRE,
478 {t3_vsc8211_phy_prep, CAPS_1G | SUPPORTED_TP | SUPPORTED_IRQ,
479 "10/100/1000BASE-T"},
480 {NULL, CAPS_1G | SUPPORTED_TP | SUPPORTED_IRQ,
481 "10/100/1000BASE-T"},
482 {t3_xaui_direct_phy_prep, CAPS_10G | SUPPORTED_TP, "10GBASE-CX4"},
483 {NULL, CAPS_10G, "10GBASE-KX4"},
484 {t3_qt2045_phy_prep, CAPS_10G | SUPPORTED_TP, "10GBASE-CX4"},
485 {t3_ael1006_phy_prep, CAPS_10G | SUPPORTED_FIBRE,
487 {NULL, CAPS_10G | SUPPORTED_TP, "10GBASE-CX4"},
493 #define VPD_ENTRY(name, len) \
494 u8 name##_kword[2]; u8 name##_len; u8 name##_data[len]
497 * Partial EEPROM Vital Product Data structure. Includes only the ID and
506 VPD_ENTRY(pn, 16); /* part number */
507 VPD_ENTRY(ec, 16); /* EC level */
508 VPD_ENTRY(sn, 16); /* serial number */
509 VPD_ENTRY(na, 12); /* MAC address base */
510 VPD_ENTRY(cclk, 6); /* core clock */
511 VPD_ENTRY(mclk, 6); /* mem clock */
512 VPD_ENTRY(uclk, 6); /* uP clk */
513 VPD_ENTRY(mdc, 6); /* MDIO clk */
514 VPD_ENTRY(mt, 2); /* mem timing */
515 VPD_ENTRY(xaui0cfg, 6); /* XAUI0 config */
516 VPD_ENTRY(xaui1cfg, 6); /* XAUI1 config */
517 VPD_ENTRY(port0, 2); /* PHY0 complex */
518 VPD_ENTRY(port1, 2); /* PHY1 complex */
519 VPD_ENTRY(port2, 2); /* PHY2 complex */
520 VPD_ENTRY(port3, 2); /* PHY3 complex */
521 VPD_ENTRY(rv, 1); /* csum */
522 u32 pad; /* for multiple-of-4 sizing and alignment */
525 #define EEPROM_MAX_POLL 4
526 #define EEPROM_STAT_ADDR 0x4000
527 #define VPD_BASE 0xc00
530 * t3_seeprom_read - read a VPD EEPROM location
531 * @adapter: adapter to read
532 * @addr: EEPROM address
533 * @data: where to store the read data
535 * Read a 32-bit word from a location in VPD EEPROM using the card's PCI
536 * VPD ROM capability. A zero is written to the flag bit when the
537 * addres is written to the control register. The hardware device will
538 * set the flag to 1 when 4 bytes have been read into the data register.
540 int t3_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
543 int attempts = EEPROM_MAX_POLL;
544 unsigned int base = adapter->params.pci.vpd_cap_addr;
546 if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3))
549 pci_write_config_word(adapter->pdev, base + PCI_VPD_ADDR, addr);
552 pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val);
553 } while (!(val & PCI_VPD_ADDR_F) && --attempts);
555 if (!(val & PCI_VPD_ADDR_F)) {
556 CH_ERR(adapter, "reading EEPROM address 0x%x failed\n", addr);
559 pci_read_config_dword(adapter->pdev, base + PCI_VPD_DATA, data);
560 *data = le32_to_cpu(*data);
565 * t3_seeprom_write - write a VPD EEPROM location
566 * @adapter: adapter to write
567 * @addr: EEPROM address
568 * @data: value to write
570 * Write a 32-bit word to a location in VPD EEPROM using the card's PCI
571 * VPD ROM capability.
573 int t3_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
576 int attempts = EEPROM_MAX_POLL;
577 unsigned int base = adapter->params.pci.vpd_cap_addr;
579 if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3))
582 pci_write_config_dword(adapter->pdev, base + PCI_VPD_DATA,
584 pci_write_config_word(adapter->pdev,base + PCI_VPD_ADDR,
585 addr | PCI_VPD_ADDR_F);
588 pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val);
589 } while ((val & PCI_VPD_ADDR_F) && --attempts);
591 if (val & PCI_VPD_ADDR_F) {
592 CH_ERR(adapter, "write to EEPROM address 0x%x failed\n", addr);
599 * t3_seeprom_wp - enable/disable EEPROM write protection
600 * @adapter: the adapter
601 * @enable: 1 to enable write protection, 0 to disable it
603 * Enables or disables write protection on the serial EEPROM.
605 int t3_seeprom_wp(struct adapter *adapter, int enable)
607 return t3_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
611 * Convert a character holding a hex digit to a number.
613 static unsigned int hex2int(unsigned char c)
615 return isdigit(c) ? c - '0' : toupper(c) - 'A' + 10;
619 * get_vpd_params - read VPD parameters from VPD EEPROM
620 * @adapter: adapter to read
621 * @p: where to store the parameters
623 * Reads card parameters stored in VPD EEPROM.
625 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
631 * Card information is normally at VPD_BASE but some early cards had
634 ret = t3_seeprom_read(adapter, VPD_BASE, (u32 *)&vpd);
637 addr = vpd.id_tag == 0x82 ? VPD_BASE : 0;
639 for (i = 0; i < sizeof(vpd); i += 4) {
640 ret = t3_seeprom_read(adapter, addr + i,
641 (u32 *)((u8 *)&vpd + i));
646 p->cclk = simple_strtoul(vpd.cclk_data, NULL, 10);
647 p->mclk = simple_strtoul(vpd.mclk_data, NULL, 10);
648 p->uclk = simple_strtoul(vpd.uclk_data, NULL, 10);
649 p->mdc = simple_strtoul(vpd.mdc_data, NULL, 10);
650 p->mem_timing = simple_strtoul(vpd.mt_data, NULL, 10);
652 /* Old eeproms didn't have port information */
653 if (adapter->params.rev == 0 && !vpd.port0_data[0]) {
654 p->port_type[0] = uses_xaui(adapter) ? 1 : 2;
655 p->port_type[1] = uses_xaui(adapter) ? 6 : 2;
657 p->port_type[0] = hex2int(vpd.port0_data[0]);
658 p->port_type[1] = hex2int(vpd.port1_data[0]);
659 p->xauicfg[0] = simple_strtoul(vpd.xaui0cfg_data, NULL, 16);
660 p->xauicfg[1] = simple_strtoul(vpd.xaui1cfg_data, NULL, 16);
663 for (i = 0; i < 6; i++)
664 p->eth_base[i] = hex2int(vpd.na_data[2 * i]) * 16 +
665 hex2int(vpd.na_data[2 * i + 1]);
669 /* serial flash and firmware constants */
671 SF_ATTEMPTS = 5, /* max retries for SF1 operations */
672 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
673 SF_SIZE = SF_SEC_SIZE * 8, /* serial flash size */
675 /* flash command opcodes */
676 SF_PROG_PAGE = 2, /* program page */
677 SF_WR_DISABLE = 4, /* disable writes */
678 SF_RD_STATUS = 5, /* read status register */
679 SF_WR_ENABLE = 6, /* enable writes */
680 SF_RD_DATA_FAST = 0xb, /* read flash */
681 SF_ERASE_SECTOR = 0xd8, /* erase sector */
683 FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */
684 FW_VERS_ADDR = 0x77ffc, /* flash address holding FW version */
685 FW_MIN_SIZE = 8 /* at least version and csum */
689 * sf1_read - read data from the serial flash
690 * @adapter: the adapter
691 * @byte_cnt: number of bytes to read
692 * @cont: whether another operation will be chained
693 * @valp: where to store the read data
695 * Reads up to 4 bytes of data from the serial flash. The location of
696 * the read needs to be specified prior to calling this by issuing the
697 * appropriate commands to the serial flash.
699 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
704 if (!byte_cnt || byte_cnt > 4)
706 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
708 t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
709 ret = t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
711 *valp = t3_read_reg(adapter, A_SF_DATA);
716 * sf1_write - write data to the serial flash
717 * @adapter: the adapter
718 * @byte_cnt: number of bytes to write
719 * @cont: whether another operation will be chained
720 * @val: value to write
722 * Writes up to 4 bytes of data to the serial flash. The location of
723 * the write needs to be specified prior to calling this by issuing the
724 * appropriate commands to the serial flash.
726 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
729 if (!byte_cnt || byte_cnt > 4)
731 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
733 t3_write_reg(adapter, A_SF_DATA, val);
734 t3_write_reg(adapter, A_SF_OP,
735 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
736 return t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
740 * flash_wait_op - wait for a flash operation to complete
741 * @adapter: the adapter
742 * @attempts: max number of polls of the status register
743 * @delay: delay between polls in ms
745 * Wait for a flash operation to complete by polling the status register.
747 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
753 if ((ret = sf1_write(adapter, 1, 1, SF_RD_STATUS)) != 0 ||
754 (ret = sf1_read(adapter, 1, 0, &status)) != 0)
766 * t3_read_flash - read words from serial flash
767 * @adapter: the adapter
768 * @addr: the start address for the read
769 * @nwords: how many 32-bit words to read
770 * @data: where to store the read data
771 * @byte_oriented: whether to store data as bytes or as words
773 * Read the specified number of 32-bit words from the serial flash.
774 * If @byte_oriented is set the read data is stored as a byte array
775 * (i.e., big-endian), otherwise as 32-bit words in the platform's
778 int t3_read_flash(struct adapter *adapter, unsigned int addr,
779 unsigned int nwords, u32 *data, int byte_oriented)
783 if (addr + nwords * sizeof(u32) > SF_SIZE || (addr & 3))
786 addr = swab32(addr) | SF_RD_DATA_FAST;
788 if ((ret = sf1_write(adapter, 4, 1, addr)) != 0 ||
789 (ret = sf1_read(adapter, 1, 1, data)) != 0)
792 for (; nwords; nwords--, data++) {
793 ret = sf1_read(adapter, 4, nwords > 1, data);
797 *data = htonl(*data);
803 * t3_write_flash - write up to a page of data to the serial flash
804 * @adapter: the adapter
805 * @addr: the start address to write
806 * @n: length of data to write
807 * @data: the data to write
809 * Writes up to a page of data (256 bytes) to the serial flash starting
810 * at the given address.
812 static int t3_write_flash(struct adapter *adapter, unsigned int addr,
813 unsigned int n, const u8 *data)
817 unsigned int i, c, left, val, offset = addr & 0xff;
819 if (addr + n > SF_SIZE || offset + n > 256)
822 val = swab32(addr) | SF_PROG_PAGE;
824 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
825 (ret = sf1_write(adapter, 4, 1, val)) != 0)
828 for (left = n; left; left -= c) {
830 for (val = 0, i = 0; i < c; ++i)
831 val = (val << 8) + *data++;
833 ret = sf1_write(adapter, c, c != left, val);
837 if ((ret = flash_wait_op(adapter, 5, 1)) != 0)
840 /* Read the page to verify the write succeeded */
841 ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
845 if (memcmp(data - n, (u8 *) buf + offset, n))
851 * t3_check_tpsram_version - read the tp sram version
852 * @adapter: the adapter
854 * Reads the protocol sram version from serial eeprom.
856 int t3_check_tpsram_version(struct adapter *adapter)
860 unsigned int major, minor;
862 /* Get version loaded in SRAM */
863 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0);
864 ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0,
869 vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
871 major = G_TP_VERSION_MAJOR(vers);
872 minor = G_TP_VERSION_MINOR(vers);
874 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
881 * t3_check_tpsram - check if provided protocol SRAM
882 * is compatible with this driver
883 * @adapter: the adapter
884 * @tp_sram: the firmware image to write
887 * Checks if an adapter's tp sram is compatible with the driver.
888 * Returns 0 if the versions are compatible, a negative error otherwise.
890 int t3_check_tpsram(struct adapter *adapter, u8 *tp_sram, unsigned int size)
894 const u32 *p = (const u32 *)tp_sram;
896 /* Verify checksum */
897 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
899 if (csum != 0xffffffff) {
900 CH_ERR(adapter, "corrupted protocol SRAM image, checksum %u\n",
908 enum fw_version_type {
914 * t3_get_fw_version - read the firmware version
915 * @adapter: the adapter
916 * @vers: where to place the version
918 * Reads the FW version from flash.
920 int t3_get_fw_version(struct adapter *adapter, u32 *vers)
922 return t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0);
926 * t3_check_fw_version - check if the FW is compatible with this driver
927 * @adapter: the adapter
929 * Checks if an adapter's FW is compatible with the driver. Returns 0
930 * if the versions are compatible, a negative error otherwise.
932 int t3_check_fw_version(struct adapter *adapter)
936 unsigned int type, major, minor;
938 ret = t3_get_fw_version(adapter, &vers);
942 type = G_FW_VERSION_TYPE(vers);
943 major = G_FW_VERSION_MAJOR(vers);
944 minor = G_FW_VERSION_MINOR(vers);
946 if (type == FW_VERSION_T3 && major == FW_VERSION_MAJOR &&
947 minor == FW_VERSION_MINOR)
950 CH_ERR(adapter, "found wrong FW version(%u.%u), "
951 "driver needs version %u.%u\n", major, minor,
952 FW_VERSION_MAJOR, FW_VERSION_MINOR);
957 * t3_flash_erase_sectors - erase a range of flash sectors
958 * @adapter: the adapter
959 * @start: the first sector to erase
960 * @end: the last sector to erase
962 * Erases the sectors in the given range.
964 static int t3_flash_erase_sectors(struct adapter *adapter, int start, int end)
966 while (start <= end) {
969 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
970 (ret = sf1_write(adapter, 4, 0,
971 SF_ERASE_SECTOR | (start << 8))) != 0 ||
972 (ret = flash_wait_op(adapter, 5, 500)) != 0)
980 * t3_load_fw - download firmware
981 * @adapter: the adapter
982 * @fw_data: the firmware image to write
985 * Write the supplied firmware image to the card's serial flash.
986 * The FW image has the following sections: @size - 8 bytes of code and
987 * data, followed by 4 bytes of FW version, followed by the 32-bit
988 * 1's complement checksum of the whole image.
990 int t3_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size)
994 const u32 *p = (const u32 *)fw_data;
995 int ret, addr, fw_sector = FW_FLASH_BOOT_ADDR >> 16;
997 if ((size & 3) || size < FW_MIN_SIZE)
999 if (size > FW_VERS_ADDR + 8 - FW_FLASH_BOOT_ADDR)
1002 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
1003 csum += ntohl(p[i]);
1004 if (csum != 0xffffffff) {
1005 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1010 ret = t3_flash_erase_sectors(adapter, fw_sector, fw_sector);
1014 size -= 8; /* trim off version and checksum */
1015 for (addr = FW_FLASH_BOOT_ADDR; size;) {
1016 unsigned int chunk_size = min(size, 256U);
1018 ret = t3_write_flash(adapter, addr, chunk_size, fw_data);
1023 fw_data += chunk_size;
1027 ret = t3_write_flash(adapter, FW_VERS_ADDR, 4, fw_data);
1030 CH_ERR(adapter, "firmware download failed, error %d\n", ret);
1034 #define CIM_CTL_BASE 0x2000
1037 * t3_cim_ctl_blk_read - read a block from CIM control region
1039 * @adap: the adapter
1040 * @addr: the start address within the CIM control region
1041 * @n: number of words to read
1042 * @valp: where to store the result
1044 * Reads a block of 4-byte words from the CIM control region.
1046 int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
1047 unsigned int n, unsigned int *valp)
1051 if (t3_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
1054 for ( ; !ret && n--; addr += 4) {
1055 t3_write_reg(adap, A_CIM_HOST_ACC_CTRL, CIM_CTL_BASE + addr);
1056 ret = t3_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
1059 *valp++ = t3_read_reg(adap, A_CIM_HOST_ACC_DATA);
1066 * t3_link_changed - handle interface link changes
1067 * @adapter: the adapter
1068 * @port_id: the port index that changed link state
1070 * Called when a port's link settings change to propagate the new values
1071 * to the associated PHY and MAC. After performing the common tasks it
1072 * invokes an OS-specific handler.
1074 void t3_link_changed(struct adapter *adapter, int port_id)
1076 int link_ok, speed, duplex, fc;
1077 struct port_info *pi = adap2pinfo(adapter, port_id);
1078 struct cphy *phy = &pi->phy;
1079 struct cmac *mac = &pi->mac;
1080 struct link_config *lc = &pi->link_config;
1082 phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
1084 if (link_ok != lc->link_ok && adapter->params.rev > 0 &&
1085 uses_xaui(adapter)) {
1088 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
1089 link_ok ? F_TXACTENABLE | F_RXEN : 0);
1091 lc->link_ok = link_ok;
1092 lc->speed = speed < 0 ? SPEED_INVALID : speed;
1093 lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
1094 if (lc->requested_fc & PAUSE_AUTONEG)
1095 fc &= lc->requested_fc;
1097 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1099 if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
1100 /* Set MAC speed, duplex, and flow control to match PHY. */
1101 t3_mac_set_speed_duplex_fc(mac, speed, duplex, fc);
1105 t3_os_link_changed(adapter, port_id, link_ok, speed, duplex, fc);
1109 * t3_link_start - apply link configuration to MAC/PHY
1110 * @phy: the PHY to setup
1111 * @mac: the MAC to setup
1112 * @lc: the requested link configuration
1114 * Set up a port's MAC and PHY according to a desired link configuration.
1115 * - If the PHY can auto-negotiate first decide what to advertise, then
1116 * enable/disable auto-negotiation as desired, and reset.
1117 * - If the PHY does not auto-negotiate just reset it.
1118 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1119 * otherwise do it later based on the outcome of auto-negotiation.
1121 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
1123 unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1126 if (lc->supported & SUPPORTED_Autoneg) {
1127 lc->advertising &= ~(ADVERTISED_Asym_Pause | ADVERTISED_Pause);
1129 lc->advertising |= ADVERTISED_Asym_Pause;
1131 lc->advertising |= ADVERTISED_Pause;
1133 phy->ops->advertise(phy, lc->advertising);
1135 if (lc->autoneg == AUTONEG_DISABLE) {
1136 lc->speed = lc->requested_speed;
1137 lc->duplex = lc->requested_duplex;
1138 lc->fc = (unsigned char)fc;
1139 t3_mac_set_speed_duplex_fc(mac, lc->speed, lc->duplex,
1141 /* Also disables autoneg */
1142 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
1143 phy->ops->reset(phy, 0);
1145 phy->ops->autoneg_enable(phy);
1147 t3_mac_set_speed_duplex_fc(mac, -1, -1, fc);
1148 lc->fc = (unsigned char)fc;
1149 phy->ops->reset(phy, 0);
1155 * t3_set_vlan_accel - control HW VLAN extraction
1156 * @adapter: the adapter
1157 * @ports: bitmap of adapter ports to operate on
1158 * @on: enable (1) or disable (0) HW VLAN extraction
1160 * Enables or disables HW extraction of VLAN tags for the given port.
1162 void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on)
1164 t3_set_reg_field(adapter, A_TP_OUT_CONFIG,
1165 ports << S_VLANEXTRACTIONENABLE,
1166 on ? (ports << S_VLANEXTRACTIONENABLE) : 0);
1170 unsigned int mask; /* bits to check in interrupt status */
1171 const char *msg; /* message to print or NULL */
1172 short stat_idx; /* stat counter to increment or -1 */
1173 unsigned short fatal:1; /* whether the condition reported is fatal */
1177 * t3_handle_intr_status - table driven interrupt handler
1178 * @adapter: the adapter that generated the interrupt
1179 * @reg: the interrupt status register to process
1180 * @mask: a mask to apply to the interrupt status
1181 * @acts: table of interrupt actions
1182 * @stats: statistics counters tracking interrupt occurences
1184 * A table driven interrupt handler that applies a set of masks to an
1185 * interrupt status word and performs the corresponding actions if the
1186 * interrupts described by the mask have occured. The actions include
1187 * optionally printing a warning or alert message, and optionally
1188 * incrementing a stat counter. The table is terminated by an entry
1189 * specifying mask 0. Returns the number of fatal interrupt conditions.
1191 static int t3_handle_intr_status(struct adapter *adapter, unsigned int reg,
1193 const struct intr_info *acts,
1194 unsigned long *stats)
1197 unsigned int status = t3_read_reg(adapter, reg) & mask;
1199 for (; acts->mask; ++acts) {
1200 if (!(status & acts->mask))
1204 CH_ALERT(adapter, "%s (0x%x)\n",
1205 acts->msg, status & acts->mask);
1206 } else if (acts->msg)
1207 CH_WARN(adapter, "%s (0x%x)\n",
1208 acts->msg, status & acts->mask);
1209 if (acts->stat_idx >= 0)
1210 stats[acts->stat_idx]++;
1212 if (status) /* clear processed interrupts */
1213 t3_write_reg(adapter, reg, status);
1217 #define SGE_INTR_MASK (F_RSPQDISABLED)
1218 #define MC5_INTR_MASK (F_PARITYERR | F_ACTRGNFULL | F_UNKNOWNCMD | \
1219 F_REQQPARERR | F_DISPQPARERR | F_DELACTEMPTY | \
1221 #define MC7_INTR_MASK (F_AE | F_UE | F_CE | V_PE(M_PE))
1222 #define XGM_INTR_MASK (V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR) | \
1223 V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR) | \
1224 F_TXFIFO_UNDERRUN | F_RXFIFO_OVERFLOW)
1225 #define PCIX_INTR_MASK (F_MSTDETPARERR | F_SIGTARABT | F_RCVTARABT | \
1226 F_RCVMSTABT | F_SIGSYSERR | F_DETPARERR | \
1227 F_SPLCMPDIS | F_UNXSPLCMP | F_RCVSPLCMPERR | \
1228 F_DETCORECCERR | F_DETUNCECCERR | F_PIOPARERR | \
1229 V_WFPARERR(M_WFPARERR) | V_RFPARERR(M_RFPARERR) | \
1230 V_CFPARERR(M_CFPARERR) /* | V_MSIXPARERR(M_MSIXPARERR) */)
1231 #define PCIE_INTR_MASK (F_UNXSPLCPLERRR | F_UNXSPLCPLERRC | F_PCIE_PIOPARERR |\
1232 F_PCIE_WFPARERR | F_PCIE_RFPARERR | F_PCIE_CFPARERR | \
1233 /* V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR) | */ \
1234 V_BISTERR(M_BISTERR) | F_PEXERR)
1235 #define ULPRX_INTR_MASK F_PARERR
1236 #define ULPTX_INTR_MASK 0
1237 #define CPLSW_INTR_MASK (F_TP_FRAMING_ERROR | \
1238 F_SGE_FRAMING_ERROR | F_CIM_FRAMING_ERROR | \
1239 F_ZERO_SWITCH_ERROR)
1240 #define CIM_INTR_MASK (F_BLKWRPLINT | F_BLKRDPLINT | F_BLKWRCTLINT | \
1241 F_BLKRDCTLINT | F_BLKWRFLASHINT | F_BLKRDFLASHINT | \
1242 F_SGLWRFLASHINT | F_WRBLKFLASHINT | F_BLKWRBOOTINT | \
1243 F_FLASHRANGEINT | F_SDRAMRANGEINT | F_RSVDSPACEINT)
1244 #define PMTX_INTR_MASK (F_ZERO_C_CMD_ERROR | ICSPI_FRM_ERR | OESPI_FRM_ERR | \
1245 V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR) | \
1246 V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR))
1247 #define PMRX_INTR_MASK (F_ZERO_E_CMD_ERROR | IESPI_FRM_ERR | OCSPI_FRM_ERR | \
1248 V_IESPI_PAR_ERROR(M_IESPI_PAR_ERROR) | \
1249 V_OCSPI_PAR_ERROR(M_OCSPI_PAR_ERROR))
1250 #define MPS_INTR_MASK (V_TX0TPPARERRENB(M_TX0TPPARERRENB) | \
1251 V_TX1TPPARERRENB(M_TX1TPPARERRENB) | \
1252 V_RXTPPARERRENB(M_RXTPPARERRENB) | \
1253 V_MCAPARERRENB(M_MCAPARERRENB))
1254 #define PL_INTR_MASK (F_T3DBG | F_XGMAC0_0 | F_XGMAC0_1 | F_MC5A | F_PM1_TX | \
1255 F_PM1_RX | F_ULP2_TX | F_ULP2_RX | F_TP1 | F_CIM | \
1256 F_MC7_CM | F_MC7_PMTX | F_MC7_PMRX | F_SGE3 | F_PCIM0 | \
1257 F_MPS0 | F_CPL_SWITCH)
1260 * Interrupt handler for the PCIX1 module.
1262 static void pci_intr_handler(struct adapter *adapter)
1264 static const struct intr_info pcix1_intr_info[] = {
1265 {F_MSTDETPARERR, "PCI master detected parity error", -1, 1},
1266 {F_SIGTARABT, "PCI signaled target abort", -1, 1},
1267 {F_RCVTARABT, "PCI received target abort", -1, 1},
1268 {F_RCVMSTABT, "PCI received master abort", -1, 1},
1269 {F_SIGSYSERR, "PCI signaled system error", -1, 1},
1270 {F_DETPARERR, "PCI detected parity error", -1, 1},
1271 {F_SPLCMPDIS, "PCI split completion discarded", -1, 1},
1272 {F_UNXSPLCMP, "PCI unexpected split completion error", -1, 1},
1273 {F_RCVSPLCMPERR, "PCI received split completion error", -1,
1275 {F_DETCORECCERR, "PCI correctable ECC error",
1276 STAT_PCI_CORR_ECC, 0},
1277 {F_DETUNCECCERR, "PCI uncorrectable ECC error", -1, 1},
1278 {F_PIOPARERR, "PCI PIO FIFO parity error", -1, 1},
1279 {V_WFPARERR(M_WFPARERR), "PCI write FIFO parity error", -1,
1281 {V_RFPARERR(M_RFPARERR), "PCI read FIFO parity error", -1,
1283 {V_CFPARERR(M_CFPARERR), "PCI command FIFO parity error", -1,
1285 {V_MSIXPARERR(M_MSIXPARERR), "PCI MSI-X table/PBA parity "
1290 if (t3_handle_intr_status(adapter, A_PCIX_INT_CAUSE, PCIX_INTR_MASK,
1291 pcix1_intr_info, adapter->irq_stats))
1292 t3_fatal_err(adapter);
1296 * Interrupt handler for the PCIE module.
1298 static void pcie_intr_handler(struct adapter *adapter)
1300 static const struct intr_info pcie_intr_info[] = {
1301 {F_PEXERR, "PCI PEX error", -1, 1},
1303 "PCI unexpected split completion DMA read error", -1, 1},
1305 "PCI unexpected split completion DMA command error", -1, 1},
1306 {F_PCIE_PIOPARERR, "PCI PIO FIFO parity error", -1, 1},
1307 {F_PCIE_WFPARERR, "PCI write FIFO parity error", -1, 1},
1308 {F_PCIE_RFPARERR, "PCI read FIFO parity error", -1, 1},
1309 {F_PCIE_CFPARERR, "PCI command FIFO parity error", -1, 1},
1310 {V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR),
1311 "PCI MSI-X table/PBA parity error", -1, 1},
1312 {V_BISTERR(M_BISTERR), "PCI BIST error", -1, 1},
1316 if (t3_handle_intr_status(adapter, A_PCIE_INT_CAUSE, PCIE_INTR_MASK,
1317 pcie_intr_info, adapter->irq_stats))
1318 t3_fatal_err(adapter);
1322 * TP interrupt handler.
1324 static void tp_intr_handler(struct adapter *adapter)
1326 static const struct intr_info tp_intr_info[] = {
1327 {0xffffff, "TP parity error", -1, 1},
1328 {0x1000000, "TP out of Rx pages", -1, 1},
1329 {0x2000000, "TP out of Tx pages", -1, 1},
1333 if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff,
1334 tp_intr_info, NULL))
1335 t3_fatal_err(adapter);
1339 * CIM interrupt handler.
1341 static void cim_intr_handler(struct adapter *adapter)
1343 static const struct intr_info cim_intr_info[] = {
1344 {F_RSVDSPACEINT, "CIM reserved space write", -1, 1},
1345 {F_SDRAMRANGEINT, "CIM SDRAM address out of range", -1, 1},
1346 {F_FLASHRANGEINT, "CIM flash address out of range", -1, 1},
1347 {F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1},
1348 {F_WRBLKFLASHINT, "CIM write to cached flash space", -1, 1},
1349 {F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1},
1350 {F_BLKRDFLASHINT, "CIM block read from flash space", -1, 1},
1351 {F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1},
1352 {F_BLKRDCTLINT, "CIM block read from CTL space", -1, 1},
1353 {F_BLKWRCTLINT, "CIM block write to CTL space", -1, 1},
1354 {F_BLKRDPLINT, "CIM block read from PL space", -1, 1},
1355 {F_BLKWRPLINT, "CIM block write to PL space", -1, 1},
1359 if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 0xffffffff,
1360 cim_intr_info, NULL))
1361 t3_fatal_err(adapter);
1365 * ULP RX interrupt handler.
1367 static void ulprx_intr_handler(struct adapter *adapter)
1369 static const struct intr_info ulprx_intr_info[] = {
1370 {F_PARERR, "ULP RX parity error", -1, 1},
1374 if (t3_handle_intr_status(adapter, A_ULPRX_INT_CAUSE, 0xffffffff,
1375 ulprx_intr_info, NULL))
1376 t3_fatal_err(adapter);
1380 * ULP TX interrupt handler.
1382 static void ulptx_intr_handler(struct adapter *adapter)
1384 static const struct intr_info ulptx_intr_info[] = {
1385 {F_PBL_BOUND_ERR_CH0, "ULP TX channel 0 PBL out of bounds",
1386 STAT_ULP_CH0_PBL_OOB, 0},
1387 {F_PBL_BOUND_ERR_CH1, "ULP TX channel 1 PBL out of bounds",
1388 STAT_ULP_CH1_PBL_OOB, 0},
1392 if (t3_handle_intr_status(adapter, A_ULPTX_INT_CAUSE, 0xffffffff,
1393 ulptx_intr_info, adapter->irq_stats))
1394 t3_fatal_err(adapter);
1397 #define ICSPI_FRM_ERR (F_ICSPI0_FIFO2X_RX_FRAMING_ERROR | \
1398 F_ICSPI1_FIFO2X_RX_FRAMING_ERROR | F_ICSPI0_RX_FRAMING_ERROR | \
1399 F_ICSPI1_RX_FRAMING_ERROR | F_ICSPI0_TX_FRAMING_ERROR | \
1400 F_ICSPI1_TX_FRAMING_ERROR)
1401 #define OESPI_FRM_ERR (F_OESPI0_RX_FRAMING_ERROR | \
1402 F_OESPI1_RX_FRAMING_ERROR | F_OESPI0_TX_FRAMING_ERROR | \
1403 F_OESPI1_TX_FRAMING_ERROR | F_OESPI0_OFIFO2X_TX_FRAMING_ERROR | \
1404 F_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
1407 * PM TX interrupt handler.
1409 static void pmtx_intr_handler(struct adapter *adapter)
1411 static const struct intr_info pmtx_intr_info[] = {
1412 {F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1},
1413 {ICSPI_FRM_ERR, "PMTX ispi framing error", -1, 1},
1414 {OESPI_FRM_ERR, "PMTX ospi framing error", -1, 1},
1415 {V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR),
1416 "PMTX ispi parity error", -1, 1},
1417 {V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR),
1418 "PMTX ospi parity error", -1, 1},
1422 if (t3_handle_intr_status(adapter, A_PM1_TX_INT_CAUSE, 0xffffffff,
1423 pmtx_intr_info, NULL))
1424 t3_fatal_err(adapter);
1427 #define IESPI_FRM_ERR (F_IESPI0_FIFO2X_RX_FRAMING_ERROR | \
1428 F_IESPI1_FIFO2X_RX_FRAMING_ERROR | F_IESPI0_RX_FRAMING_ERROR | \
1429 F_IESPI1_RX_FRAMING_ERROR | F_IESPI0_TX_FRAMING_ERROR | \
1430 F_IESPI1_TX_FRAMING_ERROR)
1431 #define OCSPI_FRM_ERR (F_OCSPI0_RX_FRAMING_ERROR | \
1432 F_OCSPI1_RX_FRAMING_ERROR | F_OCSPI0_TX_FRAMING_ERROR | \
1433 F_OCSPI1_TX_FRAMING_ERROR | F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR | \
1434 F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
1437 * PM RX interrupt handler.
1439 static void pmrx_intr_handler(struct adapter *adapter)
1441 static const struct intr_info pmrx_intr_info[] = {
1442 {F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1},
1443 {IESPI_FRM_ERR, "PMRX ispi framing error", -1, 1},
1444 {OCSPI_FRM_ERR, "PMRX ospi framing error", -1, 1},
1445 {V_IESPI_PAR_ERROR(M_IESPI_PAR_ERROR),
1446 "PMRX ispi parity error", -1, 1},
1447 {V_OCSPI_PAR_ERROR(M_OCSPI_PAR_ERROR),
1448 "PMRX ospi parity error", -1, 1},
1452 if (t3_handle_intr_status(adapter, A_PM1_RX_INT_CAUSE, 0xffffffff,
1453 pmrx_intr_info, NULL))
1454 t3_fatal_err(adapter);
1458 * CPL switch interrupt handler.
1460 static void cplsw_intr_handler(struct adapter *adapter)
1462 static const struct intr_info cplsw_intr_info[] = {
1463 /* { F_CIM_OVFL_ERROR, "CPL switch CIM overflow", -1, 1 }, */
1464 {F_TP_FRAMING_ERROR, "CPL switch TP framing error", -1, 1},
1465 {F_SGE_FRAMING_ERROR, "CPL switch SGE framing error", -1, 1},
1466 {F_CIM_FRAMING_ERROR, "CPL switch CIM framing error", -1, 1},
1467 {F_ZERO_SWITCH_ERROR, "CPL switch no-switch error", -1, 1},
1471 if (t3_handle_intr_status(adapter, A_CPL_INTR_CAUSE, 0xffffffff,
1472 cplsw_intr_info, NULL))
1473 t3_fatal_err(adapter);
1477 * MPS interrupt handler.
1479 static void mps_intr_handler(struct adapter *adapter)
1481 static const struct intr_info mps_intr_info[] = {
1482 {0x1ff, "MPS parity error", -1, 1},
1486 if (t3_handle_intr_status(adapter, A_MPS_INT_CAUSE, 0xffffffff,
1487 mps_intr_info, NULL))
1488 t3_fatal_err(adapter);
1491 #define MC7_INTR_FATAL (F_UE | V_PE(M_PE) | F_AE)
1494 * MC7 interrupt handler.
1496 static void mc7_intr_handler(struct mc7 *mc7)
1498 struct adapter *adapter = mc7->adapter;
1499 u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);
1502 mc7->stats.corr_err++;
1503 CH_WARN(adapter, "%s MC7 correctable error at addr 0x%x, "
1504 "data 0x%x 0x%x 0x%x\n", mc7->name,
1505 t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR),
1506 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0),
1507 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1),
1508 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2));
1512 mc7->stats.uncorr_err++;
1513 CH_ALERT(adapter, "%s MC7 uncorrectable error at addr 0x%x, "
1514 "data 0x%x 0x%x 0x%x\n", mc7->name,
1515 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR),
1516 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0),
1517 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1),
1518 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2));
1522 mc7->stats.parity_err++;
1523 CH_ALERT(adapter, "%s MC7 parity error 0x%x\n",
1524 mc7->name, G_PE(cause));
1530 if (adapter->params.rev > 0)
1531 addr = t3_read_reg(adapter,
1532 mc7->offset + A_MC7_ERR_ADDR);
1533 mc7->stats.addr_err++;
1534 CH_ALERT(adapter, "%s MC7 address error: 0x%x\n",
1538 if (cause & MC7_INTR_FATAL)
1539 t3_fatal_err(adapter);
1541 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause);
1544 #define XGM_INTR_FATAL (V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR) | \
1545 V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR))
1547 * XGMAC interrupt handler.
1549 static int mac_intr_handler(struct adapter *adap, unsigned int idx)
1551 struct cmac *mac = &adap2pinfo(adap, idx)->mac;
1552 u32 cause = t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset);
1554 if (cause & V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR)) {
1555 mac->stats.tx_fifo_parity_err++;
1556 CH_ALERT(adap, "port%d: MAC TX FIFO parity error\n", idx);
1558 if (cause & V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR)) {
1559 mac->stats.rx_fifo_parity_err++;
1560 CH_ALERT(adap, "port%d: MAC RX FIFO parity error\n", idx);
1562 if (cause & F_TXFIFO_UNDERRUN)
1563 mac->stats.tx_fifo_urun++;
1564 if (cause & F_RXFIFO_OVERFLOW)
1565 mac->stats.rx_fifo_ovfl++;
1566 if (cause & V_SERDES_LOS(M_SERDES_LOS))
1567 mac->stats.serdes_signal_loss++;
1568 if (cause & F_XAUIPCSCTCERR)
1569 mac->stats.xaui_pcs_ctc_err++;
1570 if (cause & F_XAUIPCSALIGNCHANGE)
1571 mac->stats.xaui_pcs_align_change++;
1573 t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause);
1574 if (cause & XGM_INTR_FATAL)
1580 * Interrupt handler for PHY events.
1582 int t3_phy_intr_handler(struct adapter *adapter)
1584 u32 mask, gpi = adapter_info(adapter)->gpio_intr;
1585 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
1587 for_each_port(adapter, i) {
1588 struct port_info *p = adap2pinfo(adapter, i);
1590 mask = gpi - (gpi & (gpi - 1));
1593 if (!(p->port_type->caps & SUPPORTED_IRQ))
1597 int phy_cause = p->phy.ops->intr_handler(&p->phy);
1599 if (phy_cause & cphy_cause_link_change)
1600 t3_link_changed(adapter, i);
1601 if (phy_cause & cphy_cause_fifo_error)
1602 p->phy.fifo_errors++;
1606 t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause);
1611 * T3 slow path (non-data) interrupt handler.
1613 int t3_slow_intr_handler(struct adapter *adapter)
1615 u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0);
1617 cause &= adapter->slow_intr_mask;
1620 if (cause & F_PCIM0) {
1621 if (is_pcie(adapter))
1622 pcie_intr_handler(adapter);
1624 pci_intr_handler(adapter);
1627 t3_sge_err_intr_handler(adapter);
1628 if (cause & F_MC7_PMRX)
1629 mc7_intr_handler(&adapter->pmrx);
1630 if (cause & F_MC7_PMTX)
1631 mc7_intr_handler(&adapter->pmtx);
1632 if (cause & F_MC7_CM)
1633 mc7_intr_handler(&adapter->cm);
1635 cim_intr_handler(adapter);
1637 tp_intr_handler(adapter);
1638 if (cause & F_ULP2_RX)
1639 ulprx_intr_handler(adapter);
1640 if (cause & F_ULP2_TX)
1641 ulptx_intr_handler(adapter);
1642 if (cause & F_PM1_RX)
1643 pmrx_intr_handler(adapter);
1644 if (cause & F_PM1_TX)
1645 pmtx_intr_handler(adapter);
1646 if (cause & F_CPL_SWITCH)
1647 cplsw_intr_handler(adapter);
1649 mps_intr_handler(adapter);
1651 t3_mc5_intr_handler(&adapter->mc5);
1652 if (cause & F_XGMAC0_0)
1653 mac_intr_handler(adapter, 0);
1654 if (cause & F_XGMAC0_1)
1655 mac_intr_handler(adapter, 1);
1656 if (cause & F_T3DBG)
1657 t3_os_ext_intr_handler(adapter);
1659 /* Clear the interrupts just processed. */
1660 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause);
1661 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
1666 * t3_intr_enable - enable interrupts
1667 * @adapter: the adapter whose interrupts should be enabled
1669 * Enable interrupts by setting the interrupt enable registers of the
1670 * various HW modules and then enabling the top-level interrupt
1673 void t3_intr_enable(struct adapter *adapter)
1675 static const struct addr_val_pair intr_en_avp[] = {
1676 {A_SG_INT_ENABLE, SGE_INTR_MASK},
1677 {A_MC7_INT_ENABLE, MC7_INTR_MASK},
1678 {A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR,
1680 {A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR,
1682 {A_MC5_DB_INT_ENABLE, MC5_INTR_MASK},
1683 {A_ULPRX_INT_ENABLE, ULPRX_INTR_MASK},
1684 {A_TP_INT_ENABLE, 0x3bfffff},
1685 {A_PM1_TX_INT_ENABLE, PMTX_INTR_MASK},
1686 {A_PM1_RX_INT_ENABLE, PMRX_INTR_MASK},
1687 {A_CIM_HOST_INT_ENABLE, CIM_INTR_MASK},
1688 {A_MPS_INT_ENABLE, MPS_INTR_MASK},
1691 adapter->slow_intr_mask = PL_INTR_MASK;
1693 t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0);
1695 if (adapter->params.rev > 0) {
1696 t3_write_reg(adapter, A_CPL_INTR_ENABLE,
1697 CPLSW_INTR_MASK | F_CIM_OVFL_ERROR);
1698 t3_write_reg(adapter, A_ULPTX_INT_ENABLE,
1699 ULPTX_INTR_MASK | F_PBL_BOUND_ERR_CH0 |
1700 F_PBL_BOUND_ERR_CH1);
1702 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK);
1703 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK);
1706 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW,
1707 adapter_info(adapter)->gpio_intr);
1708 t3_write_reg(adapter, A_T3DBG_INT_ENABLE,
1709 adapter_info(adapter)->gpio_intr);
1710 if (is_pcie(adapter))
1711 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK);
1713 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK);
1714 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask);
1715 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
1719 * t3_intr_disable - disable a card's interrupts
1720 * @adapter: the adapter whose interrupts should be disabled
1722 * Disable interrupts. We only disable the top-level interrupt
1723 * concentrator and the SGE data interrupts.
1725 void t3_intr_disable(struct adapter *adapter)
1727 t3_write_reg(adapter, A_PL_INT_ENABLE0, 0);
1728 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
1729 adapter->slow_intr_mask = 0;
1733 * t3_intr_clear - clear all interrupts
1734 * @adapter: the adapter whose interrupts should be cleared
1736 * Clears all interrupts.
1738 void t3_intr_clear(struct adapter *adapter)
1740 static const unsigned int cause_reg_addr[] = {
1742 A_SG_RSPQ_FL_STATUS,
1745 A_MC7_INT_CAUSE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR,
1746 A_MC7_INT_CAUSE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR,
1747 A_CIM_HOST_INT_CAUSE,
1760 /* Clear PHY and MAC interrupts for each port. */
1761 for_each_port(adapter, i)
1762 t3_port_intr_clear(adapter, i);
1764 for (i = 0; i < ARRAY_SIZE(cause_reg_addr); ++i)
1765 t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff);
1767 t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff);
1768 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
1772 * t3_port_intr_enable - enable port-specific interrupts
1773 * @adapter: associated adapter
1774 * @idx: index of port whose interrupts should be enabled
1776 * Enable port-specific (i.e., MAC and PHY) interrupts for the given
1779 void t3_port_intr_enable(struct adapter *adapter, int idx)
1781 struct cphy *phy = &adap2pinfo(adapter, idx)->phy;
1783 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), XGM_INTR_MASK);
1784 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */
1785 phy->ops->intr_enable(phy);
1789 * t3_port_intr_disable - disable port-specific interrupts
1790 * @adapter: associated adapter
1791 * @idx: index of port whose interrupts should be disabled
1793 * Disable port-specific (i.e., MAC and PHY) interrupts for the given
1796 void t3_port_intr_disable(struct adapter *adapter, int idx)
1798 struct cphy *phy = &adap2pinfo(adapter, idx)->phy;
1800 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), 0);
1801 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */
1802 phy->ops->intr_disable(phy);
1806 * t3_port_intr_clear - clear port-specific interrupts
1807 * @adapter: associated adapter
1808 * @idx: index of port whose interrupts to clear
1810 * Clear port-specific (i.e., MAC and PHY) interrupts for the given
1813 void t3_port_intr_clear(struct adapter *adapter, int idx)
1815 struct cphy *phy = &adap2pinfo(adapter, idx)->phy;
1817 t3_write_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx), 0xffffffff);
1818 t3_read_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx)); /* flush */
1819 phy->ops->intr_clear(phy);
1823 * t3_sge_write_context - write an SGE context
1824 * @adapter: the adapter
1825 * @id: the context id
1826 * @type: the context type
1828 * Program an SGE context with the values already loaded in the
1829 * CONTEXT_DATA? registers.
1831 static int t3_sge_write_context(struct adapter *adapter, unsigned int id,
1834 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
1835 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
1836 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff);
1837 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
1838 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
1839 V_CONTEXT_CMD_OPCODE(1) | type | V_CONTEXT(id));
1840 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
1845 * t3_sge_init_ecntxt - initialize an SGE egress context
1846 * @adapter: the adapter to configure
1847 * @id: the context id
1848 * @gts_enable: whether to enable GTS for the context
1849 * @type: the egress context type
1850 * @respq: associated response queue
1851 * @base_addr: base address of queue
1852 * @size: number of queue entries
1854 * @gen: initial generation value for the context
1855 * @cidx: consumer pointer
1857 * Initialize an SGE egress context and make it ready for use. If the
1858 * platform allows concurrent context operations, the caller is
1859 * responsible for appropriate locking.
1861 int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable,
1862 enum sge_context_type type, int respq, u64 base_addr,
1863 unsigned int size, unsigned int token, int gen,
1866 unsigned int credits = type == SGE_CNTXT_OFLD ? 0 : FW_WR_NUM;
1868 if (base_addr & 0xfff) /* must be 4K aligned */
1870 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1874 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) |
1875 V_EC_CREDITS(credits) | V_EC_GTS(gts_enable));
1876 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) |
1877 V_EC_BASE_LO(base_addr & 0xffff));
1879 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, base_addr);
1881 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
1882 V_EC_BASE_HI(base_addr & 0xf) | V_EC_RESPQ(respq) |
1883 V_EC_TYPE(type) | V_EC_GEN(gen) | V_EC_UP_TOKEN(token) |
1885 return t3_sge_write_context(adapter, id, F_EGRESS);
1889 * t3_sge_init_flcntxt - initialize an SGE free-buffer list context
1890 * @adapter: the adapter to configure
1891 * @id: the context id
1892 * @gts_enable: whether to enable GTS for the context
1893 * @base_addr: base address of queue
1894 * @size: number of queue entries
1895 * @bsize: size of each buffer for this queue
1896 * @cong_thres: threshold to signal congestion to upstream producers
1897 * @gen: initial generation value for the context
1898 * @cidx: consumer pointer
1900 * Initialize an SGE free list context and make it ready for use. The
1901 * caller is responsible for ensuring only one context operation occurs
1904 int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id,
1905 int gts_enable, u64 base_addr, unsigned int size,
1906 unsigned int bsize, unsigned int cong_thres, int gen,
1909 if (base_addr & 0xfff) /* must be 4K aligned */
1911 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1915 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, base_addr);
1917 t3_write_reg(adapter, A_SG_CONTEXT_DATA1,
1918 V_FL_BASE_HI((u32) base_addr) |
1919 V_FL_INDEX_LO(cidx & M_FL_INDEX_LO));
1920 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) |
1921 V_FL_GEN(gen) | V_FL_INDEX_HI(cidx >> 12) |
1922 V_FL_ENTRY_SIZE_LO(bsize & M_FL_ENTRY_SIZE_LO));
1923 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
1924 V_FL_ENTRY_SIZE_HI(bsize >> (32 - S_FL_ENTRY_SIZE_LO)) |
1925 V_FL_CONG_THRES(cong_thres) | V_FL_GTS(gts_enable));
1926 return t3_sge_write_context(adapter, id, F_FREELIST);
1930 * t3_sge_init_rspcntxt - initialize an SGE response queue context
1931 * @adapter: the adapter to configure
1932 * @id: the context id
1933 * @irq_vec_idx: MSI-X interrupt vector index, 0 if no MSI-X, -1 if no IRQ
1934 * @base_addr: base address of queue
1935 * @size: number of queue entries
1936 * @fl_thres: threshold for selecting the normal or jumbo free list
1937 * @gen: initial generation value for the context
1938 * @cidx: consumer pointer
1940 * Initialize an SGE response queue context and make it ready for use.
1941 * The caller is responsible for ensuring only one context operation
1944 int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id,
1945 int irq_vec_idx, u64 base_addr, unsigned int size,
1946 unsigned int fl_thres, int gen, unsigned int cidx)
1948 unsigned int intr = 0;
1950 if (base_addr & 0xfff) /* must be 4K aligned */
1952 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1956 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) |
1958 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr);
1960 if (irq_vec_idx >= 0)
1961 intr = V_RQ_MSI_VEC(irq_vec_idx) | F_RQ_INTR_EN;
1962 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
1963 V_CQ_BASE_HI((u32) base_addr) | intr | V_RQ_GEN(gen));
1964 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres);
1965 return t3_sge_write_context(adapter, id, F_RESPONSEQ);
1969 * t3_sge_init_cqcntxt - initialize an SGE completion queue context
1970 * @adapter: the adapter to configure
1971 * @id: the context id
1972 * @base_addr: base address of queue
1973 * @size: number of queue entries
1974 * @rspq: response queue for async notifications
1975 * @ovfl_mode: CQ overflow mode
1976 * @credits: completion queue credits
1977 * @credit_thres: the credit threshold
1979 * Initialize an SGE completion queue context and make it ready for use.
1980 * The caller is responsible for ensuring only one context operation
1983 int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
1984 unsigned int size, int rspq, int ovfl_mode,
1985 unsigned int credits, unsigned int credit_thres)
1987 if (base_addr & 0xfff) /* must be 4K aligned */
1989 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1993 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size));
1994 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr);
1996 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
1997 V_CQ_BASE_HI((u32) base_addr) | V_CQ_RSPQ(rspq) |
1998 V_CQ_GEN(1) | V_CQ_OVERFLOW_MODE(ovfl_mode));
1999 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) |
2000 V_CQ_CREDIT_THRES(credit_thres));
2001 return t3_sge_write_context(adapter, id, F_CQ);
2005 * t3_sge_enable_ecntxt - enable/disable an SGE egress context
2006 * @adapter: the adapter
2007 * @id: the egress context id
2008 * @enable: enable (1) or disable (0) the context
2010 * Enable or disable an SGE egress context. The caller is responsible for
2011 * ensuring only one context operation occurs at a time.
2013 int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable)
2015 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2018 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2019 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2020 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2021 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, F_EC_VALID);
2022 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_VALID(enable));
2023 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2024 V_CONTEXT_CMD_OPCODE(1) | F_EGRESS | V_CONTEXT(id));
2025 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2030 * t3_sge_disable_fl - disable an SGE free-buffer list
2031 * @adapter: the adapter
2032 * @id: the free list context id
2034 * Disable an SGE free-buffer list. The caller is responsible for
2035 * ensuring only one context operation occurs at a time.
2037 int t3_sge_disable_fl(struct adapter *adapter, unsigned int id)
2039 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2042 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2043 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2044 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, V_FL_SIZE(M_FL_SIZE));
2045 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2046 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 0);
2047 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2048 V_CONTEXT_CMD_OPCODE(1) | F_FREELIST | V_CONTEXT(id));
2049 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2054 * t3_sge_disable_rspcntxt - disable an SGE response queue
2055 * @adapter: the adapter
2056 * @id: the response queue context id
2058 * Disable an SGE response queue. The caller is responsible for
2059 * ensuring only one context operation occurs at a time.
2061 int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id)
2063 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2066 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2067 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2068 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2069 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2070 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2071 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2072 V_CONTEXT_CMD_OPCODE(1) | F_RESPONSEQ | V_CONTEXT(id));
2073 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2078 * t3_sge_disable_cqcntxt - disable an SGE completion queue
2079 * @adapter: the adapter
2080 * @id: the completion queue context id
2082 * Disable an SGE completion queue. The caller is responsible for
2083 * ensuring only one context operation occurs at a time.
2085 int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id)
2087 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2090 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2091 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2092 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2093 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2094 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2095 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2096 V_CONTEXT_CMD_OPCODE(1) | F_CQ | V_CONTEXT(id));
2097 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2102 * t3_sge_cqcntxt_op - perform an operation on a completion queue context
2103 * @adapter: the adapter
2104 * @id: the context id
2105 * @op: the operation to perform
2107 * Perform the selected operation on an SGE completion queue context.
2108 * The caller is responsible for ensuring only one context operation
2111 int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op,
2112 unsigned int credits)
2116 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2119 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, credits << 16);
2120 t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) |
2121 V_CONTEXT(id) | F_CQ);
2122 if (t3_wait_op_done_val(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2126 if (op >= 2 && op < 7) {
2127 if (adapter->params.rev > 0)
2128 return G_CQ_INDEX(val);
2130 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2131 V_CONTEXT_CMD_OPCODE(0) | F_CQ | V_CONTEXT(id));
2132 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD,
2133 F_CONTEXT_CMD_BUSY, 0, 5, 1))
2135 return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0));
2141 * t3_sge_read_context - read an SGE context
2142 * @type: the context type
2143 * @adapter: the adapter
2144 * @id: the context id
2145 * @data: holds the retrieved context
2147 * Read an SGE egress context. The caller is responsible for ensuring
2148 * only one context operation occurs at a time.
2150 static int t3_sge_read_context(unsigned int type, struct adapter *adapter,
2151 unsigned int id, u32 data[4])
2153 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2156 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2157 V_CONTEXT_CMD_OPCODE(0) | type | V_CONTEXT(id));
2158 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0,
2161 data[0] = t3_read_reg(adapter, A_SG_CONTEXT_DATA0);
2162 data[1] = t3_read_reg(adapter, A_SG_CONTEXT_DATA1);
2163 data[2] = t3_read_reg(adapter, A_SG_CONTEXT_DATA2);
2164 data[3] = t3_read_reg(adapter, A_SG_CONTEXT_DATA3);
2169 * t3_sge_read_ecntxt - read an SGE egress context
2170 * @adapter: the adapter
2171 * @id: the context id
2172 * @data: holds the retrieved context
2174 * Read an SGE egress context. The caller is responsible for ensuring
2175 * only one context operation occurs at a time.
2177 int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4])
2181 return t3_sge_read_context(F_EGRESS, adapter, id, data);
2185 * t3_sge_read_cq - read an SGE CQ context
2186 * @adapter: the adapter
2187 * @id: the context id
2188 * @data: holds the retrieved context
2190 * Read an SGE CQ context. The caller is responsible for ensuring
2191 * only one context operation occurs at a time.
2193 int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4])
2197 return t3_sge_read_context(F_CQ, adapter, id, data);
2201 * t3_sge_read_fl - read an SGE free-list context
2202 * @adapter: the adapter
2203 * @id: the context id
2204 * @data: holds the retrieved context
2206 * Read an SGE free-list context. The caller is responsible for ensuring
2207 * only one context operation occurs at a time.
2209 int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4])
2211 if (id >= SGE_QSETS * 2)
2213 return t3_sge_read_context(F_FREELIST, adapter, id, data);
2217 * t3_sge_read_rspq - read an SGE response queue context
2218 * @adapter: the adapter
2219 * @id: the context id
2220 * @data: holds the retrieved context
2222 * Read an SGE response queue context. The caller is responsible for
2223 * ensuring only one context operation occurs at a time.
2225 int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4])
2227 if (id >= SGE_QSETS)
2229 return t3_sge_read_context(F_RESPONSEQ, adapter, id, data);
2233 * t3_config_rss - configure Rx packet steering
2234 * @adapter: the adapter
2235 * @rss_config: RSS settings (written to TP_RSS_CONFIG)
2236 * @cpus: values for the CPU lookup table (0xff terminated)
2237 * @rspq: values for the response queue lookup table (0xffff terminated)
2239 * Programs the receive packet steering logic. @cpus and @rspq provide
2240 * the values for the CPU and response queue lookup tables. If they
2241 * provide fewer values than the size of the tables the supplied values
2242 * are used repeatedly until the tables are fully populated.
2244 void t3_config_rss(struct adapter *adapter, unsigned int rss_config,
2245 const u8 * cpus, const u16 *rspq)
2247 int i, j, cpu_idx = 0, q_idx = 0;
2250 for (i = 0; i < RSS_TABLE_SIZE; ++i) {
2253 for (j = 0; j < 2; ++j) {
2254 val |= (cpus[cpu_idx++] & 0x3f) << (8 * j);
2255 if (cpus[cpu_idx] == 0xff)
2258 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val);
2262 for (i = 0; i < RSS_TABLE_SIZE; ++i) {
2263 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2264 (i << 16) | rspq[q_idx++]);
2265 if (rspq[q_idx] == 0xffff)
2269 t3_write_reg(adapter, A_TP_RSS_CONFIG, rss_config);
2273 * t3_read_rss - read the contents of the RSS tables
2274 * @adapter: the adapter
2275 * @lkup: holds the contents of the RSS lookup table
2276 * @map: holds the contents of the RSS map table
2278 * Reads the contents of the receive packet steering tables.
2280 int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map)
2286 for (i = 0; i < RSS_TABLE_SIZE; ++i) {
2287 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE,
2289 val = t3_read_reg(adapter, A_TP_RSS_LKP_TABLE);
2290 if (!(val & 0x80000000))
2293 *lkup++ = (val >> 8);
2297 for (i = 0; i < RSS_TABLE_SIZE; ++i) {
2298 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2300 val = t3_read_reg(adapter, A_TP_RSS_MAP_TABLE);
2301 if (!(val & 0x80000000))
2309 * t3_tp_set_offload_mode - put TP in NIC/offload mode
2310 * @adap: the adapter
2311 * @enable: 1 to select offload mode, 0 for regular NIC
2313 * Switches TP to NIC/offload mode.
2315 void t3_tp_set_offload_mode(struct adapter *adap, int enable)
2317 if (is_offload(adap) || !enable)
2318 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE,
2319 V_NICMODE(!enable));
2323 * pm_num_pages - calculate the number of pages of the payload memory
2324 * @mem_size: the size of the payload memory
2325 * @pg_size: the size of each payload memory page
2327 * Calculate the number of pages, each of the given size, that fit in a
2328 * memory of the specified size, respecting the HW requirement that the
2329 * number of pages must be a multiple of 24.
2331 static inline unsigned int pm_num_pages(unsigned int mem_size,
2332 unsigned int pg_size)
2334 unsigned int n = mem_size / pg_size;
2339 #define mem_region(adap, start, size, reg) \
2340 t3_write_reg((adap), A_ ## reg, (start)); \
2344 * partition_mem - partition memory and configure TP memory settings
2345 * @adap: the adapter
2346 * @p: the TP parameters
2348 * Partitions context and payload memory and configures TP's memory
2351 static void partition_mem(struct adapter *adap, const struct tp_params *p)
2353 unsigned int m, pstructs, tids = t3_mc5_size(&adap->mc5);
2354 unsigned int timers = 0, timers_shift = 22;
2356 if (adap->params.rev > 0) {
2357 if (tids <= 16 * 1024) {
2360 } else if (tids <= 64 * 1024) {
2363 } else if (tids <= 256 * 1024) {
2369 t3_write_reg(adap, A_TP_PMM_SIZE,
2370 p->chan_rx_size | (p->chan_tx_size >> 16));
2372 t3_write_reg(adap, A_TP_PMM_TX_BASE, 0);
2373 t3_write_reg(adap, A_TP_PMM_TX_PAGE_SIZE, p->tx_pg_size);
2374 t3_write_reg(adap, A_TP_PMM_TX_MAX_PAGE, p->tx_num_pgs);
2375 t3_set_reg_field(adap, A_TP_PARA_REG3, V_TXDATAACKIDX(M_TXDATAACKIDX),
2376 V_TXDATAACKIDX(fls(p->tx_pg_size) - 12));
2378 t3_write_reg(adap, A_TP_PMM_RX_BASE, 0);
2379 t3_write_reg(adap, A_TP_PMM_RX_PAGE_SIZE, p->rx_pg_size);
2380 t3_write_reg(adap, A_TP_PMM_RX_MAX_PAGE, p->rx_num_pgs);
2382 pstructs = p->rx_num_pgs + p->tx_num_pgs;
2383 /* Add a bit of headroom and make multiple of 24 */
2385 pstructs -= pstructs % 24;
2386 t3_write_reg(adap, A_TP_CMM_MM_MAX_PSTRUCT, pstructs);
2388 m = tids * TCB_SIZE;
2389 mem_region(adap, m, (64 << 10) * 64, SG_EGR_CNTX_BADDR);
2390 mem_region(adap, m, (64 << 10) * 64, SG_CQ_CONTEXT_BADDR);
2391 t3_write_reg(adap, A_TP_CMM_TIMER_BASE, V_CMTIMERMAXNUM(timers) | m);
2392 m += ((p->ntimer_qs - 1) << timers_shift) + (1 << 22);
2393 mem_region(adap, m, pstructs * 64, TP_CMM_MM_BASE);
2394 mem_region(adap, m, 64 * (pstructs / 24), TP_CMM_MM_PS_FLST_BASE);
2395 mem_region(adap, m, 64 * (p->rx_num_pgs / 24), TP_CMM_MM_RX_FLST_BASE);
2396 mem_region(adap, m, 64 * (p->tx_num_pgs / 24), TP_CMM_MM_TX_FLST_BASE);
2398 m = (m + 4095) & ~0xfff;
2399 t3_write_reg(adap, A_CIM_SDRAM_BASE_ADDR, m);
2400 t3_write_reg(adap, A_CIM_SDRAM_ADDR_SIZE, p->cm_size - m);
2402 tids = (p->cm_size - m - (3 << 20)) / 3072 - 32;
2403 m = t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
2404 adap->params.mc5.nfilters - adap->params.mc5.nroutes;
2406 adap->params.mc5.nservers += m - tids;
2409 static inline void tp_wr_indirect(struct adapter *adap, unsigned int addr,
2412 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2413 t3_write_reg(adap, A_TP_PIO_DATA, val);
2416 static void tp_config(struct adapter *adap, const struct tp_params *p)
2418 t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
2419 F_IPCHECKSUMOFFLOAD | F_UDPCHECKSUMOFFLOAD |
2420 F_TCPCHECKSUMOFFLOAD | V_IPTTL(64));
2421 t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
2422 F_MTUENABLE | V_WINDOWSCALEMODE(1) |
2423 V_TIMESTAMPSMODE(0) | V_SACKMODE(1) | V_SACKRX(1));
2424 t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
2425 V_AUTOSTATE2(1) | V_AUTOSTATE1(0) |
2426 V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) |
2427 F_AUTOCAREFUL | F_AUTOENABLE | V_DACK_MODE(1));
2428 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_IPV6ENABLE | F_NICMODE,
2429 F_IPV6ENABLE | F_NICMODE);
2430 t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
2431 t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
2432 t3_set_reg_field(adap, A_TP_PARA_REG6, 0,
2433 adap->params.rev > 0 ? F_ENABLEESND :
2436 t3_set_reg_field(adap, A_TP_PC_CONFIG,
2438 F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK |
2439 F_TXCONGESTIONMODE | F_RXCONGESTIONMODE);
2440 t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL, 0);
2441 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
2442 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
2444 if (adap->params.rev > 0) {
2445 tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);
2446 t3_set_reg_field(adap, A_TP_PARA_REG3, F_TXPACEAUTO,
2448 t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);
2449 t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEAUTOSTRICT);
2451 t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
2453 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
2454 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
2455 t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
2456 t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
2459 /* Desired TP timer resolution in usec */
2460 #define TP_TMR_RES 50
2462 /* TCP timer values in ms */
2463 #define TP_DACK_TIMER 50
2464 #define TP_RTO_MIN 250
2467 * tp_set_timers - set TP timing parameters
2468 * @adap: the adapter to set
2469 * @core_clk: the core clock frequency in Hz
2471 * Set TP's timing parameters, such as the various timer resolutions and
2472 * the TCP timer values.
2474 static void tp_set_timers(struct adapter *adap, unsigned int core_clk)
2476 unsigned int tre = fls(core_clk / (1000000 / TP_TMR_RES)) - 1;
2477 unsigned int dack_re = fls(core_clk / 5000) - 1; /* 200us */
2478 unsigned int tstamp_re = fls(core_clk / 1000); /* 1ms, at least */
2479 unsigned int tps = core_clk >> tre;
2481 t3_write_reg(adap, A_TP_TIMER_RESOLUTION, V_TIMERRESOLUTION(tre) |
2482 V_DELAYEDACKRESOLUTION(dack_re) |
2483 V_TIMESTAMPRESOLUTION(tstamp_re));
2484 t3_write_reg(adap, A_TP_DACK_TIMER,
2485 (core_clk >> dack_re) / (1000 / TP_DACK_TIMER));
2486 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG0, 0x3020100);
2487 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG1, 0x7060504);
2488 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG2, 0xb0a0908);
2489 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG3, 0xf0e0d0c);
2490 t3_write_reg(adap, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) |
2491 V_RXTSHIFTMAXR1(4) | V_RXTSHIFTMAXR2(15) |
2492 V_PERSHIFTBACKOFFMAX(8) | V_PERSHIFTMAX(8) |
2495 #define SECONDS * tps
2497 t3_write_reg(adap, A_TP_MSL, adap->params.rev > 0 ? 0 : 2 SECONDS);
2498 t3_write_reg(adap, A_TP_RXT_MIN, tps / (1000 / TP_RTO_MIN));
2499 t3_write_reg(adap, A_TP_RXT_MAX, 64 SECONDS);
2500 t3_write_reg(adap, A_TP_PERS_MIN, 5 SECONDS);
2501 t3_write_reg(adap, A_TP_PERS_MAX, 64 SECONDS);
2502 t3_write_reg(adap, A_TP_KEEP_IDLE, 7200 SECONDS);
2503 t3_write_reg(adap, A_TP_KEEP_INTVL, 75 SECONDS);
2504 t3_write_reg(adap, A_TP_INIT_SRTT, 3 SECONDS);
2505 t3_write_reg(adap, A_TP_FINWAIT2_TIMER, 600 SECONDS);
2511 * t3_tp_set_coalescing_size - set receive coalescing size
2512 * @adap: the adapter
2513 * @size: the receive coalescing size
2514 * @psh: whether a set PSH bit should deliver coalesced data
2516 * Set the receive coalescing size and PSH bit handling.
2518 int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh)
2522 if (size > MAX_RX_COALESCING_LEN)
2525 val = t3_read_reg(adap, A_TP_PARA_REG3);
2526 val &= ~(F_RXCOALESCEENABLE | F_RXCOALESCEPSHEN);
2529 val |= F_RXCOALESCEENABLE;
2531 val |= F_RXCOALESCEPSHEN;
2532 size = min(MAX_RX_COALESCING_LEN, size);
2533 t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) |
2534 V_MAXRXDATA(MAX_RX_COALESCING_LEN));
2536 t3_write_reg(adap, A_TP_PARA_REG3, val);
2541 * t3_tp_set_max_rxsize - set the max receive size
2542 * @adap: the adapter
2543 * @size: the max receive size
2545 * Set TP's max receive size. This is the limit that applies when
2546 * receive coalescing is disabled.
2548 void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size)
2550 t3_write_reg(adap, A_TP_PARA_REG7,
2551 V_PMMAXXFERLEN0(size) | V_PMMAXXFERLEN1(size));
2554 static void __devinit init_mtus(unsigned short mtus[])
2557 * See draft-mathis-plpmtud-00.txt for the values. The min is 88 so
2558 * it can accomodate max size TCP/IP headers when SACK and timestamps
2559 * are enabled and still have at least 8 bytes of payload.
2580 * Initial congestion control parameters.
2582 static void __devinit init_cong_ctrl(unsigned short *a, unsigned short *b)
2584 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
2609 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
2612 b[13] = b[14] = b[15] = b[16] = 3;
2613 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
2614 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
2619 /* The minimum additive increment value for the congestion control table */
2620 #define CC_MIN_INCR 2U
2623 * t3_load_mtus - write the MTU and congestion control HW tables
2624 * @adap: the adapter
2625 * @mtus: the unrestricted values for the MTU table
2626 * @alphs: the values for the congestion control alpha parameter
2627 * @beta: the values for the congestion control beta parameter
2628 * @mtu_cap: the maximum permitted effective MTU
2630 * Write the MTU table with the supplied MTUs capping each at &mtu_cap.
2631 * Update the high-speed congestion control table with the supplied alpha,
2634 void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
2635 unsigned short alpha[NCCTRL_WIN],
2636 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap)
2638 static const unsigned int avg_pkts[NCCTRL_WIN] = {
2639 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
2640 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
2641 28672, 40960, 57344, 81920, 114688, 163840, 229376
2646 for (i = 0; i < NMTUS; ++i) {
2647 unsigned int mtu = min(mtus[i], mtu_cap);
2648 unsigned int log2 = fls(mtu);
2650 if (!(mtu & ((1 << log2) >> 2))) /* round */
2652 t3_write_reg(adap, A_TP_MTU_TABLE,
2653 (i << 24) | (log2 << 16) | mtu);
2655 for (w = 0; w < NCCTRL_WIN; ++w) {
2658 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
2661 t3_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
2662 (w << 16) | (beta[w] << 13) | inc);
2668 * t3_read_hw_mtus - returns the values in the HW MTU table
2669 * @adap: the adapter
2670 * @mtus: where to store the HW MTU values
2672 * Reads the HW MTU table.
2674 void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS])
2678 for (i = 0; i < NMTUS; ++i) {
2681 t3_write_reg(adap, A_TP_MTU_TABLE, 0xff000000 | i);
2682 val = t3_read_reg(adap, A_TP_MTU_TABLE);
2683 mtus[i] = val & 0x3fff;
2688 * t3_get_cong_cntl_tab - reads the congestion control table
2689 * @adap: the adapter
2690 * @incr: where to store the alpha values
2692 * Reads the additive increments programmed into the HW congestion
2695 void t3_get_cong_cntl_tab(struct adapter *adap,
2696 unsigned short incr[NMTUS][NCCTRL_WIN])
2698 unsigned int mtu, w;
2700 for (mtu = 0; mtu < NMTUS; ++mtu)
2701 for (w = 0; w < NCCTRL_WIN; ++w) {
2702 t3_write_reg(adap, A_TP_CCTRL_TABLE,
2703 0xffff0000 | (mtu << 5) | w);
2704 incr[mtu][w] = t3_read_reg(adap, A_TP_CCTRL_TABLE) &
2710 * t3_tp_get_mib_stats - read TP's MIB counters
2711 * @adap: the adapter
2712 * @tps: holds the returned counter values
2714 * Returns the values of TP's MIB counters.
2716 void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps)
2718 t3_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_RDATA, (u32 *) tps,
2719 sizeof(*tps) / sizeof(u32), 0);
2722 #define ulp_region(adap, name, start, len) \
2723 t3_write_reg((adap), A_ULPRX_ ## name ## _LLIMIT, (start)); \
2724 t3_write_reg((adap), A_ULPRX_ ## name ## _ULIMIT, \
2725 (start) + (len) - 1); \
2728 #define ulptx_region(adap, name, start, len) \
2729 t3_write_reg((adap), A_ULPTX_ ## name ## _LLIMIT, (start)); \
2730 t3_write_reg((adap), A_ULPTX_ ## name ## _ULIMIT, \
2731 (start) + (len) - 1)
2733 static void ulp_config(struct adapter *adap, const struct tp_params *p)
2735 unsigned int m = p->chan_rx_size;
2737 ulp_region(adap, ISCSI, m, p->chan_rx_size / 8);
2738 ulp_region(adap, TDDP, m, p->chan_rx_size / 8);
2739 ulptx_region(adap, TPT, m, p->chan_rx_size / 4);
2740 ulp_region(adap, STAG, m, p->chan_rx_size / 4);
2741 ulp_region(adap, RQ, m, p->chan_rx_size / 4);
2742 ulptx_region(adap, PBL, m, p->chan_rx_size / 4);
2743 ulp_region(adap, PBL, m, p->chan_rx_size / 4);
2744 t3_write_reg(adap, A_ULPRX_TDDP_TAGMASK, 0xffffffff);
2748 * t3_set_proto_sram - set the contents of the protocol sram
2749 * @adapter: the adapter
2750 * @data: the protocol image
2752 * Write the contents of the protocol SRAM.
2754 int t3_set_proto_sram(struct adapter *adap, u8 *data)
2757 u32 *buf = (u32 *)data;
2759 for (i = 0; i < PROTO_SRAM_LINES; i++) {
2760 t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, cpu_to_be32(*buf++));
2761 t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, cpu_to_be32(*buf++));
2762 t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, cpu_to_be32(*buf++));
2763 t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, cpu_to_be32(*buf++));
2764 t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, cpu_to_be32(*buf++));
2766 t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31);
2767 if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1))
2770 t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, 0);
2775 void t3_config_trace_filter(struct adapter *adapter,
2776 const struct trace_params *tp, int filter_index,
2777 int invert, int enable)
2779 u32 addr, key[4], mask[4];
2781 key[0] = tp->sport | (tp->sip << 16);
2782 key[1] = (tp->sip >> 16) | (tp->dport << 16);
2784 key[3] = tp->proto | (tp->vlan << 8) | (tp->intf << 20);
2786 mask[0] = tp->sport_mask | (tp->sip_mask << 16);
2787 mask[1] = (tp->sip_mask >> 16) | (tp->dport_mask << 16);
2788 mask[2] = tp->dip_mask;
2789 mask[3] = tp->proto_mask | (tp->vlan_mask << 8) | (tp->intf_mask << 20);
2792 key[3] |= (1 << 29);
2794 key[3] |= (1 << 28);
2796 addr = filter_index ? A_TP_RX_TRC_KEY0 : A_TP_TX_TRC_KEY0;
2797 tp_wr_indirect(adapter, addr++, key[0]);
2798 tp_wr_indirect(adapter, addr++, mask[0]);
2799 tp_wr_indirect(adapter, addr++, key[1]);
2800 tp_wr_indirect(adapter, addr++, mask[1]);
2801 tp_wr_indirect(adapter, addr++, key[2]);
2802 tp_wr_indirect(adapter, addr++, mask[2]);
2803 tp_wr_indirect(adapter, addr++, key[3]);
2804 tp_wr_indirect(adapter, addr, mask[3]);
2805 t3_read_reg(adapter, A_TP_PIO_DATA);
2809 * t3_config_sched - configure a HW traffic scheduler
2810 * @adap: the adapter
2811 * @kbps: target rate in Kbps
2812 * @sched: the scheduler index
2814 * Configure a HW scheduler for the target rate
2816 int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched)
2818 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
2819 unsigned int clk = adap->params.vpd.cclk * 1000;
2820 unsigned int selected_cpt = 0, selected_bpt = 0;
2823 kbps *= 125; /* -> bytes */
2824 for (cpt = 1; cpt <= 255; cpt++) {
2826 bpt = (kbps + tps / 2) / tps;
2827 if (bpt > 0 && bpt <= 255) {
2829 delta = v >= kbps ? v - kbps : kbps - v;
2830 if (delta <= mindelta) {
2835 } else if (selected_cpt)
2841 t3_write_reg(adap, A_TP_TM_PIO_ADDR,
2842 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
2843 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
2845 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
2847 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
2848 t3_write_reg(adap, A_TP_TM_PIO_DATA, v);
2852 static int tp_init(struct adapter *adap, const struct tp_params *p)
2857 t3_set_vlan_accel(adap, 3, 0);
2859 if (is_offload(adap)) {
2860 tp_set_timers(adap, adap->params.vpd.cclk * 1000);
2861 t3_write_reg(adap, A_TP_RESET, F_FLSTINITENABLE);
2862 busy = t3_wait_op_done(adap, A_TP_RESET, F_FLSTINITENABLE,
2865 CH_ERR(adap, "TP initialization timed out\n");
2869 t3_write_reg(adap, A_TP_RESET, F_TPRESET);
2873 int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask)
2875 if (port_mask & ~((1 << adap->params.nports) - 1))
2877 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE | F_PORT0ACTIVE,
2878 port_mask << S_PORT0ACTIVE);
2883 * Perform the bits of HW initialization that are dependent on the number
2884 * of available ports.
2886 static void init_hw_for_avail_ports(struct adapter *adap, int nports)
2891 t3_set_reg_field(adap, A_ULPRX_CTL, F_ROUND_ROBIN, 0);
2892 t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0);
2893 t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_TPTXPORT0EN |
2894 F_PORT0ACTIVE | F_ENFORCEPKT);
2895 t3_write_reg(adap, A_PM1_TX_CFG, 0xffffffff);
2897 t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN);
2898 t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB);
2899 t3_write_reg(adap, A_ULPTX_DMA_WEIGHT,
2900 V_D1_WEIGHT(16) | V_D0_WEIGHT(16));
2901 t3_write_reg(adap, A_MPS_CFG, F_TPTXPORT0EN | F_TPTXPORT1EN |
2902 F_TPRXPORTEN | F_PORT0ACTIVE | F_PORT1ACTIVE |
2904 t3_write_reg(adap, A_PM1_TX_CFG, 0x80008000);
2905 t3_set_reg_field(adap, A_TP_PC_CONFIG, 0, F_TXTOSQUEUEMAPMODE);
2906 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
2907 V_TX_MOD_QUEUE_REQ_MAP(0xaa));
2908 for (i = 0; i < 16; i++)
2909 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE,
2910 (i << 16) | 0x1010);
2914 static int calibrate_xgm(struct adapter *adapter)
2916 if (uses_xaui(adapter)) {
2919 for (i = 0; i < 5; ++i) {
2920 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0);
2921 t3_read_reg(adapter, A_XGM_XAUI_IMP);
2923 v = t3_read_reg(adapter, A_XGM_XAUI_IMP);
2924 if (!(v & (F_XGM_CALFAULT | F_CALBUSY))) {
2925 t3_write_reg(adapter, A_XGM_XAUI_IMP,
2926 V_XAUIIMP(G_CALIMP(v) >> 2));
2930 CH_ERR(adapter, "MAC calibration failed\n");
2933 t3_write_reg(adapter, A_XGM_RGMII_IMP,
2934 V_RGMIIIMPPD(2) | V_RGMIIIMPPU(3));
2935 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
2936 F_XGM_IMPSETUPDATE);
2941 static void calibrate_xgm_t3b(struct adapter *adapter)
2943 if (!uses_xaui(adapter)) {
2944 t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET |
2945 F_CALUPDATE | V_RGMIIIMPPD(2) | V_RGMIIIMPPU(3));
2946 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALRESET, 0);
2947 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0,
2948 F_XGM_IMPSETUPDATE);
2949 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
2951 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALUPDATE, 0);
2952 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, F_CALUPDATE);
2956 struct mc7_timing_params {
2957 unsigned char ActToPreDly;
2958 unsigned char ActToRdWrDly;
2959 unsigned char PreCyc;
2960 unsigned char RefCyc[5];
2961 unsigned char BkCyc;
2962 unsigned char WrToRdDly;
2963 unsigned char RdToWrDly;
2967 * Write a value to a register and check that the write completed. These
2968 * writes normally complete in a cycle or two, so one read should suffice.
2969 * The very first read exists to flush the posted write to the device.
2971 static int wrreg_wait(struct adapter *adapter, unsigned int addr, u32 val)
2973 t3_write_reg(adapter, addr, val);
2974 t3_read_reg(adapter, addr); /* flush */
2975 if (!(t3_read_reg(adapter, addr) & F_BUSY))
2977 CH_ERR(adapter, "write to MC7 register 0x%x timed out\n", addr);
2981 static int mc7_init(struct mc7 *mc7, unsigned int mc7_clock, int mem_type)
2983 static const unsigned int mc7_mode[] = {
2984 0x632, 0x642, 0x652, 0x432, 0x442
2986 static const struct mc7_timing_params mc7_timings[] = {
2987 {12, 3, 4, {20, 28, 34, 52, 0}, 15, 6, 4},
2988 {12, 4, 5, {20, 28, 34, 52, 0}, 16, 7, 4},
2989 {12, 5, 6, {20, 28, 34, 52, 0}, 17, 8, 4},
2990 {9, 3, 4, {15, 21, 26, 39, 0}, 12, 6, 4},
2991 {9, 4, 5, {15, 21, 26, 39, 0}, 13, 7, 4}
2995 unsigned int width, density, slow, attempts;
2996 struct adapter *adapter = mc7->adapter;
2997 const struct mc7_timing_params *p = &mc7_timings[mem_type];
3002 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3003 slow = val & F_SLOW;
3004 width = G_WIDTH(val);
3005 density = G_DEN(val);
3007 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);
3008 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3012 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);
3013 t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
3015 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
3016 (F_BUSY | F_SGL_CAL_EN | F_CAL_FAULT)) {
3017 CH_ERR(adapter, "%s MC7 calibration timed out\n",
3023 t3_write_reg(adapter, mc7->offset + A_MC7_PARM,
3024 V_ACTTOPREDLY(p->ActToPreDly) |
3025 V_ACTTORDWRDLY(p->ActToRdWrDly) | V_PRECYC(p->PreCyc) |
3026 V_REFCYC(p->RefCyc[density]) | V_BKCYC(p->BkCyc) |
3027 V_WRTORDDLY(p->WrToRdDly) | V_RDTOWRDLY(p->RdToWrDly));
3029 t3_write_reg(adapter, mc7->offset + A_MC7_CFG,
3030 val | F_CLKEN | F_TERM150);
3031 t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3034 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB,
3039 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
3040 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) ||
3041 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) ||
3042 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
3046 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100);
3047 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLRST, 0);
3051 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
3052 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
3053 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
3054 wrreg_wait(adapter, mc7->offset + A_MC7_MODE,
3055 mc7_mode[mem_type]) ||
3056 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) ||
3057 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
3060 /* clock value is in KHz */
3061 mc7_clock = mc7_clock * 7812 + mc7_clock / 2; /* ns */
3062 mc7_clock /= 1000000; /* KHz->MHz, ns->us */
3064 t3_write_reg(adapter, mc7->offset + A_MC7_REF,
3065 F_PERREFEN | V_PREREFDIV(mc7_clock));
3066 t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */
3068 t3_write_reg(adapter, mc7->offset + A_MC7_ECC, F_ECCGENEN | F_ECCCHKEN);
3069 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0);
3070 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0);
3071 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END,
3072 (mc7->size << width) - 1);
3073 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1));
3074 t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */
3079 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
3080 } while ((val & F_BUSY) && --attempts);
3082 CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name);
3086 /* Enable normal memory accesses. */
3087 t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY);
3094 static void config_pcie(struct adapter *adap)
3096 static const u16 ack_lat[4][6] = {
3097 {237, 416, 559, 1071, 2095, 4143},
3098 {128, 217, 289, 545, 1057, 2081},
3099 {73, 118, 154, 282, 538, 1050},
3100 {67, 107, 86, 150, 278, 534}
3102 static const u16 rpl_tmr[4][6] = {
3103 {711, 1248, 1677, 3213, 6285, 12429},
3104 {384, 651, 867, 1635, 3171, 6243},
3105 {219, 354, 462, 846, 1614, 3150},
3106 {201, 321, 258, 450, 834, 1602}
3110 unsigned int log2_width, pldsize;
3111 unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt;
3113 pci_read_config_word(adap->pdev,
3114 adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL,
3116 pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
3117 pci_read_config_word(adap->pdev,
3118 adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL,
3121 fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));
3122 fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx :
3123 G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));
3124 log2_width = fls(adap->params.pci.width) - 1;
3125 acklat = ack_lat[log2_width][pldsize];
3126 if (val & 1) /* check LOsEnable */
3127 acklat += fst_trn_tx * 4;
3128 rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4;
3130 if (adap->params.rev == 0)
3131 t3_set_reg_field(adap, A_PCIE_PEX_CTRL1,
3132 V_T3A_ACKLAT(M_T3A_ACKLAT),
3133 V_T3A_ACKLAT(acklat));
3135 t3_set_reg_field(adap, A_PCIE_PEX_CTRL1, V_ACKLAT(M_ACKLAT),
3138 t3_set_reg_field(adap, A_PCIE_PEX_CTRL0, V_REPLAYLMT(M_REPLAYLMT),
3139 V_REPLAYLMT(rpllmt));
3141 t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff);
3142 t3_set_reg_field(adap, A_PCIE_CFG, F_PCIE_CLIDECEN, F_PCIE_CLIDECEN);
3146 * Initialize and configure T3 HW modules. This performs the
3147 * initialization steps that need to be done once after a card is reset.
3148 * MAC and PHY initialization is handled separarely whenever a port is enabled.
3150 * fw_params are passed to FW and their value is platform dependent. Only the
3151 * top 8 bits are available for use, the rest must be 0.
3153 int t3_init_hw(struct adapter *adapter, u32 fw_params)
3155 int err = -EIO, attempts = 100;
3156 const struct vpd_params *vpd = &adapter->params.vpd;
3158 if (adapter->params.rev > 0)
3159 calibrate_xgm_t3b(adapter);
3160 else if (calibrate_xgm(adapter))
3164 partition_mem(adapter, &adapter->params.tp);
3166 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) ||
3167 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) ||
3168 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) ||
3169 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers,
3170 adapter->params.mc5.nfilters,
3171 adapter->params.mc5.nroutes))
3175 if (tp_init(adapter, &adapter->params.tp))
3178 t3_tp_set_coalescing_size(adapter,
3179 min(adapter->params.sge.max_pkt_size,
3180 MAX_RX_COALESCING_LEN), 1);
3181 t3_tp_set_max_rxsize(adapter,
3182 min(adapter->params.sge.max_pkt_size, 16384U));
3183 ulp_config(adapter, &adapter->params.tp);
3185 if (is_pcie(adapter))
3186 config_pcie(adapter);
3188 t3_set_reg_field(adapter, A_PCIX_CFG, 0, F_CLIDECEN);
3190 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
3191 init_hw_for_avail_ports(adapter, adapter->params.nports);
3192 t3_sge_init(adapter, &adapter->params.sge);
3194 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3195 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3196 V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2));
3197 t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
3199 do { /* wait for uP to initialize */
3201 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
3203 CH_ERR(adapter, "uP initialization timed out\n");
3213 * get_pci_mode - determine a card's PCI mode
3214 * @adapter: the adapter
3215 * @p: where to store the PCI settings
3217 * Determines a card's PCI mode and associated parameters, such as speed
3220 static void __devinit get_pci_mode(struct adapter *adapter,
3221 struct pci_params *p)
3223 static unsigned short speed_map[] = { 33, 66, 100, 133 };
3224 u32 pci_mode, pcie_cap;
3226 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
3230 p->variant = PCI_VARIANT_PCIE;
3231 p->pcie_cap_addr = pcie_cap;
3232 pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA,
3234 p->width = (val >> 4) & 0x3f;
3238 pci_mode = t3_read_reg(adapter, A_PCIX_MODE);
3239 p->speed = speed_map[G_PCLKRANGE(pci_mode)];
3240 p->width = (pci_mode & F_64BIT) ? 64 : 32;
3241 pci_mode = G_PCIXINITPAT(pci_mode);
3243 p->variant = PCI_VARIANT_PCI;
3244 else if (pci_mode < 4)
3245 p->variant = PCI_VARIANT_PCIX_MODE1_PARITY;
3246 else if (pci_mode < 8)
3247 p->variant = PCI_VARIANT_PCIX_MODE1_ECC;
3249 p->variant = PCI_VARIANT_PCIX_266_MODE2;
3253 * init_link_config - initialize a link's SW state
3254 * @lc: structure holding the link state
3255 * @ai: information about the current card
3257 * Initializes the SW state maintained for each link, including the link's
3258 * capabilities and default speed/duplex/flow-control/autonegotiation
3261 static void __devinit init_link_config(struct link_config *lc,
3264 lc->supported = caps;
3265 lc->requested_speed = lc->speed = SPEED_INVALID;
3266 lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
3267 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
3268 if (lc->supported & SUPPORTED_Autoneg) {
3269 lc->advertising = lc->supported;
3270 lc->autoneg = AUTONEG_ENABLE;
3271 lc->requested_fc |= PAUSE_AUTONEG;
3273 lc->advertising = 0;
3274 lc->autoneg = AUTONEG_DISABLE;
3279 * mc7_calc_size - calculate MC7 memory size
3280 * @cfg: the MC7 configuration
3282 * Calculates the size of an MC7 memory in bytes from the value of its
3283 * configuration register.
3285 static unsigned int __devinit mc7_calc_size(u32 cfg)
3287 unsigned int width = G_WIDTH(cfg);
3288 unsigned int banks = !!(cfg & F_BKS) + 1;
3289 unsigned int org = !!(cfg & F_ORG) + 1;
3290 unsigned int density = G_DEN(cfg);
3291 unsigned int MBs = ((256 << density) * banks) / (org << width);
3296 static void __devinit mc7_prep(struct adapter *adapter, struct mc7 *mc7,
3297 unsigned int base_addr, const char *name)
3301 mc7->adapter = adapter;
3303 mc7->offset = base_addr - MC7_PMRX_BASE_ADDR;
3304 cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3305 mc7->size = mc7->size = G_DEN(cfg) == M_DEN ? 0 : mc7_calc_size(cfg);
3306 mc7->width = G_WIDTH(cfg);
3309 void mac_prep(struct cmac *mac, struct adapter *adapter, int index)
3311 mac->adapter = adapter;
3312 mac->offset = (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR) * index;
3315 if (adapter->params.rev == 0 && uses_xaui(adapter)) {
3316 t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset,
3317 is_10G(adapter) ? 0x2901c04 : 0x2301c04);
3318 t3_set_reg_field(adapter, A_XGM_PORT_CFG + mac->offset,
3323 void early_hw_init(struct adapter *adapter, const struct adapter_info *ai)
3325 u32 val = V_PORTSPEED(is_10G(adapter) ? 3 : 2);
3327 mi1_init(adapter, ai);
3328 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */
3329 V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1));
3330 t3_write_reg(adapter, A_T3DBG_GPIO_EN,
3331 ai->gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL);
3332 t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0);
3334 if (adapter->params.rev == 0 || !uses_xaui(adapter))
3337 /* Enable MAC clocks so we can access the registers */
3338 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3339 t3_read_reg(adapter, A_XGM_PORT_CFG);
3341 val |= F_CLKDIVRESET_;
3342 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3343 t3_read_reg(adapter, A_XGM_PORT_CFG);
3344 t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val);
3345 t3_read_reg(adapter, A_XGM_PORT_CFG);
3349 * Reset the adapter.
3350 * Older PCIe cards lose their config space during reset, PCI-X
3353 int t3_reset_adapter(struct adapter *adapter)
3355 int i, save_and_restore_pcie =
3356 adapter->params.rev < T3_REV_B2 && is_pcie(adapter);
3359 if (save_and_restore_pcie)
3360 pci_save_state(adapter->pdev);
3361 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE);
3364 * Delay. Give Some time to device to reset fully.
3365 * XXX The delay time should be modified.
3367 for (i = 0; i < 10; i++) {
3369 pci_read_config_word(adapter->pdev, 0x00, &devid);
3370 if (devid == 0x1425)
3374 if (devid != 0x1425)
3377 if (save_and_restore_pcie)
3378 pci_restore_state(adapter->pdev);
3383 * Initialize adapter SW state for the various HW modules, set initial values
3384 * for some adapter tunables, take PHYs out of reset, and initialize the MDIO
3387 int __devinit t3_prep_adapter(struct adapter *adapter,
3388 const struct adapter_info *ai, int reset)
3391 unsigned int i, j = 0;
3393 get_pci_mode(adapter, &adapter->params.pci);
3395 adapter->params.info = ai;
3396 adapter->params.nports = ai->nports;
3397 adapter->params.rev = t3_read_reg(adapter, A_PL_REV);
3398 adapter->params.linkpoll_period = 0;
3399 adapter->params.stats_update_period = is_10G(adapter) ?
3400 MAC_STATS_ACCUM_SECS : (MAC_STATS_ACCUM_SECS * 10);
3401 adapter->params.pci.vpd_cap_addr =
3402 pci_find_capability(adapter->pdev, PCI_CAP_ID_VPD);
3403 ret = get_vpd_params(adapter, &adapter->params.vpd);
3407 if (reset && t3_reset_adapter(adapter))
3410 t3_sge_prep(adapter, &adapter->params.sge);
3412 if (adapter->params.vpd.mclk) {
3413 struct tp_params *p = &adapter->params.tp;
3415 mc7_prep(adapter, &adapter->pmrx, MC7_PMRX_BASE_ADDR, "PMRX");
3416 mc7_prep(adapter, &adapter->pmtx, MC7_PMTX_BASE_ADDR, "PMTX");
3417 mc7_prep(adapter, &adapter->cm, MC7_CM_BASE_ADDR, "CM");
3419 p->nchan = ai->nports;
3420 p->pmrx_size = t3_mc7_size(&adapter->pmrx);
3421 p->pmtx_size = t3_mc7_size(&adapter->pmtx);
3422 p->cm_size = t3_mc7_size(&adapter->cm);
3423 p->chan_rx_size = p->pmrx_size / 2; /* only 1 Rx channel */
3424 p->chan_tx_size = p->pmtx_size / p->nchan;
3425 p->rx_pg_size = 64 * 1024;
3426 p->tx_pg_size = is_10G(adapter) ? 64 * 1024 : 16 * 1024;
3427 p->rx_num_pgs = pm_num_pages(p->chan_rx_size, p->rx_pg_size);
3428 p->tx_num_pgs = pm_num_pages(p->chan_tx_size, p->tx_pg_size);
3429 p->ntimer_qs = p->cm_size >= (128 << 20) ||
3430 adapter->params.rev > 0 ? 12 : 6;
3433 adapter->params.offload = t3_mc7_size(&adapter->pmrx) &&
3434 t3_mc7_size(&adapter->pmtx) &&
3435 t3_mc7_size(&adapter->cm);
3437 if (is_offload(adapter)) {
3438 adapter->params.mc5.nservers = DEFAULT_NSERVERS;
3439 adapter->params.mc5.nfilters = adapter->params.rev > 0 ?
3440 DEFAULT_NFILTERS : 0;
3441 adapter->params.mc5.nroutes = 0;
3442 t3_mc5_prep(adapter, &adapter->mc5, MC5_MODE_144_BIT);
3444 init_mtus(adapter->params.mtus);
3445 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3448 early_hw_init(adapter, ai);
3450 for_each_port(adapter, i) {
3452 struct port_info *p = adap2pinfo(adapter, i);
3454 while (!adapter->params.vpd.port_type[j])
3457 p->port_type = &port_types[adapter->params.vpd.port_type[j]];
3458 p->port_type->phy_prep(&p->phy, adapter, ai->phy_base_addr + j,
3460 mac_prep(&p->mac, adapter, j);
3464 * The VPD EEPROM stores the base Ethernet address for the
3465 * card. A port's address is derived from the base by adding
3466 * the port's index to the base's low octet.
3468 memcpy(hw_addr, adapter->params.vpd.eth_base, 5);
3469 hw_addr[5] = adapter->params.vpd.eth_base[5] + i;
3471 memcpy(adapter->port[i]->dev_addr, hw_addr,
3473 memcpy(adapter->port[i]->perm_addr, hw_addr,
3475 init_link_config(&p->link_config, p->port_type->caps);
3476 p->phy.ops->power_down(&p->phy, 1);
3477 if (!(p->port_type->caps & SUPPORTED_IRQ))
3478 adapter->params.linkpoll_period = 10;
3484 void t3_led_ready(struct adapter *adapter)
3486 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,