IB/ipath: Make ipath_portdata work with struct pid * not pid_t
[linux-2.6] / drivers / char / drm / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "i915_drm.h"
32 #include "i915_drv.h"
33
34 /* Really want an OS-independent resettable timer.  Would like to have
35  * this loop run for (eg) 3 sec, but have the timer reset every time
36  * the head pointer changes, so that EBUSY only happens if the ring
37  * actually stalls for (eg) 3 seconds.
38  */
39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
40 {
41         drm_i915_private_t *dev_priv = dev->dev_private;
42         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
43         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
44         int i;
45
46         for (i = 0; i < 10000; i++) {
47                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
48                 ring->space = ring->head - (ring->tail + 8);
49                 if (ring->space < 0)
50                         ring->space += ring->Size;
51                 if (ring->space >= n)
52                         return 0;
53
54                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
55
56                 if (ring->head != last_head)
57                         i = 0;
58
59                 last_head = ring->head;
60         }
61
62         return -EBUSY;
63 }
64
65 void i915_kernel_lost_context(struct drm_device * dev)
66 {
67         drm_i915_private_t *dev_priv = dev->dev_private;
68         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
69
70         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
71         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
72         ring->space = ring->head - (ring->tail + 8);
73         if (ring->space < 0)
74                 ring->space += ring->Size;
75
76         if (ring->head == ring->tail)
77                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
78 }
79
80 static int i915_dma_cleanup(struct drm_device * dev)
81 {
82         drm_i915_private_t *dev_priv = dev->dev_private;
83         /* Make sure interrupts are disabled here because the uninstall ioctl
84          * may not have been called from userspace and after dev_private
85          * is freed, it's too late.
86          */
87         if (dev->irq)
88                 drm_irq_uninstall(dev);
89
90         if (dev_priv->ring.virtual_start) {
91                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
92                 dev_priv->ring.virtual_start = 0;
93                 dev_priv->ring.map.handle = 0;
94                 dev_priv->ring.map.size = 0;
95         }
96
97         if (dev_priv->status_page_dmah) {
98                 drm_pci_free(dev, dev_priv->status_page_dmah);
99                 dev_priv->status_page_dmah = NULL;
100                 /* Need to rewrite hardware status page */
101                 I915_WRITE(0x02080, 0x1ffff000);
102         }
103
104         if (dev_priv->status_gfx_addr) {
105                 dev_priv->status_gfx_addr = 0;
106                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
107                 I915_WRITE(0x2080, 0x1ffff000);
108         }
109
110         return 0;
111 }
112
113 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
114 {
115         drm_i915_private_t *dev_priv = dev->dev_private;
116
117         dev_priv->sarea = drm_getsarea(dev);
118         if (!dev_priv->sarea) {
119                 DRM_ERROR("can not find sarea!\n");
120                 i915_dma_cleanup(dev);
121                 return -EINVAL;
122         }
123
124         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
125         if (!dev_priv->mmio_map) {
126                 i915_dma_cleanup(dev);
127                 DRM_ERROR("can not find mmio map!\n");
128                 return -EINVAL;
129         }
130
131         dev_priv->sarea_priv = (drm_i915_sarea_t *)
132             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
133
134         dev_priv->ring.Start = init->ring_start;
135         dev_priv->ring.End = init->ring_end;
136         dev_priv->ring.Size = init->ring_size;
137         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
138
139         dev_priv->ring.map.offset = init->ring_start;
140         dev_priv->ring.map.size = init->ring_size;
141         dev_priv->ring.map.type = 0;
142         dev_priv->ring.map.flags = 0;
143         dev_priv->ring.map.mtrr = 0;
144
145         drm_core_ioremap(&dev_priv->ring.map, dev);
146
147         if (dev_priv->ring.map.handle == NULL) {
148                 i915_dma_cleanup(dev);
149                 DRM_ERROR("can not ioremap virtual address for"
150                           " ring buffer\n");
151                 return -ENOMEM;
152         }
153
154         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
155
156         dev_priv->cpp = init->cpp;
157         dev_priv->back_offset = init->back_offset;
158         dev_priv->front_offset = init->front_offset;
159         dev_priv->current_page = 0;
160         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
161
162         /* We are using separate values as placeholders for mechanisms for
163          * private backbuffer/depthbuffer usage.
164          */
165         dev_priv->use_mi_batchbuffer_start = 0;
166         if (IS_I965G(dev)) /* 965 doesn't support older method */
167                 dev_priv->use_mi_batchbuffer_start = 1;
168
169         /* Allow hardware batchbuffers unless told otherwise.
170          */
171         dev_priv->allow_batchbuffer = 1;
172
173         /* Program Hardware Status Page */
174         if (!I915_NEED_GFX_HWS(dev)) {
175                 dev_priv->status_page_dmah =
176                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
177
178                 if (!dev_priv->status_page_dmah) {
179                         i915_dma_cleanup(dev);
180                         DRM_ERROR("Can not allocate hardware status page\n");
181                         return -ENOMEM;
182                 }
183                 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
184                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
185
186                 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
187                 I915_WRITE(0x02080, dev_priv->dma_status_page);
188         }
189         DRM_DEBUG("Enabled hardware status page\n");
190         return 0;
191 }
192
193 static int i915_dma_resume(struct drm_device * dev)
194 {
195         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
196
197         DRM_DEBUG("%s\n", __func__);
198
199         if (!dev_priv->sarea) {
200                 DRM_ERROR("can not find sarea!\n");
201                 return -EINVAL;
202         }
203
204         if (!dev_priv->mmio_map) {
205                 DRM_ERROR("can not find mmio map!\n");
206                 return -EINVAL;
207         }
208
209         if (dev_priv->ring.map.handle == NULL) {
210                 DRM_ERROR("can not ioremap virtual address for"
211                           " ring buffer\n");
212                 return -ENOMEM;
213         }
214
215         /* Program Hardware Status Page */
216         if (!dev_priv->hw_status_page) {
217                 DRM_ERROR("Can not find hardware status page\n");
218                 return -EINVAL;
219         }
220         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
221
222         if (dev_priv->status_gfx_addr != 0)
223                 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
224         else
225                 I915_WRITE(0x02080, dev_priv->dma_status_page);
226         DRM_DEBUG("Enabled hardware status page\n");
227
228         return 0;
229 }
230
231 static int i915_dma_init(struct drm_device *dev, void *data,
232                          struct drm_file *file_priv)
233 {
234         drm_i915_init_t *init = data;
235         int retcode = 0;
236
237         switch (init->func) {
238         case I915_INIT_DMA:
239                 retcode = i915_initialize(dev, init);
240                 break;
241         case I915_CLEANUP_DMA:
242                 retcode = i915_dma_cleanup(dev);
243                 break;
244         case I915_RESUME_DMA:
245                 retcode = i915_dma_resume(dev);
246                 break;
247         default:
248                 retcode = -EINVAL;
249                 break;
250         }
251
252         return retcode;
253 }
254
255 /* Implement basically the same security restrictions as hardware does
256  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
257  *
258  * Most of the calculations below involve calculating the size of a
259  * particular instruction.  It's important to get the size right as
260  * that tells us where the next instruction to check is.  Any illegal
261  * instruction detected will be given a size of zero, which is a
262  * signal to abort the rest of the buffer.
263  */
264 static int do_validate_cmd(int cmd)
265 {
266         switch (((cmd >> 29) & 0x7)) {
267         case 0x0:
268                 switch ((cmd >> 23) & 0x3f) {
269                 case 0x0:
270                         return 1;       /* MI_NOOP */
271                 case 0x4:
272                         return 1;       /* MI_FLUSH */
273                 default:
274                         return 0;       /* disallow everything else */
275                 }
276                 break;
277         case 0x1:
278                 return 0;       /* reserved */
279         case 0x2:
280                 return (cmd & 0xff) + 2;        /* 2d commands */
281         case 0x3:
282                 if (((cmd >> 24) & 0x1f) <= 0x18)
283                         return 1;
284
285                 switch ((cmd >> 24) & 0x1f) {
286                 case 0x1c:
287                         return 1;
288                 case 0x1d:
289                         switch ((cmd >> 16) & 0xff) {
290                         case 0x3:
291                                 return (cmd & 0x1f) + 2;
292                         case 0x4:
293                                 return (cmd & 0xf) + 2;
294                         default:
295                                 return (cmd & 0xffff) + 2;
296                         }
297                 case 0x1e:
298                         if (cmd & (1 << 23))
299                                 return (cmd & 0xffff) + 1;
300                         else
301                                 return 1;
302                 case 0x1f:
303                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
304                                 return (cmd & 0x1ffff) + 2;
305                         else if (cmd & (1 << 17))       /* indirect random */
306                                 if ((cmd & 0xffff) == 0)
307                                         return 0;       /* unknown length, too hard */
308                                 else
309                                         return (((cmd & 0xffff) + 1) / 2) + 1;
310                         else
311                                 return 2;       /* indirect sequential */
312                 default:
313                         return 0;
314                 }
315         default:
316                 return 0;
317         }
318
319         return 0;
320 }
321
322 static int validate_cmd(int cmd)
323 {
324         int ret = do_validate_cmd(cmd);
325
326 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
327
328         return ret;
329 }
330
331 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords)
332 {
333         drm_i915_private_t *dev_priv = dev->dev_private;
334         int i;
335         RING_LOCALS;
336
337         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
338                 return -EINVAL;
339
340         BEGIN_LP_RING((dwords+1)&~1);
341
342         for (i = 0; i < dwords;) {
343                 int cmd, sz;
344
345                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
346                         return -EINVAL;
347
348                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
349                         return -EINVAL;
350
351                 OUT_RING(cmd);
352
353                 while (++i, --sz) {
354                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
355                                                          sizeof(cmd))) {
356                                 return -EINVAL;
357                         }
358                         OUT_RING(cmd);
359                 }
360         }
361
362         if (dwords & 1)
363                 OUT_RING(0);
364
365         ADVANCE_LP_RING();
366
367         return 0;
368 }
369
370 static int i915_emit_box(struct drm_device * dev,
371                          struct drm_clip_rect __user * boxes,
372                          int i, int DR1, int DR4)
373 {
374         drm_i915_private_t *dev_priv = dev->dev_private;
375         struct drm_clip_rect box;
376         RING_LOCALS;
377
378         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
379                 return -EFAULT;
380         }
381
382         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
383                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
384                           box.x1, box.y1, box.x2, box.y2);
385                 return -EINVAL;
386         }
387
388         if (IS_I965G(dev)) {
389                 BEGIN_LP_RING(4);
390                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
391                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
392                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
393                 OUT_RING(DR4);
394                 ADVANCE_LP_RING();
395         } else {
396                 BEGIN_LP_RING(6);
397                 OUT_RING(GFX_OP_DRAWRECT_INFO);
398                 OUT_RING(DR1);
399                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
400                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
401                 OUT_RING(DR4);
402                 OUT_RING(0);
403                 ADVANCE_LP_RING();
404         }
405
406         return 0;
407 }
408
409 /* XXX: Emitting the counter should really be moved to part of the IRQ
410  * emit. For now, do it in both places:
411  */
412
413 static void i915_emit_breadcrumb(struct drm_device *dev)
414 {
415         drm_i915_private_t *dev_priv = dev->dev_private;
416         RING_LOCALS;
417
418         if (++dev_priv->counter > BREADCRUMB_MASK) {
419                  dev_priv->counter = 1;
420                  DRM_DEBUG("Breadcrumb counter wrapped around\n");
421         }
422
423         if (dev_priv->sarea_priv)
424                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
425
426         BEGIN_LP_RING(4);
427         OUT_RING(CMD_STORE_DWORD_IDX);
428         OUT_RING(20);
429         OUT_RING(dev_priv->counter);
430         OUT_RING(0);
431         ADVANCE_LP_RING();
432 }
433
434 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
435 {
436         drm_i915_private_t *dev_priv = dev->dev_private;
437         uint32_t flush_cmd = CMD_MI_FLUSH;
438         RING_LOCALS;
439
440         flush_cmd |= flush;
441
442         i915_kernel_lost_context(dev);
443
444         BEGIN_LP_RING(4);
445         OUT_RING(flush_cmd);
446         OUT_RING(0);
447         OUT_RING(0);
448         OUT_RING(0);
449         ADVANCE_LP_RING();
450
451         return 0;
452 }
453
454 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
455                                    drm_i915_cmdbuffer_t * cmd)
456 {
457         int nbox = cmd->num_cliprects;
458         int i = 0, count, ret;
459
460         if (cmd->sz & 0x3) {
461                 DRM_ERROR("alignment");
462                 return -EINVAL;
463         }
464
465         i915_kernel_lost_context(dev);
466
467         count = nbox ? nbox : 1;
468
469         for (i = 0; i < count; i++) {
470                 if (i < nbox) {
471                         ret = i915_emit_box(dev, cmd->cliprects, i,
472                                             cmd->DR1, cmd->DR4);
473                         if (ret)
474                                 return ret;
475                 }
476
477                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
478                 if (ret)
479                         return ret;
480         }
481
482         i915_emit_breadcrumb(dev);
483         return 0;
484 }
485
486 static int i915_dispatch_batchbuffer(struct drm_device * dev,
487                                      drm_i915_batchbuffer_t * batch)
488 {
489         drm_i915_private_t *dev_priv = dev->dev_private;
490         struct drm_clip_rect __user *boxes = batch->cliprects;
491         int nbox = batch->num_cliprects;
492         int i = 0, count;
493         RING_LOCALS;
494
495         if ((batch->start | batch->used) & 0x7) {
496                 DRM_ERROR("alignment");
497                 return -EINVAL;
498         }
499
500         i915_kernel_lost_context(dev);
501
502         count = nbox ? nbox : 1;
503
504         for (i = 0; i < count; i++) {
505                 if (i < nbox) {
506                         int ret = i915_emit_box(dev, boxes, i,
507                                                 batch->DR1, batch->DR4);
508                         if (ret)
509                                 return ret;
510                 }
511
512                 if (dev_priv->use_mi_batchbuffer_start) {
513                         BEGIN_LP_RING(2);
514                         if (IS_I965G(dev)) {
515                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
516                                 OUT_RING(batch->start);
517                         } else {
518                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
519                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
520                         }
521                         ADVANCE_LP_RING();
522                 } else {
523                         BEGIN_LP_RING(4);
524                         OUT_RING(MI_BATCH_BUFFER);
525                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
526                         OUT_RING(batch->start + batch->used - 4);
527                         OUT_RING(0);
528                         ADVANCE_LP_RING();
529                 }
530         }
531
532         i915_emit_breadcrumb(dev);
533
534         return 0;
535 }
536
537 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
538 {
539         drm_i915_private_t *dev_priv = dev->dev_private;
540         u32 num_pages, current_page, next_page, dspbase;
541         int shift = 2 * plane, x, y;
542         RING_LOCALS;
543
544         /* Calculate display base offset */
545         num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
546         current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
547         next_page = (current_page + 1) % num_pages;
548
549         switch (next_page) {
550         default:
551         case 0:
552                 dspbase = dev_priv->sarea_priv->front_offset;
553                 break;
554         case 1:
555                 dspbase = dev_priv->sarea_priv->back_offset;
556                 break;
557         case 2:
558                 dspbase = dev_priv->sarea_priv->third_offset;
559                 break;
560         }
561
562         if (plane == 0) {
563                 x = dev_priv->sarea_priv->planeA_x;
564                 y = dev_priv->sarea_priv->planeA_y;
565         } else {
566                 x = dev_priv->sarea_priv->planeB_x;
567                 y = dev_priv->sarea_priv->planeB_y;
568         }
569
570         dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
571
572         DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
573                   dspbase);
574
575         BEGIN_LP_RING(4);
576         OUT_RING(sync ? 0 :
577                  (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
578                                        MI_WAIT_FOR_PLANE_A_FLIP)));
579         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
580                  (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
581         OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
582         OUT_RING(dspbase);
583         ADVANCE_LP_RING();
584
585         dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
586         dev_priv->sarea_priv->pf_current_page |= next_page << shift;
587 }
588
589 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
590 {
591         drm_i915_private_t *dev_priv = dev->dev_private;
592         int i;
593
594         DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
595                   planes, dev_priv->sarea_priv->pf_current_page);
596
597         i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
598
599         for (i = 0; i < 2; i++)
600                 if (planes & (1 << i))
601                         i915_do_dispatch_flip(dev, i, sync);
602
603         i915_emit_breadcrumb(dev);
604
605 }
606
607 static int i915_quiescent(struct drm_device * dev)
608 {
609         drm_i915_private_t *dev_priv = dev->dev_private;
610
611         i915_kernel_lost_context(dev);
612         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
613 }
614
615 static int i915_flush_ioctl(struct drm_device *dev, void *data,
616                             struct drm_file *file_priv)
617 {
618         LOCK_TEST_WITH_RETURN(dev, file_priv);
619
620         return i915_quiescent(dev);
621 }
622
623 static int i915_batchbuffer(struct drm_device *dev, void *data,
624                             struct drm_file *file_priv)
625 {
626         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
627         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
628             dev_priv->sarea_priv;
629         drm_i915_batchbuffer_t *batch = data;
630         int ret;
631
632         if (!dev_priv->allow_batchbuffer) {
633                 DRM_ERROR("Batchbuffer ioctl disabled\n");
634                 return -EINVAL;
635         }
636
637         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
638                   batch->start, batch->used, batch->num_cliprects);
639
640         LOCK_TEST_WITH_RETURN(dev, file_priv);
641
642         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
643                                                        batch->num_cliprects *
644                                                        sizeof(struct drm_clip_rect)))
645                 return -EFAULT;
646
647         ret = i915_dispatch_batchbuffer(dev, batch);
648
649         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
650         return ret;
651 }
652
653 static int i915_cmdbuffer(struct drm_device *dev, void *data,
654                           struct drm_file *file_priv)
655 {
656         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
657         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
658             dev_priv->sarea_priv;
659         drm_i915_cmdbuffer_t *cmdbuf = data;
660         int ret;
661
662         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
663                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
664
665         LOCK_TEST_WITH_RETURN(dev, file_priv);
666
667         if (cmdbuf->num_cliprects &&
668             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
669                                 cmdbuf->num_cliprects *
670                                 sizeof(struct drm_clip_rect))) {
671                 DRM_ERROR("Fault accessing cliprects\n");
672                 return -EFAULT;
673         }
674
675         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
676         if (ret) {
677                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
678                 return ret;
679         }
680
681         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
682         return 0;
683 }
684
685 static int i915_do_cleanup_pageflip(struct drm_device * dev)
686 {
687         drm_i915_private_t *dev_priv = dev->dev_private;
688         int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
689
690         DRM_DEBUG("\n");
691
692         for (i = 0, planes = 0; i < 2; i++)
693                 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
694                         dev_priv->sarea_priv->pf_current_page =
695                                 (dev_priv->sarea_priv->pf_current_page &
696                                  ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
697
698                         planes |= 1 << i;
699                 }
700
701         if (planes)
702                 i915_dispatch_flip(dev, planes, 0);
703
704         return 0;
705 }
706
707 static int i915_flip_bufs(struct drm_device *dev, void *data,
708                           struct drm_file *file_priv)
709 {
710         drm_i915_flip_t *param = data;
711
712         DRM_DEBUG("\n");
713
714         LOCK_TEST_WITH_RETURN(dev, file_priv);
715
716         /* This is really planes */
717         if (param->pipes & ~0x3) {
718                 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
719                           param->pipes);
720                 return -EINVAL;
721         }
722
723         i915_dispatch_flip(dev, param->pipes, 0);
724
725         return 0;
726 }
727
728 static int i915_getparam(struct drm_device *dev, void *data,
729                          struct drm_file *file_priv)
730 {
731         drm_i915_private_t *dev_priv = dev->dev_private;
732         drm_i915_getparam_t *param = data;
733         int value;
734
735         if (!dev_priv) {
736                 DRM_ERROR("called with no initialization\n");
737                 return -EINVAL;
738         }
739
740         switch (param->param) {
741         case I915_PARAM_IRQ_ACTIVE:
742                 value = dev->irq ? 1 : 0;
743                 break;
744         case I915_PARAM_ALLOW_BATCHBUFFER:
745                 value = dev_priv->allow_batchbuffer ? 1 : 0;
746                 break;
747         case I915_PARAM_LAST_DISPATCH:
748                 value = READ_BREADCRUMB(dev_priv);
749                 break;
750         default:
751                 DRM_ERROR("Unknown parameter %d\n", param->param);
752                 return -EINVAL;
753         }
754
755         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
756                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
757                 return -EFAULT;
758         }
759
760         return 0;
761 }
762
763 static int i915_setparam(struct drm_device *dev, void *data,
764                          struct drm_file *file_priv)
765 {
766         drm_i915_private_t *dev_priv = dev->dev_private;
767         drm_i915_setparam_t *param = data;
768
769         if (!dev_priv) {
770                 DRM_ERROR("called with no initialization\n");
771                 return -EINVAL;
772         }
773
774         switch (param->param) {
775         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
776                 if (!IS_I965G(dev))
777                         dev_priv->use_mi_batchbuffer_start = param->value;
778                 break;
779         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
780                 dev_priv->tex_lru_log_granularity = param->value;
781                 break;
782         case I915_SETPARAM_ALLOW_BATCHBUFFER:
783                 dev_priv->allow_batchbuffer = param->value;
784                 break;
785         default:
786                 DRM_ERROR("unknown parameter %d\n", param->param);
787                 return -EINVAL;
788         }
789
790         return 0;
791 }
792
793 static int i915_set_status_page(struct drm_device *dev, void *data,
794                                 struct drm_file *file_priv)
795 {
796         drm_i915_private_t *dev_priv = dev->dev_private;
797         drm_i915_hws_addr_t *hws = data;
798
799         if (!I915_NEED_GFX_HWS(dev))
800                 return -EINVAL;
801
802         if (!dev_priv) {
803                 DRM_ERROR("called with no initialization\n");
804                 return -EINVAL;
805         }
806
807         printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr);
808
809         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
810
811         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
812         dev_priv->hws_map.size = 4*1024;
813         dev_priv->hws_map.type = 0;
814         dev_priv->hws_map.flags = 0;
815         dev_priv->hws_map.mtrr = 0;
816
817         drm_core_ioremap(&dev_priv->hws_map, dev);
818         if (dev_priv->hws_map.handle == NULL) {
819                 i915_dma_cleanup(dev);
820                 dev_priv->status_gfx_addr = 0;
821                 DRM_ERROR("can not ioremap virtual address for"
822                                 " G33 hw status page\n");
823                 return -ENOMEM;
824         }
825         dev_priv->hw_status_page = dev_priv->hws_map.handle;
826
827         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
828         I915_WRITE(0x02080, dev_priv->status_gfx_addr);
829         DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
830                         dev_priv->status_gfx_addr);
831         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
832         return 0;
833 }
834
835 int i915_driver_load(struct drm_device *dev, unsigned long flags)
836 {
837         struct drm_i915_private *dev_priv = dev->dev_private;
838         unsigned long base, size;
839         int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
840
841         /* i915 has 4 more counters */
842         dev->counters += 4;
843         dev->types[6] = _DRM_STAT_IRQ;
844         dev->types[7] = _DRM_STAT_PRIMARY;
845         dev->types[8] = _DRM_STAT_SECONDARY;
846         dev->types[9] = _DRM_STAT_DMA;
847
848         dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
849         if (dev_priv == NULL)
850                 return -ENOMEM;
851
852         memset(dev_priv, 0, sizeof(drm_i915_private_t));
853
854         dev->dev_private = (void *)dev_priv;
855
856         /* Add register map (needed for suspend/resume) */
857         base = drm_get_resource_start(dev, mmio_bar);
858         size = drm_get_resource_len(dev, mmio_bar);
859
860         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
861                          _DRM_KERNEL | _DRM_DRIVER,
862                          &dev_priv->mmio_map);
863         return ret;
864 }
865
866 int i915_driver_unload(struct drm_device *dev)
867 {
868         struct drm_i915_private *dev_priv = dev->dev_private;
869
870         if (dev_priv->mmio_map)
871                 drm_rmmap(dev, dev_priv->mmio_map);
872
873         drm_free(dev->dev_private, sizeof(drm_i915_private_t),
874                  DRM_MEM_DRIVER);
875
876         return 0;
877 }
878
879 void i915_driver_lastclose(struct drm_device * dev)
880 {
881         drm_i915_private_t *dev_priv = dev->dev_private;
882
883         if (!dev_priv)
884                 return;
885
886         if (drm_getsarea(dev) && dev_priv->sarea_priv)
887                 i915_do_cleanup_pageflip(dev);
888         if (dev_priv->agp_heap)
889                 i915_mem_takedown(&(dev_priv->agp_heap));
890
891         i915_dma_cleanup(dev);
892 }
893
894 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
895 {
896         drm_i915_private_t *dev_priv = dev->dev_private;
897         i915_mem_release(dev, file_priv, dev_priv->agp_heap);
898 }
899
900 struct drm_ioctl_desc i915_ioctls[] = {
901         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
902         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
903         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
904         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
905         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
906         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
907         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
908         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
909         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
910         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
911         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
912         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
913         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
914         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
915         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
916         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
917         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
918 };
919
920 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
921
922 /**
923  * Determine if the device really is AGP or not.
924  *
925  * All Intel graphics chipsets are treated as AGP, even if they are really
926  * PCI-e.
927  *
928  * \param dev   The device to be tested.
929  *
930  * \returns
931  * A value of 1 is always retured to indictate every i9x5 is AGP.
932  */
933 int i915_driver_device_is_agp(struct drm_device * dev)
934 {
935         return 1;
936 }