Merge branch 'for-linus' of git://oss.sgi.com/xfs/xfs
[linux-2.6] / drivers / spi / spi_imx.c
1 /*
2  * drivers/spi/spi_imx.c
3  *
4  * Copyright (C) 2006 SWAPP
5  *      Andrea Paterniani <a.paterniani@swapp-eng.it>
6  *
7  * Initial version inspired by:
8  *      linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  */
20
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/device.h>
24 #include <linux/ioport.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/spi/spi.h>
30 #include <linux/workqueue.h>
31 #include <linux/delay.h>
32 #include <linux/clk.h>
33
34 #include <asm/io.h>
35 #include <asm/irq.h>
36 #include <asm/delay.h>
37
38 #include <mach/hardware.h>
39 #include <mach/imx-dma.h>
40 #include <mach/spi_imx.h>
41
42 /*-------------------------------------------------------------------------*/
43 /* SPI Registers offsets from peripheral base address */
44 #define SPI_RXDATA              (0x00)
45 #define SPI_TXDATA              (0x04)
46 #define SPI_CONTROL             (0x08)
47 #define SPI_INT_STATUS          (0x0C)
48 #define SPI_TEST                (0x10)
49 #define SPI_PERIOD              (0x14)
50 #define SPI_DMA                 (0x18)
51 #define SPI_RESET               (0x1C)
52
53 /* SPI Control Register Bit Fields & Masks */
54 #define SPI_CONTROL_BITCOUNT_MASK       (0xF)           /* Bit Count Mask */
55 #define SPI_CONTROL_BITCOUNT(n)         (((n) - 1) & SPI_CONTROL_BITCOUNT_MASK)
56 #define SPI_CONTROL_POL                 (0x1 << 4)      /* Clock Polarity Mask */
57 #define SPI_CONTROL_POL_ACT_HIGH        (0x0 << 4)      /* Active high pol. (0=idle) */
58 #define SPI_CONTROL_POL_ACT_LOW         (0x1 << 4)      /* Active low pol. (1=idle) */
59 #define SPI_CONTROL_PHA                 (0x1 << 5)      /* Clock Phase Mask */
60 #define SPI_CONTROL_PHA_0               (0x0 << 5)      /* Clock Phase 0 */
61 #define SPI_CONTROL_PHA_1               (0x1 << 5)      /* Clock Phase 1 */
62 #define SPI_CONTROL_SSCTL               (0x1 << 6)      /* /SS Waveform Select Mask */
63 #define SPI_CONTROL_SSCTL_0             (0x0 << 6)      /* Master: /SS stays low between SPI burst
64                                                            Slave: RXFIFO advanced by BIT_COUNT */
65 #define SPI_CONTROL_SSCTL_1             (0x1 << 6)      /* Master: /SS insert pulse between SPI burst
66                                                            Slave: RXFIFO advanced by /SS rising edge */
67 #define SPI_CONTROL_SSPOL               (0x1 << 7)      /* /SS Polarity Select Mask */
68 #define SPI_CONTROL_SSPOL_ACT_LOW       (0x0 << 7)      /* /SS Active low */
69 #define SPI_CONTROL_SSPOL_ACT_HIGH      (0x1 << 7)      /* /SS Active high */
70 #define SPI_CONTROL_XCH                 (0x1 << 8)      /* Exchange */
71 #define SPI_CONTROL_SPIEN               (0x1 << 9)      /* SPI Module Enable */
72 #define SPI_CONTROL_MODE                (0x1 << 10)     /* SPI Mode Select Mask */
73 #define SPI_CONTROL_MODE_SLAVE          (0x0 << 10)     /* SPI Mode Slave */
74 #define SPI_CONTROL_MODE_MASTER         (0x1 << 10)     /* SPI Mode Master */
75 #define SPI_CONTROL_DRCTL               (0x3 << 11)     /* /SPI_RDY Control Mask */
76 #define SPI_CONTROL_DRCTL_0             (0x0 << 11)     /* Ignore /SPI_RDY */
77 #define SPI_CONTROL_DRCTL_1             (0x1 << 11)     /* /SPI_RDY falling edge triggers input */
78 #define SPI_CONTROL_DRCTL_2             (0x2 << 11)     /* /SPI_RDY active low level triggers input */
79 #define SPI_CONTROL_DATARATE            (0x7 << 13)     /* Data Rate Mask */
80 #define SPI_PERCLK2_DIV_MIN             (0)             /* PERCLK2:4 */
81 #define SPI_PERCLK2_DIV_MAX             (7)             /* PERCLK2:512 */
82 #define SPI_CONTROL_DATARATE_MIN        (SPI_PERCLK2_DIV_MAX << 13)
83 #define SPI_CONTROL_DATARATE_MAX        (SPI_PERCLK2_DIV_MIN << 13)
84 #define SPI_CONTROL_DATARATE_BAD        (SPI_CONTROL_DATARATE_MIN + 1)
85
86 /* SPI Interrupt/Status Register Bit Fields & Masks */
87 #define SPI_STATUS_TE   (0x1 << 0)      /* TXFIFO Empty Status */
88 #define SPI_STATUS_TH   (0x1 << 1)      /* TXFIFO Half Status */
89 #define SPI_STATUS_TF   (0x1 << 2)      /* TXFIFO Full Status */
90 #define SPI_STATUS_RR   (0x1 << 3)      /* RXFIFO Data Ready Status */
91 #define SPI_STATUS_RH   (0x1 << 4)      /* RXFIFO Half Status */
92 #define SPI_STATUS_RF   (0x1 << 5)      /* RXFIFO Full Status */
93 #define SPI_STATUS_RO   (0x1 << 6)      /* RXFIFO Overflow */
94 #define SPI_STATUS_BO   (0x1 << 7)      /* Bit Count Overflow */
95 #define SPI_STATUS      (0xFF)          /* SPI Status Mask */
96 #define SPI_INTEN_TE    (0x1 << 8)      /* TXFIFO Empty Interrupt Enable */
97 #define SPI_INTEN_TH    (0x1 << 9)      /* TXFIFO Half Interrupt Enable */
98 #define SPI_INTEN_TF    (0x1 << 10)     /* TXFIFO Full Interrupt Enable */
99 #define SPI_INTEN_RE    (0x1 << 11)     /* RXFIFO Data Ready Interrupt Enable */
100 #define SPI_INTEN_RH    (0x1 << 12)     /* RXFIFO Half Interrupt Enable */
101 #define SPI_INTEN_RF    (0x1 << 13)     /* RXFIFO Full Interrupt Enable */
102 #define SPI_INTEN_RO    (0x1 << 14)     /* RXFIFO Overflow Interrupt Enable */
103 #define SPI_INTEN_BO    (0x1 << 15)     /* Bit Count Overflow Interrupt Enable */
104 #define SPI_INTEN       (0xFF << 8)     /* SPI Interrupt Enable Mask */
105
106 /* SPI Test Register Bit Fields & Masks */
107 #define SPI_TEST_TXCNT          (0xF << 0)      /* TXFIFO Counter */
108 #define SPI_TEST_RXCNT_LSB      (4)             /* RXFIFO Counter LSB */
109 #define SPI_TEST_RXCNT          (0xF << 4)      /* RXFIFO Counter */
110 #define SPI_TEST_SSTATUS        (0xF << 8)      /* State Machine Status */
111 #define SPI_TEST_LBC            (0x1 << 14)     /* Loop Back Control */
112
113 /* SPI Period Register Bit Fields & Masks */
114 #define SPI_PERIOD_WAIT         (0x7FFF << 0)   /* Wait Between Transactions */
115 #define SPI_PERIOD_MAX_WAIT     (0x7FFF)        /* Max Wait Between
116                                                         Transactions */
117 #define SPI_PERIOD_CSRC         (0x1 << 15)     /* Period Clock Source Mask */
118 #define SPI_PERIOD_CSRC_BCLK    (0x0 << 15)     /* Period Clock Source is
119                                                         Bit Clock */
120 #define SPI_PERIOD_CSRC_32768   (0x1 << 15)     /* Period Clock Source is
121                                                         32.768 KHz Clock */
122
123 /* SPI DMA Register Bit Fields & Masks */
124 #define SPI_DMA_RHDMA   (0x1 << 4)      /* RXFIFO Half Status */
125 #define SPI_DMA_RFDMA   (0x1 << 5)      /* RXFIFO Full Status */
126 #define SPI_DMA_TEDMA   (0x1 << 6)      /* TXFIFO Empty Status */
127 #define SPI_DMA_THDMA   (0x1 << 7)      /* TXFIFO Half Status */
128 #define SPI_DMA_RHDEN   (0x1 << 12)     /* RXFIFO Half DMA Request Enable */
129 #define SPI_DMA_RFDEN   (0x1 << 13)     /* RXFIFO Full DMA Request Enable */
130 #define SPI_DMA_TEDEN   (0x1 << 14)     /* TXFIFO Empty DMA Request Enable */
131 #define SPI_DMA_THDEN   (0x1 << 15)     /* TXFIFO Half DMA Request Enable */
132
133 /* SPI Soft Reset Register Bit Fields & Masks */
134 #define SPI_RESET_START (0x1)           /* Start */
135
136 /* Default SPI configuration values */
137 #define SPI_DEFAULT_CONTROL             \
138 (                                       \
139         SPI_CONTROL_BITCOUNT(16) |      \
140         SPI_CONTROL_POL_ACT_HIGH |      \
141         SPI_CONTROL_PHA_0 |             \
142         SPI_CONTROL_SPIEN |             \
143         SPI_CONTROL_SSCTL_1 |           \
144         SPI_CONTROL_MODE_MASTER |       \
145         SPI_CONTROL_DRCTL_0 |           \
146         SPI_CONTROL_DATARATE_MIN        \
147 )
148 #define SPI_DEFAULT_ENABLE_LOOPBACK     (0)
149 #define SPI_DEFAULT_ENABLE_DMA          (0)
150 #define SPI_DEFAULT_PERIOD_WAIT         (8)
151 /*-------------------------------------------------------------------------*/
152
153
154 /*-------------------------------------------------------------------------*/
155 /* TX/RX SPI FIFO size */
156 #define SPI_FIFO_DEPTH                  (8)
157 #define SPI_FIFO_BYTE_WIDTH             (2)
158 #define SPI_FIFO_OVERFLOW_MARGIN        (2)
159
160 /* DMA burst length for half full/empty request trigger */
161 #define SPI_DMA_BLR                     (SPI_FIFO_DEPTH * SPI_FIFO_BYTE_WIDTH / 2)
162
163 /* Dummy char output to achieve reads.
164    Choosing something different from all zeroes may help pattern recogition
165    for oscilloscope analysis, but may break some drivers. */
166 #define SPI_DUMMY_u8                    0
167 #define SPI_DUMMY_u16                   ((SPI_DUMMY_u8 << 8) | SPI_DUMMY_u8)
168 #define SPI_DUMMY_u32                   ((SPI_DUMMY_u16 << 16) | SPI_DUMMY_u16)
169
170 /**
171  * Macro to change a u32 field:
172  * @r : register to edit
173  * @m : bit mask
174  * @v : new value for the field correctly bit-alligned
175 */
176 #define u32_EDIT(r, m, v)               r = (r & ~(m)) | (v)
177
178 /* Message state */
179 #define START_STATE                     ((void*)0)
180 #define RUNNING_STATE                   ((void*)1)
181 #define DONE_STATE                      ((void*)2)
182 #define ERROR_STATE                     ((void*)-1)
183
184 /* Queue state */
185 #define QUEUE_RUNNING                   (0)
186 #define QUEUE_STOPPED                   (1)
187
188 #define IS_DMA_ALIGNED(x)               (((u32)(x) & 0x03) == 0)
189 #define DMA_ALIGNMENT                   4
190 /*-------------------------------------------------------------------------*/
191
192
193 /*-------------------------------------------------------------------------*/
194 /* Driver data structs */
195
196 /* Context */
197 struct driver_data {
198         /* Driver model hookup */
199         struct platform_device *pdev;
200
201         /* SPI framework hookup */
202         struct spi_master *master;
203
204         /* IMX hookup */
205         struct spi_imx_master *master_info;
206
207         /* Memory resources and SPI regs virtual address */
208         struct resource *ioarea;
209         void __iomem *regs;
210
211         /* SPI RX_DATA physical address */
212         dma_addr_t rd_data_phys;
213
214         /* Driver message queue */
215         struct workqueue_struct *workqueue;
216         struct work_struct work;
217         spinlock_t lock;
218         struct list_head queue;
219         int busy;
220         int run;
221
222         /* Message Transfer pump */
223         struct tasklet_struct pump_transfers;
224
225         /* Current message, transfer and state */
226         struct spi_message *cur_msg;
227         struct spi_transfer *cur_transfer;
228         struct chip_data *cur_chip;
229
230         /* Rd / Wr buffers pointers */
231         size_t len;
232         void *tx;
233         void *tx_end;
234         void *rx;
235         void *rx_end;
236
237         u8 rd_only;
238         u8 n_bytes;
239         int cs_change;
240
241         /* Function pointers */
242         irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
243         void (*cs_control)(u32 command);
244
245         /* DMA setup */
246         int rx_channel;
247         int tx_channel;
248         dma_addr_t rx_dma;
249         dma_addr_t tx_dma;
250         int rx_dma_needs_unmap;
251         int tx_dma_needs_unmap;
252         size_t tx_map_len;
253         u32 dummy_dma_buf ____cacheline_aligned;
254
255         struct clk *clk;
256 };
257
258 /* Runtime state */
259 struct chip_data {
260         u32 control;
261         u32 period;
262         u32 test;
263
264         u8 enable_dma:1;
265         u8 bits_per_word;
266         u8 n_bytes;
267         u32 max_speed_hz;
268
269         void (*cs_control)(u32 command);
270 };
271 /*-------------------------------------------------------------------------*/
272
273
274 static void pump_messages(struct work_struct *work);
275
276 static void flush(struct driver_data *drv_data)
277 {
278         void __iomem *regs = drv_data->regs;
279         u32 control;
280
281         dev_dbg(&drv_data->pdev->dev, "flush\n");
282
283         /* Wait for end of transaction */
284         do {
285                 control = readl(regs + SPI_CONTROL);
286         } while (control & SPI_CONTROL_XCH);
287
288         /* Release chip select if requested, transfer delays are
289            handled in pump_transfers */
290         if (drv_data->cs_change)
291                 drv_data->cs_control(SPI_CS_DEASSERT);
292
293         /* Disable SPI to flush FIFOs */
294         writel(control & ~SPI_CONTROL_SPIEN, regs + SPI_CONTROL);
295         writel(control, regs + SPI_CONTROL);
296 }
297
298 static void restore_state(struct driver_data *drv_data)
299 {
300         void __iomem *regs = drv_data->regs;
301         struct chip_data *chip = drv_data->cur_chip;
302
303         /* Load chip registers */
304         dev_dbg(&drv_data->pdev->dev,
305                 "restore_state\n"
306                 "    test    = 0x%08X\n"
307                 "    control = 0x%08X\n",
308                 chip->test,
309                 chip->control);
310         writel(chip->test, regs + SPI_TEST);
311         writel(chip->period, regs + SPI_PERIOD);
312         writel(0, regs + SPI_INT_STATUS);
313         writel(chip->control, regs + SPI_CONTROL);
314 }
315
316 static void null_cs_control(u32 command)
317 {
318 }
319
320 static inline u32 data_to_write(struct driver_data *drv_data)
321 {
322         return ((u32)(drv_data->tx_end - drv_data->tx)) / drv_data->n_bytes;
323 }
324
325 static inline u32 data_to_read(struct driver_data *drv_data)
326 {
327         return ((u32)(drv_data->rx_end - drv_data->rx)) / drv_data->n_bytes;
328 }
329
330 static int write(struct driver_data *drv_data)
331 {
332         void __iomem *regs = drv_data->regs;
333         void *tx = drv_data->tx;
334         void *tx_end = drv_data->tx_end;
335         u8 n_bytes = drv_data->n_bytes;
336         u32 remaining_writes;
337         u32 fifo_avail_space;
338         u32 n;
339         u16 d;
340
341         /* Compute how many fifo writes to do */
342         remaining_writes = (u32)(tx_end - tx) / n_bytes;
343         fifo_avail_space = SPI_FIFO_DEPTH -
344                                 (readl(regs + SPI_TEST) & SPI_TEST_TXCNT);
345         if (drv_data->rx && (fifo_avail_space > SPI_FIFO_OVERFLOW_MARGIN))
346                 /* Fix misunderstood receive overflow */
347                 fifo_avail_space -= SPI_FIFO_OVERFLOW_MARGIN;
348         n = min(remaining_writes, fifo_avail_space);
349
350         dev_dbg(&drv_data->pdev->dev,
351                 "write type %s\n"
352                 "    remaining writes = %d\n"
353                 "    fifo avail space = %d\n"
354                 "    fifo writes      = %d\n",
355                 (n_bytes == 1) ? "u8" : "u16",
356                 remaining_writes,
357                 fifo_avail_space,
358                 n);
359
360         if (n > 0) {
361                 /* Fill SPI TXFIFO */
362                 if (drv_data->rd_only) {
363                         tx += n * n_bytes;
364                         while (n--)
365                                 writel(SPI_DUMMY_u16, regs + SPI_TXDATA);
366                 } else {
367                         if (n_bytes == 1) {
368                                 while (n--) {
369                                         d = *(u8*)tx;
370                                         writel(d, regs + SPI_TXDATA);
371                                         tx += 1;
372                                 }
373                         } else {
374                                 while (n--) {
375                                         d = *(u16*)tx;
376                                         writel(d, regs + SPI_TXDATA);
377                                         tx += 2;
378                                 }
379                         }
380                 }
381
382                 /* Trigger transfer */
383                 writel(readl(regs + SPI_CONTROL) | SPI_CONTROL_XCH,
384                         regs + SPI_CONTROL);
385
386                 /* Update tx pointer */
387                 drv_data->tx = tx;
388         }
389
390         return (tx >= tx_end);
391 }
392
393 static int read(struct driver_data *drv_data)
394 {
395         void __iomem *regs = drv_data->regs;
396         void *rx = drv_data->rx;
397         void *rx_end = drv_data->rx_end;
398         u8 n_bytes = drv_data->n_bytes;
399         u32 remaining_reads;
400         u32 fifo_rxcnt;
401         u32 n;
402         u16 d;
403
404         /* Compute how many fifo reads to do */
405         remaining_reads = (u32)(rx_end - rx) / n_bytes;
406         fifo_rxcnt = (readl(regs + SPI_TEST) & SPI_TEST_RXCNT) >>
407                         SPI_TEST_RXCNT_LSB;
408         n = min(remaining_reads, fifo_rxcnt);
409
410         dev_dbg(&drv_data->pdev->dev,
411                 "read type %s\n"
412                 "    remaining reads = %d\n"
413                 "    fifo rx count   = %d\n"
414                 "    fifo reads      = %d\n",
415                 (n_bytes == 1) ? "u8" : "u16",
416                 remaining_reads,
417                 fifo_rxcnt,
418                 n);
419
420         if (n > 0) {
421                 /* Read SPI RXFIFO */
422                 if (n_bytes == 1) {
423                         while (n--) {
424                                 d = readl(regs + SPI_RXDATA);
425                                 *((u8*)rx) = d;
426                                 rx += 1;
427                         }
428                 } else {
429                         while (n--) {
430                                 d = readl(regs + SPI_RXDATA);
431                                 *((u16*)rx) = d;
432                                 rx += 2;
433                         }
434                 }
435
436                 /* Update rx pointer */
437                 drv_data->rx = rx;
438         }
439
440         return (rx >= rx_end);
441 }
442
443 static void *next_transfer(struct driver_data *drv_data)
444 {
445         struct spi_message *msg = drv_data->cur_msg;
446         struct spi_transfer *trans = drv_data->cur_transfer;
447
448         /* Move to next transfer */
449         if (trans->transfer_list.next != &msg->transfers) {
450                 drv_data->cur_transfer =
451                         list_entry(trans->transfer_list.next,
452                                         struct spi_transfer,
453                                         transfer_list);
454                 return RUNNING_STATE;
455         }
456
457         return DONE_STATE;
458 }
459
460 static int map_dma_buffers(struct driver_data *drv_data)
461 {
462         struct spi_message *msg;
463         struct device *dev;
464         void *buf;
465
466         drv_data->rx_dma_needs_unmap = 0;
467         drv_data->tx_dma_needs_unmap = 0;
468
469         if (!drv_data->master_info->enable_dma ||
470                 !drv_data->cur_chip->enable_dma)
471                         return -1;
472
473         msg = drv_data->cur_msg;
474         dev = &msg->spi->dev;
475         if (msg->is_dma_mapped) {
476                 if (drv_data->tx_dma)
477                         /* The caller provided at least dma and cpu virtual
478                            address for write; pump_transfers() will consider the
479                            transfer as write only if cpu rx virtual address is
480                            NULL */
481                         return 0;
482
483                 if (drv_data->rx_dma) {
484                         /* The caller provided dma and cpu virtual address to
485                            performe read only transfer -->
486                            use drv_data->dummy_dma_buf for dummy writes to
487                            achive reads */
488                         buf = &drv_data->dummy_dma_buf;
489                         drv_data->tx_map_len = sizeof(drv_data->dummy_dma_buf);
490                         drv_data->tx_dma = dma_map_single(dev,
491                                                         buf,
492                                                         drv_data->tx_map_len,
493                                                         DMA_TO_DEVICE);
494                         if (dma_mapping_error(dev, drv_data->tx_dma))
495                                 return -1;
496
497                         drv_data->tx_dma_needs_unmap = 1;
498
499                         /* Flags transfer as rd_only for pump_transfers() DMA
500                            regs programming (should be redundant) */
501                         drv_data->tx = NULL;
502
503                         return 0;
504                 }
505         }
506
507         if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
508                 return -1;
509
510         if (drv_data->tx == NULL) {
511                 /* Read only message --> use drv_data->dummy_dma_buf for dummy
512                    writes to achive reads */
513                 buf = &drv_data->dummy_dma_buf;
514                 drv_data->tx_map_len = sizeof(drv_data->dummy_dma_buf);
515         } else {
516                 buf = drv_data->tx;
517                 drv_data->tx_map_len = drv_data->len;
518         }
519         drv_data->tx_dma = dma_map_single(dev,
520                                         buf,
521                                         drv_data->tx_map_len,
522                                         DMA_TO_DEVICE);
523         if (dma_mapping_error(dev, drv_data->tx_dma))
524                 return -1;
525         drv_data->tx_dma_needs_unmap = 1;
526
527         /* NULL rx means write-only transfer and no map needed
528          * since rx DMA will not be used */
529         if (drv_data->rx) {
530                 buf = drv_data->rx;
531                 drv_data->rx_dma = dma_map_single(dev,
532                                                 buf,
533                                                 drv_data->len,
534                                                 DMA_FROM_DEVICE);
535                 if (dma_mapping_error(dev, drv_data->rx_dma)) {
536                         if (drv_data->tx_dma) {
537                                 dma_unmap_single(dev,
538                                                 drv_data->tx_dma,
539                                                 drv_data->tx_map_len,
540                                                 DMA_TO_DEVICE);
541                                 drv_data->tx_dma_needs_unmap = 0;
542                         }
543                         return -1;
544                 }
545                 drv_data->rx_dma_needs_unmap = 1;
546         }
547
548         return 0;
549 }
550
551 static void unmap_dma_buffers(struct driver_data *drv_data)
552 {
553         struct spi_message *msg = drv_data->cur_msg;
554         struct device *dev = &msg->spi->dev;
555
556         if (drv_data->rx_dma_needs_unmap) {
557                 dma_unmap_single(dev,
558                                 drv_data->rx_dma,
559                                 drv_data->len,
560                                 DMA_FROM_DEVICE);
561                 drv_data->rx_dma_needs_unmap = 0;
562         }
563         if (drv_data->tx_dma_needs_unmap) {
564                 dma_unmap_single(dev,
565                                 drv_data->tx_dma,
566                                 drv_data->tx_map_len,
567                                 DMA_TO_DEVICE);
568                 drv_data->tx_dma_needs_unmap = 0;
569         }
570 }
571
572 /* Caller already set message->status (dma is already blocked) */
573 static void giveback(struct spi_message *message, struct driver_data *drv_data)
574 {
575         void __iomem *regs = drv_data->regs;
576
577         /* Bring SPI to sleep; restore_state() and pump_transfer()
578            will do new setup */
579         writel(0, regs + SPI_INT_STATUS);
580         writel(0, regs + SPI_DMA);
581
582         /* Unconditioned deselct */
583         drv_data->cs_control(SPI_CS_DEASSERT);
584
585         message->state = NULL;
586         if (message->complete)
587                 message->complete(message->context);
588
589         drv_data->cur_msg = NULL;
590         drv_data->cur_transfer = NULL;
591         drv_data->cur_chip = NULL;
592         queue_work(drv_data->workqueue, &drv_data->work);
593 }
594
595 static void dma_err_handler(int channel, void *data, int errcode)
596 {
597         struct driver_data *drv_data = data;
598         struct spi_message *msg = drv_data->cur_msg;
599
600         dev_dbg(&drv_data->pdev->dev, "dma_err_handler\n");
601
602         /* Disable both rx and tx dma channels */
603         imx_dma_disable(drv_data->rx_channel);
604         imx_dma_disable(drv_data->tx_channel);
605         unmap_dma_buffers(drv_data);
606
607         flush(drv_data);
608
609         msg->state = ERROR_STATE;
610         tasklet_schedule(&drv_data->pump_transfers);
611 }
612
613 static void dma_tx_handler(int channel, void *data)
614 {
615         struct driver_data *drv_data = data;
616
617         dev_dbg(&drv_data->pdev->dev, "dma_tx_handler\n");
618
619         imx_dma_disable(channel);
620
621         /* Now waits for TX FIFO empty */
622         writel(SPI_INTEN_TE, drv_data->regs + SPI_INT_STATUS);
623 }
624
625 static irqreturn_t dma_transfer(struct driver_data *drv_data)
626 {
627         u32 status;
628         struct spi_message *msg = drv_data->cur_msg;
629         void __iomem *regs = drv_data->regs;
630
631         status = readl(regs + SPI_INT_STATUS);
632
633         if ((status & (SPI_INTEN_RO | SPI_STATUS_RO))
634                         == (SPI_INTEN_RO | SPI_STATUS_RO)) {
635                 writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
636
637                 imx_dma_disable(drv_data->tx_channel);
638                 imx_dma_disable(drv_data->rx_channel);
639                 unmap_dma_buffers(drv_data);
640
641                 flush(drv_data);
642
643                 dev_warn(&drv_data->pdev->dev,
644                                 "dma_transfer - fifo overun\n");
645
646                 msg->state = ERROR_STATE;
647                 tasklet_schedule(&drv_data->pump_transfers);
648
649                 return IRQ_HANDLED;
650         }
651
652         if (status & SPI_STATUS_TE) {
653                 writel(status & ~SPI_INTEN_TE, regs + SPI_INT_STATUS);
654
655                 if (drv_data->rx) {
656                         /* Wait end of transfer before read trailing data */
657                         while (readl(regs + SPI_CONTROL) & SPI_CONTROL_XCH)
658                                 cpu_relax();
659
660                         imx_dma_disable(drv_data->rx_channel);
661                         unmap_dma_buffers(drv_data);
662
663                         /* Release chip select if requested, transfer delays are
664                            handled in pump_transfers() */
665                         if (drv_data->cs_change)
666                                 drv_data->cs_control(SPI_CS_DEASSERT);
667
668                         /* Calculate number of trailing data and read them */
669                         dev_dbg(&drv_data->pdev->dev,
670                                 "dma_transfer - test = 0x%08X\n",
671                                 readl(regs + SPI_TEST));
672                         drv_data->rx = drv_data->rx_end -
673                                         ((readl(regs + SPI_TEST) &
674                                         SPI_TEST_RXCNT) >>
675                                         SPI_TEST_RXCNT_LSB)*drv_data->n_bytes;
676                         read(drv_data);
677                 } else {
678                         /* Write only transfer */
679                         unmap_dma_buffers(drv_data);
680
681                         flush(drv_data);
682                 }
683
684                 /* End of transfer, update total byte transfered */
685                 msg->actual_length += drv_data->len;
686
687                 /* Move to next transfer */
688                 msg->state = next_transfer(drv_data);
689
690                 /* Schedule transfer tasklet */
691                 tasklet_schedule(&drv_data->pump_transfers);
692
693                 return IRQ_HANDLED;
694         }
695
696         /* Opps problem detected */
697         return IRQ_NONE;
698 }
699
700 static irqreturn_t interrupt_wronly_transfer(struct driver_data *drv_data)
701 {
702         struct spi_message *msg = drv_data->cur_msg;
703         void __iomem *regs = drv_data->regs;
704         u32 status;
705         irqreturn_t handled = IRQ_NONE;
706
707         status = readl(regs + SPI_INT_STATUS);
708
709         if (status & SPI_INTEN_TE) {
710                 /* TXFIFO Empty Interrupt on the last transfered word */
711                 writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
712                 dev_dbg(&drv_data->pdev->dev,
713                         "interrupt_wronly_transfer - end of tx\n");
714
715                 flush(drv_data);
716
717                 /* Update total byte transfered */
718                 msg->actual_length += drv_data->len;
719
720                 /* Move to next transfer */
721                 msg->state = next_transfer(drv_data);
722
723                 /* Schedule transfer tasklet */
724                 tasklet_schedule(&drv_data->pump_transfers);
725
726                 return IRQ_HANDLED;
727         } else {
728                 while (status & SPI_STATUS_TH) {
729                         dev_dbg(&drv_data->pdev->dev,
730                                 "interrupt_wronly_transfer - status = 0x%08X\n",
731                                 status);
732
733                         /* Pump data */
734                         if (write(drv_data)) {
735                                 /* End of TXFIFO writes,
736                                    now wait until TXFIFO is empty */
737                                 writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
738                                 return IRQ_HANDLED;
739                         }
740
741                         status = readl(regs + SPI_INT_STATUS);
742
743                         /* We did something */
744                         handled = IRQ_HANDLED;
745                 }
746         }
747
748         return handled;
749 }
750
751 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
752 {
753         struct spi_message *msg = drv_data->cur_msg;
754         void __iomem *regs = drv_data->regs;
755         u32 status, control;
756         irqreturn_t handled = IRQ_NONE;
757         unsigned long limit;
758
759         status = readl(regs + SPI_INT_STATUS);
760
761         if (status & SPI_INTEN_TE) {
762                 /* TXFIFO Empty Interrupt on the last transfered word */
763                 writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
764                 dev_dbg(&drv_data->pdev->dev,
765                         "interrupt_transfer - end of tx\n");
766
767                 if (msg->state == ERROR_STATE) {
768                         /* RXFIFO overrun was detected and message aborted */
769                         flush(drv_data);
770                 } else {
771                         /* Wait for end of transaction */
772                         do {
773                                 control = readl(regs + SPI_CONTROL);
774                         } while (control & SPI_CONTROL_XCH);
775
776                         /* Release chip select if requested, transfer delays are
777                            handled in pump_transfers */
778                         if (drv_data->cs_change)
779                                 drv_data->cs_control(SPI_CS_DEASSERT);
780
781                         /* Read trailing bytes */
782                         limit = loops_per_jiffy << 1;
783                         while ((read(drv_data) == 0) && --limit)
784                                 cpu_relax();
785
786                         if (limit == 0)
787                                 dev_err(&drv_data->pdev->dev,
788                                         "interrupt_transfer - "
789                                         "trailing byte read failed\n");
790                         else
791                                 dev_dbg(&drv_data->pdev->dev,
792                                         "interrupt_transfer - end of rx\n");
793
794                         /* Update total byte transfered */
795                         msg->actual_length += drv_data->len;
796
797                         /* Move to next transfer */
798                         msg->state = next_transfer(drv_data);
799                 }
800
801                 /* Schedule transfer tasklet */
802                 tasklet_schedule(&drv_data->pump_transfers);
803
804                 return IRQ_HANDLED;
805         } else {
806                 while (status & (SPI_STATUS_TH | SPI_STATUS_RO)) {
807                         dev_dbg(&drv_data->pdev->dev,
808                                 "interrupt_transfer - status = 0x%08X\n",
809                                 status);
810
811                         if (status & SPI_STATUS_RO) {
812                                 /* RXFIFO overrun, abort message end wait
813                                    until TXFIFO is empty */
814                                 writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
815
816                                 dev_warn(&drv_data->pdev->dev,
817                                         "interrupt_transfer - fifo overun\n"
818                                         "    data not yet written = %d\n"
819                                         "    data not yet read    = %d\n",
820                                         data_to_write(drv_data),
821                                         data_to_read(drv_data));
822
823                                 msg->state = ERROR_STATE;
824
825                                 return IRQ_HANDLED;
826                         }
827
828                         /* Pump data */
829                         read(drv_data);
830                         if (write(drv_data)) {
831                                 /* End of TXFIFO writes,
832                                    now wait until TXFIFO is empty */
833                                 writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
834                                 return IRQ_HANDLED;
835                         }
836
837                         status = readl(regs + SPI_INT_STATUS);
838
839                         /* We did something */
840                         handled = IRQ_HANDLED;
841                 }
842         }
843
844         return handled;
845 }
846
847 static irqreturn_t spi_int(int irq, void *dev_id)
848 {
849         struct driver_data *drv_data = (struct driver_data *)dev_id;
850
851         if (!drv_data->cur_msg) {
852                 dev_err(&drv_data->pdev->dev,
853                         "spi_int - bad message state\n");
854                 /* Never fail */
855                 return IRQ_HANDLED;
856         }
857
858         return drv_data->transfer_handler(drv_data);
859 }
860
861 static inline u32 spi_speed_hz(struct driver_data *drv_data, u32 data_rate)
862 {
863         return clk_get_rate(drv_data->clk) / (4 << ((data_rate) >> 13));
864 }
865
866 static u32 spi_data_rate(struct driver_data *drv_data, u32 speed_hz)
867 {
868         u32 div;
869         u32 quantized_hz = clk_get_rate(drv_data->clk) >> 2;
870
871         for (div = SPI_PERCLK2_DIV_MIN;
872                 div <= SPI_PERCLK2_DIV_MAX;
873                 div++, quantized_hz >>= 1) {
874                         if (quantized_hz <= speed_hz)
875                                 /* Max available speed LEQ required speed */
876                                 return div << 13;
877         }
878         return SPI_CONTROL_DATARATE_BAD;
879 }
880
881 static void pump_transfers(unsigned long data)
882 {
883         struct driver_data *drv_data = (struct driver_data *)data;
884         struct spi_message *message;
885         struct spi_transfer *transfer, *previous;
886         struct chip_data *chip;
887         void __iomem *regs;
888         u32 tmp, control;
889
890         dev_dbg(&drv_data->pdev->dev, "pump_transfer\n");
891
892         message = drv_data->cur_msg;
893
894         /* Handle for abort */
895         if (message->state == ERROR_STATE) {
896                 message->status = -EIO;
897                 giveback(message, drv_data);
898                 return;
899         }
900
901         /* Handle end of message */
902         if (message->state == DONE_STATE) {
903                 message->status = 0;
904                 giveback(message, drv_data);
905                 return;
906         }
907
908         chip = drv_data->cur_chip;
909
910         /* Delay if requested at end of transfer*/
911         transfer = drv_data->cur_transfer;
912         if (message->state == RUNNING_STATE) {
913                 previous = list_entry(transfer->transfer_list.prev,
914                                         struct spi_transfer,
915                                         transfer_list);
916                 if (previous->delay_usecs)
917                         udelay(previous->delay_usecs);
918         } else {
919                 /* START_STATE */
920                 message->state = RUNNING_STATE;
921                 drv_data->cs_control = chip->cs_control;
922         }
923
924         transfer = drv_data->cur_transfer;
925         drv_data->tx = (void *)transfer->tx_buf;
926         drv_data->tx_end = drv_data->tx + transfer->len;
927         drv_data->rx = transfer->rx_buf;
928         drv_data->rx_end = drv_data->rx + transfer->len;
929         drv_data->rx_dma = transfer->rx_dma;
930         drv_data->tx_dma = transfer->tx_dma;
931         drv_data->len = transfer->len;
932         drv_data->cs_change = transfer->cs_change;
933         drv_data->rd_only = (drv_data->tx == NULL);
934
935         regs = drv_data->regs;
936         control = readl(regs + SPI_CONTROL);
937
938         /* Bits per word setup */
939         tmp = transfer->bits_per_word;
940         if (tmp == 0) {
941                 /* Use device setup */
942                 tmp = chip->bits_per_word;
943                 drv_data->n_bytes = chip->n_bytes;
944         } else
945                 /* Use per-transfer setup */
946                 drv_data->n_bytes = (tmp <= 8) ? 1 : 2;
947         u32_EDIT(control, SPI_CONTROL_BITCOUNT_MASK, tmp - 1);
948
949         /* Speed setup (surely valid because already checked) */
950         tmp = transfer->speed_hz;
951         if (tmp == 0)
952                 tmp = chip->max_speed_hz;
953         tmp = spi_data_rate(drv_data, tmp);
954         u32_EDIT(control, SPI_CONTROL_DATARATE, tmp);
955
956         writel(control, regs + SPI_CONTROL);
957
958         /* Assert device chip-select */
959         drv_data->cs_control(SPI_CS_ASSERT);
960
961         /* DMA cannot read/write SPI FIFOs other than 16 bits at a time; hence
962            if bits_per_word is less or equal 8 PIO transfers are performed.
963            Moreover DMA is convinient for transfer length bigger than FIFOs
964            byte size. */
965         if ((drv_data->n_bytes == 2) &&
966                 (drv_data->len > SPI_FIFO_DEPTH*SPI_FIFO_BYTE_WIDTH) &&
967                 (map_dma_buffers(drv_data) == 0)) {
968                 dev_dbg(&drv_data->pdev->dev,
969                         "pump dma transfer\n"
970                         "    tx      = %p\n"
971                         "    tx_dma  = %08X\n"
972                         "    rx      = %p\n"
973                         "    rx_dma  = %08X\n"
974                         "    len     = %d\n",
975                         drv_data->tx,
976                         (unsigned int)drv_data->tx_dma,
977                         drv_data->rx,
978                         (unsigned int)drv_data->rx_dma,
979                         drv_data->len);
980
981                 /* Ensure we have the correct interrupt handler */
982                 drv_data->transfer_handler = dma_transfer;
983
984                 /* Trigger transfer */
985                 writel(readl(regs + SPI_CONTROL) | SPI_CONTROL_XCH,
986                         regs + SPI_CONTROL);
987
988                 /* Setup tx DMA */
989                 if (drv_data->tx)
990                         /* Linear source address */
991                         CCR(drv_data->tx_channel) =
992                                 CCR_DMOD_FIFO |
993                                 CCR_SMOD_LINEAR |
994                                 CCR_SSIZ_32 | CCR_DSIZ_16 |
995                                 CCR_REN;
996                 else
997                         /* Read only transfer -> fixed source address for
998                            dummy write to achive read */
999                         CCR(drv_data->tx_channel) =
1000                                 CCR_DMOD_FIFO |
1001                                 CCR_SMOD_FIFO |
1002                                 CCR_SSIZ_32 | CCR_DSIZ_16 |
1003                                 CCR_REN;
1004
1005                 imx_dma_setup_single(
1006                         drv_data->tx_channel,
1007                         drv_data->tx_dma,
1008                         drv_data->len,
1009                         drv_data->rd_data_phys + 4,
1010                         DMA_MODE_WRITE);
1011
1012                 if (drv_data->rx) {
1013                         /* Setup rx DMA for linear destination address */
1014                         CCR(drv_data->rx_channel) =
1015                                 CCR_DMOD_LINEAR |
1016                                 CCR_SMOD_FIFO |
1017                                 CCR_DSIZ_32 | CCR_SSIZ_16 |
1018                                 CCR_REN;
1019                         imx_dma_setup_single(
1020                                 drv_data->rx_channel,
1021                                 drv_data->rx_dma,
1022                                 drv_data->len,
1023                                 drv_data->rd_data_phys,
1024                                 DMA_MODE_READ);
1025                         imx_dma_enable(drv_data->rx_channel);
1026
1027                         /* Enable SPI interrupt */
1028                         writel(SPI_INTEN_RO, regs + SPI_INT_STATUS);
1029
1030                         /* Set SPI to request DMA service on both
1031                            Rx and Tx half fifo watermark */
1032                         writel(SPI_DMA_RHDEN | SPI_DMA_THDEN, regs + SPI_DMA);
1033                 } else
1034                         /* Write only access -> set SPI to request DMA
1035                            service on Tx half fifo watermark */
1036                         writel(SPI_DMA_THDEN, regs + SPI_DMA);
1037
1038                 imx_dma_enable(drv_data->tx_channel);
1039         } else {
1040                 dev_dbg(&drv_data->pdev->dev,
1041                         "pump pio transfer\n"
1042                         "    tx      = %p\n"
1043                         "    rx      = %p\n"
1044                         "    len     = %d\n",
1045                         drv_data->tx,
1046                         drv_data->rx,
1047                         drv_data->len);
1048
1049                 /* Ensure we have the correct interrupt handler */
1050                 if (drv_data->rx)
1051                         drv_data->transfer_handler = interrupt_transfer;
1052                 else
1053                         drv_data->transfer_handler = interrupt_wronly_transfer;
1054
1055                 /* Enable SPI interrupt */
1056                 if (drv_data->rx)
1057                         writel(SPI_INTEN_TH | SPI_INTEN_RO,
1058                                 regs + SPI_INT_STATUS);
1059                 else
1060                         writel(SPI_INTEN_TH, regs + SPI_INT_STATUS);
1061         }
1062 }
1063
1064 static void pump_messages(struct work_struct *work)
1065 {
1066         struct driver_data *drv_data =
1067                                 container_of(work, struct driver_data, work);
1068         unsigned long flags;
1069
1070         /* Lock queue and check for queue work */
1071         spin_lock_irqsave(&drv_data->lock, flags);
1072         if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1073                 drv_data->busy = 0;
1074                 spin_unlock_irqrestore(&drv_data->lock, flags);
1075                 return;
1076         }
1077
1078         /* Make sure we are not already running a message */
1079         if (drv_data->cur_msg) {
1080                 spin_unlock_irqrestore(&drv_data->lock, flags);
1081                 return;
1082         }
1083
1084         /* Extract head of queue */
1085         drv_data->cur_msg = list_entry(drv_data->queue.next,
1086                                         struct spi_message, queue);
1087         list_del_init(&drv_data->cur_msg->queue);
1088         drv_data->busy = 1;
1089         spin_unlock_irqrestore(&drv_data->lock, flags);
1090
1091         /* Initial message state */
1092         drv_data->cur_msg->state = START_STATE;
1093         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1094                                                 struct spi_transfer,
1095                                                 transfer_list);
1096
1097         /* Setup the SPI using the per chip configuration */
1098         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1099         restore_state(drv_data);
1100
1101         /* Mark as busy and launch transfers */
1102         tasklet_schedule(&drv_data->pump_transfers);
1103 }
1104
1105 static int transfer(struct spi_device *spi, struct spi_message *msg)
1106 {
1107         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1108         u32 min_speed_hz, max_speed_hz, tmp;
1109         struct spi_transfer *trans;
1110         unsigned long flags;
1111
1112         msg->actual_length = 0;
1113
1114         /* Per transfer setup check */
1115         min_speed_hz = spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN);
1116         max_speed_hz = spi->max_speed_hz;
1117         list_for_each_entry(trans, &msg->transfers, transfer_list) {
1118                 tmp = trans->bits_per_word;
1119                 if (tmp > 16) {
1120                         dev_err(&drv_data->pdev->dev,
1121                                 "message rejected : "
1122                                 "invalid transfer bits_per_word (%d bits)\n",
1123                                 tmp);
1124                         goto msg_rejected;
1125                 }
1126                 tmp = trans->speed_hz;
1127                 if (tmp) {
1128                         if (tmp < min_speed_hz) {
1129                                 dev_err(&drv_data->pdev->dev,
1130                                         "message rejected : "
1131                                         "device min speed (%d Hz) exceeds "
1132                                         "required transfer speed (%d Hz)\n",
1133                                         min_speed_hz,
1134                                         tmp);
1135                                 goto msg_rejected;
1136                         } else if (tmp > max_speed_hz) {
1137                                 dev_err(&drv_data->pdev->dev,
1138                                         "message rejected : "
1139                                         "transfer speed (%d Hz) exceeds "
1140                                         "device max speed (%d Hz)\n",
1141                                         tmp,
1142                                         max_speed_hz);
1143                                 goto msg_rejected;
1144                         }
1145                 }
1146         }
1147
1148         /* Message accepted */
1149         msg->status = -EINPROGRESS;
1150         msg->state = START_STATE;
1151
1152         spin_lock_irqsave(&drv_data->lock, flags);
1153         if (drv_data->run == QUEUE_STOPPED) {
1154                 spin_unlock_irqrestore(&drv_data->lock, flags);
1155                 return -ESHUTDOWN;
1156         }
1157
1158         list_add_tail(&msg->queue, &drv_data->queue);
1159         if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1160                 queue_work(drv_data->workqueue, &drv_data->work);
1161
1162         spin_unlock_irqrestore(&drv_data->lock, flags);
1163         return 0;
1164
1165 msg_rejected:
1166         /* Message rejected and not queued */
1167         msg->status = -EINVAL;
1168         msg->state = ERROR_STATE;
1169         if (msg->complete)
1170                 msg->complete(msg->context);
1171         return -EINVAL;
1172 }
1173
1174 /* the spi->mode bits understood by this driver: */
1175 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
1176
1177 /* On first setup bad values must free chip_data memory since will cause
1178    spi_new_device to fail. Bad value setup from protocol driver are simply not
1179    applied and notified to the calling driver. */
1180 static int setup(struct spi_device *spi)
1181 {
1182         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1183         struct spi_imx_chip *chip_info;
1184         struct chip_data *chip;
1185         int first_setup = 0;
1186         u32 tmp;
1187         int status = 0;
1188
1189         if (spi->mode & ~MODEBITS) {
1190                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
1191                         spi->mode & ~MODEBITS);
1192                 return -EINVAL;
1193         }
1194
1195         /* Get controller data */
1196         chip_info = spi->controller_data;
1197
1198         /* Get controller_state */
1199         chip = spi_get_ctldata(spi);
1200         if (chip == NULL) {
1201                 first_setup = 1;
1202
1203                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1204                 if (!chip) {
1205                         dev_err(&spi->dev,
1206                                 "setup - cannot allocate controller state\n");
1207                         return -ENOMEM;
1208                 }
1209                 chip->control = SPI_DEFAULT_CONTROL;
1210
1211                 if (chip_info == NULL) {
1212                         /* spi_board_info.controller_data not is supplied */
1213                         chip_info = kzalloc(sizeof(struct spi_imx_chip),
1214                                                 GFP_KERNEL);
1215                         if (!chip_info) {
1216                                 dev_err(&spi->dev,
1217                                         "setup - "
1218                                         "cannot allocate controller data\n");
1219                                 status = -ENOMEM;
1220                                 goto err_first_setup;
1221                         }
1222                         /* Set controller data default value */
1223                         chip_info->enable_loopback =
1224                                                 SPI_DEFAULT_ENABLE_LOOPBACK;
1225                         chip_info->enable_dma = SPI_DEFAULT_ENABLE_DMA;
1226                         chip_info->ins_ss_pulse = 1;
1227                         chip_info->bclk_wait = SPI_DEFAULT_PERIOD_WAIT;
1228                         chip_info->cs_control = null_cs_control;
1229                 }
1230         }
1231
1232         /* Now set controller state based on controller data */
1233
1234         if (first_setup) {
1235                 /* SPI loopback */
1236                 if (chip_info->enable_loopback)
1237                         chip->test = SPI_TEST_LBC;
1238                 else
1239                         chip->test = 0;
1240
1241                 /* SPI dma driven */
1242                 chip->enable_dma = chip_info->enable_dma;
1243
1244                 /* SPI /SS pulse between spi burst */
1245                 if (chip_info->ins_ss_pulse)
1246                         u32_EDIT(chip->control,
1247                                 SPI_CONTROL_SSCTL, SPI_CONTROL_SSCTL_1);
1248                 else
1249                         u32_EDIT(chip->control,
1250                                 SPI_CONTROL_SSCTL, SPI_CONTROL_SSCTL_0);
1251
1252                 /* SPI bclk waits between each bits_per_word spi burst */
1253                 if (chip_info->bclk_wait > SPI_PERIOD_MAX_WAIT) {
1254                         dev_err(&spi->dev,
1255                                 "setup - "
1256                                 "bclk_wait exceeds max allowed (%d)\n",
1257                                 SPI_PERIOD_MAX_WAIT);
1258                         goto err_first_setup;
1259                 }
1260                 chip->period = SPI_PERIOD_CSRC_BCLK |
1261                                 (chip_info->bclk_wait & SPI_PERIOD_WAIT);
1262         }
1263
1264         /* SPI mode */
1265         tmp = spi->mode;
1266         if (tmp & SPI_CS_HIGH) {
1267                 u32_EDIT(chip->control,
1268                                 SPI_CONTROL_SSPOL, SPI_CONTROL_SSPOL_ACT_HIGH);
1269         }
1270         switch (tmp & SPI_MODE_3) {
1271         case SPI_MODE_0:
1272                 tmp = 0;
1273                 break;
1274         case SPI_MODE_1:
1275                 tmp = SPI_CONTROL_PHA_1;
1276                 break;
1277         case SPI_MODE_2:
1278                 tmp = SPI_CONTROL_POL_ACT_LOW;
1279                 break;
1280         default:
1281                 /* SPI_MODE_3 */
1282                 tmp = SPI_CONTROL_PHA_1 | SPI_CONTROL_POL_ACT_LOW;
1283                 break;
1284         }
1285         u32_EDIT(chip->control, SPI_CONTROL_POL | SPI_CONTROL_PHA, tmp);
1286
1287         /* SPI word width */
1288         tmp = spi->bits_per_word;
1289         if (tmp == 0) {
1290                 tmp = 8;
1291                 spi->bits_per_word = 8;
1292         } else if (tmp > 16) {
1293                 status = -EINVAL;
1294                 dev_err(&spi->dev,
1295                         "setup - "
1296                         "invalid bits_per_word (%d)\n",
1297                         tmp);
1298                 if (first_setup)
1299                         goto err_first_setup;
1300                 else {
1301                         /* Undo setup using chip as backup copy */
1302                         tmp = chip->bits_per_word;
1303                         spi->bits_per_word = tmp;
1304                 }
1305         }
1306         chip->bits_per_word = tmp;
1307         u32_EDIT(chip->control, SPI_CONTROL_BITCOUNT_MASK, tmp - 1);
1308         chip->n_bytes = (tmp <= 8) ? 1 : 2;
1309
1310         /* SPI datarate */
1311         tmp = spi_data_rate(drv_data, spi->max_speed_hz);
1312         if (tmp == SPI_CONTROL_DATARATE_BAD) {
1313                 status = -EINVAL;
1314                 dev_err(&spi->dev,
1315                         "setup - "
1316                         "HW min speed (%d Hz) exceeds required "
1317                         "max speed (%d Hz)\n",
1318                         spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN),
1319                         spi->max_speed_hz);
1320                 if (first_setup)
1321                         goto err_first_setup;
1322                 else
1323                         /* Undo setup using chip as backup copy */
1324                         spi->max_speed_hz = chip->max_speed_hz;
1325         } else {
1326                 u32_EDIT(chip->control, SPI_CONTROL_DATARATE, tmp);
1327                 /* Actual rounded max_speed_hz */
1328                 tmp = spi_speed_hz(drv_data, tmp);
1329                 spi->max_speed_hz = tmp;
1330                 chip->max_speed_hz = tmp;
1331         }
1332
1333         /* SPI chip-select management */
1334         if (chip_info->cs_control)
1335                 chip->cs_control = chip_info->cs_control;
1336         else
1337                 chip->cs_control = null_cs_control;
1338
1339         /* Save controller_state */
1340         spi_set_ctldata(spi, chip);
1341
1342         /* Summary */
1343         dev_dbg(&spi->dev,
1344                 "setup succeded\n"
1345                 "    loopback enable   = %s\n"
1346                 "    dma enable        = %s\n"
1347                 "    insert /ss pulse  = %s\n"
1348                 "    period wait       = %d\n"
1349                 "    mode              = %d\n"
1350                 "    bits per word     = %d\n"
1351                 "    min speed         = %d Hz\n"
1352                 "    rounded max speed = %d Hz\n",
1353                 chip->test & SPI_TEST_LBC ? "Yes" : "No",
1354                 chip->enable_dma ? "Yes" : "No",
1355                 chip->control & SPI_CONTROL_SSCTL ? "Yes" : "No",
1356                 chip->period & SPI_PERIOD_WAIT,
1357                 spi->mode,
1358                 spi->bits_per_word,
1359                 spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN),
1360                 spi->max_speed_hz);
1361         return status;
1362
1363 err_first_setup:
1364         kfree(chip);
1365         return status;
1366 }
1367
1368 static void cleanup(struct spi_device *spi)
1369 {
1370         kfree(spi_get_ctldata(spi));
1371 }
1372
1373 static int __init init_queue(struct driver_data *drv_data)
1374 {
1375         INIT_LIST_HEAD(&drv_data->queue);
1376         spin_lock_init(&drv_data->lock);
1377
1378         drv_data->run = QUEUE_STOPPED;
1379         drv_data->busy = 0;
1380
1381         tasklet_init(&drv_data->pump_transfers,
1382                         pump_transfers, (unsigned long)drv_data);
1383
1384         INIT_WORK(&drv_data->work, pump_messages);
1385         drv_data->workqueue = create_singlethread_workqueue(
1386                                 dev_name(drv_data->master->dev.parent));
1387         if (drv_data->workqueue == NULL)
1388                 return -EBUSY;
1389
1390         return 0;
1391 }
1392
1393 static int start_queue(struct driver_data *drv_data)
1394 {
1395         unsigned long flags;
1396
1397         spin_lock_irqsave(&drv_data->lock, flags);
1398
1399         if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1400                 spin_unlock_irqrestore(&drv_data->lock, flags);
1401                 return -EBUSY;
1402         }
1403
1404         drv_data->run = QUEUE_RUNNING;
1405         drv_data->cur_msg = NULL;
1406         drv_data->cur_transfer = NULL;
1407         drv_data->cur_chip = NULL;
1408         spin_unlock_irqrestore(&drv_data->lock, flags);
1409
1410         queue_work(drv_data->workqueue, &drv_data->work);
1411
1412         return 0;
1413 }
1414
1415 static int stop_queue(struct driver_data *drv_data)
1416 {
1417         unsigned long flags;
1418         unsigned limit = 500;
1419         int status = 0;
1420
1421         spin_lock_irqsave(&drv_data->lock, flags);
1422
1423         /* This is a bit lame, but is optimized for the common execution path.
1424          * A wait_queue on the drv_data->busy could be used, but then the common
1425          * execution path (pump_messages) would be required to call wake_up or
1426          * friends on every SPI message. Do this instead */
1427         drv_data->run = QUEUE_STOPPED;
1428         while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1429                 spin_unlock_irqrestore(&drv_data->lock, flags);
1430                 msleep(10);
1431                 spin_lock_irqsave(&drv_data->lock, flags);
1432         }
1433
1434         if (!list_empty(&drv_data->queue) || drv_data->busy)
1435                 status = -EBUSY;
1436
1437         spin_unlock_irqrestore(&drv_data->lock, flags);
1438
1439         return status;
1440 }
1441
1442 static int destroy_queue(struct driver_data *drv_data)
1443 {
1444         int status;
1445
1446         status = stop_queue(drv_data);
1447         if (status != 0)
1448                 return status;
1449
1450         if (drv_data->workqueue)
1451                 destroy_workqueue(drv_data->workqueue);
1452
1453         return 0;
1454 }
1455
1456 static int __init spi_imx_probe(struct platform_device *pdev)
1457 {
1458         struct device *dev = &pdev->dev;
1459         struct spi_imx_master *platform_info;
1460         struct spi_master *master;
1461         struct driver_data *drv_data;
1462         struct resource *res;
1463         int irq, status = 0;
1464
1465         platform_info = dev->platform_data;
1466         if (platform_info == NULL) {
1467                 dev_err(&pdev->dev, "probe - no platform data supplied\n");
1468                 status = -ENODEV;
1469                 goto err_no_pdata;
1470         }
1471
1472         /* Allocate master with space for drv_data */
1473         master = spi_alloc_master(dev, sizeof(struct driver_data));
1474         if (!master) {
1475                 dev_err(&pdev->dev, "probe - cannot alloc spi_master\n");
1476                 status = -ENOMEM;
1477                 goto err_no_mem;
1478         }
1479         drv_data = spi_master_get_devdata(master);
1480         drv_data->master = master;
1481         drv_data->master_info = platform_info;
1482         drv_data->pdev = pdev;
1483
1484         master->bus_num = pdev->id;
1485         master->num_chipselect = platform_info->num_chipselect;
1486         master->dma_alignment = DMA_ALIGNMENT;
1487         master->cleanup = cleanup;
1488         master->setup = setup;
1489         master->transfer = transfer;
1490
1491         drv_data->dummy_dma_buf = SPI_DUMMY_u32;
1492
1493         drv_data->clk = clk_get(&pdev->dev, "perclk2");
1494         if (IS_ERR(drv_data->clk)) {
1495                 dev_err(&pdev->dev, "probe - cannot get clock\n");
1496                 status = PTR_ERR(drv_data->clk);
1497                 goto err_no_clk;
1498         }
1499         clk_enable(drv_data->clk);
1500
1501         /* Find and map resources */
1502         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1503         if (!res) {
1504                 dev_err(&pdev->dev, "probe - MEM resources not defined\n");
1505                 status = -ENODEV;
1506                 goto err_no_iores;
1507         }
1508         drv_data->ioarea = request_mem_region(res->start,
1509                                                 res->end - res->start + 1,
1510                                                 pdev->name);
1511         if (drv_data->ioarea == NULL) {
1512                 dev_err(&pdev->dev, "probe - cannot reserve region\n");
1513                 status = -ENXIO;
1514                 goto err_no_iores;
1515         }
1516         drv_data->regs = ioremap(res->start, res->end - res->start + 1);
1517         if (drv_data->regs == NULL) {
1518                 dev_err(&pdev->dev, "probe - cannot map IO\n");
1519                 status = -ENXIO;
1520                 goto err_no_iomap;
1521         }
1522         drv_data->rd_data_phys = (dma_addr_t)res->start;
1523
1524         /* Attach to IRQ */
1525         irq = platform_get_irq(pdev, 0);
1526         if (irq < 0) {
1527                 dev_err(&pdev->dev, "probe - IRQ resource not defined\n");
1528                 status = -ENODEV;
1529                 goto err_no_irqres;
1530         }
1531         status = request_irq(irq, spi_int, IRQF_DISABLED,
1532                              dev_name(dev), drv_data);
1533         if (status < 0) {
1534                 dev_err(&pdev->dev, "probe - cannot get IRQ (%d)\n", status);
1535                 goto err_no_irqres;
1536         }
1537
1538         /* Setup DMA if requested */
1539         drv_data->tx_channel = -1;
1540         drv_data->rx_channel = -1;
1541         if (platform_info->enable_dma) {
1542                 /* Get rx DMA channel */
1543                 drv_data->rx_channel = imx_dma_request_by_prio("spi_imx_rx",
1544                                                                DMA_PRIO_HIGH);
1545                 if (drv_data->rx_channel < 0) {
1546                         dev_err(dev,
1547                                 "probe - problem (%d) requesting rx channel\n",
1548                                 drv_data->rx_channel);
1549                         goto err_no_rxdma;
1550                 } else
1551                         imx_dma_setup_handlers(drv_data->rx_channel, NULL,
1552                                                 dma_err_handler, drv_data);
1553
1554                 /* Get tx DMA channel */
1555                 drv_data->tx_channel = imx_dma_request_by_prio("spi_imx_tx",
1556                                                                DMA_PRIO_MEDIUM);
1557                 if (drv_data->tx_channel < 0) {
1558                         dev_err(dev,
1559                                 "probe - problem (%d) requesting tx channel\n",
1560                                 drv_data->tx_channel);
1561                         imx_dma_free(drv_data->rx_channel);
1562                         goto err_no_txdma;
1563                 } else
1564                         imx_dma_setup_handlers(drv_data->tx_channel,
1565                                                 dma_tx_handler, dma_err_handler,
1566                                                 drv_data);
1567
1568                 /* Set request source and burst length for allocated channels */
1569                 switch (drv_data->pdev->id) {
1570                 case 1:
1571                         /* Using SPI1 */
1572                         RSSR(drv_data->rx_channel) = DMA_REQ_SPI1_R;
1573                         RSSR(drv_data->tx_channel) = DMA_REQ_SPI1_T;
1574                         break;
1575                 case 2:
1576                         /* Using SPI2 */
1577                         RSSR(drv_data->rx_channel) = DMA_REQ_SPI2_R;
1578                         RSSR(drv_data->tx_channel) = DMA_REQ_SPI2_T;
1579                         break;
1580                 default:
1581                         dev_err(dev, "probe - bad SPI Id\n");
1582                         imx_dma_free(drv_data->rx_channel);
1583                         imx_dma_free(drv_data->tx_channel);
1584                         status = -ENODEV;
1585                         goto err_no_devid;
1586                 }
1587                 BLR(drv_data->rx_channel) = SPI_DMA_BLR;
1588                 BLR(drv_data->tx_channel) = SPI_DMA_BLR;
1589         }
1590
1591         /* Load default SPI configuration */
1592         writel(SPI_RESET_START, drv_data->regs + SPI_RESET);
1593         writel(0, drv_data->regs + SPI_RESET);
1594         writel(SPI_DEFAULT_CONTROL, drv_data->regs + SPI_CONTROL);
1595
1596         /* Initial and start queue */
1597         status = init_queue(drv_data);
1598         if (status != 0) {
1599                 dev_err(&pdev->dev, "probe - problem initializing queue\n");
1600                 goto err_init_queue;
1601         }
1602         status = start_queue(drv_data);
1603         if (status != 0) {
1604                 dev_err(&pdev->dev, "probe - problem starting queue\n");
1605                 goto err_start_queue;
1606         }
1607
1608         /* Register with the SPI framework */
1609         platform_set_drvdata(pdev, drv_data);
1610         status = spi_register_master(master);
1611         if (status != 0) {
1612                 dev_err(&pdev->dev, "probe - problem registering spi master\n");
1613                 goto err_spi_register;
1614         }
1615
1616         dev_dbg(dev, "probe succeded\n");
1617         return 0;
1618
1619 err_init_queue:
1620 err_start_queue:
1621 err_spi_register:
1622         destroy_queue(drv_data);
1623
1624 err_no_rxdma:
1625 err_no_txdma:
1626 err_no_devid:
1627         free_irq(irq, drv_data);
1628
1629 err_no_irqres:
1630         iounmap(drv_data->regs);
1631
1632 err_no_iomap:
1633         release_resource(drv_data->ioarea);
1634         kfree(drv_data->ioarea);
1635
1636 err_no_iores:
1637         clk_disable(drv_data->clk);
1638         clk_put(drv_data->clk);
1639
1640 err_no_clk:
1641         spi_master_put(master);
1642
1643 err_no_pdata:
1644 err_no_mem:
1645         return status;
1646 }
1647
1648 static int __exit spi_imx_remove(struct platform_device *pdev)
1649 {
1650         struct driver_data *drv_data = platform_get_drvdata(pdev);
1651         int irq;
1652         int status = 0;
1653
1654         if (!drv_data)
1655                 return 0;
1656
1657         tasklet_kill(&drv_data->pump_transfers);
1658
1659         /* Remove the queue */
1660         status = destroy_queue(drv_data);
1661         if (status != 0) {
1662                 dev_err(&pdev->dev, "queue remove failed (%d)\n", status);
1663                 return status;
1664         }
1665
1666         /* Reset SPI */
1667         writel(SPI_RESET_START, drv_data->regs + SPI_RESET);
1668         writel(0, drv_data->regs + SPI_RESET);
1669
1670         /* Release DMA */
1671         if (drv_data->master_info->enable_dma) {
1672                 RSSR(drv_data->rx_channel) = 0;
1673                 RSSR(drv_data->tx_channel) = 0;
1674                 imx_dma_free(drv_data->tx_channel);
1675                 imx_dma_free(drv_data->rx_channel);
1676         }
1677
1678         /* Release IRQ */
1679         irq = platform_get_irq(pdev, 0);
1680         if (irq >= 0)
1681                 free_irq(irq, drv_data);
1682
1683         clk_disable(drv_data->clk);
1684         clk_put(drv_data->clk);
1685
1686         /* Release map resources */
1687         iounmap(drv_data->regs);
1688         release_resource(drv_data->ioarea);
1689         kfree(drv_data->ioarea);
1690
1691         /* Disconnect from the SPI framework */
1692         spi_unregister_master(drv_data->master);
1693         spi_master_put(drv_data->master);
1694
1695         /* Prevent double remove */
1696         platform_set_drvdata(pdev, NULL);
1697
1698         dev_dbg(&pdev->dev, "remove succeded\n");
1699
1700         return 0;
1701 }
1702
1703 static void spi_imx_shutdown(struct platform_device *pdev)
1704 {
1705         struct driver_data *drv_data = platform_get_drvdata(pdev);
1706
1707         /* Reset SPI */
1708         writel(SPI_RESET_START, drv_data->regs + SPI_RESET);
1709         writel(0, drv_data->regs + SPI_RESET);
1710
1711         dev_dbg(&pdev->dev, "shutdown succeded\n");
1712 }
1713
1714 #ifdef CONFIG_PM
1715
1716 static int spi_imx_suspend(struct platform_device *pdev, pm_message_t state)
1717 {
1718         struct driver_data *drv_data = platform_get_drvdata(pdev);
1719         int status = 0;
1720
1721         status = stop_queue(drv_data);
1722         if (status != 0) {
1723                 dev_warn(&pdev->dev, "suspend cannot stop queue\n");
1724                 return status;
1725         }
1726
1727         dev_dbg(&pdev->dev, "suspended\n");
1728
1729         return 0;
1730 }
1731
1732 static int spi_imx_resume(struct platform_device *pdev)
1733 {
1734         struct driver_data *drv_data = platform_get_drvdata(pdev);
1735         int status = 0;
1736
1737         /* Start the queue running */
1738         status = start_queue(drv_data);
1739         if (status != 0)
1740                 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1741         else
1742                 dev_dbg(&pdev->dev, "resumed\n");
1743
1744         return status;
1745 }
1746 #else
1747 #define spi_imx_suspend NULL
1748 #define spi_imx_resume NULL
1749 #endif /* CONFIG_PM */
1750
1751 /* work with hotplug and coldplug */
1752 MODULE_ALIAS("platform:spi_imx");
1753
1754 static struct platform_driver driver = {
1755         .driver = {
1756                 .name = "spi_imx",
1757                 .owner = THIS_MODULE,
1758         },
1759         .remove = __exit_p(spi_imx_remove),
1760         .shutdown = spi_imx_shutdown,
1761         .suspend = spi_imx_suspend,
1762         .resume = spi_imx_resume,
1763 };
1764
1765 static int __init spi_imx_init(void)
1766 {
1767         return platform_driver_probe(&driver, spi_imx_probe);
1768 }
1769 module_init(spi_imx_init);
1770
1771 static void __exit spi_imx_exit(void)
1772 {
1773         platform_driver_unregister(&driver);
1774 }
1775 module_exit(spi_imx_exit);
1776
1777 MODULE_AUTHOR("Andrea Paterniani, <a.paterniani@swapp-eng.it>");
1778 MODULE_DESCRIPTION("iMX SPI Controller Driver");
1779 MODULE_LICENSE("GPL");